Semiconductor structure and manufacturing method

Abstract

This application discloses a semiconductor structure and a method for manufacturing the same. The method includes: forming a trench on a substrate; filling the trench with a sacrificial dielectric layer; progressively etching the sacrificial dielectric layer to progressively expose the sidewalls of the trench, wherein the exposed sidewalls are at least partially oxidized to form an oxide dielectric layer, the thickness of the oxide dielectric layer within the trench increasing sequentially from the bottom of the trench towards the trench opening; and forming a conductive layer on the surface of the oxide dielectric layer within the trench.

Description

Technical Field

[0001] This application relates to semiconductor technology, and includes, but is not limited to, a semiconductor structure and its manufacturing method. Background Technology

[0002] With the rapid development of VLSI technology, the size of semiconductor devices is constantly shrinking. Due to this dramatic reduction in size, the thickness of the gate oxide layer in transistors has decreased to 2 nm or even less. However, while semiconductor devices are shrinking proportionally, the operating voltage has not decreased proportionally, resulting in a very strong gate-induced-drain leakage (GIDL) current effect in short-channel devices, which affects the reliability of semiconductor devices. Therefore, reducing the GIDL current effect in semiconductor devices has become an urgent problem to be solved. Summary of the Invention

[0003] In view of this, embodiments of this application provide a semiconductor structure and a method for manufacturing the same.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor structure, the method comprising:

[0005] Trenches are formed on the substrate;

[0006] A sacrificial medium layer is filled into the trench;

[0007] The sacrificial dielectric layer is gradually etched to gradually expose the sidewalls of the trench. The exposed sidewalls of the trench are at least partially oxidized to form an oxide dielectric layer. The thickness of the oxide dielectric layer in the trench increases sequentially in the direction extending from the bottom of the trench to the opening of the trench.

[0008] A conductive layer is formed on the surface of the oxide dielectric layer, and the conductive layer is formed within the trench.

[0009] In some embodiments, the method further includes:

[0010] Active regions arranged at intervals and isolation structures filled between the active regions are formed on the substrate, and trenches are formed in the active regions and the isolation structures.

[0011] In some embodiments, the oxide dielectric layer is formed on the sidewall of the trench in the active region.

[0012] In some embodiments, the sacrificial dielectric layer comprises an undoped amorphous carbon layer or a doped amorphous carbon layer.

[0013] In some embodiments, the stepwise etching of the sacrificial dielectric layer to gradually expose the sidewalls of the trench, wherein the exposed sidewalls of the trench are oxidized to form an oxide dielectric layer, includes:

[0014] The sacrificial dielectric layer is etched using oxygen-containing plasma, and the flow rate of the oxygen-containing plasma is controlled to gradually etch the sacrificial dielectric layer; the oxygen-containing plasma oxidizes the sidewalls of the trench to generate the oxide dielectric layer.

[0015] In some embodiments, the oxygen-containing plasma includes water vapor plasma.

[0016] In some embodiments, the method further includes:

[0017] The oxide dielectric layer and the conductive layer are etched back to the target depth to form the target structure.

[0018] In some embodiments, forming a conductive layer on the surface of the oxide dielectric layer, the conductive layer being formed within the trench, includes:

[0019] After forming the oxide dielectric layer, photoresist material is filled into the trench, with the top surface of the photoresist material being lower than the surface of the substrate.

[0020] Remove the oxide dielectric layer exposed by the photoresist material;

[0021] Remove the photoresist material;

[0022] A conductive layer is deposited within the trench.

[0023] In some embodiments, forming a conductive layer on the surface of the oxide dielectric layer, the conductive layer being formed within the trench, includes:

[0024] After forming the oxide dielectric layer, photoresist material is filled into the trench, with the top surface of the photoresist material being lower than the surface of the substrate.

[0025] Remove the oxide dielectric layer and part of the isolation structure above the photoresist material;

[0026] Remove the photoresist material;

[0027] A conductive layer is deposited within the trench.

[0028] In some embodiments, depositing a conductive layer within the trench includes:

[0029] A conductive material is deposited within the trench, and the conductive material is controlled to a target height to form the conductive layer, wherein the target height of the conductive layer is less than the height of the trench.

[0030] In some embodiments, the target height of the conductive layer is not less than the height of the oxide dielectric layer.

[0031] In some embodiments, the method further includes:

[0032] An insulating layer is covered on the conductive layer and the oxide dielectric layer, and the insulating layer is located within the trench.

[0033] In some embodiments, covering the conductive layer and the oxide dielectric layer with an insulating layer includes:

[0034] An insulating material is deposited within the trench using a low-pressure chemical vapor deposition method to form an insulating layer covering the conductive layer and the oxide dielectric layer.

[0035] Secondly, embodiments of this application also provide a semiconductor structure, including:

[0036] A substrate; wherein the substrate has trenches; and a gate structure is formed within the trenches;

[0037] The gate structure includes an oxide dielectric layer and a conductive layer. The oxide dielectric layer covers the sidewalls of the trench, and the conductive layer is located inside the trench covered by the oxide dielectric layer. The thickness of the oxide dielectric layer inside the trench increases sequentially from the bottom of the trench to the opening of the trench.

[0038] In some embodiments, the semiconductor structure further includes:

[0039] Active regions are spaced apart on the substrate and isolation structures are filled between the active regions, with trenches located in the active regions and the isolation structures.

[0040] In some embodiments, the oxide dielectric layer is formed in the trench located in the active region.

[0041] In some embodiments, the top surfaces of the conductive layer and the oxide dielectric layer are lower than the surface of the substrate; the semiconductor structure further includes:

[0042] An insulating layer, located within the trench, covers the conductive layer and the oxide dielectric layer; wherein the insulating layer serves to protect the gate structure.

[0043] In some embodiments, the trench extends through a plurality of spaced-apart active regions and isolation structures; the gate structures are connected within the trench, and in a direction parallel to the active regions, the surface width of the gate structure located in the isolation structure is greater than the surface width of the gate structure located in the active regions.

[0044] In this embodiment, a sacrificial dielectric layer is filled into the trench, and the sidewalls of the trench are gradually exposed and oxidized during the gradual etching of the sacrificial dielectric. This results in a thinner oxide dielectric layer at the bottom of the trench, giving the corresponding gate structure good switching characteristics. Simultaneously, the oxide dielectric layer becomes thicker closer to the trench opening, reducing GIDL leakage in the overlapping area between the formed gate structure and the active regions on both sides of the trench, thus improving the reliability and stability of the product. Attached Figure Description

[0045] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to one embodiment of this application;

[0046] Figure 2 This is a schematic diagram of a method for forming a gate dielectric layer in a semiconductor structure manufacturing process according to an embodiment of this application;

[0047] Figure 3 A schematic diagram of a gate structure formed in a semiconductor structure manufacturing method according to an embodiment of this application;

[0048] Figure 4 A schematic diagram of a semiconductor structure provided in one embodiment of this application;

[0049] Figure 5 A schematic diagram of a semiconductor structure provided in one embodiment of this application;

[0050] Figure 6A A top view of a semiconductor structure provided in one embodiment of this application;

[0051] Figure 6B for Figure 6A A magnified view of a portion of the image;

[0052] Figure 7 A schematic diagram of a semiconductor structure provided in one embodiment of this application;

[0053] Figure 8A A cross-sectional schematic diagram of each step in a method for manufacturing a semiconductor structure according to an embodiment of this application;

[0054] Figure 8B This is a cross-sectional schematic diagram of a semiconductor structure manufacturing method provided in one embodiment of this application;

[0055] Figure 9A A cross-sectional schematic diagram of each step in a method for manufacturing a semiconductor structure according to an embodiment of this application;

[0056] Figure 9BThis is a cross-sectional schematic diagram of a semiconductor structure manufacturing method provided in one embodiment of this application;

[0057] Figure 9C This is a cross-sectional schematic diagram of a semiconductor structure manufacturing method provided in one embodiment of this application;

[0058] Figure 9D A cross-sectional schematic diagram of each step in a method for manufacturing a semiconductor structure according to an embodiment of this application;

[0059] Figure 10 This is a cross-sectional schematic diagram of a semiconductor structure manufacturing method provided in one embodiment of this application. Detailed Implementation

[0060] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0062] This application provides a method for manufacturing a semiconductor structure, such as... Figure 1 As shown, the method includes:

[0063] Step S101: Form trenches on the substrate;

[0064] Step S102: Fill the trench with a sacrificial medium layer;

[0065] Step S103: Gradually etch the sacrificial dielectric layer to gradually expose the sidewalls of the trench. The exposed sidewalls of the trench are at least partially oxidized to form an oxide dielectric layer. The thickness of the oxide dielectric layer in the trench increases sequentially from the bottom of the trench to the trench opening.

[0066] Step S104: A conductive layer is formed on the surface of the oxide dielectric layer, and the conductive layer is formed in the trench.

[0067] In this embodiment, trenches can be formed on the substrate surface using a patterned etching method. Semiconductor structures, such as gate structures, are formed within these trenches. These gate structures can extend throughout the entire semiconductor structure and serve as word lines within the semiconductor structure. Because the gate structures are buried within the trenches rather than covering the substrate surface, this structure is also known as a buried word line (BWL).

[0068] Multiple trenches can be formed and distributed parallel to each other on the substrate. Exemplarily, the trenches can be parallel to each other and have equal spacing, depth, and width, or they can have different spacing and width. The multiple trenches can be formed simultaneously by etching.

[0069] After the trench is formed, a sacrificial dielectric layer can be filled into the trench. The sacrificial dielectric layer is used to assist in the formation of the oxide dielectric layer that serves as the gate dielectric layer. Therefore, the sacrificial dielectric layer has been removed in the final semiconductor structure.

[0070] In this embodiment, the sidewalls of the trench can be gradually exposed by progressively etching the sacrificial dielectric layer, and the sidewalls can be progressively oxidized to form an oxide dielectric layer. By progressively etching the sacrificial layer and oxidizing the trench sidewalls, the oxidation time of the sidewalls from the opening to the bottom of the trench can be gradually reduced. That is, the sidewalls closer to the trench opening are oxidized for a longer time, resulting in a thicker oxide dielectric layer; the sidewalls closer to the bottom of the trench are oxidized for a shorter time, resulting in a thinner oxide dielectric layer.

[0071] This allows the thickness of the oxide dielectric layer to increase sequentially from the bottom of the trench to the trench opening. For example... Figure 2 As shown, a trench 110 is formed in the substrate 100, the inner wall of the trench is covered with an oxide dielectric layer 121, and the thickness of the oxide dielectric layer 121 on the sidewall of the trench gradually increases from the bottom of the trench to the opening.

[0072] After the oxide dielectric layer is formed, a conductive material can be filled into the trench to form a conductive layer. The conductive material includes metallic materials or compound conductive materials, such as tungsten (W) and titanium nitride (TiN).

[0073] After the conductive layer is formed, the oxide dielectric layer and the conductive layer can be etched back to the target depth, that is, the conductive layer and the oxide dielectric layer near the opening of the trench can be removed. Using the method described in the embodiments of this application, the sidewalls of the trench are gradually oxidized by progressively etching the sacrificial dielectric layer, resulting in an oxide dielectric layer whose thickness gradually increases from the bottom of the trench to the opening. This creates a thinner oxide dielectric layer at the bottom of the trench, while the gate dielectric layer becomes thicker closer to the trench opening.

[0074] In some embodiments, the forming method further includes:

[0075] Active regions arranged at intervals and isolation structures filling the spaces between the active regions are formed on the substrate, and trenches are formed in the active regions and the isolation structures.

[0076] In this embodiment, before forming the trenches described above, active regions and isolation structures can be formed on the substrate at intervals. The active regions can be formed by doping the silicon substrate, and an insulating material, which can be silicon dioxide, is filled between each pair of active regions as an isolation structure.

[0077] The extension direction of the active region has a certain angle with the extension direction of the trench. For example, the extension direction of the active region can be perpendicular to the extension direction of the trench.

[0078] In one embodiment, an active region of a certain depth can be formed on the substrate by doping the entire area of ​​the substrate, and then a trench can be formed by etching the active region and the isolation structure between the active regions.

[0079] The aforementioned conductive layer can serve as the gate conductive layer in a semiconductor structure, providing the gate control voltage. An oxide dielectric layer with a gradually varying thickness is located between the active region and the conductive layer. The gate control voltage on the conductive layer causes charge migration in the active regions on both sides of the trench, thereby enabling the switching function of the transistor.

[0080] It should be noted that, since the active regions and isolation structures are arranged alternately, and the trenches can run through the entire semiconductor structure, the trenches can run through multiple active regions and isolation structures.

[0081] In one embodiment, the oxide dielectric layer and the conductive layer cover the sidewalls of the trench, and thus also penetrate multiple active regions and isolation structures.

[0082] In another embodiment, the aforementioned oxide dielectric layer can be formed on the sidewalls of the trench in the active region. Since both the isolation structure and the oxide dielectric layer can be made of silicon dioxide, only the sidewalls of the source region are oxidized to form the oxide dielectric layer during its formation, and it is integrated with the isolation structure.

[0083] In some embodiments, the sacrificial dielectric layer includes an undoped amorphous carbon layer or a doped amorphous carbon layer.

[0084] In this embodiment, to form an oxide dielectric layer with a gradually varying thickness, a sacrificial dielectric layer can be used. During the gradual removal of the sacrificial dielectric layer by etching, the oxide dielectric layer is simultaneously oxidized. The sacrificial dielectric layer can be made of amorphous carbon, including undoped pure amorphous carbon and doped amorphous carbon. Doped amorphous carbon materials can include boron-doped amorphous carbon (BALC).

[0085] In some embodiments, the sacrificial dielectric layer is progressively etched to progressively expose the sidewalls of the trench, the exposed sidewalls of the trench being oxidized to form an oxide dielectric layer, including:

[0086] The sacrificial dielectric layer is etched using oxygen-containing plasma, and the sacrificial dielectric layer is gradually etched by controlling the flow rate of the oxygen-containing plasma; an oxide dielectric layer is generated on the sidewall of the oxygen-containing plasma oxidation trench.

[0087] In this embodiment, oxygen-containing plasma can be used to oxidize the carbon elements in the sacrificial medium layer by sputtering, thereby removing the sacrificial medium layer.

[0088] Meanwhile, because the oxygen-containing plasma is sputtered onto the progressively exposed trench sidewalls, and because the exposed trench sidewalls contain silicon, the oxygen-containing plasma reacts with the silicon elements on the trench sidewalls to form a silicon dioxide film.

[0089] During the gradual etching of the sacrificial dielectric layer, oxygen ions are continuously sputtered onto the trench sidewalls, thickening the silica film on the sidewalls. Since the trench sidewalls are gradually exposed as the sacrificial dielectric layer is consumed, the sidewalls closer to the trench opening have a longer exposure time for oxidation, resulting in a thicker silica film; conversely, the sidewalls closer to the trench bottom have a shorter exposure time for oxidation, resulting in a thinner silica film. This creates a silica dielectric layer with a gradually varying thickness.

[0090] Once the sacrificial dielectric layer is completely removed, the bottom of the trench is exposed and undergoes an oxidation reaction to form a silicon dioxide film. This allows the inner wall of the trench to be covered with silicon dioxide.

[0091] In some embodiments, the oxygen-containing plasma includes water vapor plasma.

[0092] The aforementioned oxygen-containing plasma can be water vapor plasma, which is formed by ionizing water vapor to create a mixed plasma of hydrogen and oxygen ions. This approach offers advantages such as lower cost, increased reaction speed, and easier control.

[0093] In addition, in one embodiment, an inert gas can be mixed in the water vapor plasma to control the reaction rate and degree.

[0094] In some embodiments, the forming method further includes:

[0095] The oxide dielectric layer and conductive layer are etched back to the target depth to form the target structure.

[0096] In the semiconductor structure of this application embodiment, since the trench can be used to form buried word lines, that is, the gate structure is buried inside the substrate and connected to the word lines by a conductive layer. In the above embodiment, the formed gate dielectric layer covers the entire inner wall of the trench. Therefore, it is necessary to remove the gate dielectric layer on the sidewall at a certain depth at the trench opening, leaving only a portion of the gate dielectric layer near the bottom of the trench.

[0097] The surfaces of the conductive layer and the oxide dielectric layer can be lower than the opening of the trench. Therefore, the target structure located inside the trench and with a surface lower than the trench opening can be formed by etching back the oxide dielectric layer and the conductive layer to the target depth.

[0098] In some embodiments, a conductive layer is formed on the surface of the oxide dielectric layer, the conductive layer being formed within the trench, including:

[0099] After forming the oxide dielectric layer, the trench is filled with photoresist material, with the top surface of the photoresist material being lower than the surface of the substrate.

[0100] Remove the oxide dielectric layer exposed by the photoresist material;

[0101] Remove photoresist material;

[0102] A conductive layer is deposited in the trench.

[0103] Here, photoresist material can be filled into the trenches where the oxide dielectric layer is formed, with the thickness of the photoresist material being less than the depth of the trench. In other words, after filling with photoresist material, part of the trench still exists, and part of the oxide dielectric layer is exposed.

[0104] At this point, the exposed oxide dielectric layer can be removed by means of etching or cleaning. For example, the silicon oxide film can be removed by hydrofluoric acid solution, while a portion of the oxide dielectric layer near the bottom of the trench is covered by photoresist material and will not be removed.

[0105] The photoresist material can then be removed by cleaning, exposing the remaining oxide dielectric layer and facilitating the subsequent formation of the conductive layer. For example, an aqueous solution of sulfuric acid can be used as the cleaning solution for removing the photoresist material.

[0106] After removing the photoresist material, the trenches are re-exposed. A conductive layer can then be deposited within the trenches, filling the oxide dielectric layer. Since the surface of the conductive layer may be higher than the surface of the oxide dielectric layer, the conductive layer can be further etched back to make its surface flush with or lower than the surface of the oxide dielectric layer.

[0107] This method removes the oxide dielectric layer within a certain height at the top of the trench, thereby enlarging the trench opening and reducing the impact of premature sealing during the deposition of the conductive layer in the formation of the gate structure.

[0108] In some embodiments, a conductive layer is formed on the surface of the oxide dielectric layer, the conductive layer being formed within the trench, including:

[0109] After forming the oxide dielectric layer, the trench is filled with photoresist material, with the top surface of the photoresist material being lower than the surface of the substrate.

[0110] Remove the oxide dielectric layer and part of the isolation structure above the photoresist material;

[0111] Remove photoresist material;

[0112] A conductive layer is deposited in the trench.

[0113] In this embodiment, since the oxide dielectric layer and the isolation structure are made of the same material, during the etching process, the isolation structure exposed above the photoresist material and the oxide dielectric layer are etched away simultaneously, forming a groove. After removing the photoresist material, a conductive layer can be deposited between the oxide dielectric layers within the trench.

[0114] This allows for a larger opening at the trench opening, preventing premature sealing during the deposition of the conductive layer.

[0115] In some embodiments, depositing a conductive layer within the trench includes:

[0116] Conductive material is deposited in the trench, and the conductive material is controlled to a target height to form a conductive layer. The target height of the conductive layer is less than the height of the trench.

[0117] In another embodiment, the target height of the conductive layer is not less than the height of the oxide dielectric layer.

[0118] In this embodiment, a metal material can be filled into the trench by deposition to cover the oxide dielectric layer. The deposition method can include physical vapor deposition (PVD) or atomic layer deposition (ALD), etc.

[0119] Here, the target height of the conductive layer is less than the height of the trench. This means the top surface of the conductive layer can be flush with or slightly lower than the top surface of the oxide dielectric layer after a portion of it has been etched away. However, the top surface of the conductive layer must be lower than the top of the trench, and the conductive layer cannot contact the silicon material on the trench sidewalls. In this way, the conductive layer and the oxide dielectric layer form a complete gate structure.

[0120] Furthermore, since the trenches extend along the substrate surface and can penetrate multiple active regions and isolation layers, the conductive layer can also be penetrated to form a word line.

[0121] In some embodiments, such as Figure 3 As shown, the formation method also includes:

[0122] An insulating layer 123 is covered on the conductive layer 122 and the oxide dielectric layer 121, and the insulating layer 123 is located within the trench 110.

[0123] After forming the conductive layer and oxide dielectric layer, an insulating layer can be covered on the conductive layer and oxide dielectric layer to achieve the function of protecting the gate structure.

[0124] Since the top surfaces of the conductive layer and the oxide dielectric layer are lower than the substrate surface, meaning there is still some space after the gate structure is formed in the trench, an insulating layer covering the gate structure can be formed by depositing insulating material in the trench. This makes the conductive layer that runs through the trench called a buried word line.

[0125] In some embodiments, the insulating layer includes: a silicon nitride layer;

[0126] In other embodiments, the insulating layer may also include a thin film of oxide or organic material.

[0127] In some embodiments, the step of covering the conductive layer and the oxide dielectric layer with an insulating layer includes:

[0128] Insulating material is deposited in the trench using low-pressure chemical vapor deposition to form an insulating layer covering a conductive layer and an oxide dielectric layer.

[0129] In this embodiment, the insulating layer can be formed by depositing uniform silicon nitride in the remaining space within the trench using low-pressure chemical vapor deposition (PLCVD), thereby forming an insulating layer covering the gate structure.

[0130] This application provides a semiconductor structure, such as... Figure 4 As shown, the semiconductor structure 200 includes:

[0131] Substrate 210; wherein, substrate 210 has trench 220; and trench 220 has gate structure 230;

[0132] The gate structure 230 includes an oxide dielectric layer 231 and an electrical layer 232. The oxide dielectric layer 231 covers the sidewall of the trench 220, and the electrical layer 232 is located inside the trench 220 covered by the oxide dielectric layer 231. The thickness of the oxide dielectric layer 231 inside the trench 220 increases sequentially from the bottom of the trench 220 to the opening of the trench 220.

[0133] In this embodiment, the substrate may have multiple trenches, which are spaced apart. One, two, or more trenches may be formed on an active region. These trenches may be distributed parallel to each other on the substrate in a direction parallel to the substrate surface. Exemplarily, the multiple trenches may be parallel to each other and have equal spacing, depth, and width, or they may have different spacing and width.

[0134] The trench contains a gate structure, which serves as the switching control structure for the transistor, allowing it to switch the conductivity state of the conductive channel. Here, the gate structure is distributed within the trench, forming a buried word line.

[0135] The gate structure includes an oxide dielectric layer and a conductive layer. The oxide dielectric layer isolates the conductive layer from the substrate and therefore covers the inner wall of the trench. In this embodiment, the oxide dielectric layer located on the trench sidewall has a gradually changing thickness. The thickness of the oxide dielectric layer increases sequentially from the bottom of the trench to the opening of the trench. This results in a thinner oxide dielectric layer at the bottom of the trench, ensuring the switching characteristics of the gate structure. Simultaneously, the oxide dielectric layer becomes thicker closer to the trench opening, reducing GIDL leakage in the overlap area between the gate and the substrates on both sides of the trench, thus improving the reliability and stability of the product.

[0136] In some embodiments, Figure 5 This is a cross-sectional view of the semiconductor structure along the trench direction, such as... Figure 5 As shown, the semiconductor structure 200 also includes:

[0137] Active regions 240 and isolation structures 250 are spaced apart on the substrate, and trenches 220 are located in the active regions 240 and the isolation structures 250.

[0138] In this embodiment, the active region can be a doped semiconductor material with a certain conductivity. The active region can serve as the source and drain regions of a transistor, driving charge transfer in the semiconductor channel under the control of the gate voltage. Furthermore, the active region can be connected to external wires via contact structures to transmit electrical signals.

[0139] The spaced-apart active regions are separated by an isolation structure, which can be an insulating material, including silicon dioxide, silicon nitride, or other organic materials. The isolation structure provides electrical isolation between adjacent active regions, allowing each active region to be used in an independent transistor structure, thus forming a transistor array. The aforementioned trenches are formed within the active regions and the isolation structure, with the gate located within the trench, thereby forming a transistor structure together with the active regions.

[0140] In some embodiments, an oxide dielectric layer is formed in a trench located in the active region.

[0141] During the oxidation process of the trench inner wall, the sidewalls of the active region within the trench are oxidized to form the aforementioned oxide dielectric layer. If the material of the isolation structure is silicon dioxide, it is the same as the material of the oxide dielectric layer; therefore, after the oxide dielectric layer is formed, it will be integrated with the isolation region. In some embodiments, the top surfaces of the conductive layer and the oxide dielectric layer are lower than the surface of the substrate; such as... Figure 5 As shown, the semiconductor structure also includes:

[0142] An insulating layer 233 is located within the trench 220 and covers the conductive layer 232 and the oxide dielectric layer 231; wherein, the insulating layer 233 is used to protect the gate structure.

[0143] Since the conductive layer is located within the trench, it can be covered by an insulating layer to facilitate the formation of other structures on the substrate surface, including storage capacitors and bit lines. This allows the gate structure to be buried within the substrate, reducing electrical interference with other structures.

[0144] In some embodiments, the trench extends through multiple spaced active regions and isolation structures; gate structures are connected within the trench, and in a direction parallel to the active regions, the surface width of the gate structure located in the isolation structure is greater than the surface width of the gate structure located in the active regions. In embodiments of this application, the trench is located in spaced active regions and isolation structures, and the trench may extend through multiple active regions, thereby serving as a word line in the semiconductor structure to provide gate control signals for multiple transistors.

[0145] In one embodiment of this application, such as Figure 6AAs shown, in the direction aa' parallel to the extension of the active region, the active region can be divided into multiple regions separated by isolation structures. The gate structure 610 runs through each active region and the isolation structure, forming multiple word lines. The isolation structure can be made of silicon dioxide. When the surface of the active region is oxidized in the direction aa', the surface of the isolation structure will not be oxidized to form silicon dioxide. When the oxide dielectric layer on the surface of the active region is removed, the isolation structure will also be partially etched. That is, while removing the oxide dielectric layer, the isolation structure will also be partially etched. In the direction parallel to aa', the surface width bb' of the gate structure 610 formed in the isolation structure is greater than the surface width cc' of the gate structure 610 located between the active regions.

[0146] Figure 6B This is a partially enlarged schematic diagram of the surface where the gate structure is located. The gate structure 610 penetrates multiple isolation structures 611 and active regions 612. However, the surface width bb' of the gate structure 610 located between the active regions 612 is greater than the surface width cc' of the gate structure 610 located in the isolation structure 611.

[0147] In some embodiments, the semiconductor structure further includes:

[0148] The contact structure is located on the surface of the active region.

[0149] The contact structure connects to the surface of the active region on one hand, and to other external circuits on the other. For example, the bit line contact structure connects to the bit line, allowing signals on the bit line to be transmitted to the active region. The memory node contact structure connects to the external memory capacitor. When the gate control signal turns on the transistor, the signal transmitted by the bit line can travel through the active region connected to the bit line contact structure, through the semiconductor conductive channel, and then through the active region and the memory node contact structure to reach the memory capacitor, thereby enabling data reading and writing.

[0150] The embodiments of this application provide the following examples:

[0151] In memory products such as DRAM, word lines are used to provide gate control signals that control the conduction of transistors. When a transistor is turned on, current flows from the bit line through the transistor to the storage capacitor.

[0152] like Figure 7 As shown, from a device structure perspective, the top of the conductive layer of the buried word line (BWL) should ideally be flush with the bottom of the contact structure. This contact structure includes the bit line contact structure (BLC) and the memory node contact structure (NC). However, in actual manufacturing, perfect alignment is not achievable. There is an overlap between the contact structure, the ion implantation region N+, and the word line (BWL), leading to problems such as leakage and increased parasitic capacitance.

[0153] In this embodiment, an oxide dielectric layer with a gradually varying thickness is formed through the following steps: the oxide dielectric layer near the bottom of the trench is thinner, thus providing good switching characteristics and low parasitic capacitance at the bottom of the conductive layer; while the oxide dielectric layer near the top of the trench is thicker, which reduces the electric field between the conductive layer and the contact structure and the ion implantation region, thereby reducing the occurrence of leakage defects such as GIDL.

[0154] Figure 8A This is a schematic cross-sectional view of each step along the extension direction of trench 220 and located at the center of the trench.

[0155] like Figure 8A As shown, after forming an active region 240 and an isolation structure 250 with spaced arrangement on the substrate, a trench 220 perpendicular to the distribution direction of the active region can be formed.

[0156] Before forming the trench, a mask layer 260 can be applied to the substrate surface, and then the trench 220 can be formed by etching. After the trench is formed, the mask layer 260 can be removed. Alternatively, the mask layer 260 can be removed after the gate structure is formed within the trench. Since the active region 240 is made of silicon and the isolation structure 250 is made of silicon dioxide, both silicon dioxide and silicon need to be etched downwards simultaneously during the trench etching process to form a trench 220 of a certain depth, which is the depth required for burying the word line.

[0157] After forming trench 220, boron-doped amorphous carbon (BACL) can be deposited within trench 220 to form a sacrificial dielectric layer 221, filling trench 220. At this point, a cross-sectional view perpendicular to the trench extension direction is shown in the diagram. Figure 8B As shown.

[0158] Figure 9A This is a schematic cross-sectional view of each step located at the center of the trench, extending along the trench 220. For example... Figure 9A As shown, after the sacrificial dielectric layer 221 is formed, water vapor can be generated by ionization of oxygen (O2) and hydrogen (H2). The BACL is then gradually removed from top to bottom via plasma sputtering. Simultaneously, oxygen ions in the plasma react with the silicon elements on the gradually exposed trench sidewalls to form a silicon dioxide film. This creates a silicon dioxide film with a gradually thinning thickness from top to bottom on the trench sidewalls, serving as the oxide dielectric layer 231. The remaining space within the trench forms a trapezoidal structure. Furthermore, the rate of BACL consumption can be controlled by adjusting the gas flow rate, thereby controlling the thickness of the silicon dioxide film.

[0159] like Figure 9AAs shown, since the height of the gate structure is less than the depth of the trench, the height of the sidewalls of the trench 220 covered by the oxide dielectric layer 231 needs to be reduced after the oxide dielectric layer 231 is formed. Here, photoresist material (PR) 222 can be deposited in the trench first, and the thickness of the deposited material is the required height of the gate structure 230. At this time, a cross-sectional schematic diagram along the direction perpendicular to the trench extension is shown in the figure. Figure 9B As shown.

[0160] Next, as Figure 9C As shown, the silicon oxide film above the photoresist material 222 can be cleaned off, and then the photoresist material 222 can be removed. The remaining silicon oxide film then serves as the oxide dielectric layer 231 of the gate structure. Titanium nitride or tungsten metal is then deposited as the conductive layer 232, and finally, an insulating layer 233 is deposited to cover the conductive layer 232. A schematic diagram of the cross-sections of each step in the above process corresponding to a three-dimensional view is shown below. Figure 9D As shown. This results in a larger opening in the remaining trench, effectively filling the metal material and etching to the required word line height, reducing the premature sealing effect. Finally, silicon nitride material is deposited in the remaining trench 220 using LPCVD, or a silicon nitride film is formed by reacting silane (SiH4) and dichlorosilane (SiH2Cl2) as an insulating layer 233 covering the gate structure 230, forming a buried word line. A cross-sectional schematic diagram along the direction perpendicular to the trench extension is shown below. Figure 10 As shown.

[0161] It should be noted that, in the embodiments of this application, the etching gas for silicon, silicon oxide and silicon nitride can be one or more of the following gases in a certain proportion: sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), chlorine (Cl2), trifluoromethane (CHF3), oxygen (O2) and argon (Ar).

[0162] The technical solution of this application embodiment can form a gate structure in which the conductive layer gradually becomes thinner from top to bottom. This structure can effectively reduce the leakage of GIDL.

[0163] In addition, etching away part of the silicon oxide film on the word line results in a larger opening during the formation of the gate structure, which can reduce the premature sealing effect.

[0164] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0165] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0166] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Trenches are formed on the substrate; A sacrificial medium layer is filled into the trench; The sacrificial dielectric layer is gradually etched to gradually expose the sidewalls of the trench. The exposed sidewalls of the trench are at least partially oxidized to form an oxide dielectric layer. The thickness of the oxide dielectric layer in the trench increases sequentially in the direction extending from the bottom of the trench to the opening of the trench. A conductive layer is formed on the surface of the oxide dielectric layer, and the conductive layer is formed within the trench; The stepwise etching of the sacrificial dielectric layer to gradually expose the sidewalls of the trench, wherein the exposed sidewalls of the trench are oxidized to form an oxide dielectric layer, includes: The sacrificial dielectric layer is etched using oxygen-containing plasma, and the sacrificial dielectric layer is gradually etched by controlling the flow rate of the oxygen-containing plasma; the sidewalls of the trench are oxidized by oxygen-containing plasma to generate the oxide dielectric layer.

2. The method according to claim 1, characterized in that, The method further includes: Active regions arranged at intervals and isolation structures filled between the active regions are formed on the substrate, and trenches are formed in the active regions and the isolation structures.

3. The method according to claim 2, characterized in that, The oxide dielectric layer is formed on the sidewall of the trench in the active region.

4. The method according to claim 1, characterized in that, The sacrificial dielectric layer includes an undoped amorphous carbon layer or a doped amorphous carbon layer.

5. The method according to claim 1, characterized in that, The oxygen-containing plasma includes water vapor plasma.

6. The method according to claim 1, characterized in that, The method further includes: The oxide dielectric layer and the conductive layer are etched back to the target depth to form the target structure.

7. The method according to claim 1, characterized in that, The step of forming a conductive layer on the surface of the oxide dielectric layer, wherein the conductive layer is formed within the trench, includes: After forming the oxide dielectric layer, photoresist material is filled into the trench, with the top surface of the photoresist material being lower than the surface of the substrate. Remove the oxide dielectric layer exposed by the photoresist material; Remove the photoresist material; A conductive layer is deposited within the trench.

8. The method according to claim 2, characterized in that, The step of forming a conductive layer on the surface of the oxide dielectric layer, wherein the conductive layer is formed within the trench, includes: After forming the oxide dielectric layer, photoresist material is filled into the trench, with the top surface of the photoresist material being lower than the surface of the substrate. Remove the oxide dielectric layer and part of the isolation structure above the photoresist material; Remove the photoresist material; A conductive layer is deposited within the trench.

9. The method according to claim 7 or 8, characterized in that, The deposition of a conductive layer in the trench includes: A conductive material is deposited within the trench, and the conductive material is controlled to a target height to form the conductive layer, wherein the target height of the conductive layer is less than the height of the trench.

10. The method according to claim 9, characterized in that, The target height of the conductive layer is not less than the height of the oxide dielectric layer.

11. The method according to claim 1, characterized in that, The method further includes: An insulating layer is covered on the conductive layer and the oxide dielectric layer, and the insulating layer is located within the trench.

12. The method according to claim 11, characterized in that, The method of covering the conductive layer and the oxide dielectric layer with an insulating layer includes: An insulating material is deposited within the trench using a low-pressure chemical vapor deposition method to form an insulating layer covering the conductive layer and the oxide dielectric layer.

13. A semiconductor structure, said semiconductor structure being formed using the manufacturing method of a semiconductor structure as described in any one of claims 1-12, characterized in that, include: A substrate; wherein the substrate has trenches; and a gate structure is formed within the trenches; The gate structure includes an oxide dielectric layer and a conductive layer. The oxide dielectric layer covers the sidewalls of the trench, and the conductive layer is located inside the trench covered by the oxide dielectric layer. The thickness of the oxide dielectric layer inside the trench increases sequentially from the bottom of the trench to the opening of the trench.

14. The semiconductor structure according to claim 13, characterized in that, The semiconductor structure also includes: Active regions are spaced apart on the substrate and isolation structures are filled between the active regions, with trenches located in the active regions and the isolation structures.

15. The semiconductor structure according to claim 14, characterized in that, The oxide dielectric layer is formed in the trench located in the active region.

16. The semiconductor structure according to claim 13, characterized in that, The top surfaces of the conductive layer and the oxide dielectric layer are lower than the surface of the substrate; The semiconductor structure also includes: An insulating layer, located within the trench, covers the conductive layer and the oxide dielectric layer; wherein the insulating layer serves to protect the gate structure.

17. The semiconductor structure according to claim 13, characterized in that, The trench extends through multiple spaced active regions and isolation structures; the gate structure is connected within the trench, and in a direction parallel to the active regions, the surface width of the gate structure located in the isolation structure is greater than the surface width of the gate structure located in the active regions.

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