Semiconductor device, method for manufacturing semiconductor device, and electronic device

Abstract

The application provides a semiconductor device, a preparation method of the semiconductor device and an electronic device, and relates to the technical field of semiconductors.The semiconductor device comprises a high-voltage depletion mode silicon carbide junction field effect transistor, the high-voltage depletion mode silicon carbide junction field effect transistor comprising a first gate, a first drain, a first source, a first gate region, a gate extension region and a first source region, the gate extension region extending in a direction away from the first source region, the first gate being connected with the first gate region and the gate extension region, and the first source being connected with the first source region; a low-voltage enhancement mode gallium nitride high electron mobility transistor, the low-voltage enhancement mode gallium nitride high electron mobility transistor comprising a second gate, a second drain and a second source; wherein the first gate is connected with the second source, and the first source is connected with the second drain, the source of the semiconductor device being the second source, the gate of the semiconductor device being the second gate, and the drain of the semiconductor device being the first drain.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device, a preparation method of the semiconductor device and an electronic equipment. BACKGROUND

[0002] Silicon carbide (SiC) power semiconductor can work in the scene of high switching frequency, has the advantages of low power consumption, long service life, high frequency, small volume, light weight and the like, and has strong development potential in rail transit, communication and photovoltaic fields.

[0003] Several SiC power devices have been commercialized, for example, junction field-effect transistor (JFET), metal-oxide-semiconductor field-effect transistor (MOSFET) and the like. Compared with SiC MOSFET, SiC JFET has higher channel mobility and lower manufacturing process requirements, and SiC JFET does not contain the preparation of gate oxide. However, the normal working reliability of SiC JFET is low, and the safety risk is great.

[0004] At present, the normally-off operation of SiC JFET can be realized by cascode configuration, in which a low-voltage Si MOSFET is connected between the gate of a high-voltage SiC JFET and the power supply, but the relatively slow switching speed and limited operating temperature of Si MOSFET device hinder the functional implementation of SiC JFET, and in the cascode type semiconductor device, the current distribution is uneven, and the device failure caused by high temperature is prone to occur. SUMMARY

[0005] The present application provides a semiconductor device, a preparation method of the semiconductor device and an electronic equipment, which can effectively prevent the occurrence of device failure caused by high temperature, and improve the reliability of the semiconductor device.

[0006] The present application provides a semiconductor device, comprising:

[0007] The high-voltage depletion mode silicon carbide junction field-effect transistor comprises a first gate, a first drain, a first source, a first gate region, a gate extension region and a first source region, the gate extension region extends in a direction away from the first source region, the first gate is connected with the first gate region and the gate extension region, and the first source is connected with the first source region.

[0008] The low-voltage enhancement-mode gallium nitride high electron mobility transistor comprises a second gate, a second drain and a second source.

[0009] The first gate is connected with the second source, and the first source is connected with the second drain.

[0010] The semiconductor device provided by the application comprises a first forward blocking mode, in which the low-voltage enhancement-mode gallium nitride high electron mobility transistor is turned off, the high-voltage depletion-mode silicon carbide junction field effect transistor is turned on, and the drain-source voltage of the semiconductor device is the voltage borne by the low-voltage enhancement-mode gallium nitride high electron mobility transistor.

[0011] The semiconductor device provided by the application comprises a second forward blocking mode, in which the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor are both turned off, and the drain-source voltage of the semiconductor device is the voltage borne by the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor.

[0012] The semiconductor device provided by the application comprises a first forward blocking mode, in which the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor are both turned on.

[0013] The semiconductor device provided by the application further comprises a first metal connection structure and a second metal connection structure, the first gate is connected with the second source through the first metal connection structure, and the first source is connected with the second drain through the second metal connection structure.

[0014] The application further provides a preparation method of the semiconductor device, which comprises the following steps:

[0015] A p-type gate contact region and an n-type drift region are formed in a first region of the SiC substrate through photolithography and ion implantation, and a gate extension region is obtained by extending towards a direction away from the n-type drift region;

[0016] A GaN layer, an AlGaN layer and a P-GaN layer are sequentially grown in a second region of the SiC substrate.

[0017] etching in the first region and the second region to form a high-voltage depletion mode silicon carbide junction field effect transistor and a low-voltage enhancement mode gallium nitride high electron mobility transistor, respectively;

[0018] connecting the first gate of the high-voltage depletion mode silicon carbide junction field effect transistor and the second source of the low-voltage enhancement mode gallium nitride high electron mobility transistor, and connecting the first source of the high-voltage depletion mode silicon carbide junction field effect transistor and the second drain of the low-voltage enhancement mode gallium nitride high electron mobility transistor to obtain a semiconductor device.

[0019] According to the semiconductor device preparation method provided by the application, the etching in the first region and the second region to form a high-voltage depletion mode silicon carbide junction field effect transistor and a low-voltage enhancement mode gallium nitride high electron mobility transistor, respectively, comprises:

[0020] etching a first source connection region, a first gate connection region and a first drain connection region in the first region to obtain the high-voltage depletion mode silicon carbide junction field effect transistor;

[0021] etching a second source connection region and a second gate connection region in the second region to obtain the low-voltage enhancement mode gallium nitride high electron mobility transistor;

[0022] The first source connection region is used for forming the first source, the first gate connection region is used for forming the first gate, the first drain connection region is used for forming the first drain, the second source connection region is used for forming the second source, and the second gate connection region is used for forming the second gate.

[0023] According to the semiconductor device preparation method provided by the application, the connecting the first gate of the high-voltage depletion mode silicon carbide junction field effect transistor and the second source of the low-voltage enhancement mode gallium nitride high electron mobility transistor, and connecting the first source of the high-voltage depletion mode silicon carbide junction field effect transistor and the second drain of the low-voltage enhancement mode gallium nitride high electron mobility transistor, comprises:

[0024] forming a first metal connection structure and a second metal connection structure by metal deposition, the first gate and the second source are connected through the first metal connection structure, and the first source and the second drain are connected through the second metal connection structure.

[0025] According to the semiconductor device preparation method provided by the application, the forming a first metal connection structure by metal deposition, comprises:

[0026] The first metal segment and the second metal segment are formed by metal deposition, one end of the first metal segment is connected with the second source, the other end of the first metal segment is connected with the second metal segment, the middle part of the second metal segment is in contact with the gate extension area, and the two ends of the second metal segment extend to form extension segments towards the p-type gate contact area, and the extension segments are in contact with the p-type gate contact area.

[0027] The application further provides an electronic device comprising the semiconductor device according to any one of the above.

[0028] The semiconductor device, the preparation method of the semiconductor device and the electronic device provided by the application integrate the high-voltage depletion type silicon carbide junction field effect transistor and the low-voltage enhancement type gallium nitride high electron mobility transistor in one device through structural design, obtain the semiconductor device with the common source and common gate structure, make the current distribution more uniform through the gate extension area, and introduce the high temperature generated by the large current into the first source area, so that the device failure caused by the excessively high temperature can be effectively prevented. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0030] Figure 1 is a top view of the semiconductor device provided by the application;

[0031] Figure 2 is a circuit structure schematic diagram of the semiconductor device provided by the application;

[0032] Figure 3 is one of the three-dimensional structure schematic diagrams of the semiconductor device provided by the application;

[0033] Figure 4 is the second three-dimensional structure schematic diagram of the semiconductor device provided by the application;

[0034] Figure 5 is the third three-dimensional structure schematic diagram of the semiconductor device provided by the application;

[0035] Figure 6 is the fourth three-dimensional structure schematic diagram of the semiconductor device provided by the application;

[0036] Figure 7 is a flowchart of the preparation method of the semiconductor device provided by the application. DETAILED DESCRIPTION

[0037] In order to make the objects, technical solutions and advantages of the present application clearer, the following will clearly and completely describe the technical solutions in the present application with reference to the drawings in the present application. Obviously, the described embodiments are only a part of embodiments of the present application, but not all embodiments of the present application. Based upon the embodiments in the present application, all other embodiments obtained by those ordinarily skilled in the art without creative efforts should fall into the scope of the present application.

[0038] In the description of the embodiments of the present application, it should be noted that the terms "center", "longitudinal", "transverse", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the embodiments of the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0039] In the description of the embodiments of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "connected", "connected" should be understood broadly, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be mechanically connected, can be electrically connected; can be directly connected, or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0040] In the embodiments of the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature, which can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature "above", "over" and "on" the second feature can be that the first feature is directly above or obliquely above the second feature, or only means that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "under" and "under" the second feature can be that the first feature is directly below or obliquely below the second feature, or only means that the horizontal height of the first feature is less than that of the second feature.

[0041] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0042] The following will be described in combination with Figures 1 to 6 The semiconductor device of the embodiments of the present application is described.

[0043] The high electron mobility transistor (HEMT) is a heterojunction field effect transistor with high mobility.

[0044] The semiconductor device provided by the embodiments of the present application includes a high-voltage depletion mode silicon carbide junction field effect transistor (D-mode SiC JFET) and a low-voltage enhancement mode gallium nitride high electron mobility transistor (E-mode GaN HEMT).

[0045] The high-voltage depletion mode silicon carbide junction field effect transistor includes a first gate, a first drain and a first source.

[0046] The high-voltage depletion mode silicon carbide junction field effect transistor includes a first gate region, a gate extension region and a first source region, the gate extension region extends in a direction away from the first source region, the first gate is connected with the first gate region and the gate extension region, and the first source is connected with the first source region. As Figure 1 shown, G JFET , D JFET and S JFET correspond to the first gate, the first drain and the first source of the high-voltage depletion mode silicon carbide junction field effect transistor, respectively.

[0047] The high-voltage depletion mode silicon carbide junction field effect transistor includes a region of P-SiC (p-type doped) and a region of N-SiC (n-type doped).

[0048] The P-SiC connected at both ends of G JFET corresponds to the first gate region, the P-SiC in the middle corresponds to the gate extension region, and the region of N-SiC includes the first source region, Figure 1 as shown near S JFET region.

[0049] In this embodiment, by setting the gate extension region, the gate region is epitaxial, the current distribution in the device is more uniform, and the epitaxial gate extension region can introduce high temperature generated by high current in the device into the N-SiC region, effectively preventing the device from failing due to excessive temperature.

[0050] The low-voltage enhancement-mode gallium nitride high electron mobility transistor includes a second gate, a second drain and a second source.

[0051] In this embodiment, the first gate of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor are connected, and the source of the semiconductor device integrated with the high-voltage depletion-mode silicon carbide junction field effect transistor and the low-voltage enhancement-mode gallium nitride high electron mobility transistor is the second source.

[0052] The first source of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second drain of the low-voltage enhancement-mode gallium nitride high electron mobility transistor are connected.

[0053] The gate of the semiconductor device integrated with the high-voltage depletion-mode silicon carbide junction field effect transistor and the low-voltage enhancement-mode gallium nitride high electron mobility transistor is the second gate, and the drain is the first drain. For example, as shown in Figure 2 , e-GaN represents the low-voltage enhancement-mode gallium nitride high electron mobility transistor side, and SiC JFET represents the high-voltage depletion-mode silicon carbide junction field effect transistor side.

[0054] G JFET , D JFET and S JFET correspond to the first gate, the first drain and the first source of the high-voltage depletion-mode silicon carbide junction field effect transistor, respectively.

[0055] G GaN , D GaN and S GaN correspond to the second gate, the second drain and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, respectively.

[0056] The first gate G JFET and the second source S GaN are connected, the first source S JFET and the second drain D GaN are connected, the source of the semiconductor device is the second source S GaN , the gate of the semiconductor device is the second gate G GaN , the drain of the semiconductor device is the first drain D JFET , and the semiconductor device forms a common-source common-gate structure (i.e. Cascode type).

[0057] According to the semiconductor device provided by the embodiment of the present application, the high-voltage depletion-mode silicon carbide junction field effect transistor and the low-voltage enhancement-mode gallium nitride high electron mobility transistor are integrated in one device through structural design, a semiconductor device with a common source and common gate structure is obtained, the current distribution is more uniform through the gate extension region, the high temperature generated by large current is introduced into the first source region, the device failure caused by excessively high temperature can be effectively prevented, and the reliability of the semiconductor device in operation can be effectively improved.

[0058] The working mode of the semiconductor device with the common source and common gate structure integrating the high-voltage depletion-mode silicon carbide junction field effect transistor and the low-voltage enhancement-mode gallium nitride high electron mobility transistor will be introduced below.

[0059] The working mode of the semiconductor device can include a first forward blocking mode, a second forward blocking mode and a first forward conduction mode.

[0060] In some embodiments, in the first forward blocking mode of the semiconductor device, the low-voltage enhancement-mode gallium nitride high electron mobility transistor is turned off, the high-voltage depletion-mode silicon carbide junction field effect transistor is turned on, and the drain-source voltage of the semiconductor device is the voltage borne by the low-voltage enhancement-mode gallium nitride high electron mobility transistor.

[0061] In this embodiment, the low-voltage enhancement-mode gallium nitride high electron mobility transistor is turned off, the high-voltage depletion-mode silicon carbide junction field effect transistor is turned on, the voltage Vds between the drain and the source of the semiconductor device (i.e. the drain-source voltage) satisfies 0 < Vds < -VTH_JFET, and the voltage Vgs between the gate and the source of the semiconductor device is 0.

[0062] VTH_JFET is the opening voltage threshold of the high-voltage depletion-mode silicon carbide junction field effect transistor.

[0063] The low-voltage enhancement-mode gallium nitride high electron mobility transistor as a switch is in the off state, the driving voltage Vgs corresponds to 0, the low-voltage enhancement-mode gallium nitride high electron mobility transistor as a switch has no current, and therefore the semiconductor device current Id = 0.

[0064] The high-voltage depletion-mode silicon carbide junction field effect transistor is in the on state, -Vgs_JFET = -Vds_GaN < Vds < -VTH_GaN.

[0065] Vgs_JFET is the voltage between the first gate and the first source of the high-voltage depletion-mode silicon carbide junction field effect transistor, Vds_GaN is the voltage between the second drain and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, and VTH_GaN is the opening voltage threshold of the low-voltage enhancement-mode gallium nitride high electron mobility transistor.

[0066] The voltage Vds between the drain and the source of the semiconductor device is the voltage that the low-voltage enhancement-mode gallium nitride high electron mobility transistor bears, that is, Vds_GaN is equal to Vds.

[0067] In some embodiments, in the second forward blocking mode of the semiconductor device, the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor are both turned off, and the drain-source voltage of the semiconductor device is the voltage that the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor bear.

[0068] In this embodiment, the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor are both turned off, the voltage Vds between the drain and the source of the semiconductor device satisfies -VTH_JFET < Vds, and the voltage Vgs between the gate and the source of the semiconductor device is 0.

[0069] VTH_JFET is the turn-on voltage threshold of the high-voltage depletion-mode silicon carbide junction field effect transistor.

[0070] The voltage Vds between the drain and the source of the semiconductor device is continuously rising, and remains -VTH_JFET < Vds, and the high-voltage depletion-mode silicon carbide junction field effect transistor is in the off state, and its drive voltage is lower than the threshold voltage.

[0071] The voltage Vds between the drain and the source of the semiconductor device is borne by the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor.

[0072] In some embodiments, in the first forward conduction mode of the semiconductor device, the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor are both turned on.

[0073] In this embodiment, the drive voltage of the semiconductor device, that is, the voltage Vgs between the gate and the source of the semiconductor device, is higher than the turn-on voltage threshold VTH_GaN of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, and the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor can both be turned on.

[0074] In some embodiments, the semiconductor device can further include a first metal connection structure and a second metal connection structure.

[0075] The first gate and the second source are connected through the first metal connection structure, and the first source and the second drain are connected through the second metal connection structure.

[0076] In this embodiment, when connecting the first gate of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, the first metal connection structure is arranged to realize the connection.

[0077] In this embodiment, when connecting the first gate of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, the first metal connection structure is arranged to realize the connection.

[0078] In actual implementation, the first metal connection structure and the second metal connection structure can be deposited by metal deposition at the corresponding positions between the high-voltage depletion-mode silicon carbide junction field effect transistor and the low-voltage enhancement-mode gallium nitride high electron mobility transistor.

[0079] It should be noted that no metal can be deposited between the first gate and the first source of the high-voltage depletion-mode silicon carbide junction field effect transistor to avoid short circuit.

[0080] It can be understood that in the structural design of the semiconductor device, the length, width, height and doping concentration of the device can be controlled to improve the performance of the semiconductor device.

[0081] The embodiment of the present application also provides a preparation method of a semiconductor device, which can be used to prepare the semiconductor device.

[0082] As shown in Figure 7 The preparation method of the semiconductor device provided by the embodiment of the present application comprises:

[0083] In step 710, a p-type gate contact region and an n-type drift region are formed in the first region of the SiC substrate by photoetching and ion implantation, and a gate extension region is obtained by extending in a direction away from the n-type drift region.

[0084] As shown in Figure 3 The p-type gate contact region (the region of P-SiC) and the n-type drift region (the region of N-SiC) are formed by ion implantation in the first region of the SiC substrate, wherein one end of the n-type drift region is a first source region for forming a first source, and the other end is a first drain region for forming a first drain.

[0085] In this step, the gate extension region is formed by ion implantation above the n-type drift region and away from the n-type drift region.

[0086] The p-type gate contact region and the n-type drift region are located in the same plane of the SiC substrate, and the gate extension region extends upward relative to the plane where the p-type gate contact region and the n-type drift region are located.

[0087] In this embodiment, by setting a gate extension region, the gate region is epitaxial, and the current distribution within the device is more uniform. The epitaxial gate extension region can introduce the high temperature generated by the large current within the device into the n-type drift region, effectively preventing the device from failing due to excessive temperature.

[0088] Step 720: In the second region of the SiC substrate, GaN layer, AlGaN layer and P-GaN layer are grown sequentially.

[0089] like Figure 4 As shown, GaN, AlGaN, and P-GaN layers are grown sequentially from the SiC substrate upwards. The AlGaN layer serves as a barrier layer, and the GaN layer serves as a buffer layer. There is a certain lattice mismatch between the GaN and AlGaN layers. The magnitude of the lattice mismatch is related to the Al composition. The device reliability can be improved by adjusting the Al composition to reduce the stress in the barrier layer.

[0090] In this step, GaN, AlGaN, and P-GaN layers are grown in a second region of the SiC substrate for subsequent etching to obtain a low-voltage enhancement-mode gallium nitride high electron mobility transistor.

[0091] Step 730: Etching is performed in the first region and the second region to form a high-voltage depletion-type silicon carbide junction field-effect transistor and a low-voltage enhancement-type gallium nitride high electron mobility transistor, respectively.

[0092] Etching is performed in the first and second regions to form trench structures through dry etching. High-voltage depletion-type silicon carbide junction field-effect transistors are etched in the first region, and low-voltage enhancement-type gallium nitride high electron mobility transistors are etched in the second region.

[0093] In actual implementation, such as Figure 4 As shown, during etching in the first and second regions, the connection regions of the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field-effect transistor are etched to facilitate subsequent connection.

[0094] Step 740: Connect the first gate of the high-voltage depletion-type silicon carbide junction field-effect transistor and the second source of the low-voltage enhancement-type gallium nitride high electron mobility transistor, and connect the first source of the high-voltage depletion-type silicon carbide junction field-effect transistor and the second drain of the low-voltage enhancement-type gallium nitride high electron mobility transistor to obtain a semiconductor device.

[0095] like Figure 1 As shown, a first source (i.e., S) is formed at the point where the first region connects to the second region. JFET A first drain (i.e., D) is formed at the end of the first region furthest from the second region. JFET A first gate (i.e., G) is formed in the p-type gate contact region and the gate extension region.JFET )。

[0096] In this embodiment, part of the second region is etched to obtain a low-voltage enhancement-mode gallium nitride high electron mobility transistor including a second gate (i.e., G GaN ), a second drain and a second source (i.e., S GaN ).

[0097] As shown in Figure 6 , the first gate G JFET is connected with the second source S GaN , the first source S JFET is connected with the second drain D GaN , the source of the semiconductor device (corresponding to S shown in Figure 6 ) is the second source S GaN , the gate of the semiconductor device (corresponding to G shown in Figure 6 ) is the second gate G GaN , and the drain of the semiconductor device (corresponding to D shown in Figure 6 ) is the first drain D JFET , thereby forming a semiconductor device in a cascode structure (i.e., Cascode type).

[0098] According to the method for manufacturing the semiconductor device provided by the embodiment of the present application, by means of structural design, a high-voltage depletion-mode silicon carbide junction field effect transistor and a low-voltage enhancement-mode gallium nitride high electron mobility transistor are integrated in one device, thereby obtaining a semiconductor device in a cascode structure. By means of the gate extension region, the current distribution is more uniform, and the high temperature generated by large current is introduced into the first source region, thereby effectively preventing the device from failing due to excessively high temperature.

[0099] In some embodiments, the step 730 of etching in the first region and the second region to form the high-voltage depletion-mode silicon carbide junction field effect transistor and the low-voltage enhancement-mode gallium nitride high electron mobility transistor, respectively, can include:

[0100] etching the first source connection region, the first gate connection region and the first drain connection region in the first region to obtain the high-voltage depletion-mode silicon carbide junction field effect transistor;

[0101] etching the second source connection region and the second gate connection region in the second region to obtain the low-voltage enhancement-mode gallium nitride high electron mobility transistor;

[0102] wherein the first source connection region is used for forming the first source, the first gate connection region is used for forming the first gate, the first drain connection region is used for forming the first drain, the second source connection region is used for forming the second source, and the second gate connection region is used for forming the second gate.

[0103] As shown in Figure 5As shown, etching is performed in the first region to etch both ends of the n-type drift region to obtain a first source connection region and a first drain connection region, respectively; and to etch the p-type gate contact region and the gate extension region to obtain a first gate connection region.

[0104] Etching is performed in the second region to etch the GaN layer, the AlGaN layer, the P-GaN layer, and the SiC substrate below the GaN layer, to form a second gate connection region in the P-GaN layer and a second source connection region in the GaN layer and the AlGaN layer.

[0105] In some embodiments, the step 740 of connecting the first gate of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, and connecting the first source of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second drain of the low-voltage enhancement-mode gallium nitride high electron mobility transistor can include:

[0106] The first metal connection structure and the second metal connection structure are formed by metal deposition, the first gate and the second source are connected by the first metal connection structure, and the first source and the second drain are connected by the second metal connection structure.

[0107] In this embodiment, the first metal connection structure is deposited between the first gate of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor to connect the first gate and the second source.

[0108] The second metal connection structure is deposited between the first source of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second drain of the low-voltage enhancement-mode gallium nitride high electron mobility transistor to connect the first source and the second drain.

[0109] It should be noted that no metal can be deposited between the first gate and the first source of the high-voltage depletion-mode silicon carbide junction field effect transistor to avoid short circuit.

[0110] In some embodiments, the step of forming the first metal connection structure by metal deposition can include:

[0111] The first metal segment and the second metal segment are formed by metal deposition, one end of the first metal segment is connected to the second source, the other end of the first metal segment is connected to the second metal segment, the middle of the second metal segment is in contact with the gate extension region, and both ends of the second metal segment extend towards the p-type gate contact region to form an extension segment, which is in contact with the p-type gate contact region.

[0112] In this embodiment, the first metal connection structure formed by metal deposition includes the first metal segment and the second metal segment.

[0113] As Figure 6As shown, the first metal segment can be a metal segment along the length direction of the semiconductor device, i.e. Figure 1 As shown, connect S GaN and G JFET The metal segment.

[0114] like Figure 6 As shown, the second metal segment can be a metal segment along the width direction of the semiconductor device, i.e. Figure 1 G shown JFET The metal segment.

[0115] In this embodiment, the two ends of the second metal segment extend toward the p-type gate contact region to form an extension segment, the extension segment contacts the p-type gate contact region, the middle part of the second metal segment contacts the gate extension region, and the p-type gate contact region and the gate extension region together form the first gate.

[0116] The extended gate region makes the current distribution within the device more uniform and can introduce the high temperature generated by the large current within the device into the N-SiC region, effectively preventing the device from failing due to excessive temperature.

[0117] This invention also provides an electronic device, including the semiconductor device described above.

[0118] The semiconductor devices in electronic equipment are common-source, common-gate devices consisting of high-voltage depletion-type silicon carbide junction field-effect transistors and low-voltage enhancement-type gallium nitride high electron mobility transistors. By extending the gate region, the current distribution becomes more uniform, and the high temperature generated by the large current is introduced into the first source region, which can effectively prevent the device from failing due to excessive temperature and can effectively improve the reliability of semiconductor device operation.

[0119] The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. The embodiments of the present invention do not make specific limitations.

[0120] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the same; although the present application has been described in detail with reference to the foregoing examples, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized by, Comprise: A high-voltage depletion-mode silicon carbide junction field effect transistor comprising a first gate, a first drain, a first source, a first gate region, a gate extension region extending towards a direction away from the first source region, the first gate connected to the first gate region and the gate extension region, and the first source connected to the first source region; A low-voltage enhancement-mode gallium nitride high electron mobility transistor comprising a second gate, a second drain, and a second source; Wherein the gate extension region introduces high temperature generated by large current within the device into the first source region to prevent the semiconductor device from failing due to excessively high temperature, the first gate is connected to the second source, the first source is connected to the second drain, the source of the semiconductor device is the second source, the gate of the semiconductor device is the second gate, and the drain of the semiconductor device is the first drain.

2. The semiconductor device according to claim 1, wherein The working mode of the semiconductor device comprises a first forward blocking mode, in which the low-voltage enhancement-mode gallium nitride high electron mobility transistor is turned off, the high-voltage depletion-mode silicon carbide junction field effect transistor is turned on, and the drain-source voltage of the semiconductor device is the voltage borne by the low-voltage enhancement-mode gallium nitride high electron mobility transistor.

3. The semiconductor device of claim 1, wherein The working mode of the semiconductor device comprises a second forward blocking mode, in which the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor are both turned off, and the drain-source voltage of the semiconductor device is the voltage borne by the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor.

4. The semiconductor device of claim 1, wherein The working mode of the semiconductor device comprises a first forward conduction mode, in which the low-voltage enhancement-mode gallium nitride high electron mobility transistor and the high-voltage depletion-mode silicon carbide junction field effect transistor are both turned on.

5. The semiconductor device according to any one of claims 1 to 4, wherein Further comprise: A first metal connection structure and a second metal connection structure, the first gate and the second source being connected through the first metal connection structure, and the first source and the second drain being connected through the second metal connection structure.

6. A method of manufacturing the semiconductor device according to any one of claims 1 to 5, characterized by, Comprise: Forming a p-type gate contact region and an n-type drift region in a first region of a SiC substrate through photolithography and ion implantation, and extending a gate extension region towards a direction away from the n-type drift region; Growth of a GaN layer, an AlGaN layer, and a P-GaN layer in a second region of the SiC substrate in sequence; Etching in the first region and the second region to form a high-voltage depletion-mode silicon carbide junction field effect transistor and a low-voltage enhancement-mode gallium nitride high electron mobility transistor, respectively; connecting the first gate of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, and connecting the first source of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second drain of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, to obtain the semiconductor device.

7. The method of producing a semiconductor device according to claim 6, wherein The etching in the first region and the second region to form the high-voltage depletion-mode silicon carbide junction field effect transistor and the low-voltage enhancement-mode gallium nitride high electron mobility transistor respectively comprises: etching a first source connection region, a first gate connection region and a first drain connection region in the first region to obtain the high-voltage depletion-mode silicon carbide junction field effect transistor; etching a second source connection region and a second gate connection region in the second region to obtain the low-voltage enhancement-mode gallium nitride high electron mobility transistor; The first source connection region is used for forming the first source, the first gate connection region is used for forming the first gate, the first drain connection region is used for forming the first drain, the second source connection region is used for forming the second source, and the second gate connection region is used for forming the second gate.

8. The method of producing a semiconductor device according to claim 6 or 7, wherein The connecting the first gate of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second source of the low-voltage enhancement-mode gallium nitride high electron mobility transistor, and connecting the first source of the high-voltage depletion-mode silicon carbide junction field effect transistor and the second drain of the low-voltage enhancement-mode gallium nitride high electron mobility transistor comprises: forming a first metal connection structure and a second metal connection structure by metal deposition, the first gate and the second source being connected by the first metal connection structure, and the first source and the second drain being connected by the second metal connection structure.

9. The method of producing a semiconductor device according to Claim 8, wherein The forming a first metal connection structure by metal deposition comprises: forming a first metal segment and a second metal segment by metal deposition, one end of the first metal segment being connected with the second source, the other end of the first metal segment being connected with the second metal segment, the middle part of the second metal segment being in contact with the gate extension region, and both ends of the second metal segment extending towards the p-type gate contact region to form an extension segment, the extension segment being in contact with the p-type gate contact region.

10. An electronic device, comprising: The semiconductor device comprises the semiconductor device according to any one of claims 1-5.

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