Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a trench in the substrate, a gate structure in the trench, a top surface of the gate structure being lower than a top surface of the trench, a first etching stop layer covering the top surface of the gate structure, part of a side wall of the trench and an upper surface of the substrate, a closed isolation structure between the first etching stop layer in the trench, the closed isolation structure at least blocking an opening of the trench, and an air gap between the first etching stop layer and the closed isolation structure, the air gap at least comprising a horizontal part, and a bottom of the closed isolation structure being on the horizontal part. The semiconductor structure can improve the performance of a semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor device manufacturing, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Dynamic random access memory (DRAM) is a kind of semiconductor memory widely used in electronic products such as mobile phones, computers and cars. The difficulty of DRAM process is related to the size, the smaller the size, the more difficult it is. In the future, the DRAM process technology will be around 10-15 nm, which has very strict requirements on the electrical properties of the product.

[0003] The traditional embedded gate is difficult to effectively isolate the active regions on both sides of the gate under the process of 10-15 nm, and there is also a coupling effect between the gate and other metal layers, which seriously affects the electrical performance of the semiconductor device. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor structure and a preparation method thereof in view of the above problems.

[0005] The present application discloses a semiconductor structure, comprising: a substrate comprising a trench, the trench comprising a gate structure, the top surface of the gate structure being lower than the top surface of the trench; a first etching stop layer covering the top surface of the gate structure, part of the sidewall of the trench and the upper surface of the substrate; a closed isolation structure between the first etching stop layer in the trench, the closed isolation structure at least blocking the opening of the trench; an air gap between the first etching stop layer and the closed isolation structure, the air gap comprising at least a horizontal part, and the bottom of the closed isolation structure being located on the horizontal part.

[0006] The above semiconductor structure sets an air gap in the trench where the embedded gate is located, and uses the characteristics of the smallest air dielectric constant and good isolation effect to better isolate the active regions on both sides of the gate, reducing the coupling effect between adjacent metal gates. And because the air gap has a horizontal part, the area of air isolation and the width of lateral isolation can be increased, the isolation effect is better, and the coupling effect is lower. The air gap of the horizontal part can also reduce the coupling effect between the gate and other metal materials (such as bit lines or metal layers), and improve the performance of the semiconductor device.

[0007] In one embodiment, the air gap further comprises at least one vertical part, the vertical part being located at the lower part of the closed isolation structure, and the vertical part being communicated with the horizontal part.

[0008] In one of the embodiments, the air gap further comprises a first vertical portion and a second vertical portion, the first vertical portion and the second vertical portion are located at opposite sides of the lower portion of the closed isolation structure respectively, and the bottom of the first vertical portion and the second vertical portion is communicated with the horizontal portion.

[0009] In one of the embodiments, the height of the first vertical portion is equal to or different from the height of the second vertical portion.

[0010] In one of the embodiments, the closed isolation structure comprises a second etching stop layer and a sealing isolation layer, the second etching stop layer is partially attached to the sidewall of the first etching stop layer, and the sealing isolation layer is located between the second etching stop layer and cooperates with the second etching stop layer to seal the opening of the trench.

[0011] In one of the embodiments, the width of the upper portion of the closed isolation structure is greater than the width of the lower portion, the upper portion of the second etching stop layer is attached to the sidewall of the first etching stop layer, and the lower portion of the second etching stop layer has a first spacing with the sidewall of the first etching stop layer.

[0012] In one of the embodiments, the gate structure comprises a gate oxide layer, a barrier layer and a main conductive layer which are sequentially stacked from outside to inside, the top surface of the barrier layer is lower than the top surface of the main conductive layer, and the top surface of the main conductive layer is lower than the top surface of the trench.

[0013] A method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising a trench; forming a gate structure in the trench, the top surface of the gate structure being lower than the top surface of the trench; forming a first etching stop layer, the first etching stop layer covering the top surface of the gate structure, part of the sidewall of the trench and the upper surface of the substrate; forming a closed isolation structure and an air gap in the trench, the closed isolation structure at least sealing the opening of the trench, and the air gap being located between the closed isolation structure and the first etching stop layer; wherein the air gap at least comprises a horizontal portion, and the bottom of the closed isolation structure is located on the horizontal portion.

[0014] In one of the embodiments, before forming the closed isolation structure, the method further comprises forming a sacrificial layer in the trench, and the step of forming the sacrificial layer comprises: forming a first sacrificial layer in the trench; forming a second sacrificial layer on the first sacrificial layer to fill the trench; etching the first sacrificial layer and the second sacrificial layer so that the top surface of the first sacrificial layer is lower than the top surface of the second sacrificial layer; wherein the etching rate of the first sacrificial layer is greater than the etching rate of the second sacrificial layer; and removing the second sacrificial layer to define the remaining first sacrificial layer as the sacrificial layer.

[0015] In one of the embodiments, the height of the sacrificial layer located on the sidewall of the trench is equal.

[0016] In one of the embodiments, after the second sacrificial layer is formed, the method further comprises: forming a photoresist layer on the second sacrificial layer, the photoresist layer only covers the first sacrificial layer on one side of the second sacrificial layer; etching the second sacrificial layer and the first sacrificial layer, and removing the photoresist layer, so that the height of the first sacrificial layer on both sides of the second sacrificial layer is not equal.

[0017] In one of the embodiments, the upper width of the enclosed isolation structure is greater than the lower width of the enclosed isolation structure.

[0018] In one of the embodiments, the step of forming the enclosed isolation structure comprises: forming a second etching stop layer in the trench, the second etching stop layer exposes part of the first etching stop layer; forming an enclosed isolation layer in the second etching stop layer, the bottom of the enclosed isolation layer is higher than or equal to the bottom of the second etching stop layer.

[0019] In one of the embodiments, before the enclosed isolation layer is formed, the method further comprises: removing the sacrificial layer by a wet process to form the air gap.

[0020] In one of the embodiments, the air gap comprises at least one vertical part, and the lateral part connects the vertical part, and the vertical part is between the first etching stop layer and the enclosed isolation layer.

[0021] In one of the embodiments, the air gap comprises a first vertical part and a second vertical part, the first vertical part and the second vertical part are communicated by the lateral part, and the height of the first vertical part and the height of the second vertical part are equal or not equal.

[0022] In one of the embodiments, the first vertical part and the second vertical part are respectively between the first etching stop layer and the enclosed isolation structure. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The flow chart of the method for preparing the semiconductor structure in one of the embodiments of the present application.

[0024] Figure 2 The cross-sectional structure schematic diagram of the substrate provided in one of the embodiments of the present application.

[0025] Figure 3 The cross-sectional structure schematic diagram of the semiconductor structure obtained after sequentially forming the initial etching stop layer, the mask layer and the patterned photoresist layer on the upper surface of the substrate in one of the embodiments of the present application.

[0026] Figure 4FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a trench in an embodiment of the present application. Figure 5 FIG. 2 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a gate oxide material layer in an embodiment of the present application.

[0027] Figure 6 FIG. 3 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a barrier material layer in an embodiment of the present application.

[0028] Figure 7 FIG. 4 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a main conductive material layer in an embodiment of the present application.

[0029] Figure 8 FIG. 5 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a gate structure in a trench in an embodiment of the present application.

[0030] Figure 9 FIG. 6 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a first etching barrier layer in an embodiment of the present application.

[0031] Figures 10-11 FIG. 7 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a second etching barrier material layer in an embodiment of the present application. Figure 12a 、 Figure 12b and Figure 12c FIG. 8 is a schematic diagram of a process of forming a sacrificial layer in an embodiment of the present application.

[0032] Figure 13 FIG. 9 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a second etching barrier layer in an embodiment of the present application.

[0033] Figure 14 FIG. 10 is a schematic diagram of a cross-sectional structure of a semiconductor structure after removing a sacrificial layer in an embodiment of the present application.

[0034] Figure 15 FIG. 11 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a closed isolation structure in an embodiment of the present application.

[0035] Figure 16 FIG. 12 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a closed isolation structure in another embodiment of the present application.

[0036] Figures 17-21 FIG. 13 is a schematic diagram of a process of forming a sacrificial layer in another embodiment of the present application.

[0037] Figure 22 FIG. 14 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a closed isolation structure in another embodiment of the present application.

[0038] Figure 23 FIG. 15 is a schematic diagram of a cross-sectional structure of a semiconductor structure after forming a closed isolation structure in another embodiment of the present application.

[0039] 100, substrate; 101, substrate; 102, isolation structure; 111, initial etching stop layer; 112, mask layer; 1121, Carbon layer; 1122, silicon oxynitride layer; 113, patterned photoresist layer; 114, trench; 115, gate oxide material layer; 116, barrier material layer; 117, main conductive material layer; 120, gate structure; 121, gate oxide layer; 122, barrier layer; 123, main conductive layer; 131, first etching stop layer; 134, first sacrificial layer; 135, second sacrificial layer; 136, sacrificial layer; 137, photoresist layer; 138, second etching stop material layer; 139, second etching stop layer; 140, closed isolation structure; 141, sealing isolation layer; 150, air gap; 151, first vertical portion; 152, second vertical portion; 153, horizontal portion. DETAILED DESCRIPTION

[0040] For the purposes of this disclosure the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. The terms "comprises", "comprising", "includes", "including", "has", "having", "contains", "containing", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, includes, has, contains a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "about" and "substantially" are used to describe the approximate or close value of a numerical parameter. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application. The terms "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] Unless otherwise defined, all terms used in disclosing embodiments of the application, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application. The terms "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] In describing a position relationship, unless otherwise defined, when an element such as a layer, film or substrate is referred to as being "on" another film layer, it can be directly on the other film layer or there can be an intervening film layer. Further, when a layer is referred to as being "under" another layer, it can be directly under the other layer or there can be one or more intervening layers. It can also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can be one or more intervening layers.

[0043] In the case of using "include", "have", and "contain" described herein, unless the explicit limiting term is used, such as "only", "consisting of", etc., another component can be added. Unless otherwise mentioned, the singular form of the term can include the plural form, and cannot be understood as the number of one.

[0044] As Figure 1As shown, one embodiment of the present application provides a method for preparing a semiconductor structure. The method comprises:

[0045] S10: providing a substrate comprising a trench, forming a gate structure in the trench, a top surface of the gate structure being lower than a top surface of the trench;

[0046] S20: forming a first etching stop layer covering the top surface of the gate structure, part of the sidewall of the trench and the upper surface of the substrate;

[0047] S30: forming an isolation structure and an air gap in the trench, the isolation structure at least plugging the opening of the trench, the air gap being between the isolation structure and the first etching stop layer; wherein the air gap at least comprises a lateral part, a bottom of the isolation structure being on the lateral part.

[0048] The above method for preparing a semiconductor structure forms an air gap in the trench where the buried gate is located, which takes advantage of the characteristics of air having the smallest dielectric constant and good isolation effect, better isolates the active regions on both sides of the gate, and reduces the coupling effect between adjacent metal gates. Moreover, since the air gap has a lateral part, the area of air isolation and the width of lateral isolation can be increased, the isolation effect between the gate structure and other metal lines (such as metal layers) is improved, and the coupling effect is lower.

[0049] In step S10, the provided substrate comprises a trench, wherein the number of trenches can be one or more. For example, the step of forming the substrate comprises:

[0050] S11: providing a substrate 101 comprising an active region, an isolation structure 102 being arranged around the active region, the substrate 101 and the isolation structure 102 together constituting a substrate 100, as shown in Figure 2 .

[0051] For example, the substrate 101 in the present embodiment comprises but is not limited to a silicon substrate 101. The isolation structure 102 around the active region comprises but is not limited to a shallow trench isolation trench.

[0052] S12: sequentially forming an initial etching stop layer 111, a mask layer 112 and a patterned photoresist layer 113 on the upper surface of the substrate 101, the patterned photoresist layer 113 having an opening pattern for defining the shape and position of a trench 114, as shown in Figure 3 .

[0053] By way of example, the initial etch stop layer 111 includes but is not limited to a silicon nitride layer; the mask layer 112 may be one or more layers of a SION layer, a Carbon layer (amorphous carbon layer), a SOC layer, SiO2, and a DARC layer (Dielectric Anti-Reflected Coating), and the thickness of the mask layer 112 is 50 nm to 200 nm, for example, 50 nm, 100 nm, 150 nm, 175 nm, or 200 nm. In this embodiment, the mask layer 112 includes a Carbon layer 1121 and a silicon oxynitride layer 1122 stacked sequentially from bottom to top. By way of example, the initial etch stop layer 111 and the mask layer 112 may be prepared using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

[0054] The patterned photoresist layer 113 is used to define the size, shape, and position of the grooves. The opening pattern in the patterned photoresist layer 113 can be directly determined by illumination, or the pattern can be first defined by illumination and then implemented by pitch doubling. The specific implementation method can be determined based on the width W1 of the buried gate. For example, the width W1 can range from 5 nm to 80 nm, such as 5 nm, 15 nm, 35 nm, 60 nm, or 80 nm.

[0055] S13: etching the mask layer 112 and the initial etching stop layer 111 based on the patterned photoresist layer 113;

[0056] S14: etching the substrate 101 based on the etched mask layer 112 and the initial etch barrier layer 111 to form a trench 114, such as Figure 4 shown.

[0057] For example, an opening pattern in the patterned photoresist layer 113 is defined by light, and the opening pattern exposes a portion of the upper surface of the mask layer 112. Then, the opening pattern is sequentially formed in the mask layer 112 and the initial etch stop layer 111. The substrate 101 is etched based on the opening pattern in the initial etch stop layer 111 to form a Figure 4 Grooves 114 are shown.

[0058] After forming the trench 114, a gate structure is formed in the trench 114. For example, the steps of forming the gate structure in the trench 114 include:

[0059] S15: forming a gate oxide material layer 115 on the substrate 100 and the sidewalls and bottom of the trench 114, such as Figure 5 shown.

[0060] S16: forming a barrier material layer 116, the barrier material layer 116 covers the gate oxide material layer 115, such as Figure 6 shown.

[0061] Optionally, the gate oxide material layer 115 includes, but is not limited to, an oxide layer, such as a silicon dioxide layer. The barrier material layer 116 includes, but is not limited to, a titanium nitride layer. The thickness of the gate oxide material layer 115 and the barrier material layer 116 is 1 nm to 10 nm, such as 1 nm, 5 nm, or 10 nm. The gate oxide material layer 115 is formed by a thermal oxidation process, and the barrier material layer 116 is formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. In some embodiments, the gate oxide material layer 115 can also be formed by an atomic layer deposition process, so that the gate oxide material layer 115 can also cover the initial etch stop layer 111.

[0062] S17: forming a main conductive material layer 117. The main conductive material layer 117 located in the trench 114, the gate oxide material layer 115 located in the trench 114 and the barrier material layer 116 located in the trench 114 together fill the trench 114. Figure 7 shown.

[0063] S18: removing the portion located in the trench 114 and the main conductive material layer 117, the barrier material layer 116 and the gate oxide material layer 115 located on the substrate 100 to form a gate structure 120, such as Figure 8 shown.

[0064] Optionally, the material forming the main conductive material layer 117 includes but is not limited to metal tungsten. After the main conductive material layer 117, the gate oxide material layer 115 and the barrier material layer 116 fill the trench 114, each material layer is etched back. First, the main conductive material layer 117, the barrier material layer 116 and the gate oxide material layer 115 on the substrate 100 are removed, and then the main conductive material layer 117, the barrier material layer 116 and the gate oxide material layer 115 in the trench 114 are partially etched to obtain a gate structure 120 composed of a main conductive layer 123, a barrier layer 122 and a gate oxide layer 121, as shown in FIG. Figure 8 As shown, the top surface of the gate oxide layer 121 is flush with the top surface of the trench 114, the top surface of the main conductive layer 123 is lower than the top surface of the trench 114, and the top surface of the barrier layer 122 is lower than the top surface of the main conductive layer 123. The gate oxide layer 121 can reduce stress between the first etch stop layer 131 and the substrate 101. By controlling the top surface of the barrier layer 122 to be lower than the top surface of the main conductive layer 123, leakage current in the gate structure can be improved, thereby enhancing the performance of the semiconductor device.

[0065] In step S20, a first etch stop layer 131 is formed. The first etch stop layer 131 covers the top surface of the gate structure 120, part of the sidewall of the trench 114 and the upper surface of the substrate 100. Figure 9As shown in FIG. 1C, after forming the trench 114, the initial etching stop layer 111 can be retained on the substrate 100 without being removed. In the following text, the upper surface of the substrate 100 can be understood as the upper surface of the semiconductor structure composed of the initial etching stop layer 111 and the substrate 100. For example, the first etching stop layer 131 includes but is not limited to a silicon nitride layer, and the thickness of the first etching stop layer 131 is 5-20 nm, for example, 5 nm, 10 nm, 15 nm or 20 nm. The first etching stop layer 131 can be used to protect the gate oxide layer 121 from being etched. At the same time, the first etching stop layer 131 can also prevent the sidewall of the trench 114 from being affected in the subsequent etching process, thereby preventing or reducing the occurrence of leakage.

[0066] In step S30, a closed isolation structure and an air gap are formed in the trench 114, the closed isolation structure at least blocks the opening of the trench 114, and the air gap is located between the closed isolation structure and the first etching stop layer 131; wherein the air gap at least includes a lateral part, and the bottom of the closed isolation structure is located on the lateral part.

[0067] In one embodiment, before forming the closed isolation layer, a step of forming a sacrificial layer in the trench 114 is further included, and the step of forming the sacrificial layer includes:

[0068] S311: forming a first sacrificial layer 134 in the trench 114, as shown in FIG. 1D. Figure 10

[0069] S312: forming a second sacrificial layer 135 on the first sacrificial layer 134 to fill the trench 114, as shown in FIG. 1E. Figure 11

[0070] Optionally, the first sacrificial layer 134 includes but is not limited to a silicon dioxide layer, and the thickness of the first sacrificial layer 134 can be 5-20 nm, for example, 5 nm, 10 nm, 15 nm or 20 nm. The second sacrificial layer 135 includes but is not limited to a spin-on carbon (SOC) layer.

[0071] S313: etching the first sacrificial layer 134 and the second sacrificial layer 135 so that the top surface of the first sacrificial layer 134 is lower than the top surface of the second sacrificial layer 135; wherein the etching rate of the first sacrificial layer 134 is greater than the etching rate of the second sacrificial layer 135.

[0072] For example, the second sacrificial layer 135 can be etched back first so that the upper surface of the second sacrificial layer 135 is flush with the upper surface of the first sacrificial layer 134, as shown in FIG. 1F. Figure 12a ​​The second sacrificial layer 135 (e.g., a SOC layer) has an etching selectivity to the first sacrificial layer 134 (e.g., a silicon dioxide layer) greater than 0 during the etching back of the second sacrificial layer 135. By controlling the etching selectivity of the SOC layer to the silicon dioxide layer to be greater than 0, the etching of the silicon dioxide layer can be reduced when etching back the SOC layer to obtain a desired semiconductor structure. In some embodiments, the upper surface of the second sacrificial layer 135 can be planarized with the upper surface of the first sacrificial layer 134 by a chemical mechanical polishing process.

[0073] Further, the first sacrificial layer 134 (e.g., a silicon dioxide layer) is etched using the second sacrificial layer 135 (e.g., a SOC layer) and the first etching stop layer 131 (e.g., a silicon nitride layer) as mask layers, so that the top surface of the first sacrificial layer 134 is lower than the top surface of the second sacrificial layer 135, as shown in Figure 12b The etching rate of the first sacrificial layer 134 is greater than the etching rate of the second sacrificial layer 135, for example, the etching selectivity of the silicon dioxide layer to the SOC layer can be 5-10, such as 5, 7, 9, or 10. For example, the etching selectivity of the silicon dioxide layer to the silicon nitride layer can be 5-20, such as 5, 10, 15, or 20. By controlling the etching selectivity of the silicon dioxide layer to the SOC layer to be less than the etching selectivity of the silicon dioxide layer to the silicon nitride layer, a portion of the SOC layer can be etched and removed appropriately while the silicon nitride layer is etched as little as possible during the etching of the silicon dioxide layer to obtain a semiconductor structure as shown in Figure 12b The height of the first sacrificial layer 134 on both sides of the second sacrificial layer 135 is the same.

[0074] S314: removing the second sacrificial layer 135 to define the remaining first sacrificial layer 134 as a sacrificial layer 136, as shown in Figure 12c

[0075] For example, the etching selectivity of the SOC layer to the silicon dioxide layer and the silicon nitride layer is increased to completely etch and remove the SOC layer. By controlling the etching selectivity of the SOC layer to the silicon dioxide layer, the etching degree of the silicon dioxide layer can be controlled when the SOC layer is removed, thereby obtaining a sacrificial layer 136 with different heights and different thicknesses. The shape of the sacrificial layer 136 is, for example, a concave shape.

[0076] In one embodiment, the heights of the sacrificial layers 136 on the sidewalls of the trench 114 are equal, as shown in Figure 12c

[0077] In one embodiment, the step of forming a closed isolation structure comprises:

[0078] S321: forming a second etching stop layer in the trench, the second etching stop layer exposing a portion of the first etching stop layer;​​

[0079] S322: Forming a closed isolation layer in the second etching stop layer, the bottom of the closed isolation layer is higher than or equal to the bottom of the second etching stop layer.

[0080] In step S321, the step of forming the second etching stop layer includes:

[0081] S321a: Forming a second etching stop material layer 138, the second etching stop material layer 138 covers the surface of the exposed first etching stop layer 131 and the surface of the sacrificial layer 136, as shown in Figure 13 .

[0082] For example, the second etching stop material layer 138 includes but is not limited to a silicon nitride layer, and the thickness of the second etching stop material layer 138 is 2nm-8nm, for example, 2nm, 4nm, 6nm or 8nm.

[0083] S321b: Removing the second etching stop material layer 138 on the upper surface of the first etching stop layer 131 and part of the second etching stop material layer 138 on the upper surface of the sacrificial layer 136 to obtain the second etching stop layer 139, as shown in Figure 14 .

[0084] For example, the second etching stop material layer 138 is etched back to remove the second etching stop material layer 138 located outside the trench 114 and on the upper surface of the first etching stop layer 131, and part of the second etching stop material layer 138 located inside the trench 114 and on the upper surface of the sacrificial layer 136 to obtain the second etching stop layer 139, the second etching stop layer 139 exposes part of the sacrificial layer 136, as shown in Figure 14 . At the same time, due to the presence of the sacrificial layer 136, the second etching stop layer 139 presents a shape of wide at the top and narrow at the bottom, that is, the width of the upper part of the second etching stop layer 139 is greater than the width of the lower part of the second etching stop layer 139, so when depositing material in the trench 114, the bottom of the second etching stop layer 139 can be easily sealed due to the narrow lower part of the second etching stop layer 139.

[0085] In step S322, before forming the closed isolation layer, it also includes: removing the sacrificial layer 136 by a wet process to form an air gap 150, as shown in Figure 15 .

[0086] In some embodiments, when the sacrificial layer 136 is formed, the lateral part of the sacrificial layer 136 can also be inclined, so the formed lateral part 153 can also be inclined, and the inclined lateral part 153 can increase the area of the air gap, so as to improve the isolation effect.

[0087] AsFigure 15 As shown, in an embodiment, the sacrificial layer 136 is completely removed by a wet etching process to obtain the air gap 150. The air gap 150 includes a lateral portion 153, a first vertical portion 151 and a second vertical portion 152. The first vertical portion 151 and the second vertical portion 152 have the same height.

[0088] After the air gap 150 is formed, the enclosed isolation layer 141 is formed in the second etching stop layer 139. The bottom of the enclosed isolation layer 141 is higher than or equal to the bottom of the second etching stop layer 139, as shown. Figure 16

[0089] For example, a rapid sealing process can be used to fill the isolation material between the second etching stop layer 139 in the trench 114, and a planarization process is performed on the upper surface of the isolation material to form the sealing isolation layer 141. The sealing isolation layer 141 and the second etching stop layer 139 together form the enclosed isolation structure 140. The bottom of the sealing isolation layer 141 is higher than the bottom of the second etching stop layer 139, or the bottom of the sealing isolation layer 141 is flush with the bottom of the second etching stop layer 139. The isolation material can include but is not limited to silicon nitride.

[0090] In an embodiment, as shown, the width of the upper part of the enclosed isolation structure 140 is greater than the width of the lower part of the enclosed isolation structure 140. Figure 16

[0091] The preparation method of the semiconductor structure described above, by ingeniously designing the shape of the sacrificial layer 136, can form a second etching stop layer 139 with a stepped shape, which is wide at the top and narrow at the bottom, in the trench 114, thereby reducing the process difficulty when filling the isolation material to form the sealing isolation layer 141, better controlling the filling degree of the isolation material, ensuring that the bottom of the sealing isolation layer 141 is higher than the bottom of the second etching stop layer 139, or flush with the bottom of the second etching stop layer 139, reducing the case of filling the isolation material into the air gap 150, that is, avoiding the isolation material contacting the first etching stop layer 131 on the gate structure 120. In this embodiment, the material of the first etching stop layer 131 is different from that of the sacrificial layer 136, so that the first etching stop layer 131 will not be affected when the sacrificial layer 136 is etched. The first etching stop layer 131 can also be used to protect the gate structure 120 from the outward diffusion of the material of the main conductive layer 123, and can also improve the short circuit between the subsequently formed bit line contact window and the gate structure 120.

[0092] ​​In one embodiment, the air gap 150 further comprises a first vertical portion 151 and a second vertical portion 152, the first vertical portion 151 and the second vertical portion 152 are communicated by a horizontal portion 153, the first vertical portion 151 and the second vertical portion 152 are respectively located between the first etching stop layer 131 and the closed isolation structure 140, as shown in Figure 16

[0093] After forming the sealing isolation layer 141, the complete closed isolation structure 140 is obtained. The first vertical portion 151 and the second vertical portion 152 are located between the closed isolation structure 140 and the first etching stop layer 131. The first vertical portion 151 and the second vertical portion 152 are respectively located on the opposite sides of the lower part of the closed isolation structure 140, and the first vertical portion 151 and the second vertical portion 152 are communicated by the horizontal portion 153. The first vertical portion 151, the second vertical portion 152 and the horizontal portion 153 jointly constitute the air gap 150.

[0094] In one embodiment, the height of the first vertical portion 151 and the second vertical portion 152 is the same, as shown in Figure 16 In some embodiments, the height of the first vertical portion 151 and the second vertical portion 152 is different.

[0095] The preparation method of the above semiconductor structure forms an air gap in the trench where the buried gate is located, and uses the characteristics of small dielectric constant and good isolation effect of air to better isolate the active regions on both sides of the gate and reduce the coupling effect between adjacent metal gates. In addition, the air gap has a horizontal portion, which can increase the area of the air gap and the width of the horizontal isolation, and the isolation effect is better and the coupling effect is lower.

[0096] In one embodiment of the present application, another method for forming the sacrificial layer 136 is disclosed. For example, after forming the second sacrificial layer 135, the following steps are performed:

[0097] S313a: Forming a photoresist layer 137 on the second sacrificial layer 135, the photoresist layer 137 only covers the first sacrificial layer 134 on one side of the second sacrificial layer 135, as shown in Figure 17

[0098] By accurately controlling the coverage range of the photoresist layer 137, as shown in Figure 17 The sidewall of the photoresist layer 137 is aligned with the outer sidewall of the second sacrificial layer 135 in the trench 114, so that only part of the first sacrificial layer 134 can be covered.

[0099] S313b: Etching the second sacrificial layer 135 and the first sacrificial layer 134, and removing the photoresist layer 137, so that the height of the first sacrificial layer 134 on both sides of the second sacrificial layer 135 is not equal. ​​

[0100] For example, based on etching part of the first sacrificial layer 134 and part of the second sacrificial layer 135, part of the upper surface of the first etching stop layer 131 is exposed, as shown in Figure 18 . Wherein the etching selectivity of the first sacrificial layer 134 and the second sacrificial layer 135 to the photoresist layer 137 is greater than 1.

[0101] Further, the photoresist layer 137 is removed, and the second sacrificial layer 135 is continuously etched to remove the second sacrificial layer 135 on the upper surface of the substrate 100, obtaining the semiconductor structure as shown in Figure 19 . Wherein the height of the first sacrificial layer 134 on both sides of the second sacrificial layer 135 is different.

[0102] S313c: Continue etching the first sacrificial layer 134 and the second sacrificial layer 135, so that the top of the second sacrificial layer 135 is higher than the top of the first sacrificial layer 134, as shown in Figure 20 .

[0103] For example, based on the semiconductor structure as shown in Figure 19 , the first sacrificial layer 134 (for example, a silicon dioxide layer) is etched with the second sacrificial layer 135 (for example, a SOC layer) and the first etching stop layer 131 (for example, a silicon nitride layer) as mask layers. For example, the etching selectivity of the silicon dioxide layer to the SOC layer can be 5-10, and the etching selectivity of the silicon dioxide layer to the silicon nitride layer can be 5-20, for example, 5, 10, 15 or 20. By controlling the etching selectivity of the silicon dioxide layer to the SOC layer to be 5-10, and the etching selectivity of the silicon dioxide layer to the silicon nitride layer to be 5-20, the etching speed of the silicon dioxide layer can be increased during etching, and the etching speed of the SOC layer and the silicon nitride layer can be reduced, so as to achieve the purpose of mainly etching the silicon dioxide layer. Moreover, the etching selectivity of the silicon dioxide layer to the silicon nitride layer can be greater than the etching selectivity of the silicon dioxide layer to the SOC layer, so that part of the SOC layer is etched appropriately more and the silicon nitride layer is etched as little as possible during etching of the silicon dioxide layer, to obtain the semiconductor structure as shown in Figure 20 . Wherein the part of the first sacrificial layer 134 on both sides of the second sacrificial layer 135 has a height difference. For example, the height difference can be 5-20 nm, for example, 5 nm, 10 nm, 15 nm or 20 nm.

[0104] S313d: Remove the second sacrificial layer 135 to define the remaining first sacrificial layer 134 as a sacrificial layer 136, as shown in Figure 21 .

[0105] For example, the etching selectivity of the SOC layer to the silicon dioxide layer and the silicon nitride layer is increased to completely etch and remove the SOC layer. By controlling the etching selectivity of the SOC layer to the silicon dioxide layer, the etching degree of the silicon dioxide layer can be controlled, thereby obtaining sacrificial layers 136 of different heights and thicknesses. In this embodiment, the height of the sacrificial layer 136 located on the sidewall of the trench 114 is different, such as Figure 21 shown.

[0106] After forming the sacrificial layer 136, based on the same steps as S321-S322 in the above embodiment, a second etch stop layer 139 and a sealing isolation layer 141 are sequentially formed to form a semiconductor structure with an air gap 150, as shown in FIG. Figure 22 shown.

[0107] In this embodiment, by improving the preparation process of the sacrificial layer 136, vertical portions of different heights can be formed in the air gap 150, such as Figure 22 As shown, the height of the second vertical portion 152 is greater than the height of the first vertical portion 151. The semiconductor structure formed by the above method can further increase the volume of the air gap, enhance the isolation effect, and further reduce the coupling effect between adjacent metal gates.

[0108] like Figures 17-18 , Figure 23 As shown, in some embodiments, a photoresist layer 137 is first formed on the second sacrificial layer 135, and the photoresist layer 137 does not completely cover the second sacrificial layer 135. Figure 17 Taking the trench 114 on the left side of the center as an example, the photoresist layer 137 exposes the left side of the second sacrificial layer 135. Specifically, the photoresist layer 137 exposes the first sacrificial layer 134 located to the left of the second sacrificial layer 135. Using the photoresist layer 137 as a mask, the exposed second sacrificial layer 135 is etched, followed by the first sacrificial layer 134. This completely removes the first sacrificial layer 134 located to the left of the second sacrificial layer 135, exposing the first etch stop layer 131 at the bottom. This creates a gap to the left of the second sacrificial layer 135. In this embodiment, the first sacrificial layer 134 can be etched using a dry etching process, thus reducing process time. A closed isolation layer 140 is then formed in the trench 114. Since the first sacrificial layer 134 to the left of the second sacrificial layer 135 has been etched away, the closed isolation layer 140 contacts the sidewalls of the trench 114. Specifically, the closed isolation layer 140 contacts the first etch stop layer 131, preventing the formation of an air gap to the left of the second sacrificial layer 135. Similarly, in Figure 17In the right trench 114, the first etching stop layer 131 at the bottom of the trench 114 is exposed after the second etching stop layer 135 and the first etching stop layer 134 are etched away completely. The air gap 150 is formed after the encapsulation isolation layer 140 is formed. The encapsulation isolation layer 140 fills the gap, and thus, the air gap 150 is not formed at the right side of the second etching stop layer 135, as shown in FIG. 1C. Figure 23

[0109] As shown in FIG. 1D, in some embodiments, the air gap 150 includes a second vertical portion 152 and a horizontal portion 153. The second vertical portion 152 and the horizontal portion 153 are in communication. The air gap 150 can be formed by the steps described above, and thus, the steps are not described herein. Figure 23

[0110] Another embodiment of the present application discloses a semiconductor structure, as shown in FIG. 1E. The semiconductor structure includes a substrate 100, a first etching stop layer 131, an encapsulation isolation layer 140, and an air gap 150. The substrate 100 includes a trench 114, and a gate structure 120 is formed in the trench 114. The top surface of the gate structure 120 is lower than the top surface of the trench 114. The first etching stop layer 131 covers the top surface of the gate structure 120, part of the sidewall of the trench 114, and the upper surface of the substrate 100. The encapsulation isolation layer 140 is between the first etching stop layer 131 in the trench 114. The encapsulation isolation layer 140 at least seals the opening of the trench 114. The air gap 150 is between the first etching stop layer 131 and the encapsulation isolation layer 140. The air gap 150 includes at least a horizontal portion 153. The bottom of the encapsulation isolation layer 140 is on the horizontal portion 153. In some embodiments, the horizontal portion 153 is a horizontal portion or an inclined portion. Figure 16 The semiconductor structure described above can better isolate the active regions on both sides of the gate by setting the air gap in the trench where the buried gate is located. The air gap has the smallest dielectric constant and the best isolation effect, and thus, the coupling effect between the adjacent metal gates is reduced. In addition, the air gap 150 has the horizontal portion 153, and thus, the area of the air isolation and the width of the horizontal isolation are increased. The isolation effect is better, and the coupling effect is lower.

[0111]

[0112] ​​​The base 100 in the embodiment can be, for example, but not limited to, a silicon base. The material forming the first etching stop layer 131 and the closed isolation structure 140 can be, for example, but not limited to, silicon nitride. By providing the air gap 150 between the closed isolation structure 140 and the first etching stop layer 131, the small dielectric constant and good isolation effect of air can be utilized to better isolate the active regions on both sides of the gate and reduce the coupling effect between adjacent metal gates. Moreover, since the air gap 150 has the lateral portion 153, the area of air isolation and the width of lateral isolation can be increased, the isolation effect is better, and the coupling effect is lower.

[0113] In one embodiment, please continue to refer to Figure 16 The air gap 150 further includes: a first vertical portion 151 and a second vertical portion 152, respectively located on opposite sides of the lower part of the closed isolation structure 140; the bottom of the first vertical portion 151 and the second vertical portion 152 is in communication with the lateral portion 153.

[0114] In one embodiment, as shown in Figure 16 The height of the first vertical portion 151 is equal to the height of the second vertical portion 152.

[0115] In one embodiment, as shown in Figure 22 The height of the first vertical portion 151 is not equal to the height of the second vertical portion 152. Compared with the semiconductor structure shown in Figure 16 In the embodiment, the second vertical portion 152 of the air gap 150 is higher than the first vertical portion 151, which can further increase the volume of the air gap, enhance the isolation effect, and further reduce the coupling effect between adjacent metal gates.

[0116] In one embodiment, as shown in Figure 16 The closed isolation structure 140 includes: a second etching stop layer 139 and a sealing isolation layer 141; the second etching stop layer 139 is partially attached to the sidewall of the first etching stop layer 131; the sealing isolation layer 141 is located between the second etching stop layer 139 and together with the second etching stop layer 139 to seal the opening of the trench 114.

[0117] In one embodiment, as shown in Figure 16 The width of the upper part of the closed isolation structure 140 is greater than the width of the lower part; wherein the upper part of the second etching stop layer 139 is attached to the sidewall of the first etching stop layer 131, and the lower part of the second etching stop layer 139 has a first spacing with the sidewall of the first etching stop layer 131.

[0118] The closed isolation structure 140, which is wide at the top and narrow at the bottom, can ensure the sealing effect of the opening of the trench 114. Moreover, there is a first distance between the lower part of the second etch stop layer 139 and the side wall of the first etch stop layer 131. This distance allows the air gap 150 to have a vertical portion, thereby utilizing the characteristics of air with a small dielectric constant and good isolation effect to isolate the active areas on both sides of the gate, thereby reducing the coupling effect between adjacent metal gates.

[0119] In one embodiment, Figure 16 As shown, the gate structure 120 includes a gate oxide layer 121, a barrier layer 122, and a main conductive layer 123 stacked in sequence from the outside to the inside. The top surface of the gate oxide layer 121 is flush with the top surface of the trench 114, the top surface of the main conductive layer 123 is lower than the top surface of the trench 114, and the top surface of the barrier layer 122 is lower than the top surface of the main conductive layer 123. By setting the top surface of the barrier layer 122 lower than the top surface of the main conductive layer 123, leakage current in the gate structure can be improved, thereby enhancing semiconductor performance.

[0120] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising a trench, wherein the trench comprises a gate structure, and a top surface of the gate structure is lower than a top surface of the trench; a first etch stop layer, covering a top surface of the gate structure, a portion of the sidewalls of the trench, and an upper surface of the substrate; a closed isolation structure, located between the first etch stop layers in the trench, the closed isolation structure at least blocking an opening of the trench; An air gap located between the first etch stop layer and the closed isolation structure, the air gap comprising at least a lateral portion, the bottom of the closed isolation structure being located on the lateral portion; Wherein, the air gap further includes at least one vertical portion, the vertical portion is located at the lower part of the closed isolation structure, and the vertical portion is connected to the horizontal portion.

2. The semiconductor structure according to claim 1, wherein: The air gap further includes a first vertical portion and a second vertical portion, wherein the first vertical portion and the second vertical portion are respectively located on two opposite sides of the lower portion of the closed isolation structure, and the bottoms of the first vertical portion and the second vertical portion are connected to the transverse portion.

3. The semiconductor structure according to claim 2, wherein: The height of the first vertical portion is equal to or different from the height of the second vertical portion.

4. The semiconductor structure according to claim 1, wherein: The closed isolation structure comprises: a second etch stop layer and a sealing isolation layer; The second etch stop layer is partially attached to the sidewall of the first etch stop layer; The sealing isolation layer is located between the second etch stop layers and seals the opening of the trench together with the second etch stop layers.

5. The semiconductor structure according to claim 4, wherein: The width of the upper portion of the second etch stop layer is greater than the width of the lower portion; wherein the upper portion of the second etch stop layer is attached to the sidewall of the first etch stop layer, and there is a first distance between the lower portion of the second etch stop layer and the sidewall of the first etch stop layer. The semiconductor structure according to claim 1 , wherein: The gate structure includes a gate oxide layer, a barrier layer and a main conductive layer stacked in sequence from the outside to the inside; The top surface of the barrier layer is lower than the top surface of the main conductive layer, and the top surface of the main conductive layer is lower than the top surface of the groove.

7. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a trench, forming a gate structure in the trench, wherein a top surface of the gate structure is lower than a top surface of the trench; forming a first etch stop layer, wherein the first etch stop layer covers a top surface of the gate structure, a portion of the sidewall of the trench, and an upper surface of the substrate; forming a closed isolation structure and an air gap in the trench, wherein the closed isolation structure at least blocks an opening of the trench, and the air gap is located between the closed isolation structure and the first etch stop layer; The air gap includes at least a transverse portion, and the bottom of the closed isolation structure is located on the transverse portion; the air gap also includes at least one vertical portion, which is located at the lower part of the closed isolation structure and is connected to the transverse portion.

8. The method for preparing a semiconductor structure according to claim 7, wherein: Before forming the closed isolation structure, a sacrificial layer is formed in the trench, and the step of forming the sacrificial layer includes: forming a first sacrificial layer in the trench; forming a second sacrificial layer on the first sacrificial layer to fill the trench; Etching the first sacrificial layer and the second sacrificial layer so that a top surface of the first sacrificial layer is lower than a top surface of the second sacrificial layer; wherein an etching rate of the first sacrificial layer is greater than an etching rate of the second sacrificial layer; The second sacrificial layer is removed to define the remaining first sacrificial layer as a sacrificial layer.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The sacrificial layers on the sidewalls of the trench have the same height.

10. The method for preparing a semiconductor structure according to claim 8, wherein: After forming the second sacrificial layer and before etching the first sacrificial layer and the second sacrificial layer, the method further includes: forming a photoresist layer on the second sacrificial layer, wherein the photoresist layer only covers the first sacrificial layer located on one side of the second sacrificial layer; The second sacrificial layer and the first sacrificial layer are etched, and the photoresist layer is removed, so that the heights of the first sacrificial layer on both sides of the second sacrificial layer are different.

11. The method for preparing a semiconductor structure according to claim 7, wherein: The width of the upper portion of the closed isolation structure is greater than the width of the lower portion of the closed isolation structure.

12. The method for preparing a semiconductor structure according to claim 8, wherein: The steps of forming the closed isolation structure include: forming a second etch stop layer in the trench, wherein the second etch stop layer exposes a portion of the first etch stop layer; A closed isolation layer is formed in the second etch stop layer, wherein the bottom of the closed isolation layer is higher than or equal to the bottom of the second etch stop layer.

13. The method for preparing a semiconductor structure according to claim 12, wherein: Before forming the closed isolation layer, the method further comprises: The sacrificial layer is removed by a wet process to form the air gap.

14. The method for preparing a semiconductor structure according to claim 7, wherein: The air gap includes a first vertical portion and a second vertical portion, the first vertical portion and the second vertical portion are connected through the transverse portion, and the height of the first vertical portion and the height of the second vertical portion are equal to or different from each other.

15. The method for preparing a semiconductor structure according to claim 14, wherein: The first vertical portion and the second vertical portion are respectively located between the first etch stop layer and the closed isolation structure.

Images