Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a lower device structure comprising a substrate, and a first N-type transistor and a first P-type transistor on the substrate, the first N-type transistor and the first P-type transistor comprising a first gate structure, a first source, a first drain and a first channel layer, the lower device structure having a bonding surface facing away from the substrate; one or more upper device structures stacked on the bonding surface, comprising a second N-type transistor and a second P-type transistor, the second N-type transistor and the second P-type transistor comprising a second gate structure, a second source, a second drain and a second channel layer; and a bonding layer between adjacent lower device structures and upper device structures and / or adjacent upper device structures. The application can realize the effect of circuit stacking without limitation on the number of layers, and is conducive to saving the occupied area of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, in order to better adapt to the reduction of feature size, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency.

[0003] Among them, the complementary field-effect transistor (CFET), composed of vertically stacked transistors, is a revolutionary three-dimensional transistor. A CFET device can be defined as a structure that includes a complementary fin field-effect transistor (FinFET). In other words, a CFET device is a three-dimensional electronic device that includes two different types of FinFET transistors stacked together, such as an n-type transistor stacked on top of a p-type transistor. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to saving the area occupied by the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a lower device structure including a substrate, and a first N-type transistor and a first P-type transistor located on the substrate. Each of the first N-type transistor and the first P-type transistor includes a first gate structure, a first source and a first drain located on opposite sides of the first gate structure, and a first channel layer covered by the first gate structure and connecting the first source and the first drain along a direction parallel to the surface of the substrate. The first gate structure includes a first gate dielectric layer and a first gate electrode layer located on the first gate dielectric layer. The lower device structure has a bonding surface facing away from the substrate; one or more layers are stacked along the normal direction of the substrate surface. The upper device structure on the bonding surface includes: a second N-type transistor and a second P-type transistor, each of which includes a second gate structure, a second source and a second drain located on both sides of the second gate structure, and a second channel layer covered by the second gate structure and connected to the second source and the second drain along a direction parallel to the substrate surface. The second gate structure includes a second gate dielectric layer and a second gate electrode layer located on the second gate dielectric layer. A bonding layer is located between adjacent lower and upper device structures, and when there are multiple upper device structures, the bonding layer is also located between adjacent upper device structures.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: forming a lower device structure, including a first substrate, and a first N-type transistor and a first P-type transistor formed on the first substrate, wherein the first N-type transistor and the first P-type transistor each include a first gate structure, a first source and a first drain located on both sides of the first gate structure, and a first channel layer covered by the first gate structure and connected to the first source and the first drain in a direction parallel to the surface of the first substrate, the lower device structure having a bonding surface facing away from the first substrate; performing one or more device stacking processes to form one or more upper device structures stacked above the lower device structure in a direction normal to the surface of the first substrate, the device stacking process including: forming a bonding layer on the bonding surface; forming a second N-type transistor and a second P-type transistor on the bonding layer, wherein the second N-type transistor and the second P-type transistor each include a second gate structure, a second source and a second drain located on both sides of the second gate structure, and a second channel layer covered by the second gate structure and connected to the second source and the second drain in a direction parallel to the surface of the bonding layer.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure provided by this invention, the lower-layer device structure includes a first N-type transistor and a first P-type transistor, and the upper-layer device structure includes a second N-type transistor and a second P-type transistor. In this invention, each layer of device structure includes both N-type and P-type transistors, so the lower-layer and upper-layer device structures can each independently form a circuit structure and be electrically connected. This allows the semiconductor structure to be formed by stacking circuits. Compared to a single-layer device structure where only one type of channel conductivity transistor is formed, requiring two layers to form a circuit structure, and thus only allowing double-layer stacking each time, this invention can achieve unlimited-layer circuit stacking. It can stack one or more upper-layer device structures on the lower-layer device structure according to process requirements, reducing the limitation on the number of upper-layer device structures. At the same time, using multi-layer stacking helps save the area occupied by the semiconductor structure.

[0009] In the semiconductor structure formation method provided by the embodiments of the present invention, a lower device structure is formed, including a first N-type transistor and a first P-type transistor. One or more device stacking processes are performed to form one or more upper device structures stacked above the lower device structure along the normal to the surface of the first substrate. The upper device structure includes a second N-type transistor and a second P-type transistor. In the embodiments of the present invention, each device structure includes both N-type and P-type transistors. Therefore, the lower and upper device structures can each independently constitute a circuit structure and be electrically connected. This allows the semiconductor structure to be formed using circuit stacking. Compared to a device structure where only one type of channel conductivity transistor is formed in the same layer, requiring two device structures to form a circuit structure, and thus only allowing double-layer stacking each time, the embodiments of the present invention can achieve unlimited-layer circuit stacking. It can form one or more upper device structures on the lower device structure according to process requirements, reducing the limitation on the number of upper device structures. Furthermore, using multi-layer stacking helps save the area occupied by the semiconductor structure. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a semiconductor structure;

[0011] Figures 2 to 9 This is a schematic diagram of an embodiment of the semiconductor structure of the present invention;

[0012] Figures 10 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] As the background technology shows, the CFET structure is a complementary field-effect transistor composed of vertically stacked components. However, it is currently difficult to save the area occupied by the CFET structure.

[0014] We will now analyze the reasons why it is difficult to save the area occupied by a CFET structure, using a semiconductor structure as an example.

[0015] Figure 1 This is a schematic diagram of a semiconductor structure.

[0016] The semiconductor structure includes: a lower device structure 10, which includes a substrate 11 and a first transistor located on the substrate 11. The first transistor includes a first gate structure 13, first source / drain doped layers 12 located on both sides of the first gate structure 13, and a first channel layer (not shown) covered by the first gate structure 13 and connected to the first source / drain doped layers 12 in a direction parallel to the surface of the substrate 11. The channel conductivity types of the first transistor are all the same. An upper device structure 20 is stacked above the lower device structure 10. The upper device structure 20 includes a second transistor, which includes a second gate structure 23, second source / drain doped layers 22 located on both sides of the second gate structure 23, and a second channel layer (not shown) covered by the second gate structure 23 and connected to the second source / drain doped layers 22 in a direction parallel to the surface of the substrate 11. The channel conductivity types of the second transistor are all the same.

[0017] The first transistor and the second transistor are electrically connected to their corresponding ports through conductive plugs 30, thereby forming a circuit structure.

[0018] However, in the CFET structure, the lower device structure 10 includes only one type of transistor with a single channel conductivity, and the upper device structure 20 also includes only one type of transistor with a single channel conductivity. That is, either the first transistor or the second transistor is an NMOS transistor, and the other is a PMOS transistor. Therefore, the first transistor and the second transistor, which are stacked perpendicularly to each other, constitute a complementary field-effect transistor. Two stacked transistor structures are required to form a circuit structure. If stacking is to continue, multiple two-layer stacked circuit structures need to be formed to form the final circuit structure. In other words, each stacking can only be a double-layer stack. Therefore, the design of the CFET structure results in a large area occupied by the semiconductor structure, making it difficult to cope with the increasingly high density of semiconductor devices.

[0019] To address the aforementioned technical problems, the semiconductor structure provided in this embodiment of the invention includes a lower-layer device structure comprising a first N-type transistor and a first P-type transistor, and an upper-layer device structure comprising a second N-type transistor and a second P-type transistor. In this embodiment, each layer of the device structure includes both N-type and P-type transistors, allowing both the lower and upper-layer device structures to independently form circuit structures and be electrically connected. This enables the formation of a semiconductor circuit structure through circuit stacking. Compared to a single-layer device structure where only one type of channel conductivity transistor is formed, requiring two layers to form a circuit structure and thus limiting stacking to double layers, this embodiment of the invention achieves unlimited-layer circuit stacking. It allows for stacking one or more upper-layer device structures on the lower-layer device structure according to process requirements, reducing the limitation on the number of upper-layer device structures. Furthermore, the multi-layer stacking method helps save the area occupied by the semiconductor structure.

[0020] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Reference Figures 2 to 9 , Figure 2 and Figure 3 This is a perspective view of an embodiment of the semiconductor structure of the present invention. Figure 4 This is a circuit diagram of an embodiment of the semiconductor structure of the present invention. Figure 5 This is a schematic diagram of the projection pattern of the first channel layer, the first gate structure, the first source, and the first drain on the substrate in one embodiment of the semiconductor structure of the present invention. Figure 6 This is a schematic diagram of the projection pattern of the second channel layer, the second gate structure, the second source, and the second drain on the substrate in one embodiment of the semiconductor structure of the present invention. Figure 7 yes Figure 2 Cross-sectional view along the AA direction. Figure 8 yes Figure 2 Cross-sectional view along the BB direction. Figure 9 yes Figure 2 Cross-sectional view along the CC direction.

[0022] in, Figure 3 for Figure 2 A schematic diagram of the structure of the lower-level device that is obscured in the middle.

[0023] The semiconductor structure includes: a lower device structure 100, including a substrate 300, and a first N-type transistor 110 and a first P-type transistor 120 located on the substrate 300. The first N-type transistor 110 and the first P-type transistor 120 each include a first gate structure 140, a first source 420 and a first drain 410 located on opposite sides of the first gate structure 140, and a first channel layer 130 covered by the first gate structure 140 and connecting the first source 420 and the first drain 410 along a direction parallel to the surface of the substrate 300. The first gate structure 140 includes a first gate dielectric layer 150 and a first gate electrode layer 160 located on the first gate dielectric layer 150. The lower device structure 100 has a bonding surface 510 facing away from the substrate 300; one or more bonding surfaces along the normal direction of the surface of the substrate 300 (e.g., ...). Figure 3 (As shown in the Z-direction) An upper device structure 200 is stacked on the bonding surface 510. The upper device structure 200 includes: a second N-type transistor 210 and a second P-type transistor 220. The second N-type transistor 210 and the second P-type transistor 220 each include a second gate structure 240, a second source 620 and a second drain 610 located on both sides of the second gate structure 240, and a second channel layer 230 covered by the second gate structure 240 and connected to the second source 620 and the second drain 610 in a direction parallel to the surface of the substrate 300. The second gate structure 240 includes a second gate dielectric layer 250 and a second gate electrode layer 260 located on the second gate dielectric layer 250. A bonding layer 500 is located between adjacent lower device structures 100 and upper device structures 200. When there are multiple upper device structures 200, the bonding layer 500 is also located between adjacent upper device structures 200.

[0024] In this embodiment, each device structure includes both N-type and P-type transistors, and the lower device structure 100 and the upper device structure 200 can each independently form a circuit structure and be electrically connected. This allows for the formation of a semiconductor circuit structure through circuit stacking. Compared to a device structure where only one type of channel conductivity is formed in the same layer, requiring two device structures to form a circuit structure, and thus only allowing for double-layer stacking each time, this embodiment achieves the effect of unlimited circuit stacking. Depending on process requirements, one or more upper device structures 200 can be stacked on the lower device structure 100, reducing the limitation on the number of upper device structures 200. At the same time, using a multi-layer stacking method helps to save the area occupied by the semiconductor structure.

[0025] It should be noted that in this embodiment, only the case where one upper device structure 200 is stacked on the lower device structure 100 is shown. In other embodiments, multiple upper device structures may be stacked on the lower device structure according to process requirements.

[0026] The lower-level device structure 100 includes a first N-type transistor 110 and a first P-type transistor 120. Both the first N-type transistor 110 and the first P-type transistor 120 include a first channel layer 130, a first gate structure 140, a first source 420, and a first drain 410, thereby realizing the normal function of the first N-type transistor 110 and the first P-type transistor 120.

[0027] In this embodiment, depending on the structure type of the lower-level device structure 100, the first N-type transistor 110 and the first P-type transistor 120 include FinFETs or Gate-All-Around (GAA) transistors. Specifically, the GAA transistor can be a horizontal nanosheet transistor or a nanowire transistor. This embodiment takes the example where both the first N-type transistor 110 and the first P-type transistor 120 are FinFETs.

[0028] The substrate 300 is used to provide a process platform for the formation of semiconductor structures. In this embodiment, the substrate 300 includes a substrate 310, a bottom fin 330 protruding from the substrate 310, and an isolation layer 320 located on the substrate 310, the isolation layer 320 covering the sidewalls of the bottom fin 330.

[0029] In this embodiment, the substrate 310 is made of silicon. In other embodiments, the substrate 310 may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate 310 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. As an example, the bottom fin 330 and the substrate 310 are integrally formed.

[0030] In this embodiment, the isolation layer 320 can be a shallow trench isolation structure (STI). The material of the isolation layer 320 is an insulating material. As an example, the material of the isolation layer 320 is silicon oxide.

[0031] The first channel layer 130 is used to provide channels for the first N-type transistor 110 and the first P-type transistor 120. Depending on the type of the first N-type transistor 110 and the first P-type transistor 120, the first channel layer 130 may be one or more of fins, nanowires, and nanosheets.

[0032] In this embodiment, taking the first N-type transistor 110 and the first P-type transistor 120 as FinFETs, the first channel layer 130 is a first channel fin 133 protruding from the substrate 300.

[0033] In other embodiments, when the first N-type transistor and the first P-type transistor are GAA transistors, the first channel layer is located on the substrate and spaced apart from the substrate. Specifically, the first channel layer is located on the bottom fin and spaced apart from the bottom fin. The first channel layer includes one or more spaced-apart first sub-channel layers.

[0034] In other embodiments, depending on process requirements, the first channel layer types corresponding to the transistors included in the lower device structure may also be different. For example, the first channel layer type corresponding to some transistors is a fin, and the first channel layer type corresponding to some transistors is a nanosheet.

[0035] The material of the first channel layer 130 includes silicon, silicon germanide, germanium, or a group III-V semiconductor material. The material of the first channel layer 130 is determined based on the channel conductivity type and performance requirements of the first N-type transistor 110 and the first P-type transistor 120. As an example, the material of the first channel layer 130 is silicon. In other embodiments, the materials of the first channel layers corresponding to the first N-type transistor and the first P-type transistor may be different; for example, the material of the first channel layer corresponding to the first N-type transistor may be silicon, and the material of the first channel layer corresponding to the first P-type transistor may be silicon germanide.

[0036] In this embodiment, the first gate structure 130 spans the first channel fin 133 and covers a portion of the top and sidewalls of the first channel fin 133. In other embodiments, when the first N-type transistor and the first P-type transistor are GAA transistors, the first gate structure surrounds and covers the first sub-channel layer.

[0037] The first gate structure 130 is used to control the opening or closing of the channels of the first N-type transistor 110 and the first P-type transistor 120. In this embodiment, the first gate electrode layer 160 spans the first channel fin 133 and covers a portion of the top and sidewalls of the first channel fin 133 with the first gate dielectric layer 150. In other embodiments, when the first channel layer is located on the bottom fin and spaced apart from the bottom fin, the first gate electrode layer surrounds and covers the first gate dielectric layer on each of the first sub-channel layers.

[0038] In this embodiment, the first gate electrode layer 160 is a metal gate electrode layer. The material of the first gate electrode layer 160 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, the first gate electrode layer 160 includes a first work function layer (not shown) and a first electrode layer (not shown) covering the first work function layer. The first work function layer is used to adjust the threshold voltages of the first N-type transistor and the first P-type transistor, and the first electrode layer is used to bring out the electrical properties of the first gate electrode layer 160.

[0039] In this embodiment, the first gate dielectric layer 150 is located between the first gate electrode layer 160 and the first channel layer 130. The first gate dielectric layer 150 is used to isolate the first gate electrode layer 160 and the first channel layer 130. The material of the first gate dielectric layer 150 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the first gate dielectric layer 150 includes a first gate oxide layer (not shown) and a first high-k gate dielectric layer (not shown) covering the first gate oxide layer.

[0040] In this embodiment, the material of the first gate oxide layer is silicon oxide, and the material of the first high-k gate dielectric layer is a high-k dielectric material. A high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the material of the first high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the first high-k gate dielectric layer is HfO2.

[0041] It should be noted that the first gate dielectric layer 150 and the first gate electrode layer 160 are formed by a process of forming a high k last metal gate last after forming a high k last gate dielectric layer. Therefore, the first gate dielectric layer 150 is also located between the bottom of the first gate electrode layer 160 and the substrate 300, and extends to cover the sidewall of the first gate electrode layer 160.

[0042] It should also be noted that, in other embodiments, depending on process requirements, the first gate electrode layer may also be a polysilicon gate layer or other types of device gate layers.

[0043] The first source 420 serves as the source of the first N-type transistor 110 and the first P-type transistor 120, and the first drain 410 serves as the drain of the first N-type transistor 110 and the first P-type transistor 120. In this embodiment, the first source 420 and the first drain 410 include a first epitaxial layer doped with ions, and the conductivity type of the doped ions in the first epitaxial layer is the same as the channel conductivity type of the corresponding transistor in the underlying device structure. That is, in the first N-type transistor 110, the conductivity type of the doped ions in the first epitaxial layer is N-type, and N-type ions include one or more of As, P, and Sb; in the first P-type transistor 120, the conductivity type of the doped ions in the first epitaxial layer is P-type, and P-type ions include one or more of B, Ga, and In. The material of the epitaxial layer in the first epitaxial layer includes Si, SiGe, or SiP. Specific descriptions of the first source 420 and the first drain 410 are not repeated here.

[0044] In this embodiment, the first N-type transistor 110 and the first P-type transistor 120 further include a first gate sidewall 180 covering the sidewall of the first gate electrode layer 160. Specifically, the first gate sidewall 180 covers the first gate dielectric layer 150 located on the sidewall of the first gate electrode layer 160. The first gate sidewall 180 is used to protect the sidewalls of the first gate electrode layer 160 and the first gate dielectric layer 150, and also to define the positions of the first source 420 and the first drain 410. The first gate sidewall 180 can be a single-layer structure or a multilayer structure, and the material of the first gate sidewall 180 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the first gate sidewall 180 is a single-layer structure, and the material of the first gate sidewall 180 is silicon nitride.

[0045] In other embodiments, when the first N-type transistor and the first P-type transistor are GAA transistors, the first N-type transistor and the first P-type transistor may further include: a first inner wall, which is located between adjacent first sub-channel layers along the normal direction of the substrate surface, or between the first sub-channel layer and the substrate, and along the first direction, the first inner wall is located between the sidewall of the first gate dielectric layer and the first source and the first drain.

[0046] In this embodiment, the lower device structure 100 further includes a first interlayer dielectric layer 170, located on the substrate 300, and covering the sidewall of the first gate structure 140.

[0047] The first interlayer dielectric layer 170 is used to isolate adjacent transistors in the underlying device structure 100. The first interlayer dielectric layer 170 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the first interlayer dielectric layer 170 is made of silicon oxide. Correspondingly, the first gate dielectric layer 150 is located between the bottom of the first gate electrode layer 160 and the substrate 300, and between the sidewall of the first gate electrode layer 160 and the first interlayer dielectric layer 170.

[0048] In this embodiment, the lower device structure 100 has a bonding surface 510 facing away from the substrate 300. The bonding surface 510 is the front side of the lower device structure 100. During the fabrication of the semiconductor structure, the bonding surface 510 is used as a process platform to fabricate the upper device structure 200 on top of the bonding surface 510.

[0049] The bonding layer 500 is located on the bonding surface 510. During the fabrication of the upper device structure 200, the substrate required to form the upper device structure 200 is bonded to the bonding surface 510 through the bonding layer 500, thereby enabling the lower device structure 100 and the upper device structure 200 to be fabricated independently. The lower device structure 100 and the upper device structure 200 are independent of each other, which allows for electrical coupling and electrical isolation between the lower device structure 100 and the upper device structure 200 according to different process requirements. Moreover, fabricating the upper device structure 200 on the bonding layer 500 is beneficial to improving the positional accuracy of each component in the upper device structure 200. For example, specific components in the lower device structure 100 can be used as alignment marks.

[0050] The bonding layer 500 enhances the bonding strength between the lower device structure 100 and the upper device structure 200, thereby improving the reliability of the semiconductor structure. In addition, the bonding layer 500 also protects the lower device structure 100 during the fabrication of the upper device structure 200.

[0051] It should be noted that in other embodiments, multiple upper device structures are formed on the lower device structure, and the bonding layer is also located between adjacent upper device structures. That is, after the fabrication process of one upper device structure is completed, the fabricated upper device structure also has a bonding surface facing away from the lower device structure. Correspondingly, the substrate required to form another upper device structure is bonded to the bonding surface of the fabricated upper device structure through the bonding layer.

[0052] In this embodiment, the bonding layer 500 is made of a dielectric material, which provides electrical isolation between the lower device structure 100 and the upper device structure 200, and makes the bonding layer 500 compatible with semiconductor processes.

[0053] The bonding layer 500 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide. In this embodiment, the bonding layer 500 is made of silicon oxide. By using silicon oxide, bonding can be achieved through fusion bonding, which is beneficial for improving bonding efficiency and bonding strength. Moreover, it is also beneficial for further improving the electrical isolation effect between the lower device structure 100 and the upper device structure 200. In addition, by using silicon oxide, the bonding temperature is lower, thereby reducing the impact on the performance of the first N-type transistor 110 and the first P-type transistor 120 in the lower device structure 100.

[0054] It should be noted that conductive structures can also be provided in the bonding layer 500, thereby enabling circuit redistribution to meet design requirements.

[0055] It should also be noted that the bonding layer 500 is located on the bonding surface 510. The bonding layer 500 not only covers the top of the first gate electrode layer 160, but also covers the top of the first interlayer dielectric layer 170.

[0056] The upper device structure 200 is located on the bonding layer 500. The upper device structure includes a second N-type transistor 210 and a second P-type transistor 220. Both the second N-type transistor 210 and the second P-type transistor 220 include a second channel layer 230, a second gate structure 240, a second source 620 and a second drain 610, thereby realizing the normal function of the second N-type transistor 210 and the second P-type transistor 220.

[0057] Depending on the structure type of the upper-layer device structure 200, the second N-type transistor 210 and the second P-type transistor 220 include fin field-effect transistors or GAA transistors. Specifically, the GAA transistor can be a horizontal nanosheet transistor or a nanowire transistor. This embodiment uses the second N-type transistor 210 and the second P-type transistor 220 as FinFETs as an example.

[0058] The second channel layer 230 is used to provide channels for the second N-type transistor 210 and the second P-type transistor 220. Depending on the type of the second N-type transistor 210 and the second P-type transistor 220, the second channel layer 230 may be one or more of fins, nanowires, and nanosheets.

[0059] In this embodiment, taking the second N-type transistor 210 and the second P-type transistor 220 as FinFETs, the second channel layer 230 is a second channel fin 233 protruding on the bonding layer 500.

[0060] In other embodiments, when the second N-type transistor and the second P-type transistor are GAA transistors, the second channel layer is located on the bonding layer and spaced apart from the bonding layer, and the second channel layer includes one or more spaced second sub-channel layers.

[0061] In other embodiments, depending on process requirements, the second channel layer types corresponding to the transistors included in the upper device structure may also be different. For example, the second channel layer type corresponding to some transistors is a fin, and the second channel layer type corresponding to some transistors is a nanosheet.

[0062] It should be noted that, in this embodiment, during the fabrication of the upper device structure 200, the substrate bonded to the bonding surface 510 is directly patterned as the second channel layer 230. Therefore, the upper device structure 200 does not contain an additional substrate (e.g., a substrate). Accordingly, the second channel fin 233 is in contact with the bonding layer 500.

[0063] The material of the second channel layer 230 includes silicon, silicon germanide, germanium, or a group III-V semiconductor material. The material of the second channel layer 230 is determined according to the channel conductivity type and performance requirements of the second N-type transistor 210 and the second P-type transistor 220. As an example, the material of the second channel layer 230 is silicon. In other embodiments, the materials of the second channel layers corresponding to the second N-type transistor and the second P-type transistor may be different; for example, the material of the first channel layer corresponding to the second N-type transistor may be silicon, and the material of the first channel layer corresponding to the second P-type transistor may be silicon germanide.

[0064] In this embodiment, the second gate structure 230 spans the second channel fin 233 and covers a portion of the top and sidewalls of the second channel fin 233. In other embodiments, when the second N-type transistor and the second P-type transistor are GAA transistors, the second gate structure surrounds and covers the second sub-channel layer.

[0065] The second gate structure 230 is used to control the turning on or off of the channels of the second N-type transistor 210 and the second P-type transistor 220. In this embodiment, the second gate electrode layer 260 spans the second channel fin 233 and covers a portion of the top and sidewalls of the second channel fin 233 of the second gate dielectric layer 250. In other embodiments, when the second channel layer is located on and spaced apart from the bonding layer, the corresponding second gate electrode layer surrounds and covers the second gate dielectric layer on each of the second sub-channel layers.

[0066] In this embodiment, the second gate electrode layer 260 is a metal gate electrode layer, and the material of the second gate electrode layer 260 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, the second gate electrode layer 260 includes a second work function layer (not shown) and a second electrode layer (not shown) covering the second work function layer. For a detailed description of the second work function layer and the second electrode layer and their materials, please refer to the foregoing descriptions of the first work function layer and the first electrode layer, respectively, which will not be repeated here.

[0067] In this embodiment, the second gate dielectric layer 250 is located between the second gate electrode layer 260 and the second channel layer 230, and is also located between the second gate electrode layer 260 and the bonding layer 500.

[0068] The second gate dielectric layer 250 is used to isolate the second gate electrode layer 260 and the second channel layer 230. The material of the second gate dielectric layer 250 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. As an example, the second gate dielectric layer 250 includes a second gate oxide layer and a second high-k gate dielectric layer covering the second gate oxide layer. For a detailed description of the second gate dielectric layer 250, please refer to the foregoing description of the first gate dielectric layer 150, which will not be repeated here.

[0069] In this embodiment, the upper device structure 200 does not contain an additional substrate (e.g., a substrate), therefore, the second gate dielectric layer 250 is in contact with the top of the bonding layer 500.

[0070] It should be noted that the second gate dielectric layer 250 and the second gate electrode layer 260 are formed by a process of forming a high-k gate dielectric layer first and then forming a gate electrode layer. Therefore, the second gate dielectric layer 250 also conformally covers the bottom and sidewalls of the second gate electrode layer 260. That is, the second gate dielectric layer 250 is located between the second gate electrode layer 260 and the bonding layer 500, and extends to cover the sidewalls of the second gate electrode layer 260.

[0071] It should also be noted that, in other embodiments, depending on process requirements, the second gate electrode layer may also be a polysilicon gate layer or other types of device gate layers.

[0072] The second source 620 serves as the source of the second N-type transistor 210 and the second P-type transistor 220, and the second drain 610 serves as the drain of the second N-type transistor 210 and the second P-type transistor 220. In this embodiment, the second source 620 and the second drain 610 include a second epitaxial layer doped with ions, and the conductivity type of the doped ions in the second epitaxial layer is the same as the channel conductivity type of the corresponding transistor in the upper device structure. For a detailed description of the second source 620 and the second drain 610, please refer to the aforementioned description of the first source 420 and the first drain 410, which will not be repeated here.

[0073] In this embodiment, the upper device structure 200 further includes a second gate sidewall 280, covering the sidewalls of the second gate electrode layer 260 and the second gate dielectric layer 250. The second gate sidewall 280 is used to protect the sidewalls of the second gate electrode layer 260 and the second gate dielectric layer 250, and also to define the positions of the second source 620 and the second drain 610. A detailed description of the material of the second gate sidewall 280 can be found in the foregoing description of the first gate sidewall, and will not be repeated here.

[0074] In other embodiments, when the second N-type transistor and the second P-type transistor are GAA transistors, the upper device structure may further include: a second inner wall located between adjacent second channel layers along the normal direction of the substrate surface, or located between the second channel layer and the bonding layer, and along the first direction, the second inner wall is located between the sidewall of the second gate dielectric layer and the second source and the second drain.

[0075] For a detailed description of the material of the second inner wall, please refer to the aforementioned description of the first inner wall; it will not be repeated here.

[0076] In this embodiment, the upper device structure 200 further includes a second interlayer dielectric layer 270, located on the bonding layer 500 and covering the sidewalls of the second gate structure 240. The second interlayer dielectric layer 270 is used to isolate adjacent transistors in the upper device structure 200.

[0077] The material of the second interlayer dielectric layer 270 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the second interlayer dielectric layer 270 is silicon oxide.

[0078] In this embodiment, the semiconductor structure further includes an interconnect structure for electrically coupling with the corresponding ports of the first N-type transistor 110, the first P-type transistor 120, the second N-type transistor 210, and the second P-type transistor 220, thereby realizing the electrical connection between the lower device structure 100 and the upper device structure 200.

[0079] The ports include a gate port, a drain port, and a source port. Specifically, according to the circuit design, the interconnect structure realizes electrical coupling between the corresponding ports.

[0080] In this embodiment, the material of the interconnect structure includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC. The interconnect structure uses a material with good conductivity, thereby achieving a better electrical connection between the lower device structure 100 and the upper device structure 200.

[0081] In this embodiment, the first N-type transistor 110 and the first P-type transistor 120 in the lower device structure 100 constitute a first inverter; the second N-type transistor 210 and the second P-type transistor 220 in the upper device structure 200 constitute a second inverter. In this embodiment, an inverter is formed in each device structure, so that the circuit connection between inverters can be realized more easily through multi-layer stacking.

[0082] refer to Figure 4 The first inverter and the second inverter are connected in series. Specifically, the first inverter and the second inverter are connected in series through an interconnection structure.

[0083] In this embodiment, the first drains 410 of the first N-type transistor 110 and the first P-type transistor 120 are electrically coupled and used as the output terminal of the first inverter. The second gate structures 240 of the second N-type transistor 210 and the second P-type transistor 220 are electrically coupled and used as the input terminal of the second inverter. The output terminal is electrically coupled to the input terminal. In other embodiments, the first gate structures of the first N-type transistor and the first P-type transistor are electrically coupled and used as the input terminal of the first inverter. The second drains of the second N-type transistor and the second P-type transistor are electrically coupled and used as the output terminal of the second inverter. The output terminal is electrically coupled to the input terminal.

[0084] According to the circuit principle of an inverter, the gate structures of the NMOS and PMOS transistors in an inverter need to be electrically connected, and the drains of the NMOS and PMOS transistors need to be electrically connected. Therefore, in this embodiment, in the lower device structure 100, the first N-type transistor 110 and the first P-type transistor 120 share the first gate structure 140, and the first drains 410 of the first N-type transistor 110 and the first P-type transistor 120 are electrically connected. Thus, the first N-type transistor 110 and the first P-type transistor 120 constitute the first inverter. The first gate structure 140 serves as the input terminal of the first inverter, and the first drain 410 serves as the output terminal of the first inverter. The first source 420 of the first N-type transistor 110 is connected to a low potential terminal or ground (GND), and the first source 420 of the first P-type transistor 120 is connected to a high potential terminal (VDD).

[0085] Similarly, in the upper device structure 200, the second N-type transistor 210 and the second P-type transistor 220 share the second gate structure 240. The second drains 610 of the second N-type transistor 210 and the second P-type transistor 220 are electrically connected. Thus, the second N-type transistor 210 and the second P-type transistor 220 constitute a second inverter. The second gate structure 240 serves as the input terminal of the second inverter, and the second drain 610 serves as the output terminal of the second inverter. The second source 620 of the second N-type transistor 210 is connected to a low potential terminal or ground (GND), and the second source 620 of the second P-type transistor 220 is connected to a high potential terminal (VDD).

[0086] In this embodiment, the output terminal of the first inverter is electrically connected to the input terminal of the second inverter, and the first drain 410 is electrically connected to the second gate structure 240.

[0087] Specifically, in conjunction with reference Figures 2 to 9 The series connection of the first inverter and the second inverter is described in detail.

[0088] Reference Figure 3 and Figure 5 In this embodiment, the interconnect structure includes: a first drain interconnect 450, located on top of the first drain 410, and connecting the first drain 410 of the first P-type transistor 110 and the first N-type transistor 120.

[0089] In this embodiment, the first drain interconnect 450 is formed on the top of the first drain 410. Therefore, without increasing the lateral dimension of the first drain 410, the first drain interconnect 450 electrically connected to the first drain 410 can be formed, saving the area occupied by the semiconductor structure. Here, lateral refers to the direction parallel to the substrate surface.

[0090] The first drain interconnect 450 is used to realize the electrical connection of the first drain 410 corresponding to the first N-type transistor 110 and the first P-type transistor 120, and to realize the electrical connection of the first drain 410 with the external circuit structure.

[0091] In this embodiment, the first drain interconnect 450 is located in the first interlayer dielectric layer 170 and covers the top of the first drain 410, thereby enabling the first drain interconnect 450 to be electrically connected to the second gate structure 240.

[0092] By realizing the electrical connection of the first drain 410 corresponding to the first N-type transistor 110 and the first P-type transistor 120 during the fabrication of the lower-level device structure, it is beneficial to realize the electrical connection between the second gate structure 240 and the first drain 410 when fabricating the upper-level device structure, thereby reducing the difficulty of realizing the electrical connection between the second gate structure 240 and the first drain 410.

[0093] Specifically, the first drain interconnect 450 penetrates the first interlayer dielectric layer 170 on top of the first drain 410. Correspondingly, during the formation of the semiconductor structure, only the first interlayer dielectric layer 170 on top of the first drain 410 needs to be etched to form a groove for accommodating the first drain interconnect 450. The groove is relatively shallow, and the upper device structure has not yet been formed at this time, thereby reducing the process difficulty of forming the first drain interconnect 450 and improving the positional accuracy of the first drain interconnect 450.

[0094] In this embodiment, the material of the first drain interconnect 450 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC, and the above materials have good conductivity.

[0095] refer to Figure 8 In this embodiment, the interconnect structure further includes a conductive pillar 520 that penetrates the bonding layer 500 at the top of the first interconnect 450 and is located between the top of the first interconnect 450 and the bottom of the second gate structure 240. The conductive pillar 520 is electrically connected to the first interconnect 450 and the second gate structure 240.

[0096] The conductive post 520 is used to realize the electrical connection between the first drain interconnect 450 and the second gate structure 240, thereby realizing the electrical connection between the first drain 410 and the second gate structure 240, and further enabling the output terminal of the first inverter to be electrically connected to the input terminal of the second inverter.

[0097] In this embodiment, the material of the conductive pillar 520 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC, and the above materials have good conductivity.

[0098] In this embodiment, to improve process efficiency, the step of forming the conductive pillar 520 includes: forming a through-hole penetrating the bonding layer 500 at the top of the first drain interconnect 450, the through-hole exposing the top of the first drain interconnect 450; in the step of forming the second gate structure 240, the conductive material of the second gate structure 240 (i.e., the material of the second gate electrode layer 260) is also filled in the through-hole to form the conductive pillar 520 located in the through-hole. Therefore, the conductive pillar 520 and the second gate electrode layer 260 in the second gate structure 240 are an integral structure, and correspondingly, the conductive pillar 520 and the second gate electrode layer 260 in the second gate structure 240 are made of the same material.

[0099] Accordingly, in conjunction with references Figure 2 and Figure 6 In this embodiment, the interconnect structure further includes a second drain interconnect 650, located on top of the second drain 610, and connected to the second drain 610 of the second N-type transistor 210 and the second P-type transistor 220.

[0100] In this embodiment, the second drain interconnect 650 is formed on the top of the second drain 610. Therefore, the second drain interconnect 650 electrically connected to the second drain 610 can be formed without increasing the lateral dimension of the second drain 610, thus saving the area occupied by the semiconductor structure.

[0101] The second drain interconnect 650 is used to realize the electrical connection of the second drain 610 corresponding to the second N-type transistor 210 and the second P-type transistor 220, and to realize the electrical connection of the second drain 610 with the external circuit structure.

[0102] In this embodiment, the second drain interconnect 650 is located in the second interlayer dielectric layer 270 and covers the top of the second drain 610, thereby making the second drain interconnect 650 serve as the output terminal of the upper device structure 200.

[0103] Specifically, the second drain interconnect 650 penetrates the second interlayer dielectric layer 270 on top of the second drain 610. Accordingly, during the formation of the semiconductor structure, only the second interlayer dielectric layer 270 on top of the second drain 610 needs to be etched to form a groove for accommodating the second drain interconnect 650. The groove is shallow, and no other device structures (e.g., another upper-layer device structure) have been formed at this time, thereby reducing the process difficulty of forming the second drain interconnect 650 and improving the positional accuracy of the second drain interconnect 650.

[0104] In this embodiment, the material of the second drain interconnect 650 includes two or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC, and the above materials have good conductivity.

[0105] refer to Figure 7 In this embodiment, the interconnect structure further includes a gate plug 530, which is located on the side of the second gate structure and penetrates the bonding layer 500 at the top of the first gate structure 140. The gate plug 530 is electrically connected to the first gate structure 140.

[0106] In this embodiment, there is no need to increase the lateral dimension of the first gate structure 140. The first gate structure 140 and the second gate structure 240 are simply misaligned in the lateral direction so that a second interlayer dielectric layer 270 is formed on the top of the first gate structure 140, thereby forming a gate plug 530 that is electrically connected to the first gate structure 140, thus saving the area occupied by the semiconductor structure.

[0107] The gate plug 530 is used to realize the electrical connection between the first gate electrode layer 160 and the external circuit structure.

[0108] Specifically, the gate plug 530 also penetrates the second interlayer dielectric layer 270 on top of the first gate electrode layer 160. In this embodiment, the first interlayer dielectric layer 170 only covers the sidewall of the first gate electrode layer 160, exposing the top of the first gate electrode layer 160. Therefore, in this embodiment, the gate plug 530 penetrates the second interlayer dielectric layer 270 and the bonding layer 500 on top of the first gate electrode layer 160.

[0109] In this embodiment, the material of the gate plug 530 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC, and the above materials have good conductivity.

[0110] Reference Figure 2 and Figure 9In this embodiment, the interconnect structure further includes: a first source plug 440 located on the top and sidewall of the second source 620 of the second N-type transistor 210. The first source plug 440 also penetrates downward through the bonding layer 500 and extends to the top of the first source 420 of the first N-type transistor 110. The first source plug 440 is electrically connected to the first source 420 of the first N-type transistor 110.

[0111] In this embodiment, the first source plug 440 is formed on top of the first source 420 and the second source 620. Therefore, there is no need to increase the lateral dimensions of the first source 420 and the second source 620. The source plug 440 electrically connected to the first source 420 and the second source 620 can be formed simply by slightly offsetting the first source 420 and the second source 620 in the lateral direction, thus saving the area occupied by the semiconductor structure.

[0112] The first source plug 440 is used to realize the electrical connection between the first source 420 of the first N-type transistor 110 and the second source 620 of the second N-type transistor 210 and the external circuit structure.

[0113] Specifically, the first source plug 440 also penetrates the first interlayer dielectric layer 170 at the top of the corresponding first source 420.

[0114] In this embodiment, the material of the first source plug 440 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC, and the above materials have good conductivity.

[0115] Accordingly, the semiconductor structure further includes a second source plug 640 located on the top and sidewall of the second source 620 of the second P-type transistor 220. The second source plug 640 also penetrates downward through the bonding layer 500 and extends to the top of the first source 420 of the first P-type transistor 120. The second source plug 420 is electrically connected to the first source 420 of the first P-type transistor 120.

[0116] Specifically, the second source plug 640 also penetrates the first interlayer dielectric layer 170 at the top of the corresponding first source 420.

[0117] For a detailed description of the second source plug 640, please refer to the aforementioned description of the first source plug 440, which will not be repeated here.

[0118] In this embodiment, after the first source 420 of the first N-type transistor 110 and the second source 620 of the second N-type transistor 210 are electrically connected, they are then connected together to a low potential terminal or ground (GND). After the first source 420 of the first P-type transistor 120 and the second source 620 of the second P-type transistor 220 are electrically connected, they are then connected together to a high potential terminal (VDD). This eliminates the need to extend the first source 420 in order to bring out the electrical properties of the first source 420 in the lower device structure 100, thus saving the area occupied by the semiconductor structure.

[0119] Figures 10 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0120] Reference Figures 10 to 12 , Figure 10 This is a perspective view of an embodiment of the lower-level device structure of the present invention. Figure 11 This is a schematic diagram of the projection patterns of the first channel layer, the first gate structure, the first source, and the first drain on the first substrate in one embodiment of the lower-level device structure of the present invention. Figure 12 yes Figure 10 A cross-sectional view along the AA direction shows a lower device structure 101, including a first substrate 301 and a first N-type transistor 111 and a first P-type transistor 121 formed on the first substrate 301. The first N-type transistor 111 and the first P-type transistor 121 each include a first gate structure 141, a first source 421 and a first drain 411 located on both sides of the first gate structure 141, and a first channel layer 131 covered by the first gate structure 141 and connected to the first source 421 and the first drain 411 in a direction parallel to the surface of the first substrate 301. The lower device structure 101 has a bonding surface 511 facing away from the first substrate 301.

[0121] Both the first N-type transistor 111 and the first P-type transistor 121 include a first channel layer 131, a first gate structure 141, a first drain 411, and a first source 421, thereby realizing the normal function of the first N-type transistor 111 and the first P-type transistor 121. Depending on the structure type of the underlying device structure 100, the first N-type transistor 111 and the first P-type transistor 121 may be FinFETs or GAA transistors. This embodiment takes the example where both the first N-type transistor 111 and the first P-type transistor 121 are FinFETs.

[0122] The first substrate 301 is used to provide a process platform for the formation of semiconductor structures. In this embodiment, the first substrate 301 includes a substrate 311, a bottom fin 331 protruding from the substrate 311, and an isolation layer 120 located on the substrate 311, the isolation layer 120 covering the sidewalls of the bottom fin 331.

[0123] The first channel layer 131 is used to provide channels for the first N-type transistor 111 and the first P-type transistor 121. Depending on the type of the first N-type transistor 111 and the first P-type transistor 121, the first channel layer 131 may be one or more of fins, nanowires, and nanosheets.

[0124] In this embodiment, the first channel layer 131 is a first channel fin 132 protruding from the first substrate 301. In other embodiments, when the first N-type transistor and the first P-type transistor are GAA transistors, the first channel layer is located on the bottom fin and spaced apart from the bottom fin. The first channel layer includes one or more spaced-apart first sub-channel layers.

[0125] In other embodiments, depending on process requirements, the first channel layer types corresponding to the transistors included in the lower device structure may also be different. For example, the first channel layer type corresponding to some transistors is a fin, and the first channel layer type corresponding to some transistors is a nanosheet.

[0126] In this embodiment, the first gate structure 141 spans the first channel fin 132 and covers a portion of the top and a portion of the sidewalls of the first channel fin 132. In other embodiments, when located on and spaced apart from the bottom fin, the first gate structure correspondingly surrounds and covers the first sub-channel layer.

[0127] In this embodiment, the first gate structure 141 includes a first gate dielectric layer 151 and a first gate electrode layer 161 located on the first gate dielectric layer 151.

[0128] As an example, the first gate electrode layer 161 includes a first work function layer (not shown) and a first electrode layer (not shown) covering the first work function layer.

[0129] In this embodiment, the first gate dielectric layer 151 is located between the first gate electrode layer 161 and the first channel layer 131. Specifically, the first gate dielectric layer 151 includes a first gate oxide layer and a first high-k gate dielectric layer covering the first gate oxide layer. It should be noted that the first gate dielectric layer 151 and the first gate electrode layer 161 are formed using a process that forms the high-k gate dielectric layer first and then the gate electrode layer. Therefore, the first gate dielectric layer 151 also covers the bottom and sidewalls of the first gate electrode layer 161.

[0130] It should also be noted that, in other embodiments, depending on process requirements, the first gate electrode layer may also be a polysilicon gate layer or other types of device gate layers.

[0131] In this embodiment, the first N-type transistor 111 and the first P-type transistor 121 in the lower device structure 101 are used to form a first inverter. According to the circuit principle of the inverter, the gate structures of the NMOS transistor and the PMOS transistor in the inverter need to be electrically connected. Therefore, in this embodiment, in the lower device structure 101, the first N-type transistor 111 and the first P-type transistor 121 share the first gate structure 141. The first drains 411 of the first N-type transistor 111 and the first P-type transistor 121 are electrically connected. Thus, the first N-type transistor 111 and the first P-type transistor 121 constitute the first inverter. The first gate structure 141 serves as the input terminal of the first inverter, and the first drain 411 serves as the output terminal of the first inverter. The first source 421 of the first N-type transistor 111 is connected to a low potential terminal or ground (VSS), and the first source 421 of the first P-type transistor 121 is connected to a high potential terminal (VDD).

[0132] Both the first source 421 and the second drain 411 include a first epitaxial layer doped with ions, and the conductivity type of the doped ions in the first epitaxial layer is the same as the channel conductivity type of the transistor.

[0133] In this embodiment, the first N-type transistor 111 and the first P-type transistor 121 further include a first gate sidewall 181 covering the sidewall of the first gate electrode layer 161. Specifically, the first gate sidewall 181 covers the first gate dielectric layer 151 located on the sidewall of the first gate electrode layer 161. The first gate sidewall 181 is used to protect the sidewalls of the first gate electrode layer 161 and the first gate dielectric layer 151, and also to define the positions of the first source 421 and the first drain 411.

[0134] In other embodiments, when the first N-type transistor and the first P-type transistor are GAA transistors, the first N-type transistor and the first P-type transistor may further include: a first inner wall, which is located between adjacent first sub-channel layers along the normal direction of the substrate surface, or between the first sub-channel layer and the substrate, and along the first direction, the first inner wall is located between the sidewall of the first gate dielectric layer and the first source and the first drain.

[0135] In this embodiment, the lower device structure 101 further includes a first interlayer dielectric layer 171, located on the substrate 301, and covering the sidewall of the first gate structure 141.

[0136] The first interlayer dielectric layer 171 is used to isolate adjacent transistors in the underlying device structure 101.

[0137] For a detailed description of the lower-level device structure 101, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0138] In this embodiment, the lower device structure 101 has a bonding surface 511 facing away from the first substrate 301. The bonding surface 511 is the front side of the lower device structure 101. Subsequently, the upper device structure is fabricated on the bonding surface 511 as a process platform to form a circuit stack structure.

[0139] refer to Figure 13 , Figure 13 Based on Figure 11 The schematic diagram further includes, before forming the upper device structure, forming a first drain interconnect 451 covering the top of the first drain 411, the first drain interconnect 451 connecting the first drain 411 of the first P-type transistor 121 and the first drain 411 of the first N-type transistor 111.

[0140] In this embodiment, the first drain interconnect 451 is formed on the top of the first drain 411. Therefore, without increasing the lateral dimension of the first drain 411, the first drain interconnect 451 electrically connected to the first drain 411 can be formed, saving the area occupied by the semiconductor structure. Here, lateral refers to the direction parallel to the substrate surface.

[0141] The first drain interconnect 451 is used to realize the electrical connection of the first drain 411 corresponding to the first N-type transistor 111 and the first P-type transistor 121, and to realize the electrical connection of the first drain 411 with the external circuit structure.

[0142] By realizing the electrical connection of the first drain 411 corresponding to the first N-type transistor 111 and the first P-type transistor 121 during the fabrication of the lower-level device structure, it is beneficial to realize the electrical connection between the second gate structure 241 and the first drain 411 when fabricating the upper-level device structure.

[0143] Specifically, the step of forming the first drain interconnect 451 includes: etching the first interlayer dielectric layer 171 located on top of the first drain 411 to form a first groove exposing the top of the first drain 411; and filling the first groove to form the first drain interconnect 451. Therefore, in this embodiment, a first drain interconnect 441 covering the top of the first drain 411 is formed in the first interlayer dielectric layer 171, with the first interlayer dielectric layer 171 exposing the top of the first drain interconnect 451, thereby enabling the first drain interconnect 451 to be electrically connected to the second gate structure 241.

[0144] In this embodiment, only the first interlayer dielectric layer 171 on the top of the first drain 411 needs to be etched to form the first groove. The depth of the first groove is small, and the upper device structure has not yet been formed at this time, thereby reducing the process difficulty of forming the first drain interconnect 451 and improving the positional accuracy of the first drain interconnect 451.

[0145] In this embodiment, the material of the first drain interconnect 451 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC, and the above materials have good conductivity.

[0146] Reference Figures 14 to 23 Perform one or more device stacking processes to form one or more devices along the normal direction of the surface of the first substrate 301 (e.g., ...). Figure 16 (As shown in the Z-direction) An upper device structure 201 is stacked above the lower device structure 101. The device stacking process includes: forming a bonding layer 501 on the bonding surface 511; forming a second N-type transistor 211 and a second P-type transistor 221 on the bonding layer 501. The second N-type transistor 211 and the second P-type transistor 221 each include a second gate structure 241, a second source 621 and a second drain 611 located on both sides of the second gate structure 241, and a second channel layer 231 covered by the second gate structure 241 and connected to the second source 621 and the second drain 611 in a direction parallel to the surface of the bonding layer 501.

[0147] in, Figure 14 and Figure 15 Based on Figure 12 sectional view, Figure 16 This is a three-dimensional view corresponding to the formation of the semiconductor structure. Figure 17 This is a three-dimensional view of the underlying device structure that is obscured after the semiconductor structure is formed. Figure 18 This is a circuit diagram of the semiconductor structure. Figure 19 This is a schematic diagram of the projection patterns of the first channel layer, first gate structure, first source, and first drain on the substrate in the lower-level device structure. Figure 20 This is a schematic diagram of the projection patterns of the second channel layer, second gate structure, second source, and second drain on the substrate in the upper-layer device structure. Figure 21 yes Figure 16 Cross-sectional view along the AA direction. Figure 22 yes Figure 16 Cross-sectional view along the BB direction. Figure 23 yes Figure 16 Cross-sectional view along the CC direction.

[0148] In this embodiment, each layer of the device structure includes both N-type and P-type transistors. Therefore, the lower layer device structure 101 and the upper layer device structure 201 can each independently form a circuit structure and be electrically connected. This allows for the formation of a semiconductor circuit structure through circuit stacking. Compared to a single layer device structure where only one type of channel conductivity transistor is formed, requiring two layers to form a circuit structure, and thus only allowing for double-layer stacking each time, this embodiment achieves the effect of unlimited circuit stacking. Depending on process requirements, one or more upper layer device structures 201 can be formed on the lower layer device structure 101, reducing the limitation on the number of upper layer device structures 201. Furthermore, the multi-layer stacking method helps save the area occupied by the semiconductor structure.

[0149] It should be noted that this embodiment is described using a single device stacking process as an example, and accordingly, only the case where an upper device structure 201 is formed on the lower device structure 101 is shown. In other embodiments, multiple device stacking processes can also be performed, and multiple upper device structures can be formed on the lower device structure accordingly.

[0150] It should also be noted that, in the step of forming a bonding layer on the bonding surface, the projection of the bonding layer on the first substrate coincides with the first substrate 301.

[0151] In this embodiment, the first N-type transistor 101 and the first P-type transistor 121 in the lower device structure 101 are used to form a first inverter; the second N-type transistor 211 and the second P-type transistor 221 in the upper device structure 211 are used to form a second inverter. In this embodiment, an inverter is formed in each device structure, so that the circuit connection between inverters can be realized more easily through multi-layer stacking.

[0152] refer to Figure 18 The first inverter is used to connect the second inverter in series.

[0153] In this embodiment, the first drains 411 of the first N-type transistor 111 and the first P-type transistor 121 are electrically coupled and used as the output terminal of the first inverter. The second gate structure 241 of the second N-type transistor 211 and the second P-type transistor 221 is electrically coupled and used as the input terminal of the second inverter. The output terminal is electrically coupled to the input terminal. In other embodiments, the first gate structures of the first N-type transistor and the first P-type transistor are electrically coupled and used as the input terminal of the first inverter. The second drains of the second N-type transistor and the second P-type transistor are electrically coupled and used as the output terminal of the second inverter. The output terminal is electrically coupled to the input terminal.

[0154] According to the circuit principle of an inverter, the gate structures of the NMOS and PMOS transistors in an inverter need to be electrically connected, and the drains of the NMOS and PMOS transistors need to be electrically connected. Therefore, in this embodiment, in the upper device structure 201, the second N-type transistor 211 and the second P-type transistor 221 share the second gate structure 241, and the second drains 611 of the second N-type transistor 211 and the second P-type transistor 221 are electrically connected. Thus, the second N-type transistor 211 and the second P-type transistor 221 constitute a second inverter. The second gate structure 241 serves as the input terminal of the second inverter, and the second drain 611 serves as the output terminal of the second inverter. The second source 621 of the second N-type transistor 211 is connected to a low potential terminal or ground (GND), and the second source 621 of the second P-type transistor 221 is connected to a high potential terminal (VDD).

[0155] In this embodiment, the output terminal of the first inverter is electrically connected to the input terminal of the second inverter, and the first drain 411 is electrically connected to the second gate structure 241.

[0156] The following detailed explanation of the device stacking process is provided in conjunction with the accompanying drawings.

[0157] refer to Figure 14 After forming the first drain interconnect 451, the second substrate 302 is bonded to the bonding surface 511 using the bonding layer 501.

[0158] The second substrate 302 is used to form the second channel layer 231 in the upper device structure 201.

[0159] In this embodiment, the second substrate 302 is bonded to the bonding surface 511 by bonding. That is, after the fabrication process of the lower device structure 101 is completed, the fabrication process of the upper device structure 201 can be completed independently, which reduces the process difficulty of fabricating the upper device structure 201 and the impact of the fabrication process of the upper device structure 201 on the lower device structure 101.

[0160] The bonding layer 501 is used to improve the bonding strength between the lower device structure 101 and the second substrate 302, thereby improving the reliability of the semiconductor structure. In addition, during the fabrication of the upper device structure 201, the bonding layer 501 can also protect the lower device structure 101.

[0161] In this embodiment, the bonding layer 501 is made of a dielectric material, thereby providing electrical isolation between the lower device structure 101 and the upper device structure 201, and making the bonding layer 501 compatible with semiconductor processes. The bonding layer 501 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide. In this embodiment, the bonding layer 501 is made of silicon oxide. By using silicon oxide, bonding can be achieved through fusion bonding, which is beneficial for improving bonding efficiency and bonding strength; moreover, it is also beneficial for further improving the electrical isolation effect of the bonding layer 501; in addition, by using silicon oxide, the bonding temperature is lower, thereby reducing the impact on the performance of the first N-type transistor 111 and the first P-type transistor 121 in the lower device structure 101.

[0162] It should be noted that the bonding layer 501 also contains conductive structures, which enable the redistribution of the circuit to meet design requirements.

[0163] In this embodiment, the bonding layer 501 is located between the second substrate 302 and the lower device structure 101, and the bonding layer 501 covers the top of the first gate structure 141 and the top of the first interlayer dielectric layer 171.

[0164] Specifically, as an example, the bonding surface 511 of the lower device structure 101 is used as the first bonding surface (not shown), and the second substrate 302 includes a second bonding surface (not shown). The step of bonding the second substrate 302 to the bonding surface 511 using the bonding layer 501 includes: forming the bonding layer 501 on the bonding surface 511; and bonding the second substrate 302 to the bonding layer 501 using the second bonding surface.

[0165] In this embodiment, a deposition process (e.g., chemical vapor deposition) is used to form the bonding layer 501.

[0166] In this embodiment, taking the second N-type transistor 211 and the second P-type transistor 221 as both being FinFETs, in the step of bonding the second substrate 302 to the bonding surface 511 using the bonding layer 501, the second substrate 302 is a fin material layer 303.

[0167] The fin material layer 303 may be made of silicon, silicon germanide, germanium, or a group III-V semiconductor material. The material of the fin material layer 303 is determined based on the channel conductivity type and performance requirements of the second N-type transistor 211 and the second P-type transistor 221. As an example, the fin material layer 303 may be made of silicon.

[0168] Specifically, an initial substrate is provided, which includes the same material layer as the fin material layer 303. After bonding, the initial substrate is thinned until the target thickness of the fin material layer 303 is reached.

[0169] In other embodiments, when the formed second N-type transistor and second P-type transistor are GAA transistors, in the step of bonding the second substrate to the bonding surface using a bonding layer, the second substrate includes one or more stacked channel material stacks, the channel material stacks include a sacrificial material layer and a channel material layer located on the sacrificial material layer, and in the same channel material stack, the sacrificial material layer is closer to the bonding layer than the channel material layer.

[0170] Accordingly, after the second substrate is bonded to the bonding surface using a bonding layer, the initial substrate is thinned until the remaining initial substrate reaches the target thickness, and the target thickness of the remaining initial substrate is equal to the target thickness of the channel material layer.

[0171] refer to Figure 15 The step of forming a second N-type transistor 211 and a second P-type transistor 221 on the bonding layer 501 includes: patterning the second substrate 302 to form a discrete second channel layer 231.

[0172] Therefore, in this embodiment, after the upper device structure 201 is formed, the upper device structure 201 does not contain an additional substrate (e.g., a substrate).

[0173] The second channel layer 231 is used to provide channels for the second N-type transistor 211 and the second P-type transistor 221. As an example, the material of the second channel layer 231 is silicon.

[0174] Depending on the type of the second N-type transistor 211 and the second P-type transistor 221, the type of the second channel layer 231 includes one or more of fins, nanowires, and nanosheets. In this embodiment, taking the type of the second channel layer 231 as a fin as an example, in the step of patterning the second substrate 302, the second channel layer 231 is a second channel fin 232 protruding from the bonding layer 501.

[0175] In other embodiments, when the type of the second channel layer is a nanowire or nanosheet, that is, when the second substrate is a channel material stack, the step of patterning the second substrate involves patterning the channel material stack as one or more stacked channel stacks protruding from the bonding layer, the channel stack including a sacrificial layer and sub-channel layers located on the sacrificial layer, the one or more sub-channel layers constituting the second channel layer.

[0176] It should be noted that the first channel layer includes one or more first sub-channel layers spaced apart. Therefore, in the step of graphically representing the second substrate, the sub-channel layers in the channel stack are defined as second sub-channel layers, and the one or more second sub-channel layers constitute the second channel layer.

[0177] In this embodiment, after the second substrate 302 is bonded to the bonding surface 511 using the bonding layer 501, the second substrate 302 is then patterned. During the patterning of the second substrate 302, the structures in the lower-layer device structure 101 can be used as alignment marks, which facilitates precise control of the relative positional relationship between the second channel layer 231 and the first channel layer 131. Correspondingly, when forming the second gate structure 241, the structures in the lower-layer device structure 101 can also be used as alignment marks, which facilitates precise control of the relative positional relationship between the second gate structure 241 and the first gate structure 141.

[0178] Reference Figures 16 to 23 A second gate structure 241 covering the second channel layer 231, and a second source 621 and a second drain 611 located on the bonding layers 501 on both sides of the second gate structure 241 are formed.

[0179] In this embodiment, the second gate structure 241 includes a second gate dielectric layer 251 and a second gate electrode layer 261 located on the second gate dielectric layer 251. The second gate dielectric layer 251 and the second gate electrode layer 261 are formed using a process of forming a high k last metal gate last after forming a high k last metal gate last. Therefore, before forming the second gate dielectric layer 251, the second gate electrode layer 261, the second source 621 and the second drain 611, a step of forming a pseudo-gate structure is also included.

[0180] Specifically, after forming the discrete second channel layer 231, a pseudo-gate structure (not shown) is formed across the second channel layer 231, the pseudo-gate structure covering part of the top and part of the sidewalls of the second channel layer 231.

[0181] The pseudo-gate structure is used to occupy space in the subsequent formation of the second gate structure 241.

[0182] In other embodiments, when the second channel layer is a channel stack protruding from the bonding layer, the pseudo-gate structure spans the channel stack and covers a portion of the top and sidewalls of the channel stack.

[0183] After forming the dummy gate structure, the method further includes: forming a second gate sidewall 281 on the sidewall of the dummy gate structure; after forming the second gate sidewall 281, forming a second drain 611 and a second source 621 in the second channel layer 231 on both sides of the dummy gate structure, wherein the second drain 611 and the second source 621 are in contact with the end of the second channel layer 231 located below the dummy gate structure.

[0184] After forming the pseudo-gate structure, the second channel layer 231 on both sides of the pseudo-gate structure is removed to form a source-drain groove (not shown); a second drain electrode 611 and a second source electrode 621 are formed in the source-drain groove.

[0185] The second source 621 serves as the source of the second N-type transistor 211 and the second P-type transistor 221, and the second drain 611 serves as the drain of the second N-type transistor 211 and the second P-type transistor 221. In this embodiment, the second source 621 and the second drain 611 include a second epitaxial layer doped with ions, and the conductivity type of the doped ions in the second epitaxial layer is the same as the channel conductivity type of the second transistor. Specifically, after removing the second channel layer 231 on both sides of the dummy gate structure, the second source 621 and the second drain 611 are formed using an epitaxial process.

[0186] In other embodiments, the second channel layer is a channel stack. After removing the second channel layers on both sides of the pseudo-gate structure and before forming the second source and the second drain, the method further includes: laterally etching out a portion of the exposed sacrificial layer to form a trench surrounded by adjacent second channel layers and sacrificial layers, or a trench surrounded by second channel layers, bonding layers and sacrificial layers; and forming a second inner sidewall in the trench.

[0187] For a detailed description of the second gate sidewall, the second source 621, the second drain 611, and the second inner sidewall, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0188] In this embodiment, the stacking process further includes forming a second interlayer dielectric layer 271 on the bonding layer 501.

[0189] In this embodiment, the second interlayer dielectric layer 271 covers the sidewall of the second gate structure 241.

[0190] Specifically, after forming the second source 621 and the second drain 611 on both sides of the pseudo-gate structure, a second interlayer dielectric layer 271 is formed before removing the pseudo-gate structure.

[0191] After forming the second source 621 and the second drain 611, a second interlayer dielectric layer 271 is formed on the bonding layer 501 on the side of the pseudo-gate structure. The second interlayer dielectric layer 271 covers the sidewall of the pseudo-gate structure and exposes the top of the pseudo-gate structure.

[0192] The second interlayer dielectric layer 271 is used to isolate adjacent transistors in the upper device structure 201 and also to provide a process basis for forming the second gate structure 241. The material of the second interlayer dielectric layer 271 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the second interlayer dielectric layer 271 is silicon oxide.

[0193] After forming the second interlayer dielectric layer 271, the dummy gate structure is removed, and a gate opening is formed in the second interlayer dielectric layer 271.

[0194] The gate opening is used to provide a spatial location for forming the second gate structure 241.

[0195] In other embodiments, after forming the gate opening, the method further includes: removing the sacrificial layer exposed by the gate opening to form a through-slot communicating with the gate opening. The through-slot also provides space for the subsequent formation of a second gate structure.

[0196] In this embodiment, the step of forming the second gate structure 241 includes: forming a second gate dielectric layer 251 covering the bottom and sidewalls of the gate opening, the second gate dielectric layer 251 also covering the top and sidewalls of the second channel layer 231 in the gate opening; forming a second gate electrode layer 261 in the gate opening, the second gate electrode layer 261 and the second gate dielectric layer 251 constituting the second gate structure 241.

[0197] In this embodiment, the second gate dielectric layer 251 is used to isolate the second gate electrode layer 261 and the second channel layer 231. In this embodiment, the second gate dielectric layer 251 includes a second gate oxide layer and a second high-k gate dielectric layer covering the second gate oxide layer. The second gate oxide layer conformally covers each surface of the second channel layer 231; the second high-k gate dielectric layer conformally covers the gate oxide layer and also conformally covers the bottom and sidewalls of the gate opening. For a detailed description of the second gate dielectric layer 251, please refer to the foregoing description of the first gate dielectric layer 151, which will not be repeated here.

[0198] It should be noted that in the step of forming the second gate dielectric layer 251, the second gate dielectric layer 251 will also cover the top of the second interlayer dielectric layer 271.

[0199] The second gate electrode layer 261 is used to control the opening or closing of the channel of the second transistor. In this embodiment, the second gate electrode layer 261 spans the second channel fin 232 and covers part of the top and part of the sidewall of the second gate dielectric layer 251 of the second channel fin 232. In other embodiments, when the second channel layer is a channel stack, the second gate electrode layer surrounds and covers the second gate dielectric layer on the second channel layer. In this embodiment, the second gate electrode layer 261 is a metal gate electrode layer, and the material of the second gate electrode layer 261 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the second gate electrode layer 261 includes a second work function layer (not shown) and a second electrode layer (not shown) covering the second work function layer. For a detailed description of the second work function layer and the second electrode layer, please refer to the foregoing descriptions of the first work function layer and the first electrode layer, respectively, which will not be repeated here.

[0200] Specifically, a second gate electrode layer 261 is formed in the gate opening through a deposition step and a planarization step performed sequentially. During the planarization process, the second gate dielectric layer 251 located on top of the second interlayer dielectric layer 271 is also removed.

[0201] refer to Figure 22 In this embodiment, the device stacking process further includes: after forming the bonding layer 501 and before forming the second gate structure 241, forming a conductive pillar 521, the conductive pillar 521 penetrating the bonding layer 501 at the top of the first drain interconnect 451 and located in the region where the second gate structure 241 is to be formed; after forming the second gate structure 241, the conductive pillar 251 is located between the top of the first mutual drain interconnect 451 and the bottom of the second gate structure 241, and the conductive pillar 501 is electrically connected to the first drain interconnect 451 and the second gate structure 241.

[0202] The conductive post 521 is used to realize the electrical connection between the first interconnect 451 and the second gate structure 241, thereby realizing the electrical connection between the first drain 411 and the second gate structure 241.

[0203] In this embodiment, the step of forming the conductive pillar 521 includes: before forming the second gate structure 241, forming a through hole (not shown) through the bonding layer 501 in the region where the second gate structure 241 is to be formed, with the through hole exposing the top of the first interconnect 451.

[0204] The through-hole is used to provide space for the subsequent formation of conductive pillars.

[0205] In this embodiment, after forming the second gate dielectric layer 251 and before forming the second gate electrode layer 261, a through-hole is formed on the top of the first interconnect 451, penetrating the bonding layer 501, and the through-hole exposes the top of the first interconnect 451.

[0206] Specifically, the via is formed by etching the second gate dielectric layer 251, bonding layer 501 and first interlayer dielectric layer 171 on top of the first interconnect 451 through the gate opening.

[0207] The via formed by the gate opening enables the conductive pillar 521 to be formed simultaneously with the subsequent formation of the second gate electrode layer 261. This improves the process compatibility of forming the conductive pillar 521, simplifies the process flow, and increases process efficiency.

[0208] In this embodiment, the step of forming the conductive pillar 521 includes: in the step of forming the second gate structure 241, the conductive material (second gate electrode layer 261) of the second gate structure 241 is also filled in the through hole to form a conductive pillar 521 located in the through hole, which is used to electrically connect the first interconnect line 451 and the second gate structure 241.

[0209] In this embodiment, the conductive pillar 521 and the second gate electrode layer 261 in the second gate structure 241 are an integral structure, which is beneficial to improving process efficiency.

[0210] In this embodiment, the material of the conductive post 521 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC, and the above materials have good conductivity.

[0211] It should be noted that in other embodiments, the conductive pillars may be formed separately before forming the second gate structure.

[0212] Reference Figure 19 , Figure 20 and Figure 23 The forming method further includes: forming a first source plug 441 on the top and sidewall of the second source 621 of the second N-type transistor 211, the first source plug 441 extending downward through the bonding layer 501 and extending to the top of the first source 421 of the first N-type transistor 111, the first source plug 441 being electrically connected to the first source 421 of the first N-type transistor 111.

[0213] In this embodiment, the first source plug 441 is formed on the top and sidewall of the first source 421 and the second source 621, and the second source 621 shares the first source plug 441 with the corresponding first source 421. Therefore, there is no need to increase the lateral dimensions of the first source 421 and the second source 621. The first source 421 and the second source 621 can be formed by slightly offsetting them laterally, thus saving the area occupied by the semiconductor structure.

[0214] The first source plug 441 is used to realize the electrical connection between the first source 421 of the first N-type transistor 111 and the second source 621 of the second N-type transistor 211 and the external circuit structure.

[0215] Specifically, the step of forming the first source plug 441 includes: etching the second interlayer dielectric layer 271 located on the top and side of the second source 621, as well as the bonding layer 501 and the first interlayer dielectric layer 171 on the side of the second source 621, above the top of the first source 421, to form a source contact hole exposing the top of the first source 421 and the top and sidewalls of the second source 621; filling the source contact hole to form the first source plug 441. Therefore, in this embodiment, the first source plug 441 penetrates the first interlayer dielectric layer 171 at the top of the corresponding first source 421 and the second interlayer dielectric layer 271 at the top of the corresponding second source 621.

[0216] In this embodiment, the material of the first source plug 441 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC, and the above materials have good conductivity.

[0217] Accordingly, the forming method further includes: forming a second source plug 641 on the top and sidewall of the second source 621 of the second P-type transistor 221, the second source plug 641 further penetrating downward through the bonding layer 501 and extending to the top of the first source 421 of the first P-type transistor 121, the second source plug 641 being electrically connected to the first source 421 of the first P-type transistor 121.

[0218] Specifically, in this embodiment, the second source plug 641 penetrates the first interlayer dielectric layer 171 at the top of the corresponding first source 421 and the second interlayer dielectric layer 271 at the top of the corresponding second source 621.

[0219] For a detailed description of the second source plug 641, please refer to the aforementioned description of the first source plug 441, which will not be repeated here.

[0220] In this embodiment, after the first source 421 of the first N-type transistor 111 and the second source 621 of the second N-type transistor 211 are electrically connected, they are then connected together to a low potential terminal or ground (GND). After the first source 421 of the first P-type transistor 121 and the second source 621 of the second P-type transistor 221 are electrically connected, they are then connected together to a high potential terminal (VDD). This eliminates the need to increase the lateral dimension of the first source 421 in order to bring out the electrical properties of the first source 421 in the lower device structure 111, thus saving the area occupied by the semiconductor structure.

[0221] refer to Figure 21 In this embodiment, the forming method further includes: forming a gate plug 531 penetrating the bonding layer 501 on the top of the first gate structure 141 at the side of the second gate structure 241, wherein the gate plug 531 is electrically connected to the first gate structure 141.

[0222] The gate plug 531 is used to realize the electrical connection between the first gate electrode layer 161 and the external circuit structure.

[0223] Specifically, the step of forming the gate plug 531 includes: etching the bonding layer 501 and the second interlayer dielectric layer 271 located on top of the first gate structure 141 to form a gate contact hole exposing the top of the first gate structure 141; and filling the gate contact hole to form the gate plug 531. Therefore, in this embodiment, the gate plug 531 also penetrates the second interlayer dielectric layer 271 on top of the first gate electrode layer 161.

[0224] In this embodiment, the material of the gate plug 531 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC, and the above materials have good conductivity.

[0225] refer to Figure 20 In this embodiment, the forming method further includes: forming a second drain interconnect 651 covering the top of the second drain 611, wherein the second drain interconnect 651 connects the second drain 611 of the second N-type transistor 211 and the second drain 611 of the second P-type transistor 221.

[0226] In this embodiment, the second drain interconnect 651 is formed on the top of the second drain 611. Therefore, without increasing the lateral dimension of the second drain 611, the second drain interconnect 651 electrically connected to the second drain 611 can be formed, saving the area occupied by the semiconductor structure.

[0227] The second drain interconnect 651 is used to realize the electrical connection of the second drain 611 corresponding to the second N-type transistor 211 and the second P-type transistor 221, and to realize the electrical connection of the second drain 611 with the external circuit structure.

[0228] Specifically, the step of forming the second drain interconnect 651 includes: etching the second interlayer dielectric layer 271 located on top of the second drain 611 to form a second groove exposing the top of the second drain 611; and filling the second groove to form the second drain interconnect 651. Therefore, in this embodiment, a second drain interconnect 651 covering the top of the second drain 611 is formed in the second interlayer dielectric layer 271, with the top of the second drain interconnect 651 exposed, thereby enabling the second drain interconnect 651 to serve as an output terminal of the upper-layer device structure 211.

[0229] In this embodiment, the material of the second drain interconnect 651 includes two or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC, and the above materials have good conductivity.

[0230] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a lower device structure comprising a substrate, and a first N-type transistor and a first P-type transistor on the substrate, the first N-type transistor and the first P-type transistor each comprising a first gate structure, a first source and a first drain located on two sides of the first gate structure respectively, and a first channel layer covered by the first gate structure and connecting the first source and the first drain in a direction parallel to a surface of the substrate, the first gate structure comprising a first gate dielectric layer and a first gate electrode layer on the first gate dielectric layer, the lower device structure having a bonding surface facing away from the substrate; one or more upper device structures stacked on the bonding surface in a direction normal to the surface of the substrate, the upper device structure comprising: a second N-type transistor and a second P-type transistor, the second N-type transistor and the second P-type transistor each comprising a second gate structure, a second source and a second drain located on two sides of the second gate structure respectively, and a second channel layer covered by the second gate structure and connecting the second source and the second drain in a direction parallel to the surface of the substrate, the second gate structure comprising a second gate dielectric layer and a second gate electrode layer on the second gate dielectric layer; a bonding layer located between adjacent lower device structures and upper device structures, and when the number of upper device structures is more than one, the bonding layer is also located between adjacent upper device structures; the first N-type transistor and the first P-type transistor in the lower device structure form a first inverter, the second N-type transistor and the second P-type transistor in the upper device structure form a second inverter, and the second inverter is connected in series with the first inverter.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises an interconnection structure for electrically coupling corresponding ports of the first N-type transistor, the first P-type transistor, the second N-type transistor and the second P-type transistor.

3. The semiconductor structure of claim 2, wherein, The first N-type transistor and the first P-type transistor share the first gate structure, and the second N-type transistor and the second P-type transistor share the second gate structure. The interconnection structure comprises: a first drain interconnection line located on top of the first drain and connecting the first drain of the first P-type transistor and the first N-type transistor; and a second drain interconnection line located on top of the second drain and connecting the second drain of the second N-type transistor and the second P-type transistor. The interconnection structure further comprises: a conductive pillar penetrating the bonding layer and located between the top of the first drain interconnection line and the bottom of the second gate structure, the conductive pillar being electrically connected with the first drain interconnection line and the second gate structure.

4. The semiconductor structure of claim 3, wherein, The conductive pillar and the second gate electrode layer in the second gate structure are an integral structure.

5. The semiconductor structure of claim 4, wherein, The interconnection structure further comprises: a first source plug located on top of and a sidewall of the second source of the second N-type transistor, the first source plug further penetrating the bonding layer downward and extending to the top of the first source of the first N-type transistor, the first source plug being electrically connected with the first source of the first N-type transistor.

6. The semiconductor structure of claim 3, wherein, ​ A second source plug on top of and sidewall of the second source of the second P-type transistor, the second source plug further downwardly penetrating the bonding layer and extending to top of the first source of the first P-type transistor, the second source plug electrically connected with the first source of the first P-type transistor.

7. The semiconductor structure of claim 3, wherein, The interconnection structure further comprises: a gate plug on a side of the second gate structure and penetrating the bonding layer on top of the first gate structure, the gate plug electrically connected with the first gate structure.

8. The semiconductor structure of claim 6, wherein, The lower device structure further comprises: a first interlayer dielectric layer on the substrate and covering sidewall of the first gate structure; The first drain interconnection line is in the first interlayer dielectric layer and covers top of the first drain; The first and second source plugs further penetrate the first interlayer dielectric layer above the corresponding first source.

9. The semiconductor structure of claim 6, wherein, The upper device structure further comprises: a second interlayer dielectric layer on the bonding layer and covering sidewall of the second gate structure; The second drain interconnection line is in the second interlayer dielectric layer and covers top of the second drain; The first and second source plugs further penetrate the second interlayer dielectric layer above the corresponding second source.

10. The semiconductor structure of claim 3, wherein, The material of the first drain interconnection line comprises one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC; the material of the second drain interconnection line comprises one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC.

11. The semiconductor structure of claim 4, wherein, The material of the conductive pillar comprises one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC.

12. The semiconductor structure of claim 6, wherein, The material of the first source plug comprises one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC; the material of the second source plug comprises one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN and TiAlC.

13. The semiconductor structure of claim 1, wherein, The first channel layer is a first channel fin standing on the substrate; the first gate structure straddles the first channel fin and covers part of top and part of sidewall of the first channel fin; Alternatively, the first channel layer is on the substrate and spaced apart from the substrate, the first channel layer comprises one or more first sub-channel layers spaced apart; the first gate structure surrounds and covers the first sub-channel layer; The second channel layer is a second channel fin standing on the bonding layer; the second gate structure straddles the second channel fin and covers part of top and part of sidewall of the second channel fin; Alternatively, the second channel layer is on the bonding layer and spaced apart from the bonding layer, the second channel layer comprises two or more second sub-channel layers spaced apart; the second gate structure surrounds and covers the second sub-channel layer.

14. The semiconductor structure of claim 1, wherein, The material of the first channel layer comprises silicon, silicon germanium, germanium or group III-V semiconductor material; the material of the second channel layer comprises silicon, silicon germanium, germanium or group III-V semiconductor material.

15. The semiconductor structure of claim 1, wherein, The material of the bonding layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride and carbon-doped silicon oxide.

16. The semiconductor structure of claim 1, wherein, The material of the first gate medium layer comprises one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; the material of the second gate medium layer comprises one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; the material of the first gate electrode layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC; the material of the second gate electrode layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

17. A method of forming a semiconductor structure, comprising: Comprise: forming a lower device structure, comprising a first substrate, and a first N-type transistor and a first P-type transistor formed on the first substrate, the first N-type transistor and the first P-type transistor each comprising a first gate structure, a first source and a first drain respectively located on two sides of the first gate structure, and a first channel layer covered by the first gate structure and connecting the first source and the first drain in a direction parallel to a surface of the first substrate, the lower device structure having a bonding surface facing away from the first substrate; performing one or more device stacking processes to form one or more upper device structures stacked above the lower device structure in a direction of a normal of the surface of the first substrate, the device stacking process comprising: forming a bonding layer on the bonding surface; forming a second N-type transistor and a second P-type transistor on the bonding layer, the second N-type transistor and the second P-type transistor each comprising a second gate structure, a second source and a second drain respectively located on two sides of the second gate structure, and a second channel layer covered by the second gate structure and connecting the second source and the second drain in a direction parallel to a surface of the bonding layer; in the step of forming the lower device structure, the first N-type transistor and the first P-type transistor in the lower device structure are used to constitute a first inverter; in the process of the device stacking process, the second N-type transistor and the second P-type transistor in the upper device structure are used to constitute a second inverter, and the second inverter is used to realize series connection with the first inverter.

18. The method of forming a semiconductor structure of claim 17, wherein, The step of forming a bonding layer on the bonding surface comprises: bonding a second substrate on the bonding surface by using a bonding layer; The step of forming a second N-type transistor and a second P-type transistor on the bonding layer comprises: patterning the second substrate to form discrete second channel layers; forming a second gate structure covering the second channel layer, and a second source and a second drain on the bonding layer on two sides of the second gate structure.

19. The method of forming a semiconductor structure of claim 18, wherein, The first N-type transistor and the first P-type transistor share the first gate structure; the second N-type transistor and the second P-type transistor share the second gate structure; The forming method further comprises: before forming the upper device structure, forming a first drain interconnection line covering the top of the first drain, the first drain interconnection line connecting the first drains of the first P-type transistor and the first N-type transistor; After forming the second N-type transistor and the second P-type transistor, a second drain interconnection line covering the top of the second drain is formed, the second drain interconnection line connecting the second drains of the second N-type transistor and the second P-type transistor.

20. The method of forming a semiconductor structure of claim 19, wherein, In the process of the device stacking process, further comprising: after forming the bonding layer, before forming the second gate structure, forming a conductive pillar, the conductive pillar penetrating through the bonding layer on the top of the first drain interconnection line and located in the region where the second gate structure is to be formed; After forming the second gate structure, the conductive pillar is located between the top of the first drain interconnection line and the bottom of the second gate structure, and the conductive pillar is electrically connected with the first drain interconnection line and the second gate structure.

21. The method of forming a semiconductor structure of claim 20, wherein, In the process of the device stacking process, before forming the second gate structure, further comprising: in the region where the second gate structure is to be formed, forming a via penetrating through the bonding layer on the top of the first drain interconnection line, the via exposing the top of the first drain interconnection line; The step of forming the conductive pillar comprises: in the step of forming the second gate structure, the conductive material of the second gate structure also fills in the via, forming a conductive pillar in the via, and the two ends of the conductive pillar are electrically connected with the first drain interconnection line and the second gate structure respectively.

22. The method of forming a semiconductor structure of claim 19, wherein, The forming method further comprises: forming a first source plug on the top and sidewall of the second source of the second N-type transistor, the first source plug also penetrating downward through the bonding layer and extending to the top of the first source of the first N-type transistor, and the first source plug is electrically connected with the first source of the first N-type transistor; Forming a second source plug on the top and sidewall of the second source of the second P-type transistor, the second source plug also penetrating downward through the bonding layer and extending to the top of the first source of the first P-type transistor, and the second source plug is electrically connected with the first source of the first P-type transistor.

23. The method of forming a semiconductor structure of claim 19, wherein, The forming method further comprises: forming a gate plug penetrating through the bonding layer on the top of the first gate structure on the side of the second gate structure, and the gate plug is electrically connected with the first gate structure.

24. The method of forming a semiconductor structure of claim 22, wherein, In the step of forming the lower device structure, the lower device structure further comprises a first interlayer dielectric layer located on the first substrate and covering the sidewall of the first gate structure; In the step of forming the first drain interconnection line on the top of the first drain, the first drain interconnection line covering the top of the first drain is formed in the first interlayer dielectric layer, and the first interlayer dielectric layer exposes the top of the first drain interconnection line; In the step of forming the first source plug, the first source plug also penetrates a first interlayer dielectric layer corresponding to the first source top portion; In the step of forming the second source plug, the second source plug also penetrates a second interlayer dielectric layer corresponding to the second source top portion.

25. The method of forming a semiconductor structure of claim 22, wherein, In the step of performing the stacking process, further comprising: forming a second interlayer dielectric layer on the bonding layer, the second interlayer dielectric layer covering sidewalls of the second gate structure; In the step of forming the second drain interconnect line on the second drain top portion, forming a second drain interconnect line covering the second drain top portion in the second interlayer dielectric layer, the second interlayer dielectric layer exposing a top portion of the second drain interconnect line; In the step of forming the first source plug, the first source plug also penetrates a second interlayer dielectric layer corresponding to the second source top portion; In the step of forming the second source plug, the second source plug also penetrates a second interlayer dielectric layer corresponding to the second source top portion.

26. The method of forming a semiconductor structure of claim 17, wherein, In the step of forming the lower device structure, the type of the first channel layer includes one or more of a fin, a nanowire, and a nanosheet; In the step of forming the upper device structure, the type of the second channel layer includes one or more of a fin, a nanowire, and a nanosheet.

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