Power device, method of manufacture and vehicle

Abstract

The application discloses a power device, a preparation method and a vehicle, and relates to the technical field of power devices. The power device comprises a substrate, a central region of the substrate forms a cell structure, and a part of the substrate away from the central region forms a voltage-withstanding terminal; an edge position of the voltage-withstanding terminal is provided with a step part; and a first passivation layer is deposited on the step part, and ions are implanted in the first passivation layer to modulate a carrier distribution in the substrate at the voltage-withstanding terminal. The step part is arranged at the edge position of the voltage-withstanding terminal, the three-dimensional structure of the substrate is fully utilized, and the area of the voltage-withstanding terminal is reduced. The first passivation layer is deposited on the step part, and charged ions are implanted in the first passivation layer, so that the charged ions are pinned in the first passivation layer and cannot move with an applied electric field, and the purpose of modulating the carrier distribution in the substrate is achieved, and the effectiveness and stability of the voltage-withstanding of the voltage-withstanding terminal are effectively realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a power device, a method for fabricating the power device, and a vehicle having the power device. Background Technology

[0002] There are many types of power devices, including insulated-gate bipolar transistors (IGBTs), fast recovery diodes (FRDs), and metal-oxide-semiconductor field-effect transistors (MOSFETs), which are widely used in high-voltage, high-current industrial applications. These high-voltage semiconductor devices have vastly different structures, but for high-voltage, high-current applications, it is usually necessary to consider the voltage withstand capability of the structure.

[0003] Currently, the voltage withstand termination design of power devices in existing technologies is located on the top surface of the chip, which is a planar design and occupies a relatively large area. While reducing the area of ​​the planar voltage withstand termination, the structure of the planar voltage withstand termination becomes increasingly complex, posing challenges to reliability and limiting its withstand voltage performance. Summary of the Invention

[0004] One objective of this application is to provide a new technical solution for power devices and their fabrication methods, which can at least solve the problems of complex voltage-resistant terminal structures and limited voltage-resistant performance of power devices in the prior art.

[0005] According to a first aspect of this application, a power device is provided, comprising: a substrate including a cellular structure and a voltage-resistant terminal, wherein the cellular structure is formed in a central region of the substrate, and the voltage-resistant terminal is formed in a portion of the substrate away from the central region; a stepped portion is provided at the edge of the voltage-resistant terminal; and a first passivation layer deposited on the stepped portion, wherein ions are implanted in the first passivation layer to modulate the carrier distribution in the substrate at the voltage-resistant terminal.

[0006] Optionally, the substrate has a first surface and a second surface arranged opposite to each other in the thickness direction, the stepped portion extends obliquely between the first surface and the second surface, and the orthographic projection of the first surface onto the second surface covers the second surface.

[0007] Optionally, the first passivation layer is uniformly deposited on the step portion so that the shape of the first passivation layer corresponds to the shape of the step portion.

[0008] Optionally, the stepped portion is a plurality of continuous, smoothly transitioned steps, the plurality of steps extending obliquely in the thickness direction of the substrate, and a first passivation layer is uniformly deposited on each step.

[0009] Optionally, the amount of the first passivation layer deposited in the thickness direction of the substrate is different, so that the cross-sectional shape formed by the first passivation layer and the step portion is rectangular.

[0010] Optionally, the ions implanted in the first passivation layer are located near the boundary between the first passivation layer and the substrate.

[0011] Optionally, the substrate has a plurality of spaced trenches on the first surface, the plurality of trenches being located at the pressure-resistant terminal, and each of the trenches extending toward the second surface.

[0012] Optionally, the depth of each of the trenches gradually decreases in the direction away from the cell structure.

[0013] Optionally, each of the grooves corresponds to the position of one of the steps.

[0014] Optionally, a second passivation layer is deposited on the inner wall and bottom surface of each trench, and a conductive layer is deposited on the surface of the second passivation layer.

[0015] According to a second aspect of this application, a method for fabricating a power device is provided, for fabricating the power device described in the above embodiments, the method comprising:

[0016] A substrate is provided, wherein a cellular structure is formed in a central region of the substrate, and a voltage-resistant terminal is formed in a portion of the substrate away from the central region;

[0017] A stepped portion is provided at the edge of the pressure-resistant terminal;

[0018] A first passivation layer is deposited on the stepped portion;

[0019] Ions are implanted into the first passivation layer to modulate the carrier distribution in the substrate at the withstand voltage terminal.

[0020] Optionally, the preparation method further includes:

[0021] Multiple grooves are provided on the pressure-resistant terminal, spaced apart from each other on the first surface and extending toward the second surface, with the depth of each groove gradually decreasing in the direction away from the cellular structure;

[0022] A second passivation layer is deposited on the inner wall and bottom surface of each of the trenches;

[0023] A conductive layer is deposited on the surface of the second passivation layer.

[0024] According to a third aspect of this application, a vehicle is provided, including the power devices described in the above embodiments.

[0025] According to an embodiment of the power device of the present invention, a stepped portion is provided at the edge of the withstand voltage terminal to fully utilize the three-dimensional structure of the substrate and reduce the area of ​​the withstand voltage terminal. A first passivation layer is deposited on the stepped portion, and charged ions are injected into the first passivation layer so that the charged ions are pinned within the first passivation layer and do not move with the applied electric field, thus not affecting the migration of charge carriers in the cell structure. At the same time, it can attract the movement of charge carriers inside the substrate located at the withstand voltage terminal, control the potential inside the substrate to gradually decrease along the extension direction of the stepped portion, achieve the purpose of modulating the distribution of charge carriers inside the substrate, and effectively realize the withstand voltage effectiveness and stability of the withstand voltage terminal.

[0026] Other features and advantages of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the present application and, together with their description, serve to explain the principles of the present application.

[0028] Figure 1 This is a cross-sectional view of an existing power device;

[0029] Figure 2 This is yet another cross-sectional view of an existing power device;

[0030] Figure 3 This is a cross-sectional view of the power device of the present invention;

[0031] Figure 4 This is another cross-sectional view of the power device of the present invention;

[0032] Figure 5 This is another cross-sectional view of the power device of the present invention;

[0033] Figure 6 This is a flowchart illustrating the fabrication method of the power device according to the present invention.

[0034] Figure label:

[0035] Field limiting ring 1; floating field plate 2; field ring 3;

[0036] Power devices 100;

[0037] Cellular structure 10;

[0038] Withstand voltage terminal 20; Step portion 21; Step 211; First passivation layer 22; Trench 23; Second passivation layer 24; Conductive layer 25;

[0039] First surface 31; second surface 32. Detailed Implementation

[0040] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present application.

[0041] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this application and its application or use.

[0042] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0043] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0044] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0045] The power device 100 according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

[0046] like Figures 3 to 5 As shown, the power device 100 according to an embodiment of the present invention includes a substrate and a first passivation layer 22.

[0047] Specifically, the substrate includes a cell structure 10 and a voltage-resistant terminal 20. The cell structure 10 is formed in the central region of the substrate, and the voltage-resistant terminal 20 is formed in the portion of the substrate away from the central region. A step portion 21 is provided at the edge of the voltage-resistant terminal 20. A first passivation layer 22 is deposited on the step portion 21, and ions are implanted in the first passivation layer 22 to modulate the carrier distribution in the substrate at the voltage-resistant terminal 20.

[0048] In other words, the power device 100 according to an embodiment of the present invention mainly consists of a substrate and a first passivation layer 22. See also... Figure 3 The substrate includes a cell structure 10 and a voltage-resistant terminal 20. The cell structure 10 is located in the central region of the substrate, and the portion of the substrate away from the central region is the voltage-resistant terminal 20. Figures 3 to 5 This is a cross-sectional view of a portion of the structure of power device 100, where, see... Figure 3 With the dashed line as the boundary, the portion of the substrate to the left of the dashed line is the voltage-resistant structure 20 (e.g., Figure 3 The part to the right of the dashed line (as shown by the arrow pointing to the left) represents cell structure 10 (e.g., ...). Figure 3(As shown by the arrow pointing to the right). The withstand voltage termination 20 is located at the edge of the power device 100. The withstand voltage termination 20 should be understood as the portion away from the central region of the device relative to the central region. A stepped portion 21 is provided at the edge of the withstand voltage termination 20, which makes full use of the three-dimensional structure of the substrate. By constructing a three-dimensional stepped portion 21 at the edge of the substrate, the area of ​​the withstand voltage termination 20 is effectively reduced.

[0049] A first passivation layer 22 is deposited on the step portion 21. High-concentration ions can be injected into the first passivation layer 22, with the ion injection intensity determined by not penetrating the first passivation layer 22. By depositing the first passivation layer 22 on the step portion 21 and injecting charged ions into the first passivation layer 22, the charged ions are pinned within the first passivation layer 22 and do not move with the applied electric field. This does not affect the migration of charge carriers in the cell structure 10. At the same time, it can attract the movement of charge carriers inside the substrate located at the withstand voltage terminal 20, controlling the potential inside the substrate to gradually decrease along the extension direction of the step portion 21, thereby modulating the distribution of charge carriers inside the substrate and effectively achieving the effectiveness and stability of the withstand voltage terminal 20.

[0050] In this application, the substrate can be a semiconductor material such as silicon or silicon carbide. The first passivation layer 22 can be an insulating material such as silicon dioxide or silicon nitride. It should be noted that when ions are implanted into the first passivation layer 22, for an n-type semiconductor substrate, the implanted ions are p-type implanted. For a p-type semiconductor substrate, the implanted ions are n-type implanted. For example, boron or indium is implanted into an n-type silicon structure. The ions implanted in the first passivation layer 22 cannot move with the applied electric field, but they will attract the charge carriers inside the chip at the voltage withstand terminal 20, change the charge carrier distribution at the chip edge, and at the same time, do not affect the migration of charge carriers in the chip at the cell structure 10, thereby guiding the potential inside the chip at the voltage withstand terminal 20 to gradually decrease along the step 21 direction, improving the voltage withstand capability of the voltage withstand terminal 20.

[0051] The power device 100 of this application can be widely used in high-voltage, high-current industrial applications. In the prior art, the voltage-resistant terminals 20 are all located on the top surface of the chip, which is basically a planar design and occupies a relatively large area. Reducing the area of ​​the planar terminals inevitably leads to a more complex structure, and the voltage resistance and reliability are greatly challenged.

[0052] Currently, see Figure 1 and Figure 2 The field limiting ring 1, the floating field plate 2, and the terminal extension structure are commonly used structural designs for the pressure-resistant terminal 20. Among them, such as... Figure 1As shown, field-limiting ring 1 is a series of identical doped ring structures designed around the cell structure 10 of power device 100. As the number of field-limiting rings 1 increases, the breakdown voltage of the voltage-delayed terminal 20 increases accordingly. However, the relationship between them is not linear. When the number of field-limiting rings 1 increases to a certain point, the breakdown voltage of the voltage-delayed terminal 20 reaches its peak and no longer increases. The advantages of field-limiting ring 1 are its simple structure and good compatibility with current semiconductor device processes. However, due to the limited breakdown voltage of a simple field-limiting ring 1 design, it is now rarely used alone, but rather more often used in conjunction with other breakdown voltage structures.

[0053] Floating field plate 2 is another common pressure-resistant structural design. Figure 1 The scheme combining field limiting ring 1 and floating field plate 2 is shown; see [link / reference]. Figure 1 The field plate, made of metal, typically extends along the edge of the doped structure, thereby expanding the electric field lines that contract at the edge of the cell structure 10 and avoiding electric field peaks at the edge of the cell main junction. An oxide layer (which can have a gradually varying thickness) needs to be added between the floating field plate 2 and the semiconductor material to improve the withstand voltage of the voltage-delay terminal 20. The main drawback of the field plate technology is that a large potential difference exists between the metal and silicon surfaces at the field plate edge, leading to a peak electric field between the metal field plate and the silicon material. When the peak electric field is high enough, it can break down the oxide layer between them, causing the field plate to fail.

[0054] See Figure 2 The terminal extension structure involves adding a series of overlapping field rings 3 along the edge of the cell structure 10. The doping depth of these field rings 3 gradually decreases as they move away from the center of the chip, thereby guiding the internal potential of the terminal structure to gradually decrease and preventing the peak electric field within the structure from exceeding a threshold. The disadvantage of this design is that it requires multiple mask exposures and hydrazine removal, increasing the complexity and cost of existing semiconductor device processes.

[0055] Compared to the planar structure of existing technologies where the terminal structure is typically located on the top surface of the chip, this application fully utilizes the three-dimensional structure of the chip to reduce the area of ​​the voltage-resistant terminal 20. By performing ion implantation and pinning on the three-dimensional structure at the chip edge, the change in the chip edge potential can be adjusted more directly than the traditional method of adjusting the potential only on the chip surface.

[0056] Therefore, in the power device 100 according to an embodiment of the present invention, a step portion 21 is provided at the edge of the voltage withstand terminal 20, making full use of the three-dimensional structure of the substrate and reducing the area of ​​the voltage withstand terminal 20. A first passivation layer 22 is deposited on the step portion 21, and charged ions are injected into the first passivation layer 22, so that the charged ions are pinned in the first passivation layer 22 and do not move with the applied electric field, thus not affecting the migration of charge carriers in the cell structure 10. At the same time, it can attract the movement of charge carriers inside the substrate located at the voltage withstand terminal 20, control the potential inside the substrate to gradually decrease along the extension direction of the step portion 21, achieve the purpose of modulating the distribution of charge carriers inside the substrate, and effectively realize the voltage withstand effectiveness and stability of the voltage withstand terminal 20.

[0057] According to one embodiment of the present invention, the substrate has a first surface 31 and a second surface 32 arranged opposite to each other in the thickness direction, a stepped portion 21 extending obliquely between the first surface 31 and the second surface 32, and the orthographic projection of the first surface 31 onto the second surface 32 covers the second surface 32.

[0058] In other words, such as Figure 3 As shown, the substrate has a first surface 31 and a second surface 32 arranged opposite to each other in the thickness direction. Taking the substrate as a chip as an example, the central region of the chip (the central region of the power device 100) is a cell structure 10, and the part of the chip away from the central region (the edge position of the power device 100) is a voltage withstand terminal 20. A step portion 21 is processed at the edge position of the chip (the edge position of the voltage withstand terminal 20). The step portion 21 extends obliquely in the thickness direction of the substrate, and after the step portion 21 is processed, the orthographic projection of the first surface 31 of the chip onto the second surface 32 covers the second surface 32. That is, the oblique extension direction of the step portion 21 is from the first surface 31 toward the central region of the substrate. Furthermore, the steps in the step portion 21 of this application have smooth transitions between each step, ensuring that the structure of the step portion 21 is relatively smooth and avoiding abrupt changes or sharp corners. By setting a step portion 21 that extends obliquely toward the central region of the substrate at the edge of the substrate, and designing a step structure that extends obliquely in the thickness direction of the chip at the edge of the chip, the structure of the voltage withstand terminal 20 is made three-dimensional, reducing the area of ​​the voltage withstand terminal 20. By depositing a first passivation layer 22 on the step portion 21 and injecting a high concentration of ions into the first passivation layer 22, the carrier distribution near the chip edge can be changed, thereby guiding the potential inside the chip to gradually decrease along the step direction, controlling the stable change of the potential at the bottom of the chip, and ensuring that the voltage-resistant terminal 20 has high voltage resistance and stability.

[0059] In some specific embodiments of this application, the first passivation layer 22 is uniformly deposited on the step portion 21 so that the shape of the first passivation layer 22 corresponds to the shape of the step portion 21.

[0060] Alternatively, the amount of the first passivation layer 22 deposited in the thickness direction of the substrate may be different, so that the cross-sectional shape formed by the first passivation layer 22 and the step portion 21 is rectangular.

[0061] In other words, in this application, as Figure 3 and Figure 5 As shown, the first passivation layer 22 can be uniformly deposited on the step portion 21. The first passivation layer 22 is composite on the surface of the step portion 21, so that the shape of the first passivation layer 22 corresponds to that of the step portion 21. The thickness of the first passivation layer 22 can be 100-200 nm. In this application, the deposition amount of the first passivation layer 22 in the thickness direction of the substrate can also be different. By increasing the deposition amount of the first passivation layer 22 in the step portion 21, the outline of the step portion 21 at the edge of the chip is filled (see...). Figure 4 This ensures that the first passivation layer 22 is flush with the surface of the chip's cell structure 10. After the first passivation layer 22 is deposited, the overall structure of the chip is more complete, and the cross-sectional shape formed by the first passivation layer 22 and the step portion 21 is rectangular. By increasing the deposition amount of the first passivation layer 22 at the step portion 21, the shape of the step portion 21 at the edge of the chip is filled, which can further improve the structural stability of the power device 100, enhance the strength of the chip surface, and prevent cracks from appearing in the chip during processing.

[0062] In this application, the step portion 21 comprises multiple continuously and smoothly transitioning steps 211, which extend obliquely in the thickness direction of the substrate. A first passivation layer 22 is uniformly deposited on each step 211. By providing multiple continuously and smoothly transitioning steps 211 extending obliquely towards the central region of the substrate at the edge of the substrate, and by extending obliquely along the chip edge in the chip thickness direction, the structure of the voltage withstand terminal 20 is made three-dimensional, reducing the area of ​​the voltage withstand terminal 20. By depositing the first passivation layer 22 on the steps 211 and injecting a high concentration of ions into the first passivation layer 22, the carrier distribution near the chip edge can be changed, thereby guiding the potential inside the chip to gradually decrease along the direction of the steps 211, controlling the smooth change of the potential at the bottom of the chip, and ensuring that the voltage withstand terminal 20 has high voltage withstand capability and stability.

[0063] According to one embodiment of the present invention, the ions implanted in the first passivation layer 22 are located near the boundary between the first passivation layer 22 and the substrate.

[0064] In other words, see Figures 3 to 5When implanting high-concentration ions into the first passivation layer 22, the ion implantation intensity needs to be such that it does not penetrate the first passivation layer 22, for example, the silicon dioxide layer, but can be as close as possible to the boundary between the first passivation layer 22 and the substrate. For n-type semiconductor materials (substrates), the implanted ions need to be p-type implanted, for example, boron, indium, etc., implanted in an n-type silicon structure; and vice versa. Ions implanted in the oxide (first passivation layer 22 of silicon dioxide) cannot move with the applied electric field, but they will attract charge carriers inside the chip, change the charge carrier distribution near the chip edge, thereby guiding the potential inside the chip to gradually decrease along the extension direction of step 211, realizing the function of the terminal structure.

[0065] In some specific embodiments of the present invention, a plurality of spaced trenches 23 are provided on the first surface 31 of the substrate. The plurality of trenches 23 are located at the withstand voltage terminal 20, and each trench 23 extends toward the second surface 32. The depth of each trench 23 gradually decreases in the direction away from the cell structure 10. A second passivation layer 24 is deposited on the inner wall surface and the bottom surface of each trench 23, and a conductive layer 25 is deposited on the surface of the second passivation layer 24.

[0066] In other words, see Figure 5 This application allows for the formation of multiple trenches 23 along the top edge of the chip. These trenches 23 are located in the region of the voltage-bearing termination 20 of the chip, and each trench 23 extends along the thickness direction of the chip. The trenches 23 are spaced apart on the chip. The trenches 23 are formed on the edge structure of the chip's top surface (the region of the voltage-bearing termination 20), and the edges of the trenches 23 should avoid abrupt structural changes or sharp corners. The shape of the trenches 23 can be rectangular, trapezoidal, or any other shape. By forming trenches 23 on the top surface of the chip, the distorted electric field of the cell structure 10 can be interrupted, forcing a smooth change in the potential at the top of the chip, thus ensuring that the power device 100 has better efficiency and voltage-bearing stability.

[0067] The depth of each trench 23 gradually decreases in the direction away from the cell structure 10. By digging trenches 23 with varying depths at the top edge of the chip, the withstand voltage capability of the three-dimensional voltage-resistant terminal 20 can be further enhanced, which helps in the engineering implementation of the power device 100.

[0068] Optionally, each trench 23 corresponds to the position of a step 211. The deeper the trench 23, the closer the step 211 is to the bottom of the chip, and the shallower the trench 23, the closer the step 211 is to the top of the chip. This helps to ensure that the potential trend in the chip is closer to the trend of the step 211 with a continuous and smooth transition, and forces the potential change at the top of the chip to be smoother, thus ensuring that the power device 100 has better effectiveness and withstand voltage stability.

[0069] In this application, as Figure 5As shown, a second passivation layer 24 is deposited on both the inner wall and bottom surface of each trench 23. The second passivation layer 24 can be silicon dioxide, silicon nitride, etc. The thickness of the second passivation layer 24 can be 70-120 nm. A conductive layer 25 can be deposited on the surface of the second passivation layer 24. The conductive layer 25 can be made of polysilicon or metal as the conductive material. After the conductive layer 25 is deposited, the material deposited on the chip surface can be etched and trimmed.

[0070] This application adopts a combination of carrier modulation within the chip and distortion electric field smoothing to design a three-dimensional withstand voltage terminal 20, which makes the withstand voltage terminal 20 more effective and has better withstand voltage stability.

[0071] In some specific embodiments of this application, besides using a semiconductor material (e.g., silicon) as a substrate to fabricate the voltage-resistant terminal 20 on a silicon material (chip), this application is not limited to the process of using a semiconductor material (e.g., silicon) as a substrate. In this application, a passivation layer material (e.g., silicon dioxide) can also be used as a substrate, with the voltage-resistant terminal 20 first fabricated on silicon dioxide, and then the corresponding semiconductor device fabricated on silicon dioxide.

[0072] Of course, other structures and working principles of the power device 100 are understandable and achievable by those skilled in the art, and will not be described in detail in this application.

[0073] In summary, the power device 100 according to the present invention can be designed with a three-dimensional withstand voltage termination 20 by combining the modulation of charge carriers inside the chip with the smoothing of the distorted electric field. A step portion 21 is provided at the edge of the withstand voltage termination 20 to fully utilize the three-dimensional structure of the substrate and reduce the area of ​​the withstand voltage termination 20. A first passivation layer 22 is deposited on the step portion 21, and charged ions are injected into the first passivation layer 22, causing the charged ions to be pinned within the first passivation layer 22 and not move with the applied electric field, thus not affecting the migration of charge carriers in the cell structure 10. Simultaneously, it can attract the movement of charge carriers inside the substrate located at the withstand voltage termination 20, controlling the potential inside the substrate to gradually decrease along the extension direction of the step portion 21, achieving the purpose of modulating the distribution of charge carriers inside the substrate, and effectively realizing the withstand voltage effectiveness and stability of the withstand voltage termination 20. By providing a trench 23 on the top surface of the chip, the distorted electric field of the cell structure 10 can be interrupted, forcing a smooth change in the potential at the top of the chip, ensuring that the power device 100 has better effectiveness and withstand voltage stability.

[0074] According to a second aspect of this application, a method for fabricating a power device 100 is also provided, for fabricating the power device 100 in the above embodiments, such as... Figure 6 As shown, the preparation method includes:

[0075] S1. A substrate is provided, wherein a cell structure 10 is formed in the central region of the substrate, and a voltage-resistant terminal 20 is formed in the portion of the substrate away from the central region.

[0076] S2. A step portion 21 is provided at the edge of the pressure-resistant terminal 20;

[0077] S3. Deposit a first passivation layer 22 on the step portion 21;

[0078] S4. Ions are implanted in the first passivation layer 22 to modulate the carrier distribution in the substrate at the voltage-resistant terminal 20.

[0079] Specifically, see Figure 6 In the fabrication method of the power device 100 of the present invention, firstly, a substrate, such as a silicon wafer or other silicon or silicon carbide materials, can be provided. A cell structure 10 is formed in the central region of the substrate, and a voltage withstand terminal 20 is formed in the portion of the substrate away from the central region. Then, a step portion 21 is provided at the edge of the voltage withstand terminal 20, and the inclined extension direction of the step portion 21 is from the first surface 31 toward the central region of the substrate, thereby obtaining a three-dimensional voltage withstand terminal 20 fabricated on the chip. In this application, the steps in the step portion 21 are smoothly transitioned between each step, ensuring that the structure of the step portion 21 is relatively smooth and avoiding abrupt changes or sharp corners. By providing a step portion 21 that extends obliquely toward the central region of the substrate at the edge of the substrate, and designing a step structure that extends obliquely in the chip thickness direction at the edge of the chip, the structure of the voltage withstand terminal 20 is made three-dimensional, and the area of ​​the voltage withstand terminal 20 is reduced.

[0080] Next, as Figure 3 and Figure 4 As shown, a first passivation layer 22 is deposited on the step portion 21. The material of the first passivation layer 22 can be an insulating material such as silicon dioxide or silicon nitride. Finally, a high concentration of ions is implanted into the first passivation layer 22. When implanting a high concentration of ions into the first passivation layer 22, the ion implantation intensity needs to not penetrate the first passivation layer 22, for example, the silicon dioxide layer, but can be as close as possible to the boundary between the first passivation layer 22 and the substrate. For n-type semiconductor materials (substrate), the implanted ions need to be p-type implanted, for example, boron, indium, etc., implanted in an n-type silicon structure; and vice versa. Ions implanted in the oxide (silicon dioxide first passivation layer 22) cannot move with the applied electric field, pinning the ions in the first passivation layer 22. However, the ions implanted in the first passivation layer 22 will attract charge carriers inside the chip, changing the charge carrier distribution near the chip edge, thereby guiding the potential inside the chip to gradually decrease along the step direction, ensuring that the voltage-resistant terminal 20 has high voltage resistance and stability.

[0081] According to one embodiment of the present invention, the preparation method further includes:

[0082] Multiple grooves 23 are provided on the pressure-resistant terminal 20, which are spaced apart on the first surface 31 and extend toward the second surface 32. The depth of each groove 23 gradually decreases in the direction away from the cell structure 10.

[0083] A second passivation layer 24 is deposited on the inner wall and bottom surface of each trench 23;

[0084] A conductive layer 25 is deposited on the surface of the second passivation layer 24.

[0085] In other words, in the preparation method of this application, such as Figure 5 As shown, multiple trenches 23 can also be formed on the top edge of the chip. These trenches 23 are located in the region of the voltage-bearing termination 20 of the chip, and each trench 23 extends along the thickness direction of the chip. The trenches 23 are spaced apart on the chip. The trenches 23 are dug into the edge structure of the top surface of the chip (the region of the voltage-bearing termination 20), and the edges of the trenches 23 should avoid abrupt structural changes or sharp corners. The shape of the trenches 23 can be rectangular, trapezoidal, or any other shape. By forming trenches 23 on the top surface of the chip, the distorted electric field of the cell structure 10 can be interrupted, forcing a smooth change in the potential at the top of the chip, ensuring that the power device 100 has better efficiency and voltage-bearing stability.

[0086] Each trench 23 has a second passivation layer 24 deposited on its inner wall and bottom surface. The second passivation layer 24 can be silicon dioxide, silicon nitride, etc. The thickness of the second passivation layer 24 can be 70-120 nm. A conductive layer 25 can be deposited on the surface of the second passivation layer 24. The conductive layer 25 can be made of polysilicon or metal. After the conductive layer 25 is deposited, the material deposited on the chip surface can be etched and trimmed.

[0087] This application adopts a combination of carrier modulation within the chip and distortion electric field smoothing to design a three-dimensional withstand voltage terminal 20. The overall process is simple, and the withstand voltage terminal 20 has better effectiveness and withstand voltage stability.

[0088] Of course, in some specific embodiments of this application, besides using a semiconductor material (e.g., silicon) as a substrate to fabricate the voltage-resistant terminal 20 on a silicon material (chip), this application may also be limited to processes using a semiconductor material (e.g., silicon) as a substrate. In this application, the processes for fabricating the voltage-resistant terminal 20 on substrates of two different materials are basically the same. For example, using a passivation layer (e.g., silicon dioxide) as a substrate, the voltage-resistant terminal 20 is first fabricated on silicon dioxide, and then the corresponding semiconductor device is fabricated on silicon dioxide.

[0089] In summary, the fabrication method of the power device 100 of this application can be achieved by combining the modulation of charge carriers inside the chip with the smoothing of the distorted electric field to fabricate a three-dimensional withstand voltage terminal 20. A step portion 21 is provided at the edge of the withstand voltage terminal 20 to fully utilize the three-dimensional structure of the substrate and reduce the area of ​​the withstand voltage terminal 20. A first passivation layer 22 is deposited on the step portion 21, and charged ions are injected into the first passivation layer 22. These charged ions are pinned within the first passivation layer 22 and do not move with the applied electric field, thus not affecting the migration of charge carriers in the cell structure 10. Simultaneously, they can attract the movement of charge carriers inside the substrate located at the withstand voltage terminal 20, controlling the potential inside the substrate to gradually decrease along the extension direction of the step portion 21, thereby modulating the distribution of charge carriers inside the substrate and effectively achieving the withstand voltage effectiveness and stability of the withstand voltage terminal 20. By setting trenches 23 on the top surface of the chip, the distorted electric field of the cell structure 10 can be cut off, forcing a smooth change in the potential at the top of the chip, thus ensuring that the power device 100 has better efficiency and voltage withstand stability.

[0090] According to a third aspect of this application, a vehicle is provided, including the power device 100 in the above embodiments. Since the power device 100 according to the embodiments of the present invention has the above-described technical effects, the vehicle according to the embodiments of the present invention should also have corresponding technical effects; that is, the vehicle of this application, by employing the power device 100, can possess better efficiency and pressure resistance stability.

[0091] Of course, other structures and working principles of the vehicle are understandable and achievable by those skilled in the art, and will not be described in detail in this application.

[0092] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.

Claims

1. A power device, characterized in that, include: A substrate comprising a cellular structure and a voltage-resistant terminal, wherein the cellular structure is formed in a central region of the substrate, and the voltage-resistant terminal is formed in a portion of the substrate away from the central region; a stepped portion is provided at the edge of the voltage-resistant terminal; A first passivation layer is deposited on the stepped portion, and ions are implanted in the first passivation layer to modulate the carrier distribution in the substrate at the withstand voltage terminal. The substrate has a first surface and a second surface arranged opposite to each other in the thickness direction, the stepped portion extends obliquely from the first surface to the second surface, and the orthographic projection of the first surface onto the second surface covers the second surface.

2. The power device according to claim 1, characterized in that, The first passivation layer is uniformly deposited on the step portion so that the shape of the first passivation layer corresponds to the shape of the step portion.

3. The power device according to claim 1, characterized in that, The stepped portion consists of multiple continuous, smoothly transitioned steps, which extend obliquely in the thickness direction of the substrate, and a first passivation layer is uniformly deposited on each step.

4. The power device according to claim 1, characterized in that, The first passivation layer is deposited in different amounts in the thickness direction of the substrate so that the cross-sectional shape formed by the first passivation layer and the step portion is rectangular.

5. The power device according to claim 2 or 4, characterized in that, The ions implanted in the first passivation layer are located near the boundary between the first passivation layer and the substrate.

6. The power device according to claim 3, characterized in that, The substrate has a plurality of spaced trenches on the first surface, the plurality of trenches being located within the voltage-resistant terminal, and each trench extending toward the second surface.

7. The power device according to claim 6, characterized in that, The depth of each trench gradually decreases in the direction away from the cell structure.

8. The power device according to claim 6, characterized in that, Each of the grooves corresponds to the position of one of the steps.

9. The power device according to claim 6, characterized in that, Each of the trenches has a second passivation layer deposited on its inner wall and bottom surface, and a conductive layer is deposited on the surface of the second passivation layer.

10. A method for fabricating a power device, used to fabricate the power device according to any one of claims 1-9, characterized in that, The preparation method includes: A substrate is provided, wherein a cellular structure is formed in a central region of the substrate, and a voltage-resistant terminal is formed in a portion of the substrate away from the central region; A stepped portion is provided at the edge of the pressure-resistant terminal; A first passivation layer is deposited on the stepped portion; Ions are implanted into the first passivation layer to modulate the carrier distribution in the substrate at the withstand voltage terminal.

11. The method for fabricating a power device according to claim 10, characterized in that, The preparation method further includes: Multiple grooves are provided on the pressure-resistant terminal, spaced apart from each other on the first surface and extending toward the second surface, with the depth of each groove gradually decreasing in the direction away from the cellular structure; A second passivation layer is deposited on the inner wall and bottom surface of each of the trenches; A conductive layer is deposited on the surface of the second passivation layer.

12. A vehicle, characterized in that, The power device includes any one of claims 1-9.

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