Stepped cathode emitter reverse blocking double-ended solid thyratron and its preparation method

Abstract

This invention discloses a stepped cathode-emitter reverse blocking double-ended solid-state thyristor and its fabrication method. The double-ended solid-state thyristor has a four-layer PNPN structure, with Al electrodes on both the cathode and anode sides; the N on the cathode side... + The emitter has a stepped structure with n steps. Along the direction from the first step to the nth step, the junction depth increases with each step, and the concentration gradually decreases at the deeper junction. The emitter P on the anode side... + Doping concentration of 1×10 14 cm ‑3 ~1×10 21 cm ‑3 The depth is 35μm to 100μm, and there are tens of thousands of short-circuit points with diameters of 200μm to 300μm on the cathode side; when n is 3, the doping concentration of the first step is 1×10. 19 cm ‑3 ~1×10 21 cm ‑3 The junction depth is 12μm to 20μm, and the doping concentration of the second-stage step is 1×10⁻⁶. 17 cm ‑3 ~1×10 21 cm ‑3 Its junction depth is 17μm to 25μm, and the doping concentration of the third step is 8×10⁻⁶. 16 cm ‑3 ~1×10 21 cm ‑3 The junction depth is 21μm to 29μm. The stepped cathode-emitter RBDT increases the voltage drop at the nth step cathode by diffusing the cathode-emitter n times. This increases the turn-on area of ​​the RBDT chip under the same dv / dt trigger pulse, thereby increasing the di / dt withstand capability of the RBDT chip.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of pulse power technology, and more particularly relates to a step-shaped cathode emitter reverse blocking two-terminal solid-state thyratron and a preparation method. BACKGROUND

[0002] Pulse power technology was born in the 1960s, which is an electrical physical technology that stores energy at a lower power and transforms it into pulsed electromagnetic energy at a much higher power and releases it to a specific load, and is also an electrical energy conversion technology. Modern pulse power technology has a wide range of applications in electromagnetic emission, light sources, environmental protection, materials, biology, medicine and other fields. Similar to a generation of power electronic devices determining a generation of power electronic circuits, the pulse power switch is also the bottleneck of the entire pulse power system, and the level that the switch can reach directly affects the key indicators such as pulse amplitude, rise time and repetition frequency of the entire system output.

[0003] Reverse blocking diode thyristor (RBDT) is a new type of semiconductor pulse power switch invented by the United States in the 1970s for radar modulators. The RBDT device was originally named reverse switching rectifier (RSR). RBDT device and another semiconductor device-gate turn-off thyristor have similar structures, both of which are PNPN four-layer structures and can be prepared by diffusion technology, but RBDT needs to be triggered by a high dv / dt voltage pulse, and the maximum current rise rate (di / dt) tolerance can reach 5kA / μs. Researchers have optimized the design of the cathode short-circuit point and the emitter and P base region, and the di / dt tolerance has reached 18kA / μs. However, the opening of RBDT is a diffusion process from the four corners to the middle, and when the dv / dt is insufficient, the opening area of RBDT is small, only in the four corners of the RBDT chip, thereby affecting the di / dt tolerance of the RBDT current rise rate, and in the worst case, the RBDT is damaged due to excessive local heating. SUMMARY

[0004] In view of the defects of the prior art, the purpose of the present application is to provide a step-shaped cathode emitter reverse blocking two-terminal solid-state thyratron, which aims to solve the problems of small opening area of conventional RBDT, insufficient di / dt tolerance of RBDT current rise rate and low chip current carrying capacity.

[0005] The present application provides a step-shaped cathode emitter reverse blocking two-terminal solid-state thyratron, which is a four-layer PNPN structure, and Al electrodes are arranged on the cathode side and the anode side; the N +The emitter is a stepped structure, and has n steps, and the junction depth of each step is deeper and the concentration at the junction depth is gradually reduced along the direction from the first step to the n-th step; the emitter P + The doping concentration is 1×10 14 cm -3 ~1×10 21 cm -3 , the depth is 35μm~100μm, and thousands of short-circuit points with a diameter of 200μm~300μm are arranged on the cathode side; n is a positive integer greater than or equal to 2.

[0006] Further, when n is 3, the doping concentration of the first step is 1×10 19 cm -3 ~1×10 21 cm -3 , the junction depth is 12μm~20μm, the doping concentration of the second step is 1×10 17 cm -3 ~1×10 21 cm -3 , the junction depth is 17μm~25μm, and the doping concentration of the third step is 8×10 16 cm -3 ~1×10 21 cm -3 , the junction depth is 21μm~29μm.

[0007] The doping concentration of the P base region is 1×10 14 cm -3 ~1×10 19 cm -3 , the depth is 35μm~100μm, and the doping concentration of the N base region is 2×10 13 cm -3 ~1×10 14 cm -3 , the depth is 100μm~400μm.

[0008] The width of the groove is 400μm~2000μm, and the depth is 40μm~200μm.

[0009] The application further provides a method for preparing the stepped cathode emitter reverse blocking double-end solid-state thyratron, which comprises the following steps:

[0010] S1: a single-face diffusion groove is formed on an N-type single crystal Si sheet by using a laser, and a PNP structure is formed by diffusion treatment;

[0011] S2: a cathode N+ emitter with n steps is formed by multiple diffusion and ion implantation treatments;

[0012] S3: The anode emitter is subjected to diffusion treatment again to improve the anode emitter injection efficiency;

[0013] S4: Grooving is performed on the cathode side of the RBDT to form a termination structure, which improves the device withstand voltage and protects the RBDT with the termination structure.

[0014] S5: Cut Si wafers according to requirements, and form a stepped cathode emitter reverse blocking double-ended solid thyristor after sintering and coating.

[0015] Furthermore, step S2 specifically includes:

[0016] S21 forms the first step N on the cathode side through oxidation, etching, and diffusion. + emitter;

[0017] S22 is obtained through secondary oxidation, etching, and diffusion in the first stage N. + A second step N is formed on the cathode side of the emitter. + emitter;

[0018] S23 adjusts the junction depth and the concentration at the junction depth of the second step through ion implantation;

[0019] S24 is obtained through a three-stage oxidation, etching, and diffusion process in the second stage N. + A third step N is formed on the cathode side of the emitter. + emitter;

[0020] S25 adjusts the junction depth and the concentration at the junction depth of the third step through ion implantation;

[0021] S26 undergoes n oxidation, etching, and diffusion processes at step (n-1) N. + The nth step N is formed on the cathode side of the emitter. + emitter;

[0022] S27 adjusts the junction depth and junction depth concentration of the nth step through ion implantation.

[0023] Among these methods, the injected ions are subjected to high-temperature annealing to activate them and eliminate lattice damage.

[0024] Furthermore, step S4 specifically includes:

[0025] The (n+1)th oxidation process is performed on the surface of the Si wafer to form a SiO2 masking layer.

[0026] Wide grooves are etched around the outer edge of the cathode.

[0027] A silicon dioxide protective film is formed at low temperatures;

[0028] The above-mentioned slot is protected by glass passivation.

[0029] The width of the wide slot is 400-2000 microns, and the depth is 40-200 microns.

[0030] Compared with the prior art, the step-shaped cathode emitter structure adopted by the present application can increase the part of the cathode emitter of the step-shaped cathode emitter RBDT that is above the PN junction Vbi potential under the same dv / dt trigger voltage pulse, thereby increasing the opening area. With the increase of the chip area, the potential in the center of the conventional RBDT cathode emitter gradually decreases, thereby continuously reducing the opening area. Only the part around the chip can be first opened, and even the problem that only part of the chip area can flow current can occur, thereby causing waste of the chip area. The step-shaped cathode emitter structure adopted by the present application can effectively increase the opening area of the RBDT, and can make the opening area of the step-shaped cathode emitter RBDT close to 100%, thereby increasing the di / dt tolerance of the device. Since a larger area of the cathode emitter can be opened, the RBDT can be increased, thereby making the RBDT work at a higher voltage and generate a larger peak current pulse. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 Fig. 1 is a schematic diagram of a cell of a step-shaped cathode emitter RBDT;

[0032] Figure 2 Fig. 2 is a schematic diagram of a cell of a step-shaped cathode emitter RBDT with a cathode voltage-resistant slot;

[0033] Figure 3 Fig. 3 is a P-base potential distribution result of a step-shaped cathode emitter RBDT and a conventional RBDT under a trigger voltage pulse;

[0034] Figure 4 Fig. 4 is a current density distribution result of a step-shaped cathode emitter RBDT and a conventional RBDT when the current is 170A;

[0035] Figure 5 Fig. 5 is a current density distribution result of a step-shaped cathode emitter RBDT and a conventional RBDT when the current is a peak current. DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0037] This invention provides a novel RBDT structure with a large open-circuit area, which solves the problems of small open-circuit area, insufficient current rise rate tolerance, and low chip current carrying capacity of conventional RBDTs. The stepped cathode-emitter reverse blocking double-ended solid-state thyristor provided by this invention is a semiconductor switch with a four-layer PNPN structure. Both the anode and cathode sides of this switch have Al electrodes; the cathode side of the switch has N... + The emitter is stepped, with a total of n steps. The doping concentration of the first step is 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 The junction depth is 12μm to 20μm, and the doping concentration of the second-stage step is 1×10⁻⁶. 17 cm -3 ~1×10 21 cm -3 Its junction depth is 17μm to 25μm, and the doping concentration of the third step is 8×10⁻⁶. 16 cm -3 ~1×10 21 cm -3 The junction depth ranges from 21 μm to 29 μm, with each step increasing the junction depth and the concentration gradually decreasing at the deeper junctions; the doping concentration in the P-base region is 1 × 10⁻⁶. 14 cm -3 ~1×10 19 cm -3 The depth is 35μm to 100μm, and the N-based region doping concentration is 2×10⁻⁶. 13 cm -3 ~1×10 14 cm -3 The depth is 100μm to 400μm, and the emitter P on the anode side is... + Doping concentration of 1×10 14 cm -3 ~1×10 21 cm -3 The depth is 35μm to 100μm, and there are tens of thousands of short-circuit points with a diameter of 200μm to 300μm on the cathode side.

[0038] The specific steps of the above-mentioned method for fabricating a semiconductor pulse power switch include:

[0039] S1: A single-sided diffusion groove is opened on an N-type single-crystal Si wafer using a laser, and the diffusion process is used to form a PNP structure.

[0040] Step S1 specifically involves:

[0041] (1) Single crystal (alkali corrosion): Clean the N-type Si wafer with a thickness of 400μm to 5000μm with cleaning solution for 5min to 30min;

[0042] (2) Laser grooving: Laser is used to groove one side of the chip. The groove is square, with a depth of 350μm to 4250μm and a width of 80μm to 400μm.

[0043] (3) Closed-tube diffusion of impurities (forming a through-hole): Diffusion of light impurities (Al, B, Ga or other positively charged impurities) is carried out on the cleaned N-type Si wafer to increase the surface and bulk concentration and form a PNP structure.

[0044] (4) Anode thinning: Chemical etching is performed to thin the anode until the anode thickness is 55-100μm, thereby reducing the emitter resistance;

[0045] (5) Closed-tube diffusion of impurities: The P region is then diffused with positive ion impurities (Al, B, Ga or other impurities with positive ions) to increase the surface concentration.

[0046] S2: Multiple diffusion and ion implantation processes are used to form a stepped cathode N+ emitter;

[0047] Step S2 includes:

[0048] S21 forms the first step N on the cathode side through oxidation, etching, and diffusion. + Emitter; specifically:

[0049] Primary oxidation: A SiO2 masking layer is formed on the surface of the Si wafer described above;

[0050] First etching of the cathode emitter area: The pattern of the first photomask is transferred to the Si wafer cathode, so that a photoresist protective film is formed on the cathode emitter;

[0051] Degumming: Removing N + Photoresist at the emitter;

[0052] Etching: Remove the SiO2 layer from areas without photoresist protection;

[0053] Phosphorus pre-expansion + main expansion: forming the first step N on the cathode side + Emitter, concentration 1×10 19 -1×10 21 cm -3 ;

[0054] S22 is obtained through secondary oxidation, etching, and diffusion in the first stage N.+ Forming the second step N on the cathode side of the emitter + The emitter; in particular:

[0055] Second oxidation: forming a SiO2 layer mask on the surface of the Si wafer;

[0056] Second lithography of the cathode emission area: transferring the pattern of the second lithography plate to the cathode of the Si wafer, so that a photoresist protective film is formed on the cathode emitter;

[0057] Photoresist removal: removing the photoresist on the emitter where the second diffusion is needed;

[0058] Etching: removing the SiO2 layer without photoresist protection;

[0059] Second phosphorus pre-diffusion + main diffusion: forming the third step N on the cathode side of the emitter + The emitter, with a concentration of 1×10 17 -1×10 21 cm -3 ;

[0060] S23 adjusts the junction depth and concentration at the junction depth of the second step by ion implantation; in particular:

[0061] Ion implantation: ion implantation on the second step N + formed by the second diffusion to adjust the junction depth and concentration at the junction depth;

[0062] High-temperature annealing: high-temperature annealing of the implanted ions to activate the ions and eliminate lattice damage.

[0063] S24 forms the third step N on the cathode side of the emitter by three times of oxidation, etching and diffusion + + The emitter; in particular:

[0064] Third oxidation: forming a SiO2 layer mask on the surface of the Si wafer;

[0065] Third lithography of the cathode emission area: transferring the pattern of the third lithography plate to the cathode of the Si wafer, so that a photoresist protective film is formed on the cathode emitter;

[0066] Photoresist removal: removing the photoresist on the emitter where the third diffusion is needed;

[0067] Etching: removing the SiO2 layer without photoresist protection;

[0068] Third phosphorus pre-diffusion + main diffusion: forming the third step N on the cathode side of the emitter + The emitter, with a concentration of 8×10 16 -1×10 21 ​cm -3 .

[0069] S25 adjust the junction depth and the concentration at the junction depth of the third step by ion implantation; specifically:

[0070] ion implantation: ion implantation is performed on the third step N + emitter formed by the third diffusion to adjust the junction depth and the concentration at the junction depth of the third step;

[0071] high-temperature annealing: high-temperature annealing is performed on the implanted ions to activate the ions and eliminate lattice damage;

[0072] S26 form the nth step N + emitter on the (n-1)th step N + emitter on the cathode side by n times of oxidation, etching and diffusion; specifically:

[0073] n times of oxidation: form a SiO2 layer mask on the surface of the Si wafer by oxidation;

[0074] n times of etching: transfer the pattern of the nth photoresist plate to the Si wafer cathode to form a photoresist protective film on the cathode emitter;

[0075] degluing: remove the photoresist on the emitter where the nth diffusion is to be performed;

[0076] etching: remove the SiO2 layer without photoresist protection;

[0077] n times of phosphorus pre-diffusion + main diffusion: form the nth step N + emitter on the cathode side.

[0078] S27 adjust the junction depth and the concentration at the junction depth of the nth step by ion implantation; specifically:

[0079] ion implantation: ion implantation is performed on the nth step N + emitter formed by the nth diffusion to adjust the junction depth and the concentration at the junction depth of the nth step;

[0080] high-temperature annealing: high-temperature annealing is performed on the implanted ions to activate the ions and eliminate lattice damage.

[0081] S3: perform diffusion treatment on the anode emitter again to improve the implantation efficiency of the anode emitter; specifically:

[0082] P + diffusion: perform boron diffusion on the anode P + emitter region with a concentration of 1×10 14 cm -3 ~ 1×10 21 cm-3 ;

[0083] S4: Slotting the cathode side of the RBDT to form a terminal structure, improve the voltage resistance of the device, and protect the RBDT with the terminal structure; specifically:

[0084] n+1 oxidation: Re-oxidizing the surface of the Si wafer to form a SiO2 layer mask;

[0085] Wide groove etching + etching: Wide groove etching is performed on the outer edge of the cathode, with a width of 400-2000 μm and a depth of 40 μm-200 μm;

[0086] LTO film: Forming a silicon dioxide protective film at low temperature;

[0087] Glass passivation: Glass passivation is performed on the slotting.

[0088] S5: Cutting the Si wafer according to requirements, and forming a step-shaped cathode emitter reverse blocking double-end solid-state thyratron through sintering and glue coating treatment; specifically:

[0089] Lead hole etching: Lead hole etching is performed on the cathode and anode of the chip, respectively;

[0090] Metalization + dicing: Multiple layers of metal are evaporated on both sides of the Si wafer, and the Si wafer is then cut;

[0091] Sintering: Sintering is performed in a vacuum sintering furnace at 690-700 °C;

[0092] Glue coating protection: Glue coating protection is performed on the mesa and terminal;

[0093] Testing: The chip produced is tested for voltage resistance, etc.

[0094] The above preparation method can obtain a step-shaped cathode emitter structure. Under the same dv / dt trigger voltage pulse, the cathode emitter of the step-shaped cathode emitter RBDT can reach a part above the PN junction Vbi potential, thereby increasing the on-area. In the step-shaped cathode emitter structure, the junction depth continuously increases from the periphery of the cathode emitter to the middle of the cathode emitter, which can effectively increase the on-area of the RBDT, and can make the on-area of the step-shaped cathode emitter RBDT close to 100%, thereby increasing the di / dt tolerance of the device. Since a larger area of the cathode emitter can be turned on, the RBDT can be increased, thereby enabling the RBDT to work at a higher voltage and generate a larger peak current pulse.

[0095] In order to further illustrate the step-shaped cathode emitter reverse blocking double-terminal solid-state thyratron and the preparation method thereof provided by the embodiments of the present application, the two-stage step-shaped cathode emitter RBDT is taken as a specific embodiment and is described in detail below with reference to the drawings.

[0096] The N-type Si single crystal with a resistivity of 44 Ω·cm and a thickness of 1000 μm is selected.

[0097] The Si wafer is cleaned. The cleaning liquid configured by using ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O) at a ratio of 1:2:5 and the cleaning liquid configured by using hydrochloric acid (HCL), hydrogen peroxide (H2O2) and water (H2O) at a ratio of 1:2:8 are used to clean the silicon wafer at 65°C for 10 minutes.

[0098] Laser grooving: the laser is used to groove around the cathode of the above cleaned Si wafer, the groove width is 80 μm-150 μm, and the groove depth is 850 μm-870 μm;

[0099] Closed tube aluminum expansion (forming P-N junction): the Si wafer and the high-purity aluminum source are placed in a closed quartz tube, and then the quartz tube is placed in a diffusion furnace to diffuse at a temperature of 1200°C-1250°C for 60 minutes, so as to form a P-N structure;

[0100] Chemical etching to thin the anode. The etching liquid configured by using hydrofluoric acid (HF), nitric acid (HNO3) and acetic acid (CH3COOH) at a ratio of 1:2:3 is used to thin the diffused Si on one side, the temperature is about 30°C, and the time is about 30 minutes;

[0101] Closed tube gallium expansion: the Si wafer and the high-purity gallium source are placed in a closed quartz tube, and then the quartz tube is placed in a diffusion furnace to diffuse at a temperature of 1200°C-1250°C for 60 minutes;

[0102] First oxidation to form a SiO2 layer mask. The silicon wafer is oxidized at 1180°C, and dry oxygen (O2) is passed for 1 hour-wet oxygen (steam) for 4 hours-dry oxygen (O2) for 1 hour;

[0103] First photoetching: the pattern of the photoetching plate is transferred to the cathode of the Si wafer, so that the cathode emitter forms a photoresist protective film;

[0104] Photoresist removal: concentrated sulfuric acid (H2SO4) is used to remove the residual photoresist on the Si wafer at the emitter; +

[0105] Etching: the SiO2 layer without photoresist protection is removed. The reagent configured by using hydrofluoric acid (HF), ammonium fluoride (NH4F) and water (H2O) at a ratio of 3:6:10 is used to etch the photoetched silicon wafer, the water bath temperature is 65°C, and the time is 3 minutes;

[0106] ​Phosphorus pre-diffusion + main diffusion: liquid source diffusion of phosphorus oxychloride (POCl3), pre-diffusion temperature 1200°C, time 100 minutes, source temperature 0°C, phosphorus main diffusion temperature 1260°C, time 100 minutes, to form a first step emitter, with a concentration of 1 x 1018cm-3 at the junction depth and a junction depth of 12-20μm; 19 -1 x 1018cm-3 21 cm -3 , and a junction depth of 12-20μm;

[0107] Second oxidation, to form a SiO2layer mask. Oxidize the silicon wafer at 1180°C, dry oxygen (O2) for 1 hour - wet oxygen (steam) for 4 hours - dry oxygen (O2) for 1 hour;

[0108] Second lithography: transfer the pattern of the lithography plate to the Si wafer cathode, to form a photoresist protective film on the cathode emitter;

[0109] Photoresist removal: use concentrated sulfuric acid (H2SO4) to remove the residual photoresist on the Si wafer cathode emitter where secondary diffusion is required;

[0110] Etching: remove the SiO2layer where there is no photoresist protection. Use a reagent of hydrofluoric acid (HF), ammonium fluoride (NH4F), and water (H2O) in a ratio of 3:6:10 to etch the silicon wafer after lithography, with a water bath temperature of 65°C and a time of 3 minutes;

[0111] Phosphorus pre-diffusion + main diffusion: liquid source diffusion of phosphorus oxychloride (POCl3), pre-diffusion temperature 1200°C, time 150 minutes, source temperature 0°C, phosphorus main diffusion temperature 1300°C, time 120 minutes, to form a second step cathode emitter;

[0112] Ion implantation: ion implantation of the second step N + emitter formed by secondary diffusion, to adjust the junction depth and concentration at the junction depth of the second step, so that the doping concentration at the junction depth of the second step cathode is 1 x 1018cm-3 17 -1 x 1018cm-3 21 cm -3 , with a junction depth of 16-25μm;

[0113] High-temperature annealing: high-temperature annealing of the implanted N + ions at 1200°C-1600°C to activate the ions and eliminate lattice damage;

[0114] P + diffusion: solid boron nitride pre-diffusion temperature 1200°C, time 100 minutes, main diffusion temperature 1260°C, time 100 minutes;

[0115] Third oxidation, to form a SiO2layer mask. Oxidize the silicon wafer at 1180°C, dry oxygen (O2) for 1 hour - wet oxygen (steam) for 4 hours - dry oxygen (O2) for 1 hour;

[0116] Etching and corrosion: HF, HNO3, CH3COOH are mixed in the ratio of 1:3:1 to form a corrosion solution, and the Si piece is subjected to wide groove corrosion at a temperature of about 30℃ for about 5-8 minutes, the width of the wide groove is 500-1000μm, and the depth is 50-100μm;

[0117] LTO film: LTO film is deposited by LPCVD at a temperature of 420℃, a pressure of 0.3Torr, a SiH4 flow rate of 150cc / min, an O2 flow rate of 40cc / min, and a deposition time of 35min;

[0118] Glass passivation protection: lead-aluminum silicate glass is coated on the surface of the chip and in the groove, and is placed on a 200℃ hot plate for rapid baking for 3 minutes, and then is pushed into a sintering furnace for sintering for 10 minutes at a temperature of 500-900℃, and then is cooled to form a passivation layer;

[0119] Lead hole etching: lead holes of cathode and anode are etched by laser on the cathode and anode of the chip respectively;

[0120] Metalization: multiple layers of chromium, nickel and silver are evaporated on both sides of the silicon piece, the evaporation thickness of chromium is 500-1000A 0 m, the evaporation thickness of nickel is 4000-5000A 0 m, and the evaporation thickness of silver is 6000-6500A 0 m;

[0121] Dicing: the Si piece is cut into a square piece of 4mm x 7mm;

[0122] Sintering: the sintering furnace is vacuumized, the vacuum degree reaches 10 -1 Pa or above, the sintering temperature is controlled at 690℃, the constant temperature time is 5 minutes, the sintering furnace is cooled at a rate of 15℃ / min, and when the temperature is below 400℃, the sintering furnace is naturally cooled in air;

[0123] Glue coating protection: silicon rubber is coated on the mesa and the terminal for protection, and is cured at room temperature for 3 days;

[0124] Testing: the chip is subjected to circuit testing.

[0125] The present application provides a new structure of RBDT, i.e. a step cathode emitter RBDT and a preparation method thereof, Figure 1The schematic diagram of the cell of the stepped cathode emitter RBDT. Since the RBDT is triggered by the displacement current, a voltage difference is formed at the cathode PN junction, and then the breakdown occurs to make the whole chip enter the on state. However, due to the difference in the resistivity of the P base region, the voltage formed at the whole cathode emitter is different under the same dv / dt pulse trigger, and the overall trend is that the voltage at the periphery of the cathode emitter is greater than that in the middle. Therefore, under a lower dv / dt trigger, the RBDT will be turned on from the periphery and then spread inward. The reduction of the on area leads to the reduction of the di / dt tolerance of the RBDT. The stepped cathode emitter RBDT is formed by n times diffusion of the cathode emitter, so that the voltage drop at the n-th stepped cathode is appropriately increased, thereby increasing the on area of the RBDT chip under the same dv / dt trigger pulse, and thus increasing the di / dt tolerance of the RBDT chip.

[0126] Figure 2 The schematic diagram of the cell of the stepped cathode emitter RBDT with a cathode voltage resistance groove. The cathode wide groove is used for terminal shaping, and a wide groove width (400 μm-2000 μm) and a shallow groove depth (40 μm-200 μm) are combined to make the voltage resistance groove form a small inclination angle (1°-10°) with the RBDT voltage resistance, thereby increasing the voltage resistance of the device. Further, under a higher working voltage, a higher current and a larger current rise rate can be generated. By adjusting the concentration and the junction depth at the n-th stepped cathode step junction, the on area of the RBDT can theoretically approach 100%, greatly enhancing the current rise rate tolerance of the device, and laying a foundation for the application of the RBDT in high di / dt application occasions.

[0127] Figure 4 (a) and (b) are the current density distribution results of the two-step stepped cathode emitter RBDT and the conventional RBDT respectively when the current is 170 A: from the figure, it can be seen that when the current is 170 A, the maximum current density of the stepped cathode RBDT is 1.32×10 5 A / cm 3 , and the maximum current density of the conventional RBDT reaches 5.831×10 5 A / cm 3 . The maximum current density of the stepped cathode RBDT is only 20% of that of the conventional RBDT, and the on area of the stepped cathode RBDT is 5 times that of the conventional RBDT, greatly reducing the heat generation of the device and increasing the di / dt tolerance of the RBDT.

[0128] Figure 5(a), (b) are the current density distribution results of two-stage step cathode emitter RBDT and conventional RBDT respectively when the current is peak current, from the figure, it can be seen that when the peak current is reached, the current density distribution of the conventional RBDT is uneven, and does not occupy the entire chip area, thereby causing waste of chip area; but the current density of the step cathode emitter RBDT occupies the entire chip area, so that the current density distribution is more uniform, the chip utilization is higher, and the current-carrying capacity of the device can be effectively improved.

[0129] In addition, in the embodiment, the RBDT with four cells theoretically needs to have three steps to make the RBDT have a better opening area, but in fact, the RBDT with two steps can make the RBDT have a good enough opening effect, such as Figure 4 (a) the middle part has been opened, because when the surface concentration and step junction depth of the second step are accurately controlled, after the trigger pulse dv / dt is applied, the potential of the middle part of the chip can also be greater than the opening potential Vbi of the PN junction, but this is not achieved by the conventional RBDT. Therefore, for RBDT with more cells, accurately controlling the surface concentration and junction depth of the second step, the third step, … (here, the step number is less than the number of cells of the RBDT) can effectively reduce the number of steps of the cathode emitter of the RBDT, not only can reduce the process steps, but also can make the RBDT have a larger opening area, so that the RBDT has high di / dt tolerance.

[0130] Those skilled in the art can easily understand that the above description is only a preferred embodiment of the present application, and is not intended to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A step cathode emitter reverse blocking two-terminal solid state thyratron, characterized by, The double-ended solid-state thyratron has a four-layer PNPN structure, and Al electrodes are arranged on the cathode side and the anode side. The N of the cathode side + The emitter is a stepped structure, and has n stepped levels. In the direction from the first stepped level to the n stepped level, the junction depth of each stepped level is deeper and the concentration at the junction depth is gradually reduced. The anode side emitter P + Doping concentration is 1×10 14 cm -3 ~1×10 21 cm -3 Depth is 35μm~100μm, and thousands of short-circuit points with a diameter of 200μm~300μm are arranged on the cathode side; The direction along the first step to the nth step is from the cathode to the anode n is a positive integer greater than or equal to 2.

2. The double-ended solid state thyratron of claim 1, wherein, When n is 3, the doping concentration of the first step is 1 x 10 19 cm -3 ~1 x 10 21 cm -3 , the junction depth is 12 μm~20 μm, the doping concentration of the second step is 1 x 10 17 cm -3 ~1 x 10 21 cm -3 , the junction depth is 17 μm~25 μm, and the doping concentration of the third step is 8 x 10 16 cm -3 ~1 x 10 21 cm -3 , the junction depth is 21 μm~29 μm.

3. The double-ended solid state thyratron according to claim 1 or 2, characterized in that P base region doping concentration is 1 x 10 14 cm -3 ~1 x 10 19 cm -3 , depth is 35 μm ~ 100 μm, N base region doping concentration is 2 x 10 13 cm -3 ~1 x 10 14 cm -3 , depth is 100 μm ~ 400 μm.

4. A double-ended solid state thyratron according to any one of claims 1-3, characterized in that, A groove with a width of 400 μm to 2000 μm and a depth of 40 μm to 200 μm is arranged on the outer edge of the cathode.

5. A method of making a step cathode emitter reverse blocking two-terminal solid state thyratron, characterized by, The method comprises the following steps: S1: a single-face diffusion groove is formed on an N-type single-crystal Si wafer by laser; S2: a cathode N+ emitter with n-stage steps is formed by multiple diffusion and ion implantation processes; S3: the anode emitter is subjected to diffusion treatment again, so as to improve the ion implantation efficiency of the anode emitter; S4: a groove is formed on the cathode side of the RBDT, so as to form a terminal structure, improve the voltage resistance of the device, and protect the RBDT with the terminal structure; S5: the Si wafer is cut according to requirements, and a step-shaped cathode emitter reverse blocking double-ended solid-state thyratron is formed after sintering and glue coating treatment.

6. The method of claim 5, wherein, Step S2 is specifically as follows: S21 forming a first step N on the cathode side by oxidation, etching and diffusion + emitter S22 forms a second step N on the cathode side of the emitter by means of secondary oxidation, etching and diffusion + S22 forms a second step N on the cathode side of the emitter by means of secondary oxidation, etching and diffusion + emitter; S23: the junction depth and the concentration at the junction depth of the second step are adjusted by ion implantation; S24 forms a third step N on the cathode side of the emitter by three times of oxidation, etching and diffusion + S24 forms a third step N on the cathode side of the emitter by three times of oxidation, etching and diffusion + emitter; S25: the junction depth and the concentration at the junction depth of the third step are adjusted by ion implantation; S26 through n times of oxidation, etching and diffusion in the (n-1) step N + The n step N of the cathode side is formed on the emitter + The emitter; S27: the junction depth and the concentration at the junction depth of the nth step are adjusted by ion implantation.

7. The method of claim 6, wherein, The implanted ions are subjected to high-temperature annealing, so as to activate the ions and eliminate lattice damage.

8. The method of claim 6, wherein, Step S4 is specifically as follows: The Si wafer surface is subjected to n+1 times of oxidation to form a SiO2 layer mask layer; Wide groove etching is performed on the outer edge of the cathode; A silicon dioxide protective film is formed at low temperature; The wide groove is subjected to glass passivation protection.

9. The method of claim 8, wherein, The width of the wide groove is 400 μm to 2000 μm, and the depth is 40 μm to 200 μm.

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