Method, equipment and system for detecting maximum junction temperature of multi-chip parallel device

Abstract

The embodiment of the invention relates to the technical field of power systems, in particular to a method, equipment and a system for detecting the maximum junction temperature of a multi-chip parallel device. The method comprises the following steps: collecting direct current distribution data of each chip in the multi-chip parallel device; obtaining on-state voltage drop data of the multi-chip parallel device in a forward conduction state and a reverse follow current state; inputting the on-state voltage drop data and the direct current distribution data into a pre-established current-junction temperature-on-state voltage drop function relationship, and calculating junction temperature data of each chip; and comparing the junction temperature data of each chip, and determining the maximum junction temperature data in the multi-chip parallel device and the corresponding chip. The method can break through the limitation that a conventional on-state voltage drop monitoring inversion technology can only obtain the average junction temperature of the chip, and achieves the precise positioning of the chip with the highest junction temperature in the device.

Description

Technical Field

[0001] This invention relates to the field of power system technology, and in particular to a method, device and system for detecting the maximum junction temperature of multi-chip parallel devices. Background Technology

[0002] High-voltage IGBTs (High-Voltage Insulated Gate Bipolar Transistors) are core components of UHVDC flexible DC converter valves. Their operational performance directly determines the overall operating state of the converter valve, thus having a critical impact on the safety and stability of the entire flexible DC transmission system. According to industry data, over 75% of faults in UHVDC transmission systems originate from the converter valve power converter, with 31% of these faults caused by power devices. Of these power device faults, approximately 60% are related to thermal fatigue. Therefore, effective monitoring of the internal temperature of high-voltage IGBT devices is a crucial prerequisite for ensuring the reliable operation of flexible DC transmission systems. Considering that common high-voltage IGBT devices often employ a multi-chip parallel structure, their overall reliability is often determined by the chip with the highest internal junction temperature. Therefore, accurately monitoring and obtaining this maximum junction temperature is a core requirement for targeted protection and control of the devices.

[0003] Currently, the industry standard for monitoring the temperature of high-voltage IGBT chips is to use a technical solution based on on-state voltage drop monitoring and inversion. This involves monitoring the on-state voltage drop of the device and then inverting the junction temperature information of the chip. However, due to the parallel structure of multiple chips within a high-voltage IGBT device, this technology can only obtain the average junction temperature of all parallel chips. It cannot accurately locate the chip with the highest junction temperature, nor can it accurately extract its actual junction temperature value. This makes it difficult to provide accurate data support for device protection mechanisms and control strategies, which is detrimental to ensuring the safe and stable operation of high-voltage IGBT devices and the entire flexible DC transmission system.

[0004] Therefore, how to overcome the limitation of conventional on-state voltage drop monitoring and inversion technology, which can only obtain the average junction temperature of the chip, and achieve accurate positioning of the chip with the highest junction temperature inside the device, is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide at least one method, device and system for detecting the maximum junction temperature of a multi-chip parallel device, which can overcome the limitation of conventional on-state voltage drop monitoring and inversion technology that can only obtain the average junction temperature of the chips, and achieve accurate positioning of the chip with the highest junction temperature inside the device.

[0006] To address the aforementioned technical problems, at least one embodiment of this application provides a method for detecting the maximum junction temperature of a multi-chip parallel device, comprising: Collect DC current distribution data of each chip in a multi-chip parallel device; Obtain the on-state voltage drop data of the multi-chip parallel device in both forward conduction and reverse freewheeling states; The on-state voltage drop data and the DC current distribution data are input into a pre-established current-junction temperature-on-state voltage drop function relationship to calculate the junction temperature data of each chip; The junction temperature data of each chip are compared to determine the maximum junction temperature data and the corresponding chip in the multi-chip parallel device.

[0007] In one embodiment, the method for establishing the current-junction temperature-on-state voltage drop function relationship includes: Collect multiple sets of single-current-junction temperature-on-state voltage drop data for a single chip at different junction temperatures under different total currents; the single chip and the chips in the multi-chip parallel device are of the same model. By integrating multiple sets of single current-junction temperature-on-state voltage drop data, a three-dimensional dataset of current-junction temperature-voltage drop is constructed. Based on the aforementioned three-dimensional dataset, a bivariate fitting algorithm was used to establish a function model with current and junction temperature as independent variables and on-state voltage drop as dependent variable, thereby obtaining the current-junction temperature-on-state voltage drop functional relationship.

[0008] In one embodiment, the acquisition of multiple sets of single-current-junction temperature-on-state voltage drop data of a single chip at different junction temperatures under different total currents includes: Set multiple different total calibration currents; For each group of calibration total current, the operating current of the single chip is fixed to the corresponding calibration total current of that group, and the junction temperature of the single chip is gradually changed by a temperature control device. During the single-chip junction temperature change process, the single-chip on-state voltage drop data corresponding to different junction temperatures are collected in real time to obtain the single current-junction temperature-on-state voltage drop data under the calibration total current. Obtain the single current-junction temperature-on-state voltage drop data under the total calibration current for all groups.

[0009] In one embodiment, after setting multiple different sets of calibration total currents, the method further includes: For each group of calibration total current, the average junction temperature of the multi-chip parallel device is gradually changed by the temperature control device, and the corresponding on-state voltage drop data is collected as the first data; Based on the first data, a correlation between on-state voltage drop and average junction temperature is established; Before inputting the on-state voltage drop data and the DC current distribution data into the pre-established current-junction temperature-on-state voltage drop function relationship, the method further includes: The average junction temperature of the multi-chip parallel device during actual operation was collected. Substituting the average junction temperature of the device into the on-state voltage drop-average junction temperature correlation, the theoretical on-state voltage drop is calculated. Compare the deviation between the theoretical on-state voltage drop and the actual on-state voltage drop data of the multi-chip parallel device in the forward conduction and reverse freewheeling states; If the deviation is within a preset threshold, the step of inputting the on-state voltage drop data and the DC current distribution data into the pre-established current-junction temperature-on-state voltage drop function relationship is executed; If the deviation is not within the preset threshold, the step of obtaining the on-state voltage drop data of the multi-chip parallel device in the forward conduction and reverse freewheeling states is repeated.

[0010] In one embodiment, the acquisition of DC current distribution data of each chip in the multi-chip parallel device includes: The magnetic field data generated at the bonding line directly below each sensor is acquired by a vector magnetoresistive sensor array; each sensor in the vector magnetoresistive sensor array is installed directly above the bonding line of the corresponding chip. Based on the magnetic field data, and combined with the preset position parameters of the sensor and the current-carrying conductor, the DC current distribution data of each chip in the multi-chip parallel device is calculated.

[0011] At least one embodiment of this application also provides a maximum junction temperature detection device for multi-chip parallel devices, including: a current acquisition device, an on-state voltage drop monitoring circuit, and a data processing chip connected to the current acquisition device and the on-state voltage drop monitoring circuit respectively; The current acquisition device is used to acquire DC current distribution data of each chip in the multi-chip parallel device; The on-state voltage drop monitoring circuit is used to acquire on-state voltage drop data of the multi-chip parallel device in both forward conduction and reverse freewheeling states. The data processing chip is used to input the on-state voltage drop data and the DC current distribution data into a pre-established current-junction temperature-on-state voltage drop function relationship, calculate the junction temperature data of each chip, compare the junction temperature data of each chip, and determine the maximum junction temperature data and the corresponding chip in the multi-chip parallel device.

[0012] In one embodiment, the current acquisition device includes: a vector magnetoresistive sensor array and a magnetic field calculation module; In the vector magnetoresistive sensor array, each sensor is mounted directly above the bonding wire of the corresponding chip in the multi-chip parallel device, and each sensor is used to collect magnetic field data generated by the bonding wire directly below it. The magnetic field calculation module is used to calculate the DC current distribution data of each chip in the multi-chip parallel device based on the magnetic field data and in combination with the preset position parameters of the sensor and the current-carrying conductor.

[0013] In one embodiment, the vector magnetoresistive sensor array is an HMC1021S type anisotropic magnetoresistive sensor.

[0014] In one embodiment, the input terminal of the on-state voltage drop monitoring circuit is connected to the port formed by the external driving source and the desaturation detection terminal of the multi-chip parallel device.

[0015] At least one embodiment of this application also provides a maximum junction temperature detection system for a multi-chip parallel device, comprising: a multi-chip parallel device and a maximum junction temperature detection device for the multi-chip parallel device as described above; The maximum junction temperature detection device for the multi-chip parallel device is electrically connected to the multi-chip parallel device; The maximum junction temperature detection device for the multi-chip parallel device is used to collect the DC current distribution data and the on-state voltage drop data under forward conduction and reverse freewheeling states of each chip in the multi-chip parallel device, and calculate the junction temperature data of each chip in the multi-chip parallel device based on the DC current distribution data and the on-state voltage drop data, and determine the maximum junction temperature data and the corresponding chip.

[0016] The maximum junction temperature detection method for multi-chip parallel devices provided in this application collects independent DC current distribution data for each chip. Combining this with the characteristic that the voltages of each branch in the parallel circuit are equal, the overall on-state voltage drop of the device is equivalent to the voltage drop of a single chip. Then, a preset current-junction temperature-on-state voltage drop function is used to calculate the junction temperature of a single chip independently. Finally, the maximum junction temperature and the corresponding chip are accurately located by comparing the junction temperature data. This fundamentally solves the core pain point of traditional methods that cannot identify local high temperatures in parallel chips and are difficult to locate the source of fault risk, providing a targeted target for device reliability management. In addition, the method uses a reverse logic with dual-parameter collaborative input of DC current distribution and forward / reverse freewheeling on-state voltage drop. This avoids the one-sidedness of ignoring the coupling effect of multiple factors when using a single current or single voltage drop parameter for reverse calculation. It also fully reflects the actual operating state of multi-chip parallel devices in equipment such as converters and converter valves, so that the junction temperature calculation result can truly reflect the actual temperature state of the chip. This method achieves junction temperature detection entirely based on external electrical parameter acquisition and function calculation. It does not require invasive modifications such as disassembling and repackaging multi-chip parallel devices or installing internal temperature sensing elements. This avoids damaging the original electrical performance and heat dissipation path of the device, and is compatible with the structural limitations of densely packaged devices such as high-voltage IGBTs. It reduces the implementation difficulty in practical applications and can ultimately effectively improve the working reliability and service life of the device. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, and these illustrative descriptions do not constitute a limitation on the embodiments.

[0018] Figure 1 This is a flowchart of a method for detecting the maximum junction temperature of a multi-chip parallel device provided in one embodiment of this application; Figure 2 This is a schematic diagram of a maximum junction temperature detection device for multi-chip parallel devices provided in one embodiment of this application; Figure 3 This is a schematic diagram showing the specific location arrangement of a vector magnetoresistive sensor array for a multi-chip parallel high-power IGBT module, provided in one embodiment of this application. Figure 4 This is a schematic diagram of the structure of an HMC1021S type anisotropic magnetoresistor provided in one embodiment of this application; Figure 5 This is a schematic diagram illustrating the angular relationship between a resistor and the direction of its internal magnetization and the direction of current, provided in one embodiment of this application. Figure 6 This is a schematic diagram of the structure of a multi-chip parallel device maximum junction temperature detection device provided in one embodiment of this application; Figure 7 This is an assembly schematic diagram of a multi-chip parallel device maximum junction temperature detection device provided in one embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this application to help readers better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0020] This invention proposes a method for detecting the maximum junction temperature of a multi-chip parallel device. The implementation details of the method for detecting the maximum junction temperature of a multi-chip parallel device in this embodiment are described below. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0021] Example 1: The specific process of the multi-chip parallel device maximum junction temperature detection method in this embodiment can be as follows: Figure 1 As shown, it includes: Step 101: Collect DC current distribution data of each chip in the multi-chip parallel device.

[0022] In multi-chip parallel devices, the junction temperatures of each chip often differ significantly due to variations in manufacturing processes and heat dissipation conditions. To address this, this method uses the current-junction temperature-on-state voltage drop function to inversely deduce the junction temperature of a single chip. The single-chip current is the key independent variable, as the static current distribution of parallel chips is directly affected by their own junction temperatures. An increase in junction temperature leads to changes in the chip's on-state voltage drop, thereby triggering current redistribution. This step utilizes an induction method adapted to the internal chip current-carrying structure to achieve accurate capture and quantification of single-chip-level current information.

[0023] This embodiment does not limit the specific equipment and method used to acquire the current distribution data; for example, a Rogowski coil array or a magnetoresistive array can be used. In one embodiment, a vector magnetoresistive sensor array can be used to acquire the magnetic field data generated at the bonding wire directly below each sensor. Based on the magnetic field data and combined with preset position parameters of the sensors and current-carrying conductors, the DC current distribution data of each chip in the multi-chip parallel device is calculated. Each sensor in the vector magnetoresistive sensor array is mounted directly above the bonding wire of the corresponding chip.

[0024] For each chip in a multi-chip parallel device, a vector magnetoresistive sensor is installed directly above its bonding wire (the core current-carrying structure connecting the chip to external circuitry), forming a sensor array. Utilizing the high sensitivity of vector magnetoresistive sensors to changes in magnetic fields, data such as the magnetic field strength and direction generated when the bonding wire directly below each sensor is energized are collected in real time, ensuring that each set of magnetic field data can be accurately correlated to the corresponding individual chip. Since a magnetic field is generated around a conductor when current flows through it, and the magnetic field data has a definite quantitative relationship with the magnitude and direction of the current in the conductor and the relative position of the sensor and the conductor, based on the magnetic field data collected in the first step, combined with pre-calibrated positional parameters such as the distance and angle between the sensor and the corresponding bonding wire, the energizing current of each chip's bonding wire can be calculated using electromagnetic formulas. This data is then aggregated to form the DC current distribution data of each chip in the multi-chip parallel device.

[0025] Specifically, when the total current of the device reaches I mixed At this time, measure the on-state voltage drop of the device. v cmix and the output voltage of each vector magnetoresistive sensor. v outx (x = 1, 2, ..., N, where N equals the number of IGBT chips connected in parallel within the device, which is the total number of sensors in the entire vector magnetoresistive sensor array). Based on the voltage output of the sensor array... v outxBased on the relationship of the DC current in the remaining bonding wires directly below, it can be concluded that the IGBT chip is connected in parallel within the device. Q x The magnitude of the DC current i x for

[0026] At this time, v cone = v cmix , i one = i x Substitute it into the following formula

[0027] Then in the above formula v cone and i one Since these are known numbers, the above equation can be solved to obtain... T jone And at this time T jone That is equivalent to a chip. Q x junction temperature T jx .

[0028] In this method, the sensor is installed directly above the bonding wire without damaging the device package or connecting it in series with the circuit. This avoids interference with the original structure, heat dissipation, and electrical performance of the device, making it adaptable to actual device operating scenarios. Furthermore, the vector magnetoresistive sensor possesses rapid magnetic field response characteristics, enabling it to capture magnetic field fluctuations caused by current changes in real time. This meets the real-time monitoring requirements for current distribution in multi-chip parallel devices under dynamic load changes. It should be noted that this embodiment only uses the above acquisition method as an example; other acquisition methods can be described with reference to this embodiment and will not be elaborated further.

[0029] Step 102: Obtain the on-state voltage drop data of the multi-chip parallel device in both forward conduction and reverse freewheeling states.

[0030] The on-state voltage drop is the core dependent variable in this functional relationship. Changes in junction temperature and single-chip current directly lead to corresponding changes in the on-state voltage drop. When the junction temperature rises, the resistivity change of the chip semiconductor material causes the on-state voltage drop to shift. Changes in single-chip current also affect the correlation between junction temperature and voltage drop through power loss. Moreover, when multiple chips are connected in parallel, the on-state voltage drops of each chip are consistent, and the overall on-state voltage drop of the device can be directly equivalent to the on-state voltage drop of a single chip. At the same time, in actual operation, multi-chip parallel devices (such as high-voltage IGBTs) are not only in the forward conduction state. Reverse freewheeling is a key operating condition for them to complete energy conversion and achieve normal circuit operation (such as during converter commutation). In this state, the chips will also generate heat due to current flow, and the junction temperature may rise.

[0031] This step clarifies the two core operating states of multi-chip parallel devices: forward conduction (current flows through each parallel chip along the forward path designed for the device) and reverse freewheeling (current passes through the device along the reverse freewheeling path, such as the anti-parallel diode of an IGBT). This ensures that data acquisition covers the main operating scenarios of the device. The on-state voltage drop data collected in the two states are classified and organized to form a complete on-state voltage drop dataset that includes both forward and reverse operating conditions, providing voltage parameter support for subsequent junction temperature calculations.

[0032] Step 103: Input the on-state voltage drop data and DC current distribution data into the pre-established current-junction temperature-on-state voltage drop function relationship, and calculate the junction temperature data of each chip.

[0033] The on-state voltage drop data collected from the devices under forward and reverse freewheeling states are equivalent to the on-state voltage drop input value of each single chip; at the same time, the DC current distribution data of each chip collected in the previous steps are retrieved to determine the actual current input value corresponding to each chip.

[0034] The actual current value of each chip is used as the current independent variable of the function, and the equivalent on-state voltage drop value is used as the voltage drop dependent variable of the function. These values ​​are substituted into a pre-established current-junction temperature-on-state voltage drop function relationship. This function uses current and junction temperature as independent variables and on-state voltage drop as dependent variables. The junction temperature value corresponding to each chip is derived through mathematical calculation. The calculated junction temperatures of all chips are recorded according to chip number, forming a dataset containing independent junction temperature information for each chip.

[0035] This method uses DC current distribution data to obtain the independent current value of each chip. Combined with the equivalent single-chip voltage drop of the overall on-state voltage drop of the device (the voltage of parallel circuits is equal), the junction temperature can be calculated independently for each chip after being substituted into the function. This accurately identifies the temperature differences between different chips. Compared with the traditional method of calculating the average junction temperature based on the overall on-state voltage drop of the device and the total current (such as using only the total current and the overall voltage drop of the device, and substituting the simplified relationship between total current, average junction temperature and overall voltage drop), this method fundamentally solves the technical bottleneck of the traditional method in being unable to locate local high temperatures. Moreover, this method avoids the one-sidedness of single-parameter back-calculation and adopts multi-parameter coupled back-calculation, making the calculation results more consistent with the actual junction temperature state of the chip, and the accuracy is significantly higher than that of the single-parameter method.

[0036] Step 104: Compare the junction temperature data of each chip to determine the maximum junction temperature data and the corresponding chip in the multi-chip parallel device.

[0037] The output junction temperature data is analyzed, and a one-to-one correspondence dataset of chip number and junction temperature value is established according to the chip's physical number (or preset identifier) ​​within the device. This ensures that each junction temperature data can be traced back to a specific chip, avoiding confusion in the correspondence between data and chips. Secondly, the junction temperature values ​​of all chips in the dataset are quantitatively compared. This can be done by iterating through the comparisons to filter out the maximum value, or by directly extracting the first value using descending sorting. This embodiment does not impose any restrictions on this method, but clearly defines the maximum quantized value of the junction temperature within the device. Finally, the maximum junction temperature value is reverse-linked to its corresponding chip number to determine the specific chip to which the maximum junction temperature belongs. At the same time, the specific value of the maximum junction temperature and the identification information of the corresponding chip are recorded, forming a correlation result of maximum junction temperature data and corresponding chip. This provides a direct target basis for subsequent reliability control measures such as device overheating warning and targeted control of high-temperature chips.

[0038] Based on the above introduction, the maximum junction temperature detection method for multi-chip parallel devices provided in this embodiment collects independent DC current distribution data for each chip, combines the equal voltage characteristics of each branch in the parallel circuit, and converts the overall on-state voltage drop of the device into the voltage drop of a single chip. Then, it substitutes the preset current-junction temperature-on-state voltage drop function to realize the independent calculation of the junction temperature of a single chip. Finally, by comparing the junction temperature data, the maximum junction temperature and the corresponding chip are accurately located. This fundamentally solves the core pain point of traditional methods that cannot identify local high temperature of parallel chips and are difficult to locate the source of fault risk, providing a targeted target for device reliability management. In addition, the method adopts a reverse logic with dual-parameter collaborative input of DC current distribution and forward / reverse freewheeling on-state voltage drop. This avoids the one-sidedness of ignoring the influence of multiple factors when using a single current or single voltage drop parameter for reverse calculation, and fully reflects the actual operating state of multi-chip parallel devices in equipment such as converters and converter valves, so that the junction temperature calculation result can truly reflect the actual temperature state of the chip. This method achieves junction temperature detection entirely based on external electrical parameter acquisition and function calculation. It does not require invasive modifications such as disassembling and repackaging multi-chip parallel devices or installing internal temperature sensing elements. This avoids damaging the original electrical performance and heat dissipation path of the device, and is compatible with the structural limitations of densely packaged devices such as high-voltage IGBTs. It reduces the implementation difficulty in practical applications and can ultimately effectively improve the working reliability and service life of the device.

[0039] Example 2: In the above embodiments, the junction temperature of each chip is inferred from the current-junction temperature-on-state voltage drop function relationship. However, the specific method for establishing the current-junction temperature-on-state voltage drop function relationship is not limited. For example, it can be achieved by combining overall device testing with single-chip data correction, or by adding simulation data to key operating condition test calibration.

[0040] To provide a precise, reliable, and chip-specific quantitative mathematical foundation for the aforementioned method of detecting the maximum junction temperature of multi-chip parallel devices, ensuring that the subsequent process of inferring the junction temperature from the current and voltage drop has rigorous physical basis and data support, this embodiment proposes a method for establishing the current-junction temperature-on-state voltage drop function relationship, which may specifically include the following steps: Step 105: Collect multiple sets of single-current-junction temperature-on-state voltage drop data for a single chip at different junction temperatures under different total currents.

[0041] First, a single chip with the exact same model as the chip in the multi-chip parallel device is selected as the test object. Using a single chip of the same model as the chip in the multi-chip parallel device ensures that the current-junction temperature-voltage drop characteristics obtained by the test are completely matched with the actual characteristics of the chip in the device under test, eliminating characteristic deviations caused by differences in materials and processes between different chip models.

[0042] Based on the actual operating current range of multi-chip parallel devices (covering minimum operating current, rated current and maximum withstand current), divide at least 3 or more different total current ranges as the total current test range to ensure coverage of the device's full operating current scenarios and avoid data under a single current that cannot adapt to the device's dynamic operating scenarios.

[0043] Connect the single chip to a temperature control device (such as a high-precision constant temperature chamber or heating plate), and adjust and stabilize the single chip junction temperature according to a preset gradient (such as starting from room temperature 25℃ and increasing to the maximum allowable junction temperature of the chip in steps of 5-10℃). Collect the on-state voltage drop data at this time through a high-precision voltage acquisition module. The data can be collected 3-5 times under each total current-junction temperature combination to reduce random errors. Classify and record each set of test data in the format of total current value-junction temperature value-on-state voltage drop average value to form multiple complete sets of single current-junction temperature-on-state voltage drop correlation data.

[0044] Step 106: Integrate multiple sets of single current-junction temperature-on-state voltage drop data to construct a three-dimensional dataset of current-junction temperature-voltage drop.

[0045] The raw data collected were scattered current-junction temperature-voltage drop triplets, which could not intuitively reflect the synergistic effect of the two independent variables (current and junction temperature) and the dependent variable (voltage drop). In this step, the collected multiple sets of discrete data on single current-junction temperature-voltage drop were arranged in a structured manner according to the three-dimensional dimensions of current (independent variable)-junction temperature (independent variable)-on-state voltage drop (dependent variable). For example, a data table was established in matrix form: the row dimension corresponds to multiple different total current levels (covering the actual operating current range of the device), the column dimension corresponds to different junction temperature gradients (from room temperature to the maximum allowable junction temperature of the chip), and the cells are filled with the average on-state voltage drop under the corresponding current-junction temperature combination, clarifying the unique position of each data point in the three-dimensional coordinate system, forming a three-dimensional dataset of current-junction temperature-voltage drop.

[0046] Through three-dimensional structured integration, discrete data can be transformed into ordered matrix or coordinate system data, clearly showing the influence of junction temperature on voltage drop under different currents and the influence of current on voltage drop under different junction temperatures, providing an intuitive basis for establishing functional relationships.

[0047] Step 107: Based on the three-dimensional dataset, a bivariate fitting algorithm is used to establish a function model with current and junction temperature as independent variables and on-state voltage drop as dependent variable, so as to obtain the current-junction temperature-on-state voltage drop function relationship.

[0048] Based on a 3D dataset, a bivariate fitting calculation is performed. The preprocessed independent variable matrix and dependent variable vector are input into the selected fitting algorithm. The model parameters are iteratively solved through mathematical optimization (such as the least squares method) to establish a preliminary functional expression for current-junction temperature-on-state voltage drop, such as... .in, Tjone For the junction temperature, i one For current, v cone This is the on-state pressure drop.

[0049] The bivariate fitting algorithm can simultaneously incorporate the synergistic effects of two independent variables, avoiding model distortion caused by ignoring coupling effects in univariate fitting, and ensuring that the function can accurately reproduce the physical laws of current-junction temperature-voltage drop.

[0050] Based on the above introduction, the method for establishing the current-junction temperature-on-state voltage drop function relationship provided in this embodiment uses a single chip of the same model as the chip in a multi-chip parallel device as the test object. This avoids the interference of different chip model characteristics on the authenticity of the data from the source, ensuring that the collected single current-junction temperature-on-state voltage drop data can accurately reflect the essential characteristics of the chip under test. By integrating multiple sets of data under different total currents and different junction temperatures to construct a three-dimensional dataset, it comprehensively covers the current range and junction temperature range of the actual operation of the device, avoiding insufficient model adaptability caused by single operating condition data. The function model is established based on a bivariate fitting algorithm, which can effectively capture the synergistic coupling effect of current and junction temperature on on-state voltage drop. At the same time, the random error of the original test data is reduced through mathematical optimization, ensuring that the model accurately restores the correlation law of current-junction temperature-voltage drop. The final continuous function model can directly adapt to the junction temperature back-calculation requirements under any current-voltage drop combination in the operation of multi-chip parallel devices, providing a standardized and highly reliable quantitative mathematical basis for subsequent maximum junction temperature detection.

[0051] Example 3: Based on Embodiment 2, in order to ensure that the collected single-chip data can truly reflect the essential characteristics of the chip's current-junction temperature-on-state voltage drop within the device, this embodiment proposes a method for collecting single-chip current-junction temperature-on-state voltage drop data at different junction temperatures.

[0052] Specifically, step 105 involves collecting multiple sets of single-current-junction temperature-on-state voltage drop data for a single chip at different junction temperatures under different total currents. This can be performed according to the following steps: Step 51: Set multiple different total calibration currents.

[0053] Multi-chip parallel devices do not operate under a single current condition in practice. Instead, they dynamically switch between minimum current, rated current, and maximum current ranges depending on the load. Furthermore, the junction temperature-on-state voltage drop characteristics of the chips differ at different current levels. This step involves setting multiple sets of different total calibration currents. Ideally, these sets should cover the actual operating current range of the multi-chip parallel devices. This ensures that the subsequently collected single-current-junction temperature-on-state voltage drop data covers all possible operating current scenarios for the devices. This avoids situations where the established function relationship cannot be adapted to certain operating conditions due to missing current ranges. For example, measuring only the rated current would not be sufficient to calculate the junction temperature under overload conditions.

[0054] Step 52: For each group of calibration total current, fix the operating current of the single chip to the corresponding calibration total current of that group, and control the junction temperature of the single chip to change gradually through a temperature control device.

[0055] For each set of calibration total currents previously set, first connect a single chip of the same model as the chip in the multi-chip parallel device to the test circuit. Then, use a current regulation module (such as a high-precision DC power supply) to precisely adjust the working current of the single chip to the value of the calibration total current for that set. Place the single chip in a temperature control device (such as a high-precision constant temperature test chamber or semiconductor temperature control station) to control the junction temperature of the single chip to gradually increase or decrease.

[0056] Step 53: During the single-chip junction temperature change process, collect the single-chip on-state voltage drop data corresponding to different junction temperatures in real time to obtain the single current-junction temperature-on-state voltage drop data under the total calibration current.

[0057] During the process of temperature control equipment regulating the gradual change of single-chip junction temperature, the instantaneous junction temperature is monitored in real time by the temperature sensor built into or external to the single chip. The voltage acquisition module keeps time-synchronized with the temperature monitoring equipment. When the junction temperature changes to the preset temperature node and stabilizes, voltage drop acquisition is immediately started. Then, the data is recorded in the format of current calibration total current - real-time stable junction temperature value - average on-state voltage drop. As the junction temperature continues to change according to the gradient, the above junction temperature stabilization-synchronous acquisition-data recording process is repeated. Finally, all junction temperature-voltage drop correlation data under the calibration total current are integrated to form a complete single current-junction temperature-on-state voltage drop dataset for this current range.

[0058] Step 54: Obtain single current-junction temperature-on-state voltage drop data for all groups under the total calibration current.

[0059] After all the current-junction temperature change-voltage drop acquisition tests corresponding to the preset total calibration current are completed, the total calibration current is used as the primary classification dimension. The junction temperature-on-state voltage drop correlation data in each data set is used as the secondary content and integrated in a unified format (such as a table or matrix) to form a structured set of a series of 'junction temperature-voltage drop' data corresponding to the total calibration current.

[0060] Based on the above introduction, the acquisition method provided in this embodiment overcomes the limitation of traditional single current acquisition being unable to adapt to dynamic operating conditions by acquiring junction temperature change data under multiple different calibration circuits. This ensures that the data can cover the full current scenario of the device from no-load to overload. At the same time, by using the control logic of fixed current + gradual change of junction temperature, a single variable change test environment is constructed, avoiding the problem of ambiguous attribution of voltage drop change when multiple variables fluctuate simultaneously in traditional methods. This can accurately pinpoint the influence law of junction temperature on on-state voltage drop.

[0061] Example 4: To further ensure that the established current-junction temperature-on-state voltage drop function not only closely matches the characteristics of a single chip but also matches the actual overall operating characteristics of multi-chip parallel devices, reducing errors caused by differences between the single-chip test environment (such as independent heat dissipation and no package coupling) and the actual operating environment of the device (such as multi-chip heat dissipation coupling and package thermal resistance), and improving the accuracy and engineering adaptability of subsequent junction temperature back-calculation, the following steps can be further performed during the data acquisition process, based on Example 3: Step 55: For each group of calibration total current, the average junction temperature of the multi-chip parallel devices is gradually changed by controlling the temperature control device, and the corresponding on-state voltage drop data is collected as the first data.

[0062] Step 56: Establish the correlation between on-state pressure drop and average junction temperature based on the first data fitting.

[0063] Steps 55 and 56 will be described together here.

[0064] For each set total calibration current, a multi-chip parallel device is fully connected to the test circuit. The total operating current of the device is precisely fixed to the total calibration current of that set using a current regulation module. The overall operating environment or heat dissipation conditions of the multi-chip parallel device are regulated using a temperature control device. The overall on-state voltage drop data across the device is collected as the average junction temperature of the multi-chip parallel device gradually changes. The combined data of the average value of the total calibration current, average junction temperature, and on-state voltage drop is defined as the first data. After the first data of all preset average junction temperature nodes under each set of total calibration current is collected, the corresponding first data sequence of average junction temperature and on-state voltage drop is separately organized for each set of current. An appropriate fitting algorithm is used to calculate the data sequence and construct a specific on-state voltage drop-average junction temperature correlation model under the set of total calibration current, clarifying the quantitative correspondence between the average junction temperature of the device and the overall on-state voltage drop under this current condition.

[0065] One method of fitting the relationship between average junction temperature and on-state voltage drop is as follows:

[0066] in, For the on-state voltage drop, Tj For the average junction temperature, V 0 and a are constants obtained through fitting.

[0067] Before step 103, which inputs the on-state voltage drop data and DC current distribution data into the pre-established current-junction temperature-on-state voltage drop function relationship, the following steps are further performed: Step 108: Collect the average junction temperature of the multi-chip parallel device during actual operation.

[0068] When a multi-chip parallel device is connected to an actual working circuit and is in normal operating condition (not a laboratory simulation environment), the instantaneous junction temperature data of all chips in the device is collected in real time.

[0069] Step 109: Substitute the average junction temperature of the device into the correlation between on-state voltage drop and average junction temperature to calculate the theoretical on-state voltage drop.

[0070] First, determine the actual total current of the device during operation. Based on this current value, select the correlation model that best matches the current actual total current from multiple sets of on-state voltage drop-average junction temperature correlation models established for different calibration total currents. Then, retrieve the device's average junction temperature data that has been collected and validated at this moment as the independent variable, and substitute it into the corresponding variable position of the selected on-state voltage drop-average junction temperature correlation model. The calculation result is the theoretical on-state voltage drop that the device should have under the actual operating conditions of the average junction temperature and total current at this moment.

[0071] Step 110: Compare the deviation between the theoretical on-state voltage drop and the actual on-state voltage drop data of the multi-chip parallel device in forward conduction and reverse freewheeling states; if the deviation is within a preset threshold, execute the step of inputting the on-state voltage drop data and DC current distribution data into the pre-established current-junction temperature-on-state voltage drop function relationship; if the deviation is not within the preset threshold, re-execute the step of acquiring the on-state voltage drop data of the multi-chip parallel device in forward conduction and reverse freewheeling states.

[0072] By comparing the theoretical on-state voltage drop with the actual on-state voltage drop data collected from the operation of multi-chip parallel devices under forward conduction and reverse freewheeling conditions, the deviation between the two is quantified. If the calculated deviation value is within the preset threshold range, it indicates that the actual on-state voltage drop data collected is accurate and reliable, and the subsequent steps of inputting the on-state voltage drop data and DC current distribution data into the pre-established current-junction temperature-on-state voltage drop function relationship can continue. If the deviation value exceeds the preset threshold, it indicates that there may be errors in the actual collected data, such as interference from the acquisition equipment or instantaneous device abnormalities. The steps of acquiring the on-state voltage drop data of multi-chip parallel devices under forward conduction and reverse freewheeling conditions need to be repeated until valid data that meets the deviation requirements is collected to avoid invalid data affecting the subsequent junction temperature calculation results.

[0073] The threshold in this step can be set based on the detection accuracy requirements and device characteristics, such as ≤5%, but the specific value is not limited in this embodiment.

[0074] This embodiment controls the average junction temperature change of multi-chip parallel devices for each group of calibration total current and collects voltage drop data. It then establishes a correlation between on-state voltage drop and average junction temperature, supplementing the actual operating environment characteristics of devices that cannot be covered by single-chip testing. A deviation verification step is added before the input data is sent to the core function. The theoretical voltage drop is calculated by collecting the actual average junction temperature of the device and compared with the actual voltage drop under forward and reverse operating conditions. Only data with deviations within the threshold are allowed to enter the subsequent calculation. This can effectively filter out invalid data caused by acquisition interference or instantaneous device anomalies, thereby avoiding the impact of erroneous data on the accuracy of junction temperature back-calculation.

[0075] Example 5: This embodiment relates to a maximum junction temperature detection device for multi-chip parallel devices. A schematic diagram of the maximum junction temperature detection device for multi-chip parallel devices in this embodiment can be seen as follows: Figure 2 As shown, it includes: a current acquisition device 201, an on-state voltage drop monitoring circuit 202, and a data processing chip 203 connected to the current acquisition device 201 and the on-state voltage drop monitoring circuit 202 respectively.

[0076] Among them, the current acquisition device 201 is used to acquire the DC current distribution data of each chip in the multi-chip parallel device.

[0077] In one embodiment, the current acquisition device includes a vector magnetoresistive sensor array and a magnetic field calculation module. Each sensor in the vector magnetoresistive sensor array is mounted directly above the bonding wire of its corresponding chip in the multi-chip parallel device, and each sensor is used to acquire magnetic field data generated by its corresponding bonding wire below it. Correspondingly, the magnetic field calculation module is used to calculate the DC current distribution data of each chip in the multi-chip parallel device based on the magnetic field data and preset position parameters of the sensors and current-carrying conductors.

[0078] Specifically, each vector magnetoresistive sensor in the vector magnetoresistive sensor array is installed directly above the bonding wire (the core current-carrying component connecting the chip to the external circuitry) of each corresponding chip within the device, forming a one-to-one correspondence between the chip and the sensor. This ensures that each sensor can independently collect the magnetic field data generated by the bonding wire directly below it when energized, and that this magnetic field data can be directly correlated to the corresponding single chip, laying the foundation for subsequent differentiation of the current of each chip. For example... Figure 3The diagram shows the specific layout of a vector magnetoresistive sensor array in a multi-chip parallel high-power IGBT module. A PCB substrate is placed on silicone within the IGBT module, and the vector magnetoresistive sensor array is placed on the substrate. The specific layout of the vector magnetoresistive sensor array on the PCB substrate is shown below. Figure 3 As shown in the block, the circular holes on the substrate are used to fix the entire substrate and ensure the stability of its relative position, thereby ensuring that the detection of static current distribution is not deviated due to the offset of the substrate position during actual operation.

[0079] The magnetic field calculation module, based on each set of magnetic field data transmitted from the sensor array, and combined with pre-calibrated positional parameters of the sensor and the current-carrying conductor (i.e., bond wire), such as the vertical distance and horizontal angle between the sensor and the bond wire, performs calculations using electromagnetic-related models to ultimately calculate the DC current magnitude of each chip in the multi-chip parallel device, thus forming complete DC current distribution data for each chip. This current acquisition device achieves accurate and non-invasive acquisition of the current of a single chip in a multi-chip parallel device through the collaborative logic of precise magnetic field acquisition by the sensor array and current deduction by the calculation module. Furthermore, to simplify the device structure and improve integration, the magnetic field calculation module can also be integrated into the data processing chip 203, eliminating the need for a separate hardware module.

[0080] This method can accurately locate the maximum junction temperature of all chips in the device, thereby enabling early warning of overheating faults and providing data support for the implementation of junction temperature closed-loop control strategies, ultimately effectively improving the operational reliability and service life of multi-chip parallel devices.

[0081] In this embodiment, the specific device type selected for the vector magnetoresistive sensor array is not limited; specifically, the HMC1021S anisotropic magnetoresistive sensor can be used. The HMC1021S uses an SOIC-8 package, has a supply voltage of 2-2.5V, and a bandwidth of up to 5MHz. Internally, this device employs a Wheatstone bridge structure, such as... Figure 4 The diagram shows the structure of an HMC1021S type anisotropic magnetoresistive resistor, where R1~R4 are AMRs, i.e., anisotropic magnetoresistive resistors. The resistance of this ferromagnetic material is related to the angle between the direction of its internal magnetization and the direction of the current: the resistance reaches its maximum value when the magnetization direction is parallel to the current direction; the resistance is at its minimum when the magnetization direction is perpendicular to the current direction. Figure 5 As shown in section b, to make the relationship between resistance and magnetic field strength more linear, aluminum strips are embedded at intervals in the permalloy during AMR manufacturing to force the current to flow at a 45-degree angle to the initial magnetization direction. Figure 5As shown in section a, the 45-degree angle is precisely the center of the linear region of the curve. Therefore, when the applied magnetic field strength is not large, the resistance of the permalloy is linearly related to the magnitude of the applied magnetic field. This structure is also known as the barber's stick structure. Under this structure, the direction with the highest measurement sensitivity is perpendicular to the initial magnetization direction. Applying a magnetic field in this direction has the greatest impact on the direction of magnetization intensity and also the greatest impact on the AMR resistance value. Conversely, applying a magnetic field parallel to the initial magnetization direction has almost no effect on the direction of magnetization intensity and also has almost no effect on the AMR resistance value.

[0082] Initially, if there is no external magnetic field, R1 to R4 are all equal, so the voltage between the positive and negative terminals of the output is 0. However, when a certain magnetic field is applied to the sensitive axis, the changes in R1 and R4 are opposite in polarity to the changes in R2 and R3, but the magnitudes are the same. This causes the Wheatstone bridge to become unbalanced, resulting in the output voltages not being zero. Furthermore, the sign of the output voltage reflects the direction of the upward magnetic field on the sensitive axis. Therefore, the output voltage of the Wheatstone bridge can map the magnitude and direction of the external sensitive magnetic field. The relationship between the two can be preliminarily expressed as:

[0083] Where k is the proportionality constant and B is the magnetic flux density along the sensitive axis. According to Biot-Savart's theorem, the relationship between the magnetic flux density B along the sensitive axis and the DC current i in the integer current-carrying conductor can be expressed as:

[0084] in, k 1. This depends on the relative position of the sensor and the current-carrying conductor. In the device, the position of the sensor relative to the current-carrying bond line below is fixed, so the specific value of k1 can be extracted using finite element simulation.

[0085] Combining the above two equations, the relationship between the output voltage of the vector magnetoresistive sensor and the DC current of the current-carrying bond wire below it is as follows:

[0086] Thus, the DC current distribution in each parallel chip within the device can be obtained through the vector magnetoresistive sensor array.

[0087] Of course, other types can also be selected, and all can be referred to the description in this embodiment, which will not be repeated here.

[0088] The on-state voltage drop monitoring circuit 202 is used to acquire on-state voltage drop data of multi-chip parallel devices in both forward conduction and reverse freewheeling states.

[0089] To ensure the accuracy of on-state voltage drop monitoring, the stability of signal acquisition, and compatibility with the device drive system, the input of the on-state voltage drop monitoring circuit can be connected to a port formed by the external drive source and desaturation detection terminal of a multi-chip parallel device. This connection method eliminates the need for additional modifications to the package structure of the multi-chip parallel device; the on-state voltage drop signal can be acquired using the device's existing functional ports. This simplifies circuit connection complexity and avoids reliability issues that might arise from compromising device sealing. Furthermore, the signal link between the external drive source and the desaturation detection terminal is strongly correlated with the device's conduction state, enabling rapid response to dynamic changes in the on-state voltage drop, reducing signal transmission delay, and minimizing signal interference at this port. This improves the signal-to-noise ratio of the on-state voltage drop monitoring data, providing more reliable basic parameters for subsequent inversion of the chip junction temperature using magnetic field data.

[0090] The data processing chip 203 is used to input the on-state voltage drop data and DC current distribution data into a pre-established current-junction temperature-on-state voltage drop function relationship, calculate the junction temperature data of each chip, compare the junction temperature data of each chip, and determine the maximum junction temperature data and the corresponding chip in the multi-chip parallel device.

[0091] It should be noted that the contents of the multi-chip parallel device maximum junction temperature detection device provided in this embodiment can be referred to in conjunction with the multi-chip parallel device maximum junction temperature detection method provided in the above embodiments, and the repeated parts will not be repeated in this embodiment.

[0092] In the multi-chip parallel device maximum junction temperature detection device provided in this embodiment, the current acquisition device can accurately capture the DC current distribution data of each chip, breaking through the limitation of traditional devices that can only monitor the total current of the device and cannot separate the current of a single chip, providing refined current parameter support for single-chip junction temperature calculation; the on-state voltage drop monitoring circuit specifically covers the two core operating states of the device: forward conduction and reverse freewheeling, and the acquired on-state voltage drop data is more consistent with the actual operating scenario of the device, avoiding the junction temperature calculation deviation caused by single operating condition data; the data processing chip, as the core control unit, relies on the pre-established current-junction temperature-on-state voltage drop function relationship to convert the current and voltage drop data into accurate single-chip junction temperature data, and at the same time, realizes the rapid location of the maximum junction temperature and the corresponding chip by comparing the junction temperature data. This not only solves the problem of difficulty in monitoring the junction temperature of each chip in a multi-chip parallel scenario, but also provides direct basis for device overheating fault early warning and troubleshooting of problematic chips. The components of the overall equipment work together in a closed loop from data acquisition to result output, which not only ensures the accuracy and comprehensiveness of junction temperature detection, but also enhances the engineering practical value of the test results, providing strong technical support for ensuring the reliable operation of multi-chip parallel devices.

[0093] Example 6: This embodiment relates to a maximum junction temperature detection system for multi-chip parallel devices. A schematic diagram of the maximum junction temperature detection device for multi-chip parallel devices in this embodiment can be seen as follows: Figure 6 As shown, it includes: multi-chip parallel devices and a device for detecting the maximum junction temperature of multi-chip parallel devices.

[0094] Among them, the maximum junction temperature detection equipment for multi-chip parallel devices establishes an electrical connection with the multi-chip parallel devices.

[0095] The maximum junction temperature detection equipment for multi-chip parallel devices is used to collect DC current distribution data and on-state voltage drop data under forward conduction and reverse freewheeling states of each chip in the multi-chip parallel device. Based on the DC current distribution data and on-state voltage drop data, the junction temperature data of each chip in the multi-chip parallel device is calculated to determine the maximum junction temperature data and the corresponding chip.

[0096] The relevant functional descriptions of multi-chip parallel devices and multi-chip parallel device maximum junction temperature detection equipment can be found in the descriptions of the above embodiments, and will not be repeated here.

[0097] like Figure 7 The diagram shows an assembly schematic of a maximum junction temperature detection device for a multi-chip parallel device. The device is integrated inside the device under test, with a PCB board as the core substrate. In the substrate design and layout, vector magnetoresistive sensors are positioned at corresponding locations on the current-carrying bond lines of each parallel chip within the device. The detection axis of each sensor is perpendicular to the extension direction of the bond line below, ensuring accurate magnetic field detection. Externally, a forward voltage drop detection circuit is directly connected to the device, enabling continuous monitoring and data acquisition of the overall forward voltage drop. Based on the static magnetic field distribution detection results obtained from the vector magnetoresistive sensor array on the substrate, combined with the overall voltage drop data acquired by the external forward voltage drop detection circuit, the real-time junction temperature of each parallel chip inside the device can be calculated.

[0098] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A method for detecting the maximum junction temperature of a multi-chip parallel device, characterized in that, include: Collect DC current distribution data of each chip in a multi-chip parallel device; Obtain the on-state voltage drop data of the multi-chip parallel device in both forward conduction and reverse freewheeling states; The on-state voltage drop data and the DC current distribution data are input into a pre-established current-junction temperature-on-state voltage drop function relationship to calculate the junction temperature data of each chip; The junction temperature data of each chip are compared to determine the maximum junction temperature data and the corresponding chip in the multi-chip parallel device.

2. The method for detecting the maximum junction temperature of a multi-chip parallel device according to claim 1, characterized in that, The method for establishing the current-junction temperature-on-state voltage drop function relationship includes: Collect multiple sets of single-current-junction temperature-on-state voltage drop data for a single chip at different junction temperatures under different total currents; the single chip and the chips in the multi-chip parallel device are of the same model. By integrating multiple sets of single current-junction temperature-on-state voltage drop data, a three-dimensional dataset of current-junction temperature-voltage drop is constructed. Based on the aforementioned three-dimensional dataset, a bivariate fitting algorithm was used to establish a function model with current and junction temperature as independent variables and on-state voltage drop as dependent variable, thereby obtaining the current-junction temperature-on-state voltage drop functional relationship.

3. The method for detecting the maximum junction temperature of a multi-chip parallel device according to claim 2, characterized in that, The data collected includes multiple sets of single-chip current-junction temperature-on-state voltage drop data at different junction temperatures under different total currents, including: Set multiple different total calibration currents; For each group of calibration total current, the operating current of the single chip is fixed to the corresponding calibration total current of that group, and the junction temperature of the single chip is gradually changed by a temperature control device. During the single-chip junction temperature change process, the single-chip on-state voltage drop data corresponding to different junction temperatures are collected in real time to obtain the single current-junction temperature-on-state voltage drop data under the calibration total current. Obtain the single current-junction temperature-on-state voltage drop data under the total calibration current for all groups.

4. The method for detecting the maximum junction temperature of a multi-chip parallel device according to claim 3, characterized in that, After setting multiple different sets of calibration total currents, the following is also included: For each group of calibration total current, the average junction temperature of the multi-chip parallel device is gradually changed by the temperature control device, and the corresponding on-state voltage drop data is collected as the first data; Based on the first data, a correlation between on-state voltage drop and average junction temperature is established; Before inputting the on-state voltage drop data and the DC current distribution data into the pre-established current-junction temperature-on-state voltage drop function relationship, the method further includes: The average junction temperature of the multi-chip parallel device during actual operation was collected. Substituting the average junction temperature of the device into the on-state voltage drop-average junction temperature correlation, the theoretical on-state voltage drop is calculated. Compare the deviation between the theoretical on-state voltage drop and the actual on-state voltage drop data of the multi-chip parallel device in the forward conduction and reverse freewheeling states; If the deviation is within a preset threshold, the step of inputting the on-state voltage drop data and the DC current distribution data into the pre-established current-junction temperature-on-state voltage drop function relationship is executed; If the deviation is not within the preset threshold, the step of obtaining the on-state voltage drop data of the multi-chip parallel device in the forward conduction and reverse freewheeling states is repeated.

5. The method for detecting the maximum junction temperature of a multi-chip parallel device according to claim 1, characterized in that, The acquisition of DC current distribution data for each chip in a multi-chip parallel device includes: The magnetic field data generated at the bonding line directly below each sensor is acquired by a vector magnetoresistive sensor array; each sensor in the vector magnetoresistive sensor array is installed directly above the bonding line of the corresponding chip. Based on the magnetic field data, and combined with the preset position parameters of the sensor and the current-carrying conductor, the DC current distribution data of each chip in the multi-chip parallel device is calculated.

6. A device for detecting the maximum junction temperature of a multi-chip parallel device, characterized in that, include: A current acquisition device, an on-state voltage drop monitoring circuit, and a data processing chip connected to the current acquisition device and the on-state voltage drop monitoring circuit respectively; The current acquisition device is used to acquire DC current distribution data of each chip in the multi-chip parallel device; The on-state voltage drop monitoring circuit is used to acquire on-state voltage drop data of the multi-chip parallel device in both forward conduction and reverse freewheeling states. The data processing chip is used to input the on-state voltage drop data and the DC current distribution data into a pre-established current-junction temperature-on-state voltage drop function relationship, calculate the junction temperature data of each chip, compare the junction temperature data of each chip, and determine the maximum junction temperature data and the corresponding chip in the multi-chip parallel device.

7. The maximum junction temperature detection device for multi-chip parallel devices according to claim 6, characterized in that, The current acquisition device includes: a vector magnetoresistive sensor array and a magnetic field calculation module; In the vector magnetoresistive sensor array, each sensor is mounted directly above the bonding wire of the corresponding chip in the multi-chip parallel device, and each sensor is used to collect magnetic field data generated by the bonding wire directly below it. The magnetic field calculation module is used to calculate the DC current distribution data of each chip in the multi-chip parallel device based on the magnetic field data and in combination with the preset position parameters of the sensor and the current-carrying conductor.

8. The maximum junction temperature detection device for multi-chip parallel devices according to claim 7, characterized in that, The vector magnetoresistive sensor array is an HMC1021S type anisotropic magnetoresistive sensor.

9. The maximum junction temperature detection device for multi-chip parallel devices according to claim 6, characterized in that, The input terminal of the on-state voltage drop monitoring circuit is connected to the port formed by the external driving source and the desaturation detection terminal of the multi-chip parallel device.

10. A system for detecting the maximum junction temperature of a multi-chip parallel device, characterized in that, include: A multi-chip parallel device and a maximum junction temperature detection device for a multi-chip parallel device as described in any one of claims 6 to 9; The maximum junction temperature detection device for the multi-chip parallel device is electrically connected to the multi-chip parallel device; The maximum junction temperature detection device for the multi-chip parallel device is used to collect the DC current distribution data and the on-state voltage drop data under forward conduction and reverse freewheeling states of each chip in the multi-chip parallel device, and calculate the junction temperature data of each chip in the multi-chip parallel device based on the DC current distribution data and the on-state voltage drop data, and determine the maximum junction temperature data and the corresponding chip.

Images