A reverse blocking double-ended solid-state thyristor, its triggering circuit and fabrication method

Abstract

This invention provides a reverse-blocking double-ended solid-state thyristor, its triggering circuit, and its fabrication method, belonging to the field of thyristors, which includes an N-type anode. + Silicon carbide emitter, sequentially composed of N + Silicon carbide P obtained by epitaxial growth on silicon carbide emitter ‑ Drift region, silicon carbide N drift region, silicon carbide P + Emitter and silicon carbide N + Emitter region, silicon carbide P + Emitter and silicon carbide N + The emission regions are located on different planes but are parallel to each other, and they are alternately connected to form a continuous square concave-convex surface. (Silicon carbide P) + Emitter and silicon carbide N + The emitting region is used as the cathode. This invention also provides a method for fabricating a reverse-blocking double-ended solid-state thyristor and its triggering circuit. The thyristor device of this invention has high voltage blocking capability, high turn-on rate, and high current rise rate (di / dt) capability, while its structure is more miniaturized. The triggering circuit of the reverse-blocking double-ended solid-state thyristor of this invention is suitable for use with a negative high-voltage triggering method.

Description

Technical Field

[0001] This invention belongs to the field of thyristors, and more specifically, relates to a reverse blocking double-ended solid-state thyristor, its triggering circuit, and its fabrication method. Background Technology

[0002] Pulse power technology has extremely important applications in high-tech fields, and its application scope is now expanding to industrial and civilian sectors. The reverse turn-off thyristor is an important pulse power device used in pulse power technology.

[0003] A reverse blocking diode thyristor (RBDT) is a two-terminal semiconductor closed-loop switch with a pnpn structure. Originally called a reverse switching rectifier (RSR), the RBDT was initially used as a switching element in radar modulators. The RBDT has a PNPN four-layer structure, and during triggering, a trigger pulse with a high rate of voltage change (dv / dt) needs to be applied between the anode and cathode. The unique triggering method of the RBDT causes its conduction process to occur across the entire region of the device, allowing it to withstand pulse currents with a higher rate of current rise (di / dt).

[0004] However, after a long period of research, silicon-based materials have almost reached their performance limits in the fabrication of devices. Compared to silicon, wide-bandgap silicon carbide (SiC) has a higher bandgap, saturated carrier velocity, critical breakdown electric field, and thermal conductivity, making SiC devices significantly superior in performance to silicon devices. This is especially true in pulse applications such as radar and explosive foil initiators, where there are particularly high requirements for the device's turn-on rate and current rise rate (di / dt).

[0005] Currently, devices fabricated using P-type silicon carbide as a substrate have high resistivity because the resistivity of P-type silicon carbide substrates is about two orders of magnitude higher than that of N-type silicon carbide substrates, which is detrimental to reducing forward voltage drop and conduction losses. Further research indicates that silicon-based RBDT devices are limited in applications requiring high voltage, high current, and high current rise rate due to the properties of silicon. Furthermore, high-voltage silicon-based RBDT devices suffer from drawbacks such as high on-state voltage drop and high conduction losses. In addition, using positive high voltage to trigger RBDTs poses safety hazards.

[0006] Therefore, it is necessary to further improve upon existing technologies and develop new reverse-blocking double-ended solid-state thyristors. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the present invention aims to provide a reverse-blocking double-ended solid-state thyristor, its triggering circuit, and its fabrication method, and designs a silicon carbide-based long P-base region (P... - The device features a reverse-blocking double-ended solid-state thyristor (RBDT) with a drift region, employing negative high-voltage triggering, making the device safer and more reliable. Furthermore, through the design of the process flow, device size and specifications, and the use of a P-base region, the device possesses high voltage blocking capability, high turn-on rate, and high current rise rate (di / dt), while also meeting the trend towards miniaturization.

[0008] To achieve the above-mentioned objectives, the present invention provides a reverse-blocking double-ended solid-state thyristor, which includes an N2O anode. + Silicon carbide emitter, sequentially composed of N + Silicon carbide P obtained by epitaxial growth on silicon carbide emitter - Drift region, silicon carbide N drift region and silicon carbide P + Emitter and silicon carbide N + Emitter region, silicon carbide P + Emitter and silicon carbide N + The emission regions are located on different planes but are parallel to each other, and they are alternately connected to form a continuous square concave-convex surface. (Silicon carbide P) + Emitter and silicon carbide N + The emission area is used together as the cathode.

[0009] Furthermore, the silicon carbide material is one or more of 4H-SiC, 6H-SiC, or 3C-SiC.

[0010] Furthermore, N + The silicon carbide emitter thickness is 1 μm to 5 μm, the silicon carbide P-drift region thickness is 30 μm to 150 μm, the silicon carbide N-drift region thickness is 0.8 μm to 4 μm, and the cathode is silicon carbide N... + The emitter region has a thickness of 0.1 μm to 1 μm and a width of 5 μm to 15 μm; the cathode is silicon carbide P. + The thickness of the emission region is 0.5μm to 5μm, and the width is 15μm to 25μm.

[0011] Furthermore, N + The silicon carbide emitter doping concentration is 1×10⁻⁶. 19 ~1×10 20 cm -3 Silicon carbide P - The doping concentration in the drift region is 1×10 14 ~2×10 15 cm -3 The doping concentration of the N drift region of silicon carbide is 1×10⁻⁶. 17 ~1×10 18cm -3 Cathode silicon carbide N + emitter doping concentration 1×10 19 ~1×10 20 cm -3 Cathode silicon carbide P + The emitter doping concentration is 1×10 19 ~1×10 20 cm -3 .

[0012] According to a second aspect of the present invention, a method for preparing the reverse-blocking double-ended solid thyristor as described above is also provided, characterized in that it includes the following steps:

[0013] S1: In clean N + Silicon carbide P is epitaxially grown sequentially on a silicon carbide substrate. - Drift region, silicon carbide N drift region and silicon carbide P + The emission region forms N + P - NP + structure,

[0014] S2: In silicon carbide P + The launch area is formed by etching. + Injection window, in N + N-type ion implantation is performed at the injection window.

[0015] S3: Perform high-temperature annealing treatment at 1150℃~1700℃.

[0016] S4: An ohmic contact is formed between the anode ohmic metal and the cathode ohmic metal and the silicon carbide-based material, respectively, to obtain a reverse-blocking double-ended solid thyristor semi-finished product.

[0017] S5: The sidewall of the reverse-blocking double-ended solid thyristor semi-finished product is cut to form a platform with a negative bevel angle of 1° to 10°. This platform is used as the terminal method, or...

[0018] Photolithography and etching processes are performed on the sidewalls of the reverse blocking double-ended solid-state thyristor semi-finished product to etch away a portion of the sidewalls, forming a stepped surface. Ion implantation is then performed on the stepped surface to obtain the JTE termination mode.

[0019] Negative bevel mesa termination and JTE termination can eliminate functional defects caused by curvature at the corners of the PN junction and improve the device's withstand voltage.

[0020] S6: Deposit a silicon dioxide passivation layer on the table or step surface to obtain a silicon carbide-based reverse blocking double-ended solid thyristor.

[0021] According to a third aspect of the invention, a trigger circuit comprising the reverse blocking double-ended solid-state thyristor as described above is also provided.

[0022] Furthermore, the trigger circuit employs a negative high-voltage triggering method during operation. The absolute value of the negative high-voltage pulse's dv / dt reaches 25000V / μs or higher. When the negative high-voltage pulse generator outputs the dv / dt pulse, it acts on the reverse-blocking double-ended solid-state thyristor through a diode, thereby forming a voltage drop in the silicon carbide N-type drift region, causing the silicon carbide P-type... + Ions are injected into the silicon carbide N drift region from the emitter region to enable device conduction.

[0023] In summary, compared with the prior art, the above-described technical solutions conceived by this invention have the following advantages:

[0024] Beneficial effects:

[0025] In this invention, the reverse blocking double-ended solid-state thyristor includes an N-type anode. + Silicon carbide emitter, sequentially composed of N + Silicon carbide P obtained by epitaxial growth on silicon carbide emitter - Drift region, silicon carbide N drift region and silicon carbide P + Emitter and silicon carbide N + The launch area formed N + P - NP + Furthermore, the overall material is silicon carbide, and the minority carrier lifetime of the N-type epitaxial layer is higher than that of the low-quality P-substrate epitaxial layer, which improves the current amplification factor of the two equivalent transistors inside, thereby enhancing the dynamic current carrying capacity. Further, the design employs a P-type long base region, P... - The drift region is the thickest, and due to its short carrier lifetime, it results in a high carrier recombination rate and a short turn-off time, further improving the turn-off rate of the RBDT and laying the foundation for its application in high repetition frequency fields. Because the thyristor has a P-type long base region, it can be triggered by negative high voltage, achieving more reliable device operation. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of the angled terminal P-type silicon carbide-based reverse blocking double-ended solid thyristor provided in an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of the structure of the tabletop JTE terminal P-type silicon carbide-based reverse blocking double-ended solid thyristor provided in an embodiment of the present invention;

[0028] Figure 3This is a schematic diagram of the trigger circuit structure of a P-type silicon carbide-based reverse blocking double-ended solid-state thyristor in an embodiment of the present invention.

[0029] Figure 4 This is a simulated waveform of a 6200V withstand voltage P-type silicon carbide-based reverse blocking double-ended solid thyristor in an embodiment of the present invention.

[0030] Figure 5 This is a simulated waveform of a 6200V silicon-based reverse blocking double-ended solid-state thyristor. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0032] Figure 1 This is a schematic diagram of the structure of the angled-terminal P-type silicon carbide-based reverse blocking double-ended solid-state thyristor provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of a platform-mounted JTE terminal P-type silicon carbide-based reverse-blocking double-ended solid-state thyristor provided in an embodiment of the present invention. As shown in the figure, the present invention provides a reverse-blocking double-ended solid-state thyristor, which includes an N-type anode used as the anode. + Silicon carbide emitter, sequentially composed of N + Silicon carbide P obtained by epitaxial growth on silicon carbide emitter - Drift region, silicon carbide N drift region and silicon carbide P + Emitter and silicon carbide N + Emitter region, silicon carbide P + Emitter and silicon carbide N + The emission regions are located on different planes but are parallel to each other. They alternate and connect to form a continuous square convex-concave surface. (Silicon carbide P) + Emitter and silicon carbide N + The emitter region is used as the cathode. The silicon carbide material is one or more of 4H-SiC, 6H-SiC, or 3C-SiC. + The silicon carbide emitter thickness is 1μm to 5μm, and the silicon carbide P - The drift region thickness is 30 μm to 150 μm, the silicon carbide N drift region thickness is 0.8 μm to 4 μm, and the cathode silicon carbide N... + The emitter region has a thickness of 0.1 μm to 1 μm and a width of 5 μm to 15 μm; the cathode is silicon carbide P. + The emission region has a thickness of 0.5 μm to 5 μm and a width of 15 μm to 25 μm. N + The silicon carbide emitter doping concentration is 1×10⁻⁶. 19 ~1×10 20 cm-3 Silicon carbide P - The doping concentration in the drift region is 1×10 14 ~2×10 15 cm -3 The doping concentration of the N drift region of silicon carbide is 1×10⁻⁶. 17 ~1×10 18 cm -3 The doping concentration of the N+ emitter region of the cathode silicon carbide is 1×10⁻⁶. 19 ~1×10 20 cm -3 The doping concentration of the silicon carbide P+ emitter region at the cathode is 1×10⁻⁶. 19 ~1×10 20 cm -3 The design of the above materials, structure, size, and doping concentration fully guarantees the performance of the P-type silicon carbide-based reverse blocking double-ended solid-state thyristor.

[0033] In this invention, the specifications for the size and doping concentration of the P-base region are defined, with a P-base region thickness of 30 μm to 150 μm and a doping concentration of 1 × 10⁻⁶. 14 ~2×10 15 cm -3 It can achieve high blocking voltages of 3kV to 15kV; in contrast, silicon-based devices require a base region thickness of 300μm to 1500μm to achieve the same withstand voltage. Using SiC RBDTs effectively avoids the reliability problems caused by multiple low-voltage Si RBDTs connected in series, and also helps to reduce the thickness of the device, thereby improving the on-state characteristics of the device.

[0034] In this invention, the doping concentration and size of the N-based region are limited, the thickness of the N drift region is 0.8 μm to 4 μm, and the doping concentration is 1 × 10⁻⁶. 17 ~1×10 18 cm -3 While ensuring the device's withstand voltage rating, the thickness and doping concentration of the N-drift region were improved, reducing the on-state voltage drop and ensuring excellent dynamic performance of the switch.

[0035] In this invention, since silicon carbide has a breakdown field strength of about 2.2 MV / cm, a band gap of about 3.25 eV, and a thermal conductivity of about 3.7 W / (cm·K), the P-type RBDT can achieve a withstand voltage level of 3kV to 15kV with a P-drift region thickness of only 30μm to 150μm. This solves the problem of high resistance caused by using multiple devices with low withstand voltage ratings in series. At the same time, it can work reliably at a high junction temperature of 500℃.

[0036] In this invention, a P-type long base region is adopted in the design. Based on its short carrier lifetime, the carrier recombination rate is high and the turn-off time is short, thereby further improving the turn-off rate of the RBDT and laying the foundation for its application in the field of high repetition frequency.

[0037] In this invention, there is no need to perform grinding or thinning processes on the N substrate, resulting in a chip with high hardness and greater strength.

[0038] In this invention, a P-substrate is epitaxially grown on an N-substrate. The minority carrier lifetime of the N-substrate epitaxial layer is higher than that of the low-quality P-substrate epitaxial layer, which improves the current amplification factor of the two equivalent transistors inside, thereby enhancing the dynamic current carrying capacity. However, since the resistivity of the P-substrate is two orders of magnitude higher than that of the N-substrate, using a P-substrate for epitaxial growth would increase the on-resistance of the device at the same voltage rating, which is detrimental to reducing forward voltage drop and conduction losses.

[0039] The specific steps of the method for preparing the P-type reverse blocking double-ended solid thyristor of this invention include:

[0040] (1) Select clean N + Silicon carbide substrate, sequentially in the N + Silicon carbide P-type epitaxial growth on silicon carbide substrate - Base region (silicon carbide P) - (drift region), silicon carbide N drift region and silicon carbide P drift region + The emission region forms N + P - NP + Structure. N + The silicon carbide substrate can be a 4H-SiC substrate, a 6H-SiC substrate, or a 3C-SiC substrate. (Epitaphing is a process that allows semiconductors of the same or different doping types to be grown on a semiconductor substrate.)

[0041] (2) After cleaning, an etching process is performed on silicon carbide P + Emitter region (silicon carbide P) + The emission region (used as part of the cathode) forms N + The implantation window structure can be constructed by magnetron sputtering to deposit a Ni metal mask layer, followed by photolithography and stripping with an AZ400T or acetone, and then dry etching to form the N+ implantation window. Alternatively, selective ICP etching can be performed in a mixture of fluorinated and oxygen gases at a radio frequency power of 300W–600W and an appropriate working pressure to form the ion implantation window. + The injection window and the remaining unetched silicon carbide P + The emission areas are not on the same plane, but they are parallel to each other, and they alternate to form a square concave-convex surface.

[0042] (3) Next, in N + N-type ion implantation is performed at the implantation window, causing N-type ions to be implanted on the cathode side. + Silicon carbide N is formed within the injection window. + Emitter region, silicon carbide P + Emitter and silicon carbide N + The emission regions together form the cathode.

[0043] (4) The implanted ions are activated by high-temperature annealing at 1150℃~1700℃. High-temperature heat treatment can effectively repair crystal damage caused by ion implantation in single crystals. Because when impurity ions are implanted into silicon carbide, the high-energy incident ions collide with atoms on the semiconductor lattice, causing some lattice atoms to shift, resulting in a large number of vacancies. This will cause the atoms in the implanted region to be arranged in a disordered manner or become an amorphous region. Therefore, after ion implantation, the semiconductor is annealed at an appropriate temperature to restore the crystal structure and eliminate defects, while reducing hardness and improving machinability.

[0044] (5) After annealing, the ohmic metal of the anode and the ohmic metal of the cathode are respectively connected to the silicon carbide-based material to form an ohmic contact, thereby obtaining a reverse blocking thyristor semi-finished product.

[0045] (6) Use a diamond blade to mechanically cut the reverse blocking thyristor semi-finished product to form a mesa with a negative bevel angle of 1° to 10° on the side of the structure as the termination method. Alternatively, perform photolithography and etching processes on the sidewall of the reverse blocking double-ended solid thyristor semi-finished product to etch away part of the sidewall to form a step surface, and complete ion implantation on the step surface to obtain the JTE termination method.

[0046] When SiC-type RBDTs are fabricated using ion implantation to prepare the PN junction, curvature is usually present at the corners of the PN junction, resulting in a large electric field value at the corners, i.e., a spike electric field, which causes premature breakdown of the device. Based on the structural characteristics of SiC-type RBDTs and considering that their blocking junction is a shallow junction structure, it is proposed to use a beveled or stepped surface as its termination, which can better overcome the above problems.

[0047] (7) A silicon dioxide passivation layer is prepared on a platform with a negative oblique angle of 1° to 10° by low-pressure vapor phase deposition or LPCVD deposition, and a reverse blocking double-ended solid thyristor based on silicon carbide can be obtained.

[0048] Given the current level of defect control in silicon carbide materials, this invention utilizes an easily implemented process that eliminates the need for grinding and thinning of the device, thereby protecting other areas of the device, reducing damage to the device, and improving the device's robustness.

[0049] More specifically, the method of the present invention will be explained in more detail using the preparation process of a 6200V SiC type RBDT as an example:

[0050] (1) Select N + Type 4H-SiC is used as the substrate, with a substrate thickness of 300μm to 350μm.

[0051] (2) After chemical mechanical polishing, boil in trichloroethylene, acetone and anhydrous ethanol for about 20 minutes in sequence. After washing with deionized water and boiling for 20 minutes, heat in a solution of sulfuric acid and sulfurous acid in a volume ratio of 3:1 for 20 minutes. Then rinse in deionized water. Finally, remove the surface oxide layer with 5% HF solution.

[0052] (3) In N + Epitaxial growth with a thickness of 70 μm and an aluminum ion doping concentration of 1 × 10⁻⁶ was performed on a silicon carbide substrate. 14 Up to 2×10 15 cm -3 P - The base region has an epitaxial temperature of 1650℃~1850℃, a pressure of 80mbar~150mbar, reactants are silane and propane, carrier gas is pure hydrogen, and impurity source is trimethylaluminum.

[0053] (4) In P - The base region is epitaxially grown to a thickness of 2 μm with a nitrogen ion doping concentration of 1 × 10⁻⁶. 17 Up to 2×10 17 cm -3 The N-drift region has an epitaxial temperature of 1650℃~1850℃ and a pressure of 80mbar~150mbar. The reaction gases are silane and propane, the carrier gas is pure hydrogen, and the impurity source is pure nitrogen.

[0054] (5) Epitaxial growth of aluminum ion doping concentration of 1×10⁻⁶ with a thickness of 0.5 μm to 5 μm was performed on the N-drift region. 19 Up to 9×10 19 cm -3 P + Launch area. Its epitaxial temperature is 1650℃~1850℃, pressure is 80~150mbar, the reactant gases are silane and propane, the carrier gas is pure hydrogen, and the impurity source is trimethylaluminum.

[0055] (6) Based on the structure obtained above, RCA cleaning is performed to remove impurities on the wafer surface, including organic matter, metal ions, or metal hydrides, and then photolithography is performed. The photolithography position is aligned with the target cathode side N to be formed. + The injection window is positioned accordingly.

[0056] (7) Next, magnetron sputtering is performed to deposit metallic Ni, and then the target cathode side N is removed by stripping with AZ400T or acetone. + Ni is injected into the window to ensure that only the P+ emitter region of the target silicon carbide cathode has a Ni mask, followed by dry etching to form the cathode-side N. + Inject window.

[0057] (8) Finally, from the top layer, namely the silicon carbide cathode P + N-type ion implantation is performed above the emission region, causing N-type ions to be implanted on the cathode side. + Silicon carbide N, which forms the cathode within the injection window + Launch area.

[0058] (9) N-type doped ions are nitrogen, phosphorus, or ions of the same group. Ion implantation is performed in the temperature range of 500℃~800℃, so that the cathode N + The thickness of the injection zone is 0.5 μm to 10 μm, and the injection concentration is 1 × 10⁻⁶. 19 Up to 1×10 20 cm -3 .

[0059] (10) Clean the structure after the above steps and anneal it in a high temperature argon atmosphere of 1200℃~1800℃ for 1 hour to activate it. At the same time, the high temperature annealing can also eliminate the lattice damage of SiC.

[0060] (11) A Ni / Ti / Al alloy of 110nm / 30nm / 110nm is anoly deposited on a silicon carbide wafer, and the entire silicon carbide wafer is annealed in nitrogen at 1000℃ for 3 minutes to form an ohmic contact.

[0061] (12) Photoresist is coated on the entire silicon carbide wafer anode, and then N+ ohmic contact area is formed by development. A 100nm / 35nm / 100nm / 100nm Ni / Ti / Al / Ag alloy is deposited on the entire silicon carbide wafer anode, and then the anode contact metal layer is formed by ultrasonic peeling. The entire silicon carbide wafer is annealed in nitrogen at 1000℃ for 3 minutes to form ohmic contacts.

[0062] (13) A mesa terminal is formed by mechanical cutting with a diamond blade with a 2° negative bevel angle. Specifically, when SiC type RBDT is fabricated by ion implantation to prepare the PN junction, there is usually curvature at the corner of the PN junction, which results in a large electric field value at the corner, i.e., there is a peak electric field, which causes the device to break down prematurely. Based on the structural characteristics of SiC type RBDT, and considering that its blocking junction is a shallow junction structure, it is proposed to use a mesa with a bevel angle as its terminal.

[0063] In another specific engineering practice of this invention, a Ni coating is obtained on the entire cathode end face of a silicon carbide wafer using photolithography and magnetron sputtering. After peeling, a Ni mask is formed. Dry etching is then performed to remove a portion of the sidewall of the silicon carbide wafer, creating stepped surfaces on both sides. The entire silicon carbide chip is cleaned to remove the Ni mask. Photolithography, magnetron sputtering, and Ni deposition are then performed again, followed by peeling to form a mask, exposing the stepped surfaces to form JTE implantation windows. Ion implantation is then performed to form the JTE doped region. Finally, the silicon carbide chip is cleaned to remove the Ni mask. The obtained stepped surfaces serve as JTE terminations. The advantages of using mesa JTE terminations are as follows: Because the voltage junction of a P-type SiC RBDT is shallow, mesa JTE terminations can introduce charge at the voltage junction of the SiC RBDT. When the voltage junction is subjected to voltage, the JTE region can widen the depletion region to achieve charge compensation, thereby alleviating the phenomenon of electric field concentration and improving the voltage withstand capability of the P-type SiC RBDT. Furthermore,

[0064] The advantages of dry etching are: SiC material has high hardness and stable chemical properties, making it difficult to obtain the desired morphology using chemical reagents. Since the breakdown junction of p-type SiC RBDT is shallow, better etching of the terminals is necessary to improve breakdown voltage. This embodiment uses ICP etching, which, compared to traditional reactive ion etching, has a higher ion density and faster etching rate, allowing for better control of the SiC RBDT's terminal morphology and thus improving breakdown voltage performance.

[0065] (14) LPCVD is used to deposit a SiO2 passivation layer on the mesa or step surface to complete the fabrication of the device. The thickness of the SiO2 passivation layer is 2μm, which can significantly reduce the leakage current of the device.

[0066] (15) After processing the tabletop shape (or stepped surface shape) and passivation layer, the plate is encapsulated to obtain a high-voltage silicon carbide reverse blocking double-ended solid thyristor.

[0067] Figure 3 This is a schematic diagram of the trigger circuit structure of a P-type silicon carbide-based reverse blocking double-ended solid-state thyristor in an embodiment of the present invention. As shown in the figure, the circuit consists of a main capacitor C0, a reverse blocking double-ended solid-state thyristor RBDT, a discharge diode D2, a trigger diode D1, a charging resistor Rs, a power supply U0, and a load R. L The circuit consists of an inductor Ls and a high dv / dt signal source. Trigger diode D1 prevents the main capacitor discharge current from flowing into the signal source and interfering with it, while simultaneously transmitting the high dv / dt signal to the RBDT and triggering it. Discharge diode D2 allows high peak current to flow through it and blocks the high dv / dt signal, thus affecting the voltage of the charging capacitor C0.

[0068] In this invention, a negative high-voltage triggering method is employed to achieve more reliable device operation. For a P-type reverse blocking double-ended solid-state thyristor (RBDT), a circuit using a negative high-voltage triggering method is designed, where the absolute value of the negative high-voltage pulse's dv / dt needs to reach 25000V / μs or higher. When the negative high-voltage pulse generator outputs a high dv / dt pulse, it will act on the P-type RBDT device through the trigger diode D1, thereby forming a voltage drop in the N-base region and causing the P-type RBDT to... + The emitter injects ions into the N-base region, thus turning on the device. Using a negative high-voltage triggering method, if static electricity is generated, it flows from the negative terminal to the positive terminal and can directly into the ground. With a positive high-voltage power supply, static electricity is injected through the positive terminal and directly into various components, potentially damaging the circuitry. Furthermore, negative high-voltage radiation is lower than positive high-voltage radiation, posing less harm to the human body.

[0069] Figure 4 and Figure 5 These are simulation waveforms of a P-type silicon carbide-based RBDT and a silicon-based RBDT under the same external circuit conditions. Both devices have a withstand voltage of 6200V. Figure 4 It can be seen that the peak current of the P-type SiC RBDT reaches 6750A, while Figure 5 The peak current of the silicon-based RBDT is only 1800A, while the peak current of the P-type SiC RBDT is 3.75 times that of the Si RBDT. This is because the withstand voltage region of the 6200V P-type SiC RBDT is only 70μm, while the withstand voltage region of the 6200V Si RBDT reaches 700μm, which greatly increases the conduction loss of the Si RBDT.

[0070] Furthermore, from Figure 4 It can be seen that the turn-off time of the P-type SiC RBDT is approximately 12μs. This is because at 12μs, the external circuit applies voltage to the SiC RBDT again. Since the P-type SiC RBDT can stably withstand the voltage, the turn-off time is within 12μs. However, from... Figure 5As can be seen, when a voltage is applied across the Si RBDT again at 40 μs, the Si RBDT cannot stably withstand the voltage, and current flows through the Si RBDT device again, indicating that the Si RBDT is not turned off at this time. Therefore, the turn-off time of the P-type SiC RBDT is less than 30% of that of the Si RBDT. This is because the minority carrier lifetime of the P-type SiC RBDT is short, significantly reducing the turn-off time and paving the way for its application in high-frequency fields. Furthermore, in the simulation, the drift region carrier lifetime of the P-type SiC RBDT is 1.5 μs. In actual manufacturing, the drift region carrier lifetime can be even lower than 1.5 μs. In this case, carrier recombination will be more frequent, further reducing the turn-off time of the P-type SiC RBDT.

[0071] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A reverse-blocking double-ended solid-state thyristor, characterized in that, It includes N used as the anode. + Silicon carbide emitter, sequentially composed of N + Silicon carbide P obtained by epitaxial growth on silicon carbide emitter - Drift region, silicon carbide N drift region, silicon carbide P + Emitter and silicon carbide N + The emission region, in which silicon carbide P + The launch area is formed by etching. + Injection window, in N + N-type ion implantation was performed at the implantation window to obtain silicon carbide N-type ions. + Emitter region, silicon carbide P + Emitter and silicon carbide N + The emission regions are located on different planes but are parallel to each other, and they are alternately connected to form a continuous square concave-convex surface. (Silicon carbide P) + Emitter and silicon carbide N + The continuous square concave-convex structure formed by alternating connection of the emission regions is used as the cathode.

2. The reverse blocking double-ended solid-state thyristor as described in claim 1, characterized in that, The silicon carbide material is one or more of 4H-SiC, 6H-SiC, or 3C-SiC.

3. A reverse-blocking double-ended solid-state thyristor as described in claim 2, characterized in that, N + The silicon carbide emitter thickness is 1μm to 5μm, and the silicon carbide P... - The drift region thickness is 30 μm to 150 μm, the silicon carbide N drift region thickness is 0.8 μm to 4 μm, and the cathode silicon carbide N... + The emitter region has a thickness of 0.1 μm to 1 μm and a width of 5 μm to 15 μm; the cathode is silicon carbide P. + The thickness of the emission region is 0.5μm to 5μm, and the width is 15μm to 25μm.

4. The reverse blocking double-ended solid-state thyristor as described in claim 3, characterized in that, N + The silicon carbide emitter doping concentration is 1×10⁻⁶. 19 ~1×10 20 cm -3 Silicon carbide P - The doping concentration in the drift region is 1×10 14 ~2×10 15 cm -3 The doping concentration of the N drift region of silicon carbide is 1×10⁻⁶. 17 ~1×10 18 cm -3 The doping concentration of the N+ emitter region of the cathode silicon carbide is 1×10⁻⁶. 19 ~1×10 20 cm -3 Cathode silicon carbide P + The emitter doping concentration is 1×10 19 ~1×10 20 cm -3 .

5. The method for preparing a reverse-blocking double-ended solid-state thyristor as described in any one of claims 1-4, characterized in that, It includes the following steps: S1: In clean N + Silicon carbide P is epitaxially grown sequentially on a silicon carbide substrate. - Drift region, silicon carbide N drift region and silicon carbide P + The emission region forms N + P - NP + structure, S2: In silicon carbide P + The launch area is formed by etching. + Injection window, in N + N-type ion implantation is performed at the injection window. S3: Perform high-temperature annealing treatment at 1150℃~1700℃. S4: An ohmic contact is formed between the anode ohmic metal and the cathode ohmic metal and the silicon carbide-based material, respectively, to obtain a reverse-blocking double-ended solid thyristor semi-finished product. S5: The sidewall of the reverse-blocking double-ended solid thyristor semi-finished product is cut to form a platform with a negative bevel angle of 1° to 10°. This platform is used as the terminal method, or... Photolithography and etching processes are performed on the sidewalls of the reverse-blocking double-ended solid-state thyristor semi-finished product to etch away a portion of the sidewalls, forming a stepped surface. Ion implantation is then performed on the stepped surface to obtain the JTE termination mode. Negative bevel mesa termination and JTE termination can eliminate functional defects caused by curvature at the corners of the PN junction and improve the device's withstand voltage. S6: Deposit a silicon dioxide passivation layer on the table or step surface to obtain a silicon carbide-based reverse blocking double-ended solid thyristor.

6. A trigger circuit including the reverse blocking double-ended solid-state thyristor as described in any one of claims 1-4.

7. The trigger circuit as described in claim 6, characterized in that, It is triggered by negative high voltage during operation.

8. The trigger circuit as described in claim 7, characterized in that, During operation, the absolute value of the negative high-voltage pulse dv / dt reaches 25000V / μs or higher. When the negative high-voltage pulse generator outputs the dv / dt pulse, it acts on the reverse blocking double-ended solid-state thyristor through the diode, thereby forming a voltage drop in the drift region of silicon carbide N, causing silicon carbide P + Ions are injected into the silicon carbide N drift region from the emitter region to enable device conduction.

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