An N-type silicon carbide-based reverse blocking two-terminal solid state thyristor and a method of manufacturing the same

Abstract

This invention discloses an N-type silicon carbide-based reverse-blocking double-ended solid-state thyristor and its preparation method. The N-type silicon carbide-based reverse-blocking double-ended solid-state thyristor comprises: N + Silicon carbide substrate, and sequentially N + Silicon carbide P epitaxially grown on a silicon carbide substrate + Anode emitter region, silicon carbide N ‑ The drift region and the region composed of silicon carbide P-based region and silicon carbide N-based region + The cathode emission region is composed of [a specific region / area]. The structure of the cathode emission region is formed in the following manner: [the structure is formed in the silicon carbide N-type ... + Zone P + The injection window is then used for P-type ion implantation to make the P + Silicon carbide cathode P is formed within the injection window. + The present invention, by limiting the specifications of the size and doping concentration of the N-based region and through extensive testing and verification, can, on the one hand, more easily achieve a high blocking voltage, thereby effectively avoiding reliability problems caused by series connection; on the other hand, it helps to reduce the thickness of the device, thereby improving the on-state characteristics of the device.

Description

Technical Field

[0001] This invention belongs to the field of solid-state thyristor technology, and more specifically, relates to an N-type silicon carbide-based reverse blocking double-ended solid-state thyristor and its preparation method. Background Technology

[0002] A reverse blocking diode thyristor (RBDT) is a two-terminal semiconductor closed-loop switch with a pnpn structure. Originally called a reverse switching rectifier (RSR), the RBDT was initially used as a switching element in radar modulators. The RBDT has a four-layer PNPN structure, and during triggering, a trigger pulse with a high rate of voltage change (dv / dt) needs to be applied between the anode and cathode. The unique triggering method of the RBDT causes its conduction process to occur across the entire region of the device, allowing it to withstand pulse currents with a higher rate of current rise (di / dt).

[0003] Currently, the most studied silicon carbide PNPN layer structure devices adopt the P-type long base region structure. The reason is that if the N-type long base region is used, it needs to be fabricated on a P-type silicon carbide substrate. At the same doping concentration, the resistivity of the P-type silicon carbide substrate is about two orders of magnitude higher than that of the N-type silicon carbide substrate, which is not conducive to reducing forward voltage drop and on-state loss.

[0004] However, in actual manufacturing processes, the current level of defect control in SiC materials limits the application and development of some power devices. During the epitaxial growth of 4H-SiC crystals, growth conditions, substrate damage, and substrate defects can all introduce various defects into the epitaxial material. Besides epitaxial growth, defects also arise during device fabrication processes, such as high-temperature annealing, ion implantation, and impurity diffusion. For example, impurities and dopant atoms accumulate near dislocations, altering the uniformity of impurity and dopant distribution. Silicon-based RBDT devices are limited in their application in high-voltage, high-current applications due to the properties of silicon. Furthermore, high-voltage silicon-based RBDT devices suffer from drawbacks such as high on-state voltage drop and high conduction loss. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide an N-type silicon carbide-based reverse blocking double-ended solid thyristor and its fabrication method, thereby solving the problem of high forward voltage drop and on-state loss caused by using a P-long base region structure to fabricate PNPN-type thyristors in the prior art.

[0006] This invention provides an N-type silicon carbide-based reverse blocking double-ended solid-state thyristor, comprising: N...+ Silicon carbide substrate, and sequentially in the N + Silicon carbide P epitaxially grown on a silicon carbide substrate + Anode emitter region, silicon carbide N - Drift region, silicon carbide P-based region, and cathode emission region.

[0007] Furthermore, the structure of the cathode emission region is formed by epitaxially growing N on the silicon carbide P-based region. + District, and in N + Zone P + The injection window is then used for P-type ion implantation to make the P + Silicon carbide cathode P is formed within the injection window. + district.

[0008] Among them, in the structure P + N - PP + N + In the N-type silicon carbide-based reverse blocking double-ended solid thyristor, the anode P + The emitter thickness is 1 μm to 3 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 N - The base region thickness is 30 μm to 150 μm, and the doping concentration is 1 × 10⁻⁶. 14 cm -3 ~2×10 15 cm -3 The P-drift region has a thickness of 0.8 μm to 4 μm and a doping concentration of 1 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 Cathode N + The emitter thickness is 0.5 μm to 2 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The width is 15μm~25μm; cathode P + The emitter has a thickness of 0.1 μm to 1 μm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The width is 5μm to 15μm.

[0009] Furthermore, the structure of the cathode emission region is achieved by ion implantation of silicon carbide N into the silicon carbide P-based region. + Formed.

[0010] Among them, in the structure P + N - PN + In the N-type silicon carbide-based reverse blocking double-ended solid thyristor, the anode P + Emitter thickness is 1μm to 5μm, doping concentration is 1×10⁻⁶ 19 cm -3 ~1×10 20 cm -3 The N-base region thickness is 30 μm to 150 μm, and the doping concentration is 1 × 10⁻⁶. 14 cm -3 ~2×10 15 cm -3 The P-drift region has a thickness of 2 μm to 10 μm and a doping concentration of 1 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 Cathode N + The emitter thickness is 0.5 μm to 2 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The width is 15μm to 25μm.

[0011] This invention also provides a method for preparing an N-type silicon carbide-based reverse blocking double-ended solid-state thyristor, comprising the following steps:

[0012] S100: via N + Silicon carbide P is epitaxially grown sequentially on a silicon carbide substrate. + Anode emitter region, silicon carbide N - The drift region and the region composed of silicon carbide P-based region and silicon carbide N-based region + The cathode emission region is formed, and N is generated. + P + N - PN + structure;

[0013] S101: Remove N + Silicon carbide substrate and P + N - PN + structure;

[0014] S102: For the P + N - PN + The structure is etched and in N + P-type cathode emission region formation + Injection window structure, at cathode emitter N +P-type ion implantation is performed to make the P + Silicon carbide cathode P is formed within the injection window. + district;

[0015] S103: Perform high-temperature annealing on the implanted ions and make ohmic contacts between the anode ohmic metal and the cathode ohmic metal and the silicon carbide-based material respectively.

[0016] S104: Mechanical cutting with a diamond blade creates a mesa with a 20°–70° bevel angle on the side of the structure, followed by deposition of a silicon dioxide passivation layer to obtain a P-structure. + N - PP + N + N-type silicon carbide-based reverse blocking double-ended solid thyristor.

[0017] Furthermore, in step S102, a mask layer is formed by magnetron sputtering to deposit metallic Ni, followed by photolithography and stripping using AZ400T or acetone, and then dry etching to form the P. + Injection window; or selective ICP etching in a mixture of fluorinated gas and oxygen at a radio frequency power of 300W to 600W and an appropriate working pressure to form the P + Inject window.

[0018] The thickness of the P+ emitter anode is 1 μm to 3 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 N - The base region thickness is 30 μm to 150 μm, and the doping concentration is 1 × 10⁻⁶. 14 cm -3 ~2×10 15 cm -3 The P-drift region has a thickness of 0.8 μm to 4 μm and a doping concentration of 1 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 Cathode N + The emitter thickness is 0.5 μm to 2 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The width is 15μm~25μm; cathode P + The emitter has a thickness of 0.1 μm to 1 μm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm-3 The width is 5μm to 15μm.

[0019] This invention also provides a method for preparing an N-type silicon carbide-based reverse blocking double-ended solid-state thyristor, comprising the following steps:

[0020] S200: via N + Silicon carbide P is epitaxially grown sequentially on a silicon carbide substrate. + Anode emitter region, silicon carbide N - Drift regions and silicon carbide P-based regions, and the formation of N + P + N - P-structure;

[0021] S201: Remove N + Silicon carbide substrate and P + N - P-structure;

[0022] S202: By directly transferring the pattern of the photomask onto the SiC cathode, P... + N - PN + N in the structure + A photoresist protective film is formed at the emitter, and residual photoresist is removed from the P-base region of the PNP thyristor unit on the SiC wafer.

[0023] S203: Cathode N is formed by selective ion implantation into the P-based region. + Emitter, and form P + N - PN + Four-layer structure;

[0024] S204: Perform high-temperature annealing on the ions injected into the mesa and make the anode ohmic metal and the cathode ohmic metal each form an ohmic contact with the silicon carbide-based material.

[0025] S205: Mechanical cutting with a diamond blade creates a mesa with a 20°–70° bevel angle on the side of the structure, followed by deposition of a silicon dioxide passivation layer to obtain a structure of P. + N - PN + N-type silicon carbide-based reverse blocking double-ended solid thyristor.

[0026] Among them, the anode P + Emitter thickness is 1μm to 5μm, doping concentration is 1×10⁻⁶ 19 cm -3 ~1×10 20 cm -3 N -The base region thickness is 30 μm to 150 μm, and the doping concentration is 1 × 10⁻⁶. 14 cm -3 ~2×10 15 cm -3 The P-drift region has a thickness of 2 μm to 10 μm and a doping concentration of 1 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 Cathode N + The emitter thickness is 0.5 μm to 2 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The width is 15μm to 25μm.

[0027] Compared with the prior art, the present invention has the following technical advantages based on the above-described technical solutions:

[0028] (1) By limiting the size and doping concentration of the N-base region, this invention can achieve high blocking voltage more easily through a lot of testing and verification, thereby effectively avoiding reliability problems caused by series connection. On the other hand, it is beneficial to reduce the thickness of the device, thereby improving the on-state characteristics of the device.

[0029] (2) By limiting the doping concentration and size of the P-based region, this invention can further reduce the thickness of the device while ensuring the performance of the switching device, which is conducive to the miniaturization and integration of the device.

[0030] (3) Compared with conventional silicon-based devices, the products prepared by this invention have high intrinsic temperature and high thermal conductivity, and can work reliably at high junction temperatures.

[0031] (4) The present invention uses an N-type long base region as the drift region. Since the electron mobility of the N drift region is higher, electrons will cross the N base region at a faster speed under the same thickness of N drift region, thereby making the device conduction speed faster.

[0032] (5) This invention uses an N-substrate to epitaxially grow a P-substrate. The minority carrier lifetime of the N-substrate epitaxial layer is higher than that of the low-quality P-substrate epitaxial layer, which solves the problem of large series resistance. Since the resistivity of the P-substrate is two orders of magnitude higher than that of the N-substrate, epitaxial growth using a P-substrate is not conducive to reducing forward voltage drop and on-state loss. Therefore, after epitaxially growing the PNPN structure, the N-substrate is ground off, which solves the problem that a P-substrate is required to manufacture a long N-base region reverse blocking double-ended solid-state thyristor.

[0033] (6) Given the current level of control over defects in silicon carbide materials, the two N-type SiC RBDT structures provided by this invention are easy to implement in the process. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of the N-type silicon carbide-based reverse blocking double-ended solid thyristor provided in the first embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram of the structure of the N-type silicon carbide-based reverse blocking double-ended solid thyristor provided in the second embodiment of the present invention.

[0036] Figure 3 This is a comparison diagram of the simulated current and voltage waveforms of the N-type silicon carbide-based reverse blocking double-ended solid thyristor and the silicon-based reverse blocking double-ended solid thyristor according to the first embodiment of the present invention.

[0037] Figure 4 This is a comparison of the simulation waveforms of switching losses between the N-type silicon carbide-based reverse blocking double-ended solid-state thyristor and the silicon-based reverse blocking double-ended solid-state thyristor according to the first embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0039] This invention proposes a silicon carbide-based long N-base region reverse blocking double-ended solid-state thyristor. Through the design of the process flow and device size and specifications, the device has good blocking, on-state and switching characteristics, while also meeting the trend of miniaturization.

[0040] Figure 1 The structure of the N-type silicon carbide-based reverse blocking double-ended solid-state thyristor provided in the first embodiment of the present invention is shown; preparation as follows Figure 1 The structure shown can be prepared using the following methods, specifically including:

[0041] (1) Select clean N + Silicon carbide substrate, sequentially in the N + Silicon carbide P-type epitaxial growth on silicon carbide substrate + Anode emitter region, silicon carbide N - Drift region, silicon carbide P-based region and silicon carbide N-based region + The cathode emission region forms N + P + N - PN + Structure; N-type substrates are 4H-SiC, 6H-SiC, or 3C-SiC substrates;

[0042] (2) Remove N +The method for forming silicon carbide substrates includes one or more of the following: chemical mechanical polishing, grinding, dry polishing, wet etching, plasma-assisted chemical etching, and atmospheric pressure plasma etching, to form P... + N - PN + structure;

[0043] (3) Regarding P + N - PN + A four-layer structure, after cleaning, undergoes an etching process in N... + P-type cathode emission region formation + Implantation window structure: A Ni metal mask layer can be deposited by magnetron sputtering, followed by photolithography and lift-off using an AZ400T or acetone, and then dry etching to form P. + An ion implantation window can be formed by selective ICP etching in a mixture of fluorinated gas and oxygen at a radio frequency power of 300W to 600W and an appropriate working pressure.

[0044] (4) Next, at the cathode emitter N + P-type ion implantation is performed to make the cathode side P + Silicon carbide cathode P is formed within the injection window. + district;

[0045] (5) The ions implanted on the mesa are activated by high-temperature annealing at 1200℃~1600℃. At the same time, the high-temperature annealing can also eliminate the lattice damage of SiC. The reason for choosing high-temperature annealing at 1200℃~1600℃ is that: at this temperature, silicon atoms and carbon atoms have sufficient activity. The migration of silicon atoms and carbon atoms leaves silicon vacancies and carbon vacancies, some of which form carbon-silicon vacancy equivalent point defects. On the other hand, silicon atoms and carbon atoms may also fill the original vacancies, or the vacancies may diffuse and transform into each other, thereby reducing harmful point defects and achieving effective modification.

[0046] (6) Annealing causes the anode ohmic metal and the cathode ohmic metal to each form an ohmic contact with the silicon carbide-based material;

[0047] (7) Use diamond blades for mechanical cutting to form a platform with a positive bevel angle of 20° to 70° on the side of the structure as the end method;

[0048] (8) Deposit a silicon dioxide passivation layer by low-pressure vapor phase deposition or PECVD; and a reverse blocking double-ended solid thyristor based on silicon carbide can be obtained.

[0049] The first embodiment of this invention, by limiting the dimensions and doping concentration of the N and P base regions, can more easily achieve a high blocking voltage, thereby effectively avoiding reliability issues caused by series connection. Furthermore, it facilitates a reduction in device thickness, thus improving the device's on-state characteristics. Simultaneously, using a long N-type base region with higher electron mobility as the drift region allows electrons to cross the N-base region more quickly for the same drift region thickness, resulting in faster device turn-on. Additionally, the SiC RBDT employs a recessed cathode structure, which enables better ohmic contact with the metal, reducing contact resistance and further enhancing the SiC RBDT's conduction characteristics.

[0050] Figure 2 The structure of the N-type silicon carbide-based reverse blocking double-ended solid-state thyristor provided in the second embodiment of the present invention is shown, and its fabrication is as follows: Figure 2 The structure shown can be prepared using the following methods, specifically including:

[0051] (1) Select clean N + Silicon carbide substrate, sequentially in the N + Silicon carbide P-type epitaxial growth on silicon carbide substrate + Anode emitter region, silicon carbide N - Drift regions and silicon carbide P-based regions form N + P + N - P-structure; N-type substrate is 4H-SiC substrate, 6H-SiC substrate or 3C-SiC substrate;

[0052] (2) Remove N + The method for forming silicon carbide substrates includes one or more of the following: chemical mechanical polishing, grinding, dry polishing, wet etching, plasma-assisted chemical etching, and atmospheric pressure plasma etching, to form P... + N - P-structure;

[0053] (3) Regarding P + N - The P-structure directly transfers the pattern from the photomask to the SiC cathode, making the cathode N-structure... + A photoresist protective film is formed at the emitter;

[0054] (4) Use concentrated sulfuric acid (H2SO4) to remove residual photoresist from the P-base region of the thyristor unit PNP on the SiC wafer;

[0055] (5) Next, selective ion implantation is performed in the P-based region to form the N-based cathode. + Emitter, thus forming P + N - PN + Four-layer structure;

[0056] (6) The ions implanted on the mesa are activated by high-temperature annealing at 1200-1600℃. At the same time, the high-temperature annealing can also eliminate the lattice damage of SiC.

[0057] (7) Annealing causes the anode ohmic metal and the cathode ohmic metal to each form an ohmic contact with the silicon carbide-based material;

[0058] (8) Use diamond blades for mechanical cutting to form a platform with a positive bevel angle of 20° to 70° on the side of the structure as the end method;

[0059] (9) Deposit a silicon dioxide passivation layer by low-pressure vapor phase deposition or PECVD; and a reverse blocking double-ended solid thyristor based on silicon carbide can be obtained.

[0060] The second embodiment of this invention, by limiting the dimensions and doping concentration of the N and P base regions, can more easily achieve a high blocking voltage, thereby effectively avoiding reliability issues caused by series connection. Furthermore, it facilitates a reduction in device thickness, thus improving the device's on-state characteristics. Simultaneously, using a long N-type base region with higher electron mobility as the drift region allows electrons to cross the N-base region more quickly for the same drift region thickness, resulting in faster device conduction. Additionally, the SiC RBDT cathode structure provided in the second embodiment of this invention does not require chemical etching processes; instead, it uses selective ion implantation directly into the P-base region to form the P-type base. + N - PN + The four-layer structure reduces damage to the chip and enhances its robustness and toughness.

[0061] To further illustrate the N-type silicon carbide-based reverse blocking double-ended solid thyristor and its preparation method provided in the first embodiment of the present invention, the following detailed description is provided with reference to the accompanying drawings and specific examples:

[0062] (1) N+ type 4H-SiC was selected as the substrate, with a substrate thickness of 300μm~350μm.

[0063] (2) After chemical mechanical polishing, boil in trichloroethylene, acetone and anhydrous ethanol for about 20 minutes in sequence. After washing with deionized water and boiling for 20 minutes, heat in a solution of sulfuric acid and sulfurous acid in a volume ratio of 3:1 for 20 minutes. Then rinse in deionized water. Finally, remove the surface oxide layer with 5% HF solution.

[0064] (3) Epitaxial growth of aluminum ion doping concentration of 1×10⁻⁶ with a thickness of 1μm to 3μm was performed on an N+ silicon carbide substrate. 19 ~1×10 20 cm-3 P + Launch area; wherein, the epitaxial temperature is 1650-1850℃, the pressure is 80-150mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is trimethylaluminum;

[0065] (4) In P + The epitaxial growth thickness on the emitter region is 30 μm to 150 μm, and the nitrogen ion doping concentration is 1 × 10⁻⁶. 14 ~2×10 15 cm -3 The N-based region has an epitaxial temperature of 1650℃~1850℃, a pressure of 80mbar~150mbar, the reaction gases are silane and propane, the carrier gas is pure hydrogen, and the impurity source is pure nitrogen.

[0066] (5) In N - The epitaxial growth thickness on the base region is 0.8 μm to 4 μm, and the aluminum ion doping concentration is 1 × 10⁻⁶. 17 ~1×10 18 cm -3 The P-drift region; wherein the epitaxial temperature is 1650℃~1850℃, the pressure is 80mbar~150mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is trimethylaluminum.

[0067] (6) Epitaxial growth of 0.5 μm to 2 μm thickness with nitrogen ion doping concentration of 1 × 10⁻⁶ on the P-drift region. 19 ~×10 20 cm -3 The N+ emitter layer has an epitaxial temperature of 1650℃~1850℃, a pressure of 80mbar~150mbar, the reactant gases are silane and propane, the carrier gas is pure hydrogen, and the impurity source is pure nitrogen.

[0068] (7) The method for removing N-type silicon carbide substrate is one or more of the following: chemical mechanical polishing, grinding, dry polishing, wet etching, plasma-assisted chemical etching, and atmospheric pressure plasma etching.

[0069] (8) Cathode N + The emitter layer is patterned using photolithography, eliminating the need for etching to form a nickel or aluminum protective film. Selective ICP etching is performed in a mixed gas of fluorinated and oxygen at 300W–600W RF power and appropriate operating pressure to remove the P-coating material. + N+ regions implanted by ions;

[0070] (9) In N +The emitter layer is selectively implanted with boron, aluminum, gallium, or mixtures thereof ions within a temperature range of 500℃ to 800℃, resulting in a cathode P + The thickness of the region ranges from 0.1 μm to 1.0 μm, and the injection concentration is 1 × 10⁻⁶. 19 ~1×10 20 cm -3 ;

[0071] (10) Clean the structure after the above steps, deposit a SiO2 masking layer by low pressure chemical vapor deposition, and activate it by annealing at a high temperature of 1150℃~1750℃. At the same time, the high temperature annealing can also eliminate the lattice damage of SiC.

[0072] (11) The device is then placed in BOE at room temperature for static etching to remove the deposited oxide layer;

[0073] (12) A 90nm / 35nm / 95nm Ni / Ti / Al alloy was deposited on the cathode of the silicon carbide wafer, and the entire silicon carbide wafer was annealed in nitrogen at 1000℃ for 3 minutes to form a cathode ohmic contact.

[0074] (13) Photoresist is coated onto the entire silicon carbide wafer at the anode, and then P is formed by development. + Ohmic contact area: A 900nm / 35nm / 95nm Ni / Ti / Al alloy is deposited on the entire silicon carbide wafer, and then the anode contact metal layer is formed by ultrasonic peeling; the entire silicon carbide wafer is annealed in nitrogen at 1000℃ for 3 minutes to form the anode ohmic contact.

[0075] (14) A mesa terminal is formed by mechanical cutting with a diamond blade with a 30° positive bevel angle. When SiC RBDT is fabricated using ion implantation to create the PN junction, curvature typically exists at the corners of the PN junction, resulting in a large electric field value at the corners, i.e., a spike electric field, causing premature device breakdown. Based on the structural characteristics of SiC RBDT, and considering that its blocking junction is a deep junction structure, this invention proposes using a bevel angle as its terminal. Furthermore, using a 30° positive bevel angle reduces the surface electric field strength to 33% of the bulk electric field strength, effectively improving the breakdown electric field and saving device area loss.

[0076] (15) Low-pressure vapor deposition method for SiO2 passivation layer: The deposition is carried out at low pressure (≤120Pa) and low temperature (400℃~600℃), and the deposition annealing treatment is carried out at 400℃~500℃ in nitrogen for 5min~25min to obtain a dense passivation layer with low impurity content.

[0077] (16) After the table surface is shaped and the passivation layer is processed, it is encapsulated to obtain a high-voltage silicon carbide reverse blocking double-ended solid thyristor.

[0078] Figure 3 The simulation waveforms of this embodiment and a silicon-based reverse-blocking double-ended solid-state thyristor are shown in the comparison graph under the same 3000V blocking voltage. It is clear from the graph that when a discharge experiment is conducted at 1200V, the silicon-based reverse-blocking double-ended solid-state thyristor produces 1.1kA, while the silicon carbide-based reverse-blocking double-ended solid-state thyristor can generate a peak current of 1.7kA under the same operating conditions, approximately 1.6 times that of the silicon-based one. This is because, at the same 3000V blocking voltage, the N-base region thickness of the silicon carbide-based reverse-blocking double-ended solid-state thyristor is only 30μm, while that of the silicon-based reverse-blocking double-ended solid-state thyristor reaches 300μm. Simultaneously, the conduction delay of the silicon carbide-based reverse-blocking double-ended solid-state thyristor is approximately 100ns, while that of the silicon-based reverse-blocking double-ended solid-state thyristor is approximately 210ns, demonstrating the faster conduction speed of the silicon carbide-based reverse-blocking double-ended solid-state thyristor.

[0079] Figure 4 The simulation waveforms comparing the switching losses of this embodiment and a silicon-based reverse-blocking double-ended solid-state thyristor at the same 3000V blocking voltage are shown. Due to the thinner N-base region and faster switching speed of the silicon carbide-based reverse-blocking double-ended solid-state thyristor, lower on-resistance and lower switching losses are achieved. The switching loss of the silicon carbide-based reverse-blocking double-ended solid-state thyristor (0.042J) is approximately 25% of that of the silicon-based reverse-blocking double-ended solid-state thyristor (0.178J), significantly reducing the device's switching losses and paving the way for high-frequency and high-speed applications.

[0080] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An N-type silicon carbide-based reverse blocking double-ended solid-state thyristor, characterized in that, The N-type silicon carbide-based reverse blocking double-ended solid-state thyristor sequentially includes: a silicon carbide anode P + Emitter region, silicon carbide N - Drift region, silicon carbide P-based region, and cathode emission region; The structure of the cathode emission region is formed in the following manner: N is epitaxially grown in the silicon carbide P-based region + District, and in N + Zone P + The injection window is then used for P-type ion implantation to make the P + Silicon carbide cathode P is formed within the injection window. + Launch area.

2. The N-type silicon carbide-based reverse blocking double-ended solid-state thyristor as described in claim 1, characterized in that, In structure P + N - PP + N + In the N-type silicon carbide-based reverse blocking double-ended solid thyristor, the anode P + The emitter region has a thickness of 1 μm to 3 μm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 N - The base region thickness is 30 μm to 150 μm, and the doping concentration is 1 × 10⁻⁶. 14 cm -3 ~2×10 15 cm -3 The thickness of the P-drift region is 0.8 μm to 4 μm, and the doping concentration is 1 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 Cathode N + The thickness of the emitter region is 0.5 μm to 2 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The width is 15μm~25μm; cathode P + The thickness of the emitter region is 0.1 μm to 1 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The width is 5μm~15μm.

3. A method for preparing an N-type silicon carbide-based reverse-blocking double-ended solid-state thyristor, characterized in that, Includes the following steps: S100: via N + Silicon carbide anodes P are epitaxially grown sequentially on a silicon carbide substrate. + Emitter region, silicon carbide N - The drift region and the region composed of silicon carbide P-based region and silicon carbide N-based region + The cathode emission region is formed, and N is generated. + P + N - PN + structure; S101: Remove N + Silicon carbide substrate and P + N - PN + structure; S102: For the P + N - PN + The structure is etched and then etched at the cathode N. + P-type launch zone formation + Injection window structure, in cathode N + P-type ion implantation is performed in the emission region to make the P + A silicon carbide cathode P+ emitter region is formed within the injection window; S103: A 900nm / 35nm / 95nm Ni / Ti / Al alloy is deposited on the anode of a silicon carbide wafer to form an anode contact metal layer, and a 900nm / 35nm / 95nm Ni / Ti / Al alloy is deposited on the cathode of a silicon carbide wafer to form a cathode contact metal layer. The ions implanted on the mesa are subjected to high-temperature annealing treatment, and the anode contact metal layer and the cathode contact metal layer are respectively formed with the silicon carbide base material to form an ohmic contact. S104: Mechanical cutting with a diamond blade creates a mesa with a 20°–70° bevel angle on the side of the structure, followed by deposition of a silicon dioxide passivation layer to obtain a P-structure. + N - PP + N + N-type silicon carbide-based reverse blocking double-ended solid thyristor.

4. The preparation method according to claim 3, characterized in that, In step S102, a mask layer is formed by magnetron sputtering to deposit metallic Ni. After photolithography, it is stripped using AZ400T or acetone, and dry etching is performed to form the P. + Inject window; Alternatively, selective ICP etching can be performed in a mixture of fluorinated gas and oxygen at a radio frequency power of 300W~600W and an appropriate working pressure to form the P. + Inject window.

5. The preparation method according to claim 3 or 4, characterized in that, Anode P + The thickness of the emitter region is 1 μm to 3 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 N - The base region thickness is 30 μm to 150 μm, and the doping concentration is 1 × 10⁻⁶. 14 cm -3 ~2×10 15 cm -3 The thickness of the P-drift region is 0.8 μm to 4 μm, and the doping concentration is 1 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 Cathode N + The thickness of the emitter region is 0.5 μm to 2 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The width is 15μm~25μm; cathode P + The thickness of the emitter region is 0.1 μm to 1 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The width is 5μm ~ 15μm.

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