Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: the initial composite layer includes a plurality of channel layers stacked together, a sacrificial layer between any two adjacent channel layers, a recess on the sidewall of the sacrificial layer and between any two adjacent channel layers, and an inner sidewall in the recess, the inner sidewall being recessed relative to the sidewall of the channel layer; forming a plurality of source / drain layers on the surface of the channel layer exposed by the first opening and the recess using a selective epitaxial growth process, the plurality of source / drain layers being parallel to the first direction and distributed along a second direction, the second direction being parallel to the normal direction of the substrate, and having a gap between any two adjacent source / drain layers; forming a contact layer on the surface of the source / drain layer and in the gap; and forming a conductive structure on the surface of the contact layer on the source / drain layer, which reduces the contact resistance of the surface of the source / drain layer and improves the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the current semiconductor field, the FinFET (Fin Field-Effect Transistor) is an emerging multi-gate device. Compared with planar metal-oxide-semiconductor field-effect transistors (MOSFETs), FinFETs have stronger short-channel rejection and higher operating current, and are now widely used in various semiconductor devices. However, with the further development of semiconductor technology, the transistor size has shrunk to below a few nanometers. The size of FinFETs themselves has already reached its limit. Limitations in fin spacing, short-channel effect, leakage current, and materials have made transistor manufacturing precarious, and even the physical structure cannot be completed.

[0003] Gate-all-around (GAA) devices have become a new direction for research and development in the industry. This technology is characterized by the gate completely surrounding the channel on all four sides. The source and drain no longer contact the substrate; instead, multiple source and drain electrodes, arranged laterally and perpendicularly to the gate in linear (rod-like), planar, or sheet-like shapes, are used to achieve the basic structure and function of a MOSFET. This design largely solves various problems caused by reducing the gate spacing, including capacitance effects. Furthermore, since the channel is surrounded by the gate on all four sides, the channel current flows more smoothly than with the three-sided enclosure of a FinFET.

[0004] However, the performance of existing gate-all-around devices needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of semiconductor structures.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate; a plurality of composite layers located on a portion of the substrate, the composite layers extending along a first direction, the composite layers having a first opening that exposes the substrate surface, the composite layers including a plurality of channel layers overlapping along the normal direction of the substrate surface and a second opening located between two adjacent channel layers, the second opening suspending the two adjacent channel layers, and a groove also being located between two adjacent channel layers, the groove being located on the sidewall of the second opening; a gate structure located on the surface of the channel layers and within the second opening, the gate structure surrounding the channel layers and extending along a second direction, the first direction and the second direction being... The composite layer comprises: mutually perpendicular dielectric walls located on the sidewalls of the gate structure, with the top surface of the dielectric walls flush with the top surface of the gate structure, and the outer surface of the dielectric walls flush with the sidewalls of the channel layer; an inner sidewall located within the groove and on the sidewall of the second opening, the inner sidewall being recessed relative to the sidewall of the channel layer; a plurality of source / drain layers located on the surface of the channel layer exposed by the first opening and the groove, the source / drain layers being parallel to the first direction and distributed along a second direction, the second direction being parallel to the normal direction of the substrate surface, with gaps between adjacent source / drain layers; contact layers located on the surface of the source / drain layers and within the gaps; and conductive structures located on the source / drain layers.

[0007] Optionally, it further includes: an insulating dielectric layer located on the substrate, the plurality of composite layers located on a portion of the surface of the insulating dielectric layer, and the first opening exposing the insulating dielectric layer.

[0008] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of initial composite layers, and a dummy gate structure and a dielectric wall spanning the initial composite layers and the sidewalls of the dummy gate structure on a portion of the substrate, wherein the initial composite layers extend along a first direction, and the initial composite layers on both sides of the dummy gate structure and the dielectric wall have first openings, the first openings exposing the substrate, the dummy gate structure being located on the sidewalls and top surface of the initial composite layers, the dummy gate structure including a dummy gate layer, and the initial composite layers including a plurality of overlapping channel layers located adjacent to each other. The system comprises a sacrificial layer between two channel layers, a groove located on the sidewall of the sacrificial layer and between two adjacent channel layers, and an inner sidewall within the groove, the inner sidewall being recessed relative to the sidewall of the channel layer; a plurality of source / drain layers are formed on the surface of the channel layer exposed by the first opening and the groove using a selective epitaxial growth process, the plurality of source / drain layers being parallel to the first direction and distributed along a second direction, the second direction being parallel to the normal direction of the substrate, and gaps being present between adjacent source / drain layers; a contact layer is formed on the surface of the source / drain layers and within the gaps; and a conductive structure is formed on the surface of the contact layer on the source / drain layers.

[0009] Optionally, the substrate surface has an insulating dielectric layer, the plurality of composite layers are located on a portion of the insulating dielectric layer surface, and the first opening exposes the insulating dielectric layer.

[0010] Optionally, before forming the conductive structure and after forming the contact layer, the method further includes: forming an interlayer dielectric material layer on the substrate, wherein the interlayer dielectric material layer is also located on the sidewalls and top surface of the dummy gate structure; planarizing the interlayer dielectric material layer until the dummy gate layer is exposed, thereby forming an interlayer dielectric layer.

[0011] Optionally, the method for forming the conductive structure includes: forming a third opening within the interlayer dielectric layer, the third opening exposing a contact layer on the top surface of the source / drain layer; and forming the conductive structure within the third opening.

[0012] Optionally, after forming the interlayer dielectric layer and before forming the conductive structure, the method further includes: removing the dummy gate layer and forming a gate opening within the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening and forming a second opening between adjacent channel layers; forming a composite layer with the initial composite layer, the composite layer including a plurality of overlapping channel layers and the second opening located between two adjacent channel layers; and forming a gate structure within the gate opening and the second opening.

[0013] Optionally, the selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film, and an etching process following the formation of the material film.

[0014] Optionally, the process parameters of the etching process include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.

[0015] Optionally, the method for forming the insulating dielectric layer, the plurality of initial composite layers, the dummy gate structures, and the dielectric wall includes: forming a first sacrificial material layer on the surface of the substrate, and an initial composite material layer on the surface of the first sacrificial material layer, the initial composite material layer including a plurality of overlapping channel material layers and a second sacrificial material layer located between two adjacent channel layers; forming a mask layer on the surface of the initial composite material layer, the mask layer exposing a portion of the initial composite material layer; etching the initial composite material layer using the mask layer as a mask until the surface of the first sacrificial material layer is exposed, forming a plurality of composite material layers extending along the first direction; and forming the plurality of dummy gate structures spanning the composite material layers, the plurality of dummy gate structures located in portions of the composite material layers. Sidewalls and surfaces; dielectric walls are formed on both sides of the dummy gate structure; using the dummy gate structure and the dielectric walls as masks, the composite material layers on both sides of the dummy gate structure and the dielectric walls are etched until the first sacrificial material layer is exposed, forming the transition composite layer and the first opening, the transition composite layer including the channel layer and an initial sacrificial layer located between the channel layers; after forming the transition composite layer, the first sacrificial material layer is removed to form an insulating trench on the substrate surface; an insulating dielectric layer is formed in the insulating trench, the insulating dielectric layer also located between the substrate and the transition composite layer; after forming the insulating dielectric layer, the initial sacrificial layer is etched to form the groove between two adjacent channel layers, with the initial sacrificial layer forming the sacrificial layer; the inner sidewall is formed in the groove.

[0016] Optionally, the size of the medium wall along the first direction is greater than 3 nanometers.

[0017] Optionally, the method for forming the inner sidewall includes: forming a second dielectric material layer on the surface of the insulating dielectric layer, within the groove, on the surface of the transition composite layer sidewall, on the sidewall and top surface of the dielectric wall, and on the top surface of the dummy gate structure; etching back the second dielectric material layer until the surface of the insulating dielectric layer, the surface of the transition composite layer sidewall, the top surface of the dummy gate structure, and the sidewall and top surface of the dielectric wall are exposed, forming an initial inner sidewall within the groove; and etching the initial inner sidewall until the initial inner sidewall sidewall is recessed relative to the sidewall of the channel layer, thus forming the inner sidewall.

[0018] Optionally, the etching process of the initial inner wall includes multiple dry etching processes, each of which includes: oxidizing the surface of the initial inner wall to form an oxide film on the surface of the initial inner wall; and etching away the oxide film.

[0019] Optionally, the oxidation process includes a plasma treatment process; the process gas of the plasma treatment process includes a plasma mixture of argon, oxygen and helium.

[0020] Optionally, the etching process is a pulsed laser process; the process gas for the pulsed laser process includes fluorinated carbon or hydrofluoric carbon gas.

[0021] Optionally, the dummy gate structure further includes a gate sidewall of the dummy gate layer sidewall; the gate sidewall is flush with the inner sidewall.

[0022] Optionally, the material of the first sacrificial material layer includes germanium and silicon, wherein the ratio of germanium to silicon in the first sacrificial material layer ranges from 1:10 to 1:2; the material of the second sacrificial layer includes germanium and silicon, wherein the ratio of germanium to silicon in the second sacrificial material layer ranges from 2:5 to 7:10; and the material of the channel material layer includes silicon.

[0023] Optionally, the method for forming the insulating dielectric layer includes: forming a first dielectric material layer on the substrate surface and within the insulating trench, the first dielectric material layer also being located on the sidewall of the initial composite layer, and on the sidewall and top surface of the dummy gate structure; etching the first dielectric material layer until the sidewall and top surface of the dummy gate structure, as well as the sidewall of the initial composite layer, are exposed.

[0024] Optionally, the dummy gate structure further includes a gate sidewall of the dummy gate layer sidewall; the gate sidewall is flush with the inner sidewall.

[0025] Optionally, there is a first spacing between two adjacent trench layers along the second direction, and a second spacing between two adjacent trench layers along the first direction, wherein the first spacing is greater than the second spacing.

[0026] Optionally, the first spacing ranges from 12 nanometers to 20 nanometers, and the second spacing ranges from less than 12 nanometers.

[0027] Optionally, the formation process of the contact layer includes atomic layer deposition.

[0028] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0029] In the semiconductor structure formation method provided by the present invention, a plurality of source / drain layers are formed on the surface of the channel layer exposed by the first opening and the groove using a selective epitaxial growth process. The plurality of source / drain layers are parallel to the first direction and distributed along a second direction, which is parallel to the substrate normal direction. There are gaps between adjacent source / drain layers. Contact layers are formed on the surface of the source / drain layers and in the gaps. Since the contact layers are located on the surface of each source / drain layer, the contact area between the contact layer and the source / drain layer is increased, thereby reducing the contact resistance of the source / drain layer surface and thus improving the performance of the device.

[0030] Furthermore, the selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film and an etching process after forming the material film. This reduces the possibility of the source and drain layers being connected along the second direction, which is beneficial for optimizing the morphology of the formed source and drain layers and improving the quality of the formed source and drain layers.

[0031] Furthermore, the formation process of the contact layer includes atomic layer deposition, which helps to improve the filling of the voids by the contact layer material and improve the performance of the formed contact layer.

[0032] In the semiconductor structure provided by the present invention, a plurality of source / drain layers are located on the surface of the channel layer exposed by the first opening and the groove. The source / drain layers are parallel to the first direction and distributed along a second direction, which is parallel to the normal direction of the substrate surface. There is a gap between adjacent source / drain layers. Contact layers are located on the surface of the source / drain layers and in the gaps. Since the contact layers are located on the surface of each source / drain layer, the contact area between the contact layers and the source / drain layers is increased, thereby reducing the contact resistance of the source / drain layer surface and thus improving the performance of the device. Attached Figure Description

[0033] Figures 1 to 4 This is a schematic diagram of a semiconductor structure formation process;

[0034] Figures 5 to 14 This is a schematic diagram of the structure corresponding to each step in a semiconductor structure formation method according to an embodiment of the present invention. Detailed Implementation

[0035] As described in the background section, the performance of semiconductor devices formed in the prior art needs improvement. The following analysis will illustrate this with reference to the structure of a semiconductor.

[0036] Figures 1 to 4 This is a schematic diagram of the semiconductor structure formation process.

[0037] Please refer to Figure 1A substrate 100 is provided; an insulating dielectric layer 101, a plurality of composite layers on a portion of the surface of the insulating dielectric layer 101, and a dummy gate structure on the surface of the composite layer are formed on the substrate 100. The gate structure includes a dummy gate 104 and a protective layer 105 on the surface of the gate layer. The composite layer includes a plurality of overlapping sacrificial layers 102 and a channel layer 103 located between two adjacent sacrificial layers 102.

[0038] Please refer to Figure 2 Source / drain layers 106 are formed on the substrates 100 on both sides of the composite layer, and the source / drain layers 106 are located on the sidewall surface of the channel layer 103; a contact layer 107 is formed on the surface of the source / drain layers 106.

[0039] Please refer to Figure 3 A first dielectric material layer (not shown in the figure) is formed on the surface of the substrate 100. The first dielectric material layer is also located on the surface of the source / drain layer 106 and the sidewalls and surface of the dummy gate structure. The first dielectric material layer is planarized until the top surface of the dummy gate 104 is exposed to form an interlayer dielectric layer 108. The dummy gate 104 is removed, and a gate opening (not shown in the figure) is formed in the interlayer dielectric layer 108. The sacrificial layer 102 exposed by the gate opening is removed to form a second opening (not shown in the figure) between adjacent channel layers 103. A gate structure 109 is formed in the gate opening and the second opening.

[0040] Please refer to Figure 4 A dielectric material layer 110 is formed on the surface of the interlayer dielectric layer 108 and the gate structure 109; a contact hole (not shown in the figure) is formed in the dielectric material layer 110, the contact hole exposing the surface of the contact layer 107; and a conductive structure 111 is formed in the contact hole.

[0041] The above method is used in the GAA device structure, where the contact layer 107 is made of metal silicide, which is used to reduce the contact resistance between the conductive structure 111 and the source / drain layer 106. However, as semiconductor feature sizes decrease, the contact area between the conductive structure 111 and the source / drain layer 106 becomes smaller, leading to an increase in contact resistance. The contact layer 107 formed by the above method is insufficient to reduce the contact resistance between the conductive structure 111 and the source / drain layer 106, thus affecting the performance of the GAA device.

[0042] To address the aforementioned problems, this invention provides a semiconductor structure formation method in which a plurality of source / drain layers are formed on the surface of the channel layer exposed by the first opening and the groove using a selective epitaxial growth process. The plurality of source / drain layers are parallel to the first direction and distributed along a second direction, which is parallel to the substrate normal direction. There are gaps between adjacent source / drain layers. Contact layers are formed on the surface of the source / drain layers and within the gaps. Since the contact layers are located on the surface of each source / drain layer, the contact area between the contact layer and the source / drain layer is increased, thereby reducing the contact resistance of the source / drain layer surface and thus improving the performance of the device.

[0043] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figures 5 to 14 This is a schematic diagram of the structure corresponding to each step in a semiconductor structure formation method according to an embodiment of the present invention.

[0045] Please refer to Figure 5 and Figure 6 , Figure 5 for Figure 6 Top view structural diagram, Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure along the DD1 direction is provided, showing the substrate 200.

[0046] In this embodiment, the substrate 200 is made of monocrystalline silicon; in other embodiments, the substrate may also be a semiconductor material such as polycrystalline silicon, germanium, silicon germanide, gallium arsenide, silicon-on-insulator, or germanium-on-insulator.

[0047] In this embodiment, the substrate has a well region (not shown in the figure), and the well region contains a first dopant ion. Specifically, in this embodiment, the first dopant ion is an N-type ion, used to form the well region of a PMOS device. In other embodiments, the first dopant ion is a P-type ion, used to form the well region of an NMOS device.

[0048] Subsequently, a plurality of initial composite layers, a dummy gate structure spanning the initial composite layers, and a dielectric wall extending across the sidewalls of the dummy gate structure are formed on a portion of the substrate 200. The initial composite layers extend along a first direction. The initial composite layers on both sides of the dummy gate structure and the dielectric wall have a first opening, which exposes the substrate 200. The dummy gate structure is located on the sidewalls and top surface of the initial composite layers. The dummy gate structure includes a dummy gate layer. The initial composite layers include a plurality of overlapping channel layers, a sacrificial layer located between two adjacent channel layers, a groove located on the sidewalls of the sacrificial layer and between two adjacent channel layers, and an inner sidewall within the groove. The inner sidewall is recessed relative to the sidewalls of the channel layers.

[0049] In this embodiment, the substrate 200 has an insulating dielectric layer on its surface, the plurality of composite layers are located on a portion of the surface of the insulating dielectric layer, and the first opening exposes the insulating dielectric layer. For the method of forming the insulating dielectric layer, the plurality of initial composite layers, the dummy gate structure, and the dielectric wall, please refer to [reference needed]. Figures 5 to 10 .

[0050] Please continue to refer to this. Figures 5 to 6 A first sacrificial material layer 201 is formed on the surface of the substrate 200, and an initial composite material layer is formed on the surface of the first sacrificial material layer 201. The initial composite material layer includes several overlapping channel material layers (not shown in the figure) and a second sacrificial material layer (not shown in the figure) located between two adjacent channel layers. A mask layer (not shown in the figure) is formed on the surface of the initial composite material layer, and the mask layer exposes a portion of the initial composite material layer. The initial composite material layer is etched using the mask layer as a mask until the surface of the first sacrificial material layer 201 is exposed, forming several composite material layers 202, which extend along the first direction X. Several dummy gate structures 203 are formed across the composite material layers 202, and the dummy gate structures 203 are located on a portion of the sidewalls and surface of the composite material layers 202.

[0051] The first direction X is the channel direction.

[0052] The dummy gate structure 203 includes a dummy gate layer 204. In this embodiment, the dummy gate structure 203 further includes a gate sidewall 205 located on the sidewall of the dummy gate layer 204. Specifically, the gate sidewall 205 is also located on the top surface of the dummy gate layer 204.

[0053] The first sacrificial material layer 201 occupies space for the subsequent formation of the insulating dielectric layer.

[0054] In this embodiment, before forming the first sacrificial material layer 201, a second dopant ion is implanted onto the surface of the substrate 200. The second dopant ion has a different conductivity type than the first dopant ion. Specifically, the second dopant ion is a p-type ion.

[0055] The material of the second sacrificial material layer is different from the material of the channel material layer. The channel material layer is used to form the channel layer, and the second sacrificial material layer is used to subsequently form the initial sacrificial layer, which occupies space for the subsequent formation of the gate structure. The material of the second sacrificial material layer has a higher etch selectivity than the material of the channel material layer, so that the subsequent removal of the sacrificial layer has less impact on the channel layer; the material of the second sacrificial material layer has better lattice matching than the material of the channel material layer, so as to obtain a smooth interface between the sacrificial layer and the channel layer, making the surface of the subsequently formed channel layer flat, which is conducive to obtaining a device with good performance.

[0056] The material of the second sacrificial material layer includes silicon; the material of the channel material layer includes germanium-silicon. In this embodiment, the material of the channel material layer is silicon; the material of the second sacrificial material layer is germanium-silicon. In other embodiments, the channel material layer is Ge or GeSi. In other embodiments, the material of the second sacrificial material layer can be ZnS, ZnSe, BeS, or GaP, etc.

[0057] Please refer to Figure 7 and Figure 8 , Figure 7 for Figure 8 Top view structural diagram, Figure 8 for Figure 7 A cross-sectional view along the DD1 direction shows that a dielectric wall 209 is formed on the sidewall of the dummy gate structure 203. Using the dummy gate structure 203 and the dielectric wall 209 as a mask, the composite material layer 202 on both sides of the dummy gate structure 203 and the dielectric wall 209 is etched until the first sacrificial material layer 201 is exposed, forming the transition composite layer and the first opening 206. The transition composite layer includes the channel layer 207 and an initial sacrificial layer 208 located between the channel layers 207.

[0058] The size of the medium wall 209 along the first direction X is greater than 3 nanometers.

[0059] Please refer to Figure 9 and Figure 10 After forming the transition composite layer, the first sacrificial material layer 201 is removed to form an insulating trench (not shown in the figure) on the surface of the substrate 200; an insulating dielectric layer 210 is formed in the insulating trench, and the insulating dielectric layer 210 is also located between the substrate 200 and the transition composite layer; after forming the insulating dielectric layer, the initial sacrificial layer 208 is etched to form the groove 211 between the two adjacent channel layers 207, and the initial sacrificial layer 208 forms the sacrificial layer 212; the inner sidewall 213 is formed in the groove 211.

[0060] The material of the first sacrificial material layer 201 is different from the material of the second sacrificial material layer. The initial sacrificial layer 208 is formed by the second sacrificial material layer. Therefore, the material of the first sacrificial material layer 201 is different from the material of the initial sacrificial layer 208, and the material of the first sacrificial material layer 201 is different from that of the substrate 200. This allows for the selection of an etching process with a larger etching selectivity for the first sacrificial material layer 201 relative to the initial sacrificial layer 208 and relative to the substrate 200 when removing the first sacrificial material layer 201, thereby reducing etching damage to the initial sacrificial layer 208 and the substrate 200.

[0061] The first sacrificial material layer comprises germanium and silicon, with a germanium to silicon composition ratio ranging from 1:10 to 1:2. The second sacrificial material layer comprises germanium and silicon, with a germanium to silicon composition ratio ranging from 2:5 to 7:10. The channel material layer comprises silicon. The germanium and silicon composition ranges in the first and second sacrificial material layers are different to ensure that the first sacrificial material layer 201 has a larger etching selectivity relative to the initial sacrificial layer 208 during the etching process.

[0062] The method for forming the insulating dielectric layer 210 includes: forming a first dielectric material layer (not shown in the figure) on the surface of the substrate 200 and in the insulating trench, wherein the first dielectric material layer is also located on the sidewall of the initial composite layer, and on the sidewall and top surface of the dummy gate structure 203; etching the first dielectric material layer until the sidewall and top surface of the dummy gate structure 203 and the sidewall of the initial composite layer are exposed.

[0063] In this embodiment, specifically, the method for forming the insulating dielectric layer 210 includes: forming a first dielectric material layer (not shown in the figure) on the surface of the substrate 200 and in the insulating trench, wherein the first dielectric material layer is also located on the sidewall of the initial composite layer, the sidewall and top surface of the dielectric wall 209, and the top surface of the dummy gate structure 203; etching the first dielectric material layer until the top surface of the dummy gate structure 203, the sidewall and top surface of the dielectric wall 209, and the sidewall of the initial composite layer are exposed.

[0064] The etching process for the first dielectric material layer includes inductively coupled plasma etching or capacitively coupled plasma etching.

[0065] The formation process of the first dielectric material layer includes atomic layer deposition (ALD). ALD facilitates the formation of a uniform first dielectric material layer and has excellent trench filling capability, thereby improving the performance of the insulating dielectric layer 210.

[0066] The etching process for removing the first sacrificial material layer has a selection ratio of 10:1 to 150:1 for the first sacrificial material layer and the second sacrificial material layer.

[0067] The inner wall 213 is located on the sidewall of the sacrificial layer 212, and the sidewall of the inner wall 213 is recessed relative to the sidewall of the channel layer 207.

[0068] In this embodiment, the method for forming the inner sidewall 213 includes: forming a second dielectric material layer (not shown in the figure) on the surface of the insulating dielectric layer 210, inside the groove 211, on the sidewall surface of the transition composite layer, on the sidewall and top surface of the dielectric wall 209, and on the top surface of the dummy gate structure 203; etching back the second dielectric material layer until the surface of the insulating dielectric layer 210, the sidewall surface of the transition composite layer, the top surface of the dummy gate structure 203, and the sidewall and top surface of the dielectric wall 209 are exposed, forming an initial inner sidewall (not shown in the figure) inside the groove 211; etching the initial inner sidewall until the sidewall of the initial inner sidewall is recessed relative to the sidewall of the channel layer 207, forming the inner sidewall 213.

[0069] The etching process of the initial inner wall includes multiple dry etching processes. Each dry etching process includes: oxidizing the surface of the initial inner wall to form an oxide film on the surface of the initial inner wall; and etching away the oxide film.

[0070] The oxidation process includes a plasma treatment process; the process gas for the plasma treatment process includes a plasma mixture of argon, oxygen, and helium.

[0071] The etching process is a pulsed laser process; the process gas for the pulsed laser process includes fluorinated carbon or hydrofluoric carbon gas.

[0072] In this embodiment, the sidewall of the gate sidewall 205 is flush with the sidewall of the inner sidewall 213. The inner sidewall 213 is used to isolate the gate structure and the source / drain layer, preventing the mutual diffusion of ions between the source / drain layer and the gate structure, thereby improving the stability of device performance.

[0073] Please refer to Figure 11 , Figure 11 The view direction is the same Figure 10A plurality of source / drain layers 214 are formed on the surface of the channel layer 207 exposed by the first opening 206 and the groove 211 using a selective epitaxial growth process. The plurality of source / drain layers 214 are parallel to the first direction X and distributed along the second direction Y, which is parallel to the normal direction of the substrate 200. There is a gap 215 between adjacent source / drain layers 214.

[0074] There is a first spacing between two adjacent channel layers 207 along the second direction Y, and a second spacing between two adjacent channel layers along the first direction X. The first spacing is greater than the second spacing. The purpose of having the first spacing greater than the second spacing is to allow the source / drain layer epitaxial materials on the surfaces of two adjacent channel layers along the first direction X to grow and merge together before they merge, thus forming a gap 215 in the source / drain layers 214 on the surfaces of two adjacent channel layers along the second direction Y. The gap 215 is used to form a contact layer.

[0075] The first spacing ranges from 12 nanometers to 20 nanometers, and the second spacing ranges from less than 12 nanometers.

[0076] The selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film, and an etching process following the formation of the material film.

[0077] The etching process parameters include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.

[0078] The selective epitaxial growth process allows the epitaxial material to grow directionally on the surface of the channel layer 207, which is conducive to forming a source / drain layer with a better morphology. It reduces the possibility of the source / drain layers connecting along the second direction Y, which is beneficial to optimizing the morphology of the formed source / drain layer and improving the quality of the formed source / drain layer.

[0079] Please refer to Figure 12 , Figure 12 The view direction is the same Figure 10 A contact layer 216 is formed on the surface of the source / drain layer 214 and within the void 215.

[0080] Since the contact layer 216 is located on the surface of each source / drain layer 214, the contact area between the contact layer 216 and the source / drain layer 214 is increased, thereby reducing the contact resistance on the surface of the source / drain layer 214 and thus improving the performance of the device.

[0081] The contact layer 216 is made of a metal silicide; the metal silicide includes materials such as tungsten silicide, cobalt silicide, titanium silicide, cobalt silicide, and nickel platinum silicide. In this embodiment, the metal silicide is tungsten silicide.

[0082] The contact layer 216 is formed using an atomic layer deposition process. This atomic layer deposition process improves the filling of voids by the contact layer material, thereby enhancing the performance of the formed contact layer.

[0083] Please refer to Figure 13 , Figure 13 The view direction is the same Figure 10 An interlayer dielectric material layer (not shown in the figure) is formed on the substrate 200, and the interlayer dielectric material layer is also located on the sidewall and top surface of the dummy gate structure 203; the interlayer dielectric material layer is planarized until the dummy gate layer 204 is exposed to form an interlayer dielectric layer 217.

[0084] Subsequently, a conductive structure 218 is formed on the surface of the contact layer 216 on the source / drain layer 214.

[0085] In this embodiment, after forming the interlayer dielectric layer 217 and before forming the conductive structure 218, the method further includes: removing the dummy gate layer 204, forming a gate opening (not shown in the figure) in the interlayer dielectric layer 217; removing the sacrificial layer 212 exposed by the gate opening, forming a second opening (not shown in the figure) between adjacent channel layers 207, forming a composite layer with the initial composite layer; and forming a gate structure 218 in the gate opening and the second opening.

[0086] The gate structure 218 includes a gate dielectric layer (not shown in the figure) located within the gate opening and the second opening, and a metal gate (not shown in the figure) located on the surface of the gate dielectric layer.

[0087] Please refer to Figure 14 , Figure 13 The view direction is the same Figure 10 A conductive structure 220 is formed on the surface of the contact layer 216 on the source / drain layer 214.

[0088] The method for forming the conductive structure 220 includes: forming a third opening (not shown in the figure) in the interlayer dielectric layer 217, the third opening exposing the contact layer 216 on the top surface of the source / drain layer 214; and forming the conductive structure 220 in the third opening.

[0089] In this embodiment, before forming the third opening, a dielectric layer 219 is also formed on the surface of the interlayer dielectric layer 217 and the gate structure 218; the third opening is also located within the dielectric layer 219.

[0090] Accordingly, another embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [link / reference needed]. Figure 14 The system includes: a substrate 200; and a plurality of composite layers located on a portion of the substrate 200, the composite layers extending along a first direction X, and each composite layer having a first opening 206 (e.g., ...). Figure 10 As shown in the figure, the first opening 206 exposes the surface of the substrate 200. The composite layer includes a plurality of overlapping channel layers 207 along the normal direction of the substrate 200 surface and a second opening (not shown in the figure) located between two adjacent channel layers 207. The second opening suspends the two adjacent channel layers 207. A groove 211 is also provided between the two adjacent channel layers 207, and the groove 211 is located on the sidewall of the second opening. A gate structure 218 is located on the surface of the channel layer 207 and in the second opening. The gate structure 218 surrounds the channel layer 207 and extends along the second direction Y. The first direction X is perpendicular to the second direction Y. A dielectric wall 209 is located on the side of the gate structure 218. The composite layer includes an inner sidewall 213 located within the groove 211 and on the sidewall of the second opening, the inner sidewall 213 being recessed relative to the sidewall of the channel layer 207; a plurality of source / drain layers 214 located on the surface of the channel layer 207 exposed by the first opening 206 and the groove 211, the source / drain layers 214 being parallel to the first direction X and distributed along the second direction Y, the second direction Y being parallel to the normal direction of the substrate 200, and a gap 215 (e.g., between adjacent source / drain layers 214) being provided. Figure 11 (as shown); a contact layer 216 located on the surface of the source / drain layer 214 and within the gap 215; and a conductive structure 217 located on the source / drain layer 214.

[0091] Since the contact layer 216 is located on the surface of each source / drain layer 214, the contact area between the contact layer 216 and the source / drain layer 214 is increased, thereby reducing the contact resistance on the surface of the source / drain layer 214 and thus improving the performance of the device.

[0092] In this embodiment, an insulating dielectric layer is also located on the substrate, and the plurality of composite layers are located on a portion of the surface of the insulating dielectric layer, with the first opening exposing the insulating dielectric layer.

[0093] The material of the contact layer 216 includes metal silicides.

[0094] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A plurality of composite layers are located on a portion of the substrate, the composite layers extending along a first direction, the composite layers having a first opening that exposes the substrate surface, the composite layers including a plurality of overlapping trench layers along the normal direction of the substrate surface and a second opening located between two adjacent trench layers, the second opening suspending two adjacent trench layers, and a groove also being located between two adjacent trench layers, the groove being located on the sidewall of the second opening; A gate structure is located on the surface of the channel layer and within the second opening, the gate structure surrounds the channel layer and extends along a second direction, the first direction being perpendicular to the second direction; A dielectric wall is located on the sidewall of the gate structure, and the top surface of the dielectric wall is flush with the top surface of the gate structure, and the outer surface of the dielectric wall is flush with the sidewall surface of the channel layer. The composite layer also includes an inner sidewall, which is located within the groove and on the sidewall of the second opening, and the sidewall of the inner sidewall is recessed relative to the sidewall of the channel layer; A plurality of source / drain layers are located on the surface of the channel layer exposed by the first opening and the groove. The plurality of source / drain layers are parallel to the first direction and distributed along the second direction, which is parallel to the normal direction of the substrate surface. The source / drain layers on the surfaces of two adjacent channel layers in the first direction are merged together, and there is a gap between the source / drain layers on the surfaces of two adjacent channel layers in the second direction. The contact layer is located on the surface of the source / drain layer and within the gap; The conductive structure located on the source / drain layer.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: An insulating dielectric layer is located on the substrate, the plurality of composite layers are located on a portion of the surface of the insulating dielectric layer, and the first opening exposes the insulating dielectric layer.

3. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A plurality of initial composite layers are formed on a portion of the substrate, and a dummy gate structure and a dielectric wall spanning the initial composite layers and the sidewalls of the dummy gate structure are formed. The initial composite layers extend in a first direction. The initial composite layers on both sides of the dummy gate structure and the dielectric wall have a first opening that exposes the substrate. The dummy gate structure is located on the sidewalls and top surface of the initial composite layers. The dummy gate structure includes a dummy gate layer. The initial composite layers include a plurality of overlapping channel layers, a sacrificial layer located between two adjacent channel layers, a groove located on the sidewalls of the sacrificial layer and between two adjacent channel layers, and an inner sidewall within the groove. The inner sidewall is recessed relative to the sidewalls of the channel layers. A plurality of source / drain layers are formed on the surface of the channel layer exposed by the first opening and the groove using a selective epitaxial growth process. The plurality of source / drain layers are parallel to the first direction and distributed along the second direction, which is parallel to the normal direction of the substrate. The source / drain layers on the surface of two adjacent channel layers in the first direction are merged together, and there is a gap between the source / drain layers on the surface of two adjacent channel layers in the second direction. A contact layer is formed on the surface of the source / drain layer and within the void; A conductive structure is formed on the contact layer surface of the source / drain layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The substrate surface has an insulating dielectric layer, the plurality of initial composite layers are located on a portion of the insulating dielectric layer surface, and the first opening exposes the insulating dielectric layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, Before forming the conductive structure and after forming the contact layer, the method further includes: forming an interlayer dielectric material layer on the substrate, wherein the interlayer dielectric material layer is also located on the sidewall and top surface of the dummy gate structure; planarizing the interlayer dielectric material layer until the dummy gate layer is exposed, thereby forming an interlayer dielectric layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method for forming the conductive structure includes: forming a third opening within the interlayer dielectric layer, the third opening exposing a contact layer on the top surface of the source / drain layer; and forming the conductive structure within the third opening.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, After forming the interlayer dielectric layer and before forming the conductive structure, the method further includes: removing the dummy gate layer and forming a gate opening in the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening and forming a second opening between adjacent channel layers, forming a composite layer with the initial composite layer; and forming a gate structure in the gate opening and the second opening.

8. The method for forming a semiconductor structure as described in claim 4, characterized in that, The selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film, and an etching process following the formation of the material film.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The etching process parameters include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.

10. The method for forming a semiconductor structure as described in claim 4, characterized in that, The method for forming the insulating dielectric layer, the plurality of initial composite layers, the dummy gate structures, and the dielectric wall includes: forming a first sacrificial material layer on the surface of a substrate, and an initial composite material layer on the surface of the first sacrificial material layer, the initial composite material layer including a plurality of overlapping channel material layers and a second sacrificial material layer located between two adjacent channel layers; forming a mask layer on the surface of the initial composite material layer, the mask layer exposing a portion of the initial composite material layer; etching the initial composite material layer using the mask layer as a mask until the surface of the first sacrificial material layer is exposed, forming a plurality of composite material layers extending along a first direction; and forming a plurality of dummy gate structures spanning the composite material layers, the plurality of dummy gate structures located on the side of a portion of the composite material layers. The process involves: forming a wall and a surface; forming dielectric walls on both sides of the dummy gate structure; using the dummy gate structure and the dielectric walls as a mask, etching the composite material layers on both sides of the dummy gate structure and the dielectric walls until the first sacrificial material layer is exposed, forming a transition composite layer and the first opening, the transition composite layer including the channel layer and an initial sacrificial layer located between the channel layers; after forming the transition composite layer, removing the first sacrificial material layer to form an insulating trench on the substrate surface; forming an insulating dielectric layer within the insulating trench, the insulating dielectric layer also located between the substrate and the transition composite layer; after forming the insulating dielectric layer, etching the initial sacrificial layer to form the groove between two adjacent channel layers, using the initial sacrificial layer to form the sacrificial layer; and forming the inner sidewall within the groove.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The size of the medium wall along the first direction is greater than 3 nanometers.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the inner sidewall includes: forming a second dielectric material layer on the surface of the insulating dielectric layer, within the groove, on the surface of the transition composite layer sidewall, on the sidewall and top surface of the dielectric wall, and on the top surface of the dummy gate structure; etching back the second dielectric material layer until the surface of the insulating dielectric layer, the surface of the transition composite layer sidewall, the top surface of the dummy gate structure, the sidewall and top surface of the dielectric wall are exposed, forming an initial inner sidewall within the groove; and etching the initial inner sidewall until the initial inner sidewall sidewall is recessed relative to the sidewall of the channel layer, thus forming the inner sidewall.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The etching process of the initial inner wall includes multiple dry etching processes. Each dry etching process includes: oxidizing the surface of the initial inner wall to form an oxide film on the surface of the initial inner wall; and etching away the oxide film.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The oxidation process includes a plasma treatment process; the process gas for the plasma treatment process includes a plasma mixture of argon, oxygen, and helium.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, The etching process is a pulsed laser process; the process gas for the pulsed laser process includes fluorinated carbon or hydrofluoric carbon gas.

16. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first sacrificial material layer is made of germanium-silicon, and the ratio of germanium to silicon in the first sacrificial material layer is in the range of 1:10 to 1:2; the second sacrificial material layer is made of germanium-silicon, and the ratio of germanium to silicon in the second sacrificial material layer is in the range of 2:5 to 7:

10. The material of the channel material layer includes silicon.

17. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the insulating dielectric layer includes: forming a first dielectric material layer on the surface of the substrate and in the insulating trench, the first dielectric material layer being located on the sidewall of the initial composite layer and on the sidewall and top surface of the dummy gate structure; etching the first dielectric material layer until the sidewall and top surface of the dummy gate structure and the sidewall of the initial composite layer are exposed.

18. The method for forming a semiconductor structure as described in claim 3, characterized in that, The dummy gate structure also includes a gate sidewall of the dummy gate layer sidewall; the gate sidewall is flush with the inner sidewall.

19. The method for forming a semiconductor structure as described in claim 3, characterized in that, There is a first spacing between two adjacent trench layers along the second direction, and there is a second spacing between two adjacent trench layers along the first direction, wherein the first spacing is greater than the second spacing.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The first spacing ranges from 12 nanometers to 20 nanometers, and the second spacing ranges from less than 12 nanometers.

21. The method for forming a semiconductor structure as described in claim 3, characterized in that, The formation process of the contact layer includes atomic layer deposition.

22. The method for forming a semiconductor structure as described in claim 3, characterized in that, The material of the contact layer includes metal silicides.

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