Bootlace switch

Abstract

A boot strap switch includes a first transistor, a second transistor, a first capacitor, three switches and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor and an inverter circuit. The first transistor receives an input voltage and outputs an output voltage. A first end of the second transistor receives the input voltage and a second end of the second transistor is coupled to a first end of the first capacitor. A control end of the first switch receives a clock signal. The second switch is coupled between the control end of the first transistor and the first switch. An input end of the inverter circuit is coupled to the control end of the first switch. The second capacitor is coupled between the control end of the first transistor and an output end of the inverter circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to a bootstrapped switch, and more particularly to a bootstrapped switch with fast turn-on and fast turn-off. BACKGROUND

[0002] Figure 1 A circuit diagram of a conventional bootstrapped switch. The bootstrapped switch 10 comprises switches 101, 102, 103, 104, 105, an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) (hereinafter referred to as NMOS transistor) 106, and a bootstrap capacitor 107. The input terminal VI and the output terminal VO of the bootstrapped switch 10 are coupled to the source and the drain of the NMOS transistor 106, respectively. The gate of the NMOS transistor 106 is coupled to a voltage source V3 through the switch 105, and is coupled to one end of the bootstrap capacitor 107 and one end of the switch 101. The other end of the switch 101 is coupled to a voltage source VI. The other end of the bootstrap capacitor 107 is coupled to a voltage source V2 through the switch 102, and is coupled to the source of the NMOS transistor 106 and the input terminal VI of the bootstrapped switch 10 through the switch 103. The voltage source VI is a high voltage level VDD, and the voltage sources V2 and V3 are ground levels. The operation of the bootstrapped switch 10 is well known to those skilled in the art, and thus will not be described in detail.

[0003] The state (on or off) of the switch 105 determines the state (on or off) of the NMOS transistor 106. In other words, the shorter the response time of the switch 105 (i.e., the faster the gate of the NMOS transistor 106 reaches the target voltage), the more consistent the state of the NMOS transistor 106 with the system clock, and the better the performance of the bootstrapped switch 10 (e.g., faster speed, more accurate sampling result). In other words, the design of the switch 105 plays an important role in the bootstrapped switch 10. SUMMARY

[0004] In view of the deficiencies of the prior art, one object of the present application is to provide a bootstrapped switch to improve the deficiencies of the prior art.

[0005] An embodiment of the present invention provides a bootstrapped switch for receiving an input voltage and outputting an output voltage, comprising a first transistor, a first capacitor, a second transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an inverter circuit, and a second capacitor. The first transistor has a first terminal, a second terminal, and a first control terminal, wherein the first transistor receives the input voltage at the first terminal and outputs the output voltage at the second terminal. The first capacitor has a third terminal and a fourth terminal. The second transistor has a fifth terminal, a sixth terminal, and a second control terminal, wherein the second transistor receives the input voltage at the fifth terminal, the sixth terminal is electrically connected to the third terminal of the first capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor. The first switch is coupled between the third terminal of the first capacitor and a first reference voltage. The second switch is coupled between the fourth terminal of the first capacitor and a second reference voltage. The third switch is coupled between the fourth terminal of the first capacitor and the first control terminal of the first transistor. The fourth switch has a third control terminal and is coupled to the first reference voltage. The fifth switch is coupled between the first control terminal of the first transistor and the fourth switch. The inverter circuit has an input terminal and an output terminal, wherein the input terminal is coupled to the third control terminal of the fourth switch, and the inverter circuit is used to invert a voltage at the third control terminal. The second capacitor has a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the output terminal of the inverter circuit, and the eighth terminal is coupled to the first control terminal.

[0006] Another embodiment of the present application provides a boot strap switch for receiving an input voltage and outputting an output voltage, comprising a first transistor, a first capacitor, a second transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, and a second capacitor. The first transistor has a first terminal, a second terminal, and a first control terminal, wherein the first transistor receives the input voltage from the first terminal and outputs the output voltage from the second terminal; the first capacitor has a third terminal and a fourth terminal; the second transistor has a fifth terminal, a sixth terminal, and a second control terminal, wherein the second transistor receives the input voltage from the fifth terminal, the sixth terminal is electrically connected to the third terminal of the first capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor; the first switch is coupled between the third terminal of the first capacitor and a first reference voltage; the second switch is coupled between the fourth terminal of the first capacitor and a second reference voltage; the third switch is coupled between the fourth terminal of the first capacitor and the first control terminal of the first transistor; the fourth switch has a third control terminal and is coupled to the first reference voltage; the fifth switch is coupled between the first control terminal of the first transistor and the fourth switch; the second capacitor has a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the first reference voltage through the sixth switch and coupled to the first control terminal through the seventh switch, and the eighth terminal receives the input voltage through the eighth switch and is coupled to the first reference voltage through the ninth switch. The sixth switch and the seventh switch are not simultaneously turned on, and the eighth switch and the ninth switch are not simultaneously turned on.

[0007] The boot strap switch of the present application can be quickly turned on and / or quickly turned off. Compared with the prior art, the boot strap switch of the present application can operate at a higher speed.

[0008] The features, implementations, and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A circuit diagram of a known boot strap switch;

[0010] Figure 2 A circuit diagram of an embodiment of the boot strap switch of the present application;

[0011] Figure 3 An example of the clock signal Φ1 and the clock signal Φ1b is shown;

[0012] Figure 4 A circuit diagram of another embodiment of the boot strap switch of the present application; and

[0013] Figure 5 A circuit diagram of another embodiment of the boot strap switch of the present application. Detailed Implementation

[0014] The technical terms used in the following description are based on the customary terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0015] The disclosure of this invention includes a bootie switch. Since some of the components included in the bootie switch of this invention may be known components individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention.

[0016] Figure 2 This is a circuit diagram of one embodiment of the bootie switch of the present invention. The bootie switch 100 receives an input voltage Vin from the input terminal IN and outputs an output voltage Vout from the output terminal OUT. The bootie switch 100 includes switches 110, 120, 130, 140, 150, 160, and 170, lifting capacitors Cb and Cq, and an inverter circuit 180. Switch circuit SW1 corresponds to... Figure 1 Switch 105. Switches 110, 120, 130, 140, 150, 160, and 170 can be implemented using transistors M1, M7, M2, M3, M8, M4, and M11, respectively. Each transistor has a first terminal, a second terminal, and a control terminal; the first and second terminals are the two ends of the switch formed by the transistor. For a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the first terminal can be either the source or the drain, the second terminal is either the source or the drain, and the control terminal is the gate. For a bipolar junction transistor (BJT), the first terminal can be either the collector or the emitter, the second terminal is either the collector or the emitter, and the control terminal is the base.

[0017] like Figure 2 As shown, the control terminals of transistor M1 and M7 are electrically connected to each other. Transistor M1 receives the input voltage Vin at its first terminal and outputs the output voltage Vout from its second terminal. Transistor M7 receives the input voltage Vin at its first terminal, and its second terminal is electrically connected to the first terminal of the lifting capacitor Cb. The first terminal of transistor M2 is coupled to the first terminal of the lifting capacitor Cb, and the second terminal of transistor M2 is coupled to the first reference voltage (in...). Figure 2a second reference voltage (ground level GND in the example) at a first end of the transistor M3. A second end of the transistor M3 is coupled to a second end of the bootstrap capacitor Cb. A first end of the transistor M8 is coupled to the control terminal of the transistor Ml, and a second end of the transistor M8 is coupled to the second end of the bootstrap capacitor Cb. A first end of the transistor M4 is coupled or electrically connected to the control terminal of the transistor Ml and the control terminal of the transistor M7, and a control terminal of the transistor M4 is coupled or electrically connected to the power supply voltage VDD. A first end of the transistor Ml l is coupled to a second end of the transistor M4, and a second end of the transistor Ml l is coupled or electrically connected to the first reference voltage (ground level GND). The control terminal of the transistor Ml l receives the clock signal Φlb. A first end of the capacitor Cq is coupled or electrically connected to the control terminal of the transistor Ml. The input terminal of the inverter circuit 180 receives the clock signal Φlb, and the output terminal of the inverter circuit 180 is coupled or electrically connected to a second end of the capacitor Cq. Figure 2

[0018] The switches 130, 140, 150 and 170 are rendered conductive (corresponding transistors are turned on) or non-conductive (corresponding transistors are turned off) according to the clock signals Φl and Φlb. Figure 3 An example of the clock signals Φl and Φlb is shown in FIG. 6. The clock signals Φl and Φlb are complementary to each other. The boot strap switch 100 is alternately operated in a first clock phase Phl (during which the clock signal Φl is at a first level (e.g., low level) and the clock signal Φlb is at a second level (e.g., high level)) and a second clock phase Ph2 (during which the clock signal Φl is at the second level and the clock signal Φlb is at the first level). Details of the operation of the boot strap switch 100 will be described below.

[0019] Referring to FIG. 7, the boot strap switch 100 is operated in the first clock phase Phl. The clock signal Φl is at the low level, and the clock signal Φlb is at the high level. The switches 130, 140, 160 and 170 are conductive, and the switch 150 is non-conductive. The voltages at the control terminals of the transistors Ml and M7 are substantially equal to the first reference voltage (ground level GND), so that the switches 110 and 120 are non-conductive. The voltages across the bootstrap capacitor Cb are substantially equal to the first reference voltage (ground level GND) and the second reference voltage (power supply voltage VDD), respectively. In other words, the bootstrap capacitor Cb is charged during the first clock phase Phl, and the voltage difference Vcb across the bootstrap capacitor Cb after the first clock phase Phl is substantially equal to the voltage difference between the first reference voltage and the second reference voltage. Figure 2 Figure 3 During the first clock phase Phl (when the clock signal Φl is at the low level and the clock signal Φlb is at the high level), the switches 130, 140, 160 and 170 are conductive, and the switch 150 is non-conductive. When the switches 160 and 170 are conductive, the voltages at the control terminals of the transistors Ml and M7 are substantially equal to the first reference voltage (ground level GND), so that the switches 110 and 120 are non-conductive; in other words, the switches 110 and 120 are non-conductive during the first clock phase Phl. When the switches 130 and 140 are conductive, the voltages across the bootstrap capacitor Cb are substantially equal to the first reference voltage (ground level GND) and the second reference voltage (power supply voltage VDD), respectively; in other words, the bootstrap capacitor Cb is charged during the first clock phase Phl, and the voltage difference Vcb across the bootstrap capacitor Cb after the first clock phase Phl is substantially equal to the voltage difference between the first reference voltage and the second reference voltage.​​

[0020] During the second phase Ph2 (when Φ1 is high and Φ1b is low), switches 130, 140, 160 and 170 are non-conducting, and switch 150 is conducting. When switch 150 is conducting, the control terminals of transistors M1 and M7 are essentially at the same potential as the second terminal of the bootstrap capacitor Cb, so that transistors M1 and M7 turn on due to the voltage across the bootstrap capacitor Cb, Vcb. When transistor M7 turns on, the voltage at the second terminal of the bootstrap capacitor Cb and the control terminal of transistor M1 is essentially equal to the sum of the input voltage Vin and the voltage across the bootstrap capacitor Cb, Vcb. When transistor M1 turns on, the output voltage Vout is essentially equal to the input voltage Vin, i.e., the boot strap switch 100 is conducting.

[0021] The voltage at the control terminal of transistor M1 can be greater than the supply voltage VDD (even approaching twice the supply voltage VDD). One of the purposes of transistor M4 is to block the control terminal of transistor M1 from transistor M11, so as to prevent the first terminal of transistor M11 from being subjected to this high voltage. Since the control terminal of transistor M4 is coupled or electrically connected to the supply voltage VDD, transistor M4 can withstand this high voltage. However, transistor M4 will slow down the speed of the transition of the control terminal of transistor M1 from the second level (e.g., high level) to the first level (e.g., low level), causing the boot strap switch 100 to be unable to change from the conducting state to the non-conducting state immediately after entering the first phase Ph1; in other words, transistor M4 can slow down the switching speed of the boot strap switch 100.

[0022] One of the purposes of the capacitor Cq and the inverter circuit 180 is to quickly pull up or pull down the voltage at the control terminal of transistor M1, so as to increase the voltage transition speed of the control terminal of transistor M1 (i.e., to speed up the switching speed of the boot strap switch 100).

[0023] When the clock signal Φ1b is transitioning from the first level to the second level (transistor M11 starts to conduct but has not yet fully conducted), the inverter circuit 180 outputs an output signal (i.e., a signal of the first level) that is the inverse of the clock signal Φ1b, which is then coupled to the control terminal of transistor M1 via the capacitor Cq, so that the voltage at the control terminal of transistor M1 can start to decrease before transistors M11 and M4 are fully conducting. In other words, the inverter circuit 180 and the capacitor Cq can help the voltage at the control terminal of transistor M1 to decrease faster (i.e., to speed up the closing speed of the boot strap switch 100).

[0024] When the clock signal Φ1b is converted from the second level to the first level (the transistor M11 starts to close but has not yet completely closed), the inverter circuit 180 outputs an output signal (i.e. a signal of the second level) which is opposite to the clock signal Φ1b, and then the output signal is coupled to the control terminal of the transistor M1 via the capacitor Cq, so that the voltage of the control terminal of the transistor M1 can start to rise before the transistor M11 and the transistor M4 completely close. In other words, the inverter circuit 180 and the capacitor Cq can help the voltage of the control terminal of the transistor M1 to rise faster (i.e. to accelerate the turn-on speed of the boot strap switch 100).

[0025] In summary, the inverter circuit 180 and the capacitor Cq help the voltage of the control terminal of the transistor M1 to rise or fall early, so that the boot strap switch has a faster response speed (i.e. can operate at a higher speed).

[0026] In some embodiments, the inverter circuit 180 comprises an odd number of inverters, and the capacitance value of the capacitor Cq can be about one-tenth to one-twentieth of the capacitance value of the hold-up capacitor Cb.

[0027] Figure 4 A circuit diagram of another embodiment of the boot strap switch of the present application. The boot strap switch 200 is similar to the boot strap switch 100, except that Figure 2 the switch circuit SW1 is replaced by Figure 4 the switch circuit SW2. Similarly, the switch circuit SW2 corresponds to Figure 1 the switch 105. One of the features of the boot strap switch is that when the boot strap switch is turned on, the voltage on the control terminal of the transistor M1 is the input voltage Vin plus a DC voltage (e.g. the power supply voltage VDD). However, the components of this input voltage Vin can hinder the transistor M1 from closing quickly.

[0028] The switch circuit SW2 comprises a capacitor Cq, a switch 201, a switch 202, a switch 203 and a switch 204. The first terminal of the capacitor Cq is coupled to the ground level GND via the switch 201, the first terminal of the capacitor Cq is coupled or electrically connected to the control terminal of the transistor M1 via the switch 202, the second terminal of the capacitor Cq is coupled to the ground level GND via the switch 204, and the second terminal of the capacitor Cq receives the input voltage Vin (equivalent to being coupled or electrically connected to the input terminal IN) via the switch 203.

[0029] When the clock signal Φ1 is at the high level, the switches 201 and 203 are turned on and the switches 202 and 204 are not turned on, so as to charge the capacitor Cq. After the charging is completed (i.e. the clock signal Φ1 becomes the low level), the voltage across the capacitor Cq is ideally equal to the input voltage Vin.

[0030] When the pulse Φ1 is at low level, the switches 201 and 203 are not conducting and the switches 202 and 204 are conducting, thus, the voltage across the capacitor Cq will be applied to the control terminal of the transistor M1 in reverse direction (i.e. equivalent to applying -Vin to the control terminal of the transistor M1), to offset the input voltage Vin on the control terminal of the transistor M1, which helps the voltage on the control terminal of the transistor M1 to drop faster (i.e. helps the transistor M1 to turn off faster, equivalent to speeding up the turn-off of the boot strap switch 100).

[0031] Figure 5 A circuit diagram of another embodiment of the boot strap switch of the present application. The boot strap switch 500 comprises a switch circuit SWx, a switch 185, a switch 190 and a switch 195. The switches 185, 190 and 195 are implemented by transistors M9, M5 and M6 respectively. The switch 185 is coupled between the second reference voltage and the control terminal of the transistor M8, and is controlled by the pulse Φ1. The switch 190 is coupled between the first terminal of the bootstrap capacitor Cb and the control terminal of the transistor M8, and is controlled by the pulse Φ1. The switch 195 is coupled between the first terminal of the bootstrap capacitor Cb and the control terminal of the transistor M8, and the control terminal of the transistor M6 is electrically connected to the control terminals of the transistors M1 and M7. The transistors M5, M6 and M9 are used to provide over-voltage protection during the operation of the boot strap switch 500, to prolong the life of the components, the principle of which is well known to those skilled in the art, and will not be described here. Those skilled in the art can adjust the phases or levels of the pulses Φ1 and Φ1b, and adjust the first and second reference voltages accordingly, to achieve the above disclosed embodiments, by referring to the above description. Figure 2 and Figure 4 the switch circuit SW1 or the switch circuit SW2 of Figure 5 the switch circuit SWx.

[0032] In other embodiments, the PMOS transistors and NMOS transistors in the above embodiments can be replaced by NMOS transistors and PMOS transistors respectively, and those skilled in the art know how to adjust the phases or levels of the pulses Φ1 and Φ1b accordingly, and adjust the first and second reference voltages accordingly, to achieve the above disclosed embodiments.

[0033] Please note that in the above disclosed figures, the shapes, sizes and proportions of the components are only for the purpose of helping those skilled in the art to understand the present application, and are not intended to limit the present application.

[0034] Although the present application has been described in connection with the embodiments thereof, it will occur to those skilled in the art that modifications can be made of the present application, from its teachings, without departing from the spirit and scope of the application, and it is intended to include all such modifications as fall within the scope of the claims. In other words, it is contemplated to cover or embrace any and all variations, uses, or adaptations of the application and technical field art which fall within the general scope of the application as claimed.

[0035] SYMBOL DESCRIPTION

[0036] 10, 100, 200, 500: Boot strap switch

[0037] 101, 102, 103, 104, 105, 110, 120, 130, 140, 150, 160, 170, 201, 202, 203, 204, 185, 190, 195: Switch

[0038] 106: N-type MOSFET

[0039] M1, M7, M2, M3, M8, M4, M11, M9, M5, M6: Transistor

[0040] 107, Cb: Boost capacitor

[0041] V1, V2, V3: Voltage source

[0042] VI, IN: Input

[0043] Vin: Input voltage

[0044] VO, OUT: Output

[0045] Vout: Output voltage

[0046] Cq: Capacitor

[0047] 180: Inverter circuit

[0048] SW1, SW2, SWx: Switch circuit

[0049] GND: Ground level

[0050] VDD: Power voltage

[0051] Φ1, Φ1b: Clock

[0052] Ph1: First clock phase

[0053] Ph2: Second clock phase

[0054] Vcb: Cross voltage.

Claims

1. A bootstrapped switch for receiving an input voltage and outputting an output voltage, comprising: a first transistor having a first end, a second end, and a first control end, wherein a first transistor having a first end, a second end, and a first control end, wherein the first transistor receives the input voltage at the first end and outputs the output voltage at the second end; a first capacitor having a third end and a fourth end; a second transistor having a fifth end, a sixth end, and a second control end, wherein the second transistor receives the input voltage at the fifth end, the sixth end is electrically connected to the third end of the first capacitor, and the second control end is electrically connected to the first control end of the first transistor; a first switch coupled between the third end of the first capacitor and a first reference voltage; a second switch coupled between the fourth end of the first capacitor and a second reference voltage; a third switch coupled between the fourth end of the first capacitor and the first control end of the first transistor; a fourth switch having a third control end and coupled to the first reference voltage; a fifth switch coupled between the first control end of the first transistor and the fourth switch; an inverter circuit having an input end and an output end, wherein the input end is coupled to the third control end of the fourth switch, and the inverter circuit is configured to invert a voltage at the third control end; and a second capacitor having a seventh end and an eighth end, wherein the seventh end is coupled to the output end of the inverter circuit, and the eighth end is coupled to the first control end.

2. The bootstrapped switch of claim 1, wherein, At a first clock phase, the first switch, the second switch, the fourth switch, and the fifth switch are turned on and the third switch is turned off to charge the first capacitor; at a second clock phase, the third switch is turned on and the first switch, the second switch, the fourth switch, and the fifth switch are turned off.

3. The bootstrapped switch of claim 1, wherein, The fifth switch has a fourth control end, and the fourth control end is electrically connected to the second reference voltage.

4. The bootstrapped switch of claim 1, wherein, The inverter circuit comprises an odd number of inverters.

5. A bootstrapped switch for receiving an input voltage and outputting an output voltage, comprising: a first transistor having a first end, a second end, and a first control end, wherein a first transistor having a first end, a second end, and a first control end, wherein the first transistor receives the input voltage at the first end and outputs the output voltage at the second end; a first capacitor having a third end and a fourth end; a second transistor having a fifth end, a sixth end, and a second control end, wherein the second transistor receives the input voltage at the fifth end, the sixth end is electrically connected to the third end of the first capacitor, and the second control end is electrically connected to the first control end of the first transistor; a first switch coupled between the third end of the first capacitor and a first reference voltage; a second switch coupled between the fourth end of the first capacitor and a second reference voltage; a third switch coupled between the fourth end of the first capacitor and the first control end of the first transistor; a fourth switch having a third control end and coupled to the first reference voltage; a fifth switch coupled between the first control end of the first transistor and the fourth switch; a sixth switch; a seventh switch; an eighth switch; a ninth switch; and a tenth switch. a second capacitor having a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the first reference voltage through the sixth switch and coupled to the first control terminal through the seventh switch, and the eighth terminal receives the input voltage through the eighth switch and is coupled to the first reference voltage through the ninth switch; wherein the sixth switch and the seventh switch are not simultaneously turned on, and the eighth switch and the ninth switch are not simultaneously turned on.

6. The bootstrapped switch of claim 5 wherein, At a first clock phase, the first switch, the second switch, the fourth switch and the fifth switch are turned on and the third switch is not turned on to charge the first capacitor; at a second clock phase, the third switch is turned on and the first switch, the second switch, the fourth switch and the fifth switch are not turned on.

7. The bootstrapped switch of claim 6 wherein, The seventh switch and the ninth switch are turned on at the first clock phase, and the sixth switch and the eighth switch are turned on at the second clock phase.

8. The bootstrapped switch of claim 5 wherein, The fifth switch has a fourth control terminal, and the fourth control terminal is electrically connected to the second reference voltage.

Images