Signal processing method, device and chip

Abstract

The present disclosure relates to a signal processing method, device and chip, and relates to the field of information processing. The processing method comprises: in a filter set, selecting a first number of filters capable of meeting a required channel equalization performance as a first number of equalization filters, and selecting a second number of filters capable of meeting a required anti-interference performance from the remaining filters in the filter set as a second number of anti-interference filters; and processing a multi-channel to-be-processed signal by using the equalization filters and the anti-interference filters. The technical solution of the present disclosure can reduce hardware overhead, thereby reducing cost and power consumption.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of information processing, and in particular, to a signal processing method, a signal processing apparatus, a chip and a nonvolatile computer readable storage medium. BACKGROUND

[0002] GNSS (Global Navigation Satellite System) has become an important space infrastructure after decades of development. A large number of users obtain PVT (Position Velocity Time) information through GNSS receivers.

[0003] However, the signal broadcast by the GNSS satellite is very weak in power when reaching the ground, and is extremely susceptible to other intentional or unintentional power suppression interference signals. There have been many cases of accidents due to GNSS interference in actual production and life. Therefore, the robustness of GNSS receivers in complex electromagnetic environments is increasingly concerned.

[0004] For GNSS receivers, an effective interference suppression method is to use an array antenna and an adaptive array signal processing algorithm. This method can effectively suppress various interference signals including wideband interference. With the progress of chip design and manufacturing technology, array anti-interference functional units have also begun to be integrated in GNSS chips.

[0005] In related technologies, the radio frequency channel equalization module and the anti-interference module are designed as two independent modules. SUMMARY

[0006] The present inventors have found that the above related art has the following problems: large hardware overhead, resulting in increased cost and power consumption.

[0007] In view of this, the present disclosure provides a signal processing technical solution, which can reduce hardware overhead and thus reduce cost and power consumption.

[0008] According to some embodiments of the present disclosure, a signal processing method is provided, including: in a filter set, selecting a first number of filters capable of meeting a required channel equalization performance as a first number of equalization filters, and in the remaining filters of the filter set, selecting a second number of filters capable of meeting a required anti-interference performance as a second number of anti-interference filters; and processing a multi-channel to-be-processed signal using the equalization filters and the anti-interference filters.

[0009] In some embodiments, processing the multi-channel to-be-processed signal by using the equalization filter and the interference rejection filter comprises: processing the multi-channel corrected signal by using the first number of equalization filters to determine a channel equalization processing result; updating the first number according to the channel equalization processing result; and processing the multi-channel to-be-processed signal by using the equalization filter of the updated first number.

[0010] In some embodiments, processing the multi-channel to-be-processed signal by using the equalization filter and the interference rejection filter comprises: processing the multi-channel corrected signal by using the first number of equalization filters to determine a channel equalization processing result; updating the first number and the second number in a case where the channel equalization processing result does not satisfy an equalization condition; repeating the above steps until the channel equalization processing result satisfies the equalization condition; and processing the multi-channel to-be-processed signal by using the equalization filter of the first number and the interference rejection filter of the second number when the equalization condition is satisfied.

[0011] In some embodiments, updating the first number and the second number comprises: calculating an equalization cancellation ratio of the channel equalization processing result; increasing the first number in a case where the equalization cancellation ratio is less than or equal to a threshold; and updating the second number according to a number of remaining filters of the filter set after the first number is increased.

[0012] In some embodiments, selecting the first number of filters capable of satisfying the required channel equalization performance as the equalization filters of the first number comprises: determining a minimum number of equalization filters capable of satisfying the required channel equalization performance as the first number; and selecting the first number of filters from the filter set.

[0013] In some embodiments, processing the multi-channel corrected signal by using the first number of equalization filters comprises: determining equalization filter coefficients of the equalization filters according to the first number; and processing the multi-channel corrected signal by using the equalization filter coefficients.

[0014] In some embodiments, determining the minimum number of equalization filters capable of satisfying the required channel equalization performance as the first number comprises: processing the power-split processed multi-channel corrected signal by using a plurality of radio frequency channels to determine a multi-channel digital intermediate frequency sampling signal; and calculating the minimum number according to the multi-channel digital intermediate frequency sampling signal.

[0015] In some embodiments, the filter set comprises a plurality of FIR (Finite Impulse Response) filters.

[0016] In some embodiments, the interference rejection filter is used to implement STAP (Space Time Adaptive Processing).

[0017] According to some embodiments of the present disclosure, a processing apparatus of a signal is provided, comprising: a selecting unit configured to select, in a filter set, a first number of filters capable of satisfying a required channel equalization performance as a first number of equalization filters, and select, in the remaining filters of the filter set, a second number of filters capable of satisfying a required anti-interference performance as a second number of anti-interference filters; and a processing unit configured to process a multi-channel to-be-processed signal by using the equalization filters and the anti-interference filters.

[0018] In some embodiments, the processing unit processes the multi-channel corrected signal by using the first number of equalization filters to determine a channel equalization processing result, updates the first number according to the channel equalization processing result, and processes the multi-channel to-be-processed signal by using the equalization filters of the updated first number.

[0019] In some embodiments, the processing unit processes the multi-channel corrected signal by using the first number of equalization filters to determine a channel equalization processing result, updates the first number and the second number in a case where the channel equalization processing result does not satisfy an equalization condition, repeats the above steps until the channel equalization processing result satisfies the equalization condition, and processes the multi-channel to-be-processed signal by using the equalization filters of the first number and the anti-interference filters of the second number when the equalization condition is satisfied.

[0020] In some embodiments, the processing unit calculates an equalization cancellation ratio of the channel equalization processing result, increases the first number in a case where the equalization cancellation ratio is less than or equal to a threshold value, and updates the second number according to the number of the remaining filters of the filter set after the first number is increased.

[0021] In some embodiments, the selecting unit determines the minimum number of the equalization filters capable of satisfying the required channel equalization performance as the first number, and selects the first number of filters in the filter set.

[0022] In some embodiments, the processing unit determines equalization filter coefficients of the equalization filters according to the first number, and processes the multi-channel corrected signal by using the equalization filter coefficients.

[0023] In some embodiments, the processing unit processes the multi-channel corrected signal after power splitting by using a plurality of radio frequency channels to determine a multi-channel digital intermediate frequency sampling signal, and the selecting unit calculates the minimum number according to the multi-channel digital intermediate frequency sampling signal.

[0024] In some embodiments, the filter set comprises a plurality of FIR filters.

[0025] In some embodiments, the anti-interference filters are used to implement STAP.

[0026] According to still some embodiments of the present disclosure, there is provided a signal processing apparatus, comprising: a memory; and a processor coupled to the memory, the processor being configured to perform the signal processing method of any one of the above embodiments based on instructions stored in the memory.

[0027] According to yet some embodiments of the present disclosure, there is provided a non-volatile computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the signal processing method of any one of the above embodiments.

[0028] According to still some embodiments of the present disclosure, there is provided a chip, comprising: the signal processing apparatus of any one of the above embodiments.

[0029] In the above embodiments, the commonality of the filter for the radio frequency channel equalization module and the anti-interference module is utilized, and a set of filter calculation resources is shared by the integration design of the two modules; according to the demand size of channel equalization and anti-interference in actual situation, the shared filter calculation resources are adaptively allocated to the radio frequency channel equalization module and the anti-interference module. In this way, the hardware overhead can be reduced, thereby reducing the cost and power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings, which form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0031] The present disclosure can be understood more readily by reference to the following detailed description, when taken in connection with the accompanying drawings, and wherein:

[0032] Figure 1 Flowcharts illustrating some embodiments of the signal processing method of the present disclosure;

[0033] Figures 2a-2b Schematic diagrams illustrating some embodiments of the signal processing method of the present disclosure;

[0034] Figure 3 Flowcharts illustrating some other embodiments of the signal processing method of the present disclosure;

[0035] Figure 4 Block diagrams illustrating some embodiments of the signal processing apparatus of the present disclosure;

[0036] Figure 5 Block diagrams illustrating some other embodiments of the signal processing apparatus of the present disclosure;

[0037] Figure 6 Block diagrams illustrating still some other embodiments of the signal processing apparatus of the present disclosure. DETAILED DESCRIPTION

[0038] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. Note that the relative arrangement, numerical expressions, and numerical values of components and steps set forth in these embodiments are not limiting to the scope of the present disclosure unless specifically stated otherwise.

[0039] Meanwhile, it should be understood that the sizes of the various portions shown in the drawings are exaggerated to facilitate an understanding of the present disclosure.

[0040] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way limiting to the scope of the disclosure and its applications or uses.

[0041] Techniques, methods, and apparatus known to those of ordinary skill in the relevant art can not be discussed in detail herein, but should be considered part of the specification.

[0042] In all of the examples shown and discussed herein, any specific values should be interpreted as merely illustrative and not as a limitation on the scope of the exemplary embodiments. Thus, other examples of the exemplary embodiments can have different values.

[0043] Note that like reference numerals and letters in the various drawings herein represent similar items unless otherwise specifically stated, and thus, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0044] As mentioned previously, in the GNSS array anti-jamming receiver scheme, the spatial signals are received by the array elements of the array antenna, filtered, amplified, and down-converted by the multiple RF channels, and then synchronously sampled by the multiple ADs to become multiple parallel baseband digital signals. In the receiver chip integrated with the array anti-jamming function, the baseband module processes the obtained multiple parallel baseband digital signals through an adaptive array signal processing algorithm.

[0045] For example, the adaptive array signal processing algorithm includes SAP (Space Adaptive Processing), STAP, SFAP (Space Frequency Adaptive Processing), etc. The STAP algorithm can provide a time domain degree of freedom in addition to the spatial domain degree of freedom, and the computational complexity is relatively controllable in terms of the area and power consumption of the corresponding chip, and thus is more suitable for being adopted by the GNSS receiver chip design.

[0046] In the GNSS array anti-jamming receiver, a key factor affecting the performance is the amplitude and phase inconsistency of the multiple RF channels. Poor amplitude and phase inconsistency not only reduces the maximum interference noise ratio (INR) that can be suppressed, but also introduces distortion to the satellite navigation signals, and further introduces a bias to the PVT results of the receiver.

[0047] In product requirements, the amplitude and phase consistency index requirements can be proposed only on a certain frequency point for multi-path radio frequency channels. However, in fact, the amplitude and phase inconsistency of each frequency point in the whole signal bandwidth is a factor affecting performance. In order to suppress the amplitude and phase inconsistency among channels in the whole frequency band, a digital equalization filter can be set for each channel in the baseband chip, and the frequency corresponding equalization is implemented for each channel.

[0048] In the channel equalization module, the input intermediate frequency data of each channel passes through a group of FIR equalization filters with a length of L before anti-jamming. The equalization filter coefficient e(m, l) is usually calibrated once by injecting a correction signal at the input port of the radio frequency channel before the GNSS receiver is formally started, and the coefficient does not change during the operation of the receiver.

[0049] After passing through the channel equalization module, the frequency response of all radio frequency channels is corrected to be consistent with a selected reference channel. The equalization filter length L is determined by the difference degree of the frequency response of each radio frequency channel, and the greater the difference degree, the greater L needs to be selected to achieve the required equalization effect.

[0050] In the STAP anti-jamming module, the intermediate frequency sampling data of each channel passes through a group of equalization filters with a length of N, and the filtering results of all channels are summed to generate one STAP output, and N is the time degree of freedom of STAP.

[0051] The STAP weighting coefficient w(m, n) is updated at a fast rate during the operation of the GNSS receiver. In each STAP weight coefficient update period, a plurality of time snapshots of MxN-dimensional data vectors (M is the number of array elements) are extracted, the correlation matrix is estimated, and then the STAP weight coefficient is calculated under a certain optimal criterion. Generally speaking, the greater N is, the stronger the potential anti-jamming capability of the STAP algorithm is.

[0052] However, the severity of the amplitude and phase inconsistency of the radio frequency channel is not certain, and the greater the severity of the inconsistency, the greater L required. In order to adapt to more types of radio frequency channels, the baseband chip will have to be designed according to the worst case, that is, L is reserved to be a large value, such as L is 15 or more. Moreover, in order to obtain good anti-jamming capability, a large N needs to be reserved in the STAP module, such as N is 5, 7, 9, etc.

[0053] In this way, L and N are superimposed, and the number of multipliers in the hardware will be large, increasing the cost and power consumption of the baseband chip.

[0054] In view of the above technical problems, considering that the channel equalization and the STAP anti-jamming both adopt the FIR filter structure, and the two have commonality, the channel equalization and the STAP anti-jamming can be jointly designed to obtain greater flexibility. In this way, the commonality of the channel equalization and the STAP anti-jamming calculation structure can be fully utilized to minimize the total number of FIR filter multipliers and save the cost and power consumption of the baseband chip. For example, the technical solution of the present disclosure can be implemented through the following embodiments.

[0055] Figure 1 A flowchart showing some embodiments of the signal processing method of the present disclosure is shown.

[0056] As shown in Figure 1 , in step 110, in a filter set, a first number of filters capable of meeting the required channel equalization performance are selected as equalization filters, and a second number of filters capable of meeting the required anti-jamming performance are selected from the remaining filters in the filter set as anti-jamming filters.

[0057] In some embodiments, the filters in the filter set have the same filter structure, for example, the filter set can include a plurality of FIR filters. The anti-jamming filters can be used to implement STAP.

[0058] In some embodiments, the minimum number of equalization filters capable of meeting the required channel equalization performance is determined as the first number, and the first number of filters are selected from the filter set.

[0059] For example, the power-split processed multi-channel correction signal is processed using a plurality of radio frequency channels to determine a multi-channel digital intermediate frequency sampling signal; and the minimum number is calculated according to the multi-channel digital intermediate frequency sampling signal.

[0060] For example, power splitting can be that one signal is output as multiple signals with equal power after passing through a power splitter.

[0061] In some embodiments, step 110 can be implemented through the embodiments in Figure 2a .

[0062] Figure 2a A schematic diagram showing some embodiments of the signal processing method of the present disclosure is shown.

[0063] As shown in Figure 2a , in the joint structure of radio frequency channel equalization and STAP anti-jamming, the channel equalization and the STAP anti-jamming share the FIR filter with a length of K, that is, the filter set contains a total of K filters.

[0064] In the equalization coefficient generation stage before the receiver is powered on, the correction signal (such as a Gaussian white noise signal with power higher than a threshold) RF_IN_0-3 is injected from the entrances of the respective RF channels 0-3 after being divided; the output multi-channel digital intermediate frequency sampling signals IF_IN_0-3 are sent to the equalization coefficient generation module.

[0065] The equalization coefficient generation module calculates the minimum length L of the equalization filter that can satisfy the equalization effect, and calculates the equalization filter coefficients under the L value.

[0066] After the receiver is powered on, the length of the equalization filter is fixed as L; the remaining FIR filter with a length of K-L is allocated to the STAP anti-jamming, and the STAP anti-jamming can select any value less than or equal to K-L as the length N of its filter according to needs.

[0067] In some embodiments, the equalization filter coefficients can be calculated by Figure 2b .

[0068] Figure 2b A schematic diagram showing some embodiments of the signal processing method of the present disclosure.

[0069] As shown in Figure 2b , in all RF channels, one is selected as the reference channel RF channel ref, and the rest are the channels to be corrected RF channel equ. In the reference channel, the sample with the middle time delay is selected as the reference output y ref (n), n is the sample time sequence number, indicating the change of time.

[0070] The L input samples of the channel to be corrected form a vector x:

[0071]

[0072] The equalization filter coefficients of the channel to be corrected form a vector v:

[0073] v = [v(0), v(1), …, v(L-1)] T

[0074] The output of the equalization channel is y(n) = v H x(n), and the goal of equalization is to make the error between y ref (n) and y(n) as small as possible in a statistical sense.

[0075] Based on the above conditions, the calculation of the equalization filter coefficients is modeled as a Wiener filter solving problem, and the calculation method of the equalization coefficients is:

[0076] v = R -1 r

[0077] R = E{xx H},r = E{xy * ref In the implementation, time average is used to replace the operation, and “*” represents complex conjugate operation.

[0078] After the number of equalization filters and interference rejection filters is determined, the remaining steps in the following can be used to continue the signal processing. Figure 1

[0079] In step 120, the multi-channel to-be-processed signal is processed by using the equalization filters and the interference rejection filters.

[0080] In some embodiments, the multi-channel correction signal is processed by using the equalization filters of the first number to determine a channel equalization processing result; the first number is updated according to the channel equalization processing result; and the multi-channel to-be-processed signal is processed by using the equalization filters of the updated first number.

[0081] For example, the equalization filter coefficients of the equalization filters are determined according to the first number; and the multi-channel correction signal is processed by using the equalization filter coefficients.

[0082] In some embodiments, the multi-channel correction signal is processed by using the equalization filters of the first number to determine a channel equalization processing result; the first number and the second number are updated in a case where the channel equalization processing result does not satisfy an equalization condition; the above steps are repeated until the channel equalization processing result satisfies the equalization condition; and the multi-channel to-be-processed signal is processed by using the equalization filters of the first number and the interference rejection filters of the second number when the equalization condition is satisfied.

[0083] For example, the equalization cancellation ratio of the channel equalization processing result is calculated; the first number is increased in a case where the equalization cancellation ratio is less than or equal to a threshold value; and the second number is updated according to the number of remaining filters of the filter set after the first number is increased.

[0084] For example, the equalization cancellation ratio can be calculated by the following formula:

[0085]

[0086] E{} represents an expectation operation, and a time average operation can be used to replace the expectation operation.

[0087] The greater the equalization cancellation ratio is, the better the equalization effect is. If the cancellation ratio CR is greater than a threshold value CR threshold , it can be determined that the equalization effect satisfies the requirement.

[0088] Figure 3 ​A flow chart showing another embodiment of the method of processing signals of the present disclosure.

[0089] As shown in Figure 3 , the flow of determining the equalization coefficient length L by the equalization coefficient generation module is run before the receiver is formally powered on.

[0090] In step 310, the same correction signal is injected into all the radio frequency channels from the radio frequency channel entrance.

[0091] In step 320, the multi-channel digital intermediate frequency signal after the correction signal passes through the radio frequency channel is stored in the baseband chip.

[0092] In step 330, the current value of L is initialized to a small value, such as 7, etc.

[0093] In step 340, the filter coefficient length is set to the current value of L.

[0094] In step 350, the equalization filter coefficients are calculated using the data stored in step 320 and the Figure 2b method of the above embodiment.

[0095] In step 360, the equalization cancellation ratio CR (Cancellation Ratio) is calculated.

[0096] In step 370, CR is compared with the threshold CR threshold . If CR>CR threshold , step 380 is executed; otherwise, step 390 is executed.

[0097] In step 380, the filter coefficient length is fixed to the current value of L, and the current equalization filter is written into the register of the baseband chip; and step 395 is executed.

[0098] In step 390, this step is executed, indicating that the equalization effect does not meet the expectation, and L is increased by 1, and step 340 is re-executed.

[0099] In step 395, the flow is exited.

[0100] In some embodiments, the method of processing signals of the present disclosure can be run by the software of the SoC (System on Chip) on the CPU.

[0101] In the above embodiments, the radio frequency channel equalization and the STAP anti-jamming share a set of FIR filter calculation resources through integrated design; according to the specific situation of the severity of the inconsistency of the radio frequency channels, the allocation of the FIR filter calculation resources between the radio frequency channel equalization and the STAP anti-jamming is flexibly adjusted.

[0102] In this way, the FIR filter multiplier overhead of the RF channel equalization and the overall STAP anti-jamming in the GNSS receiver baseband chip can be reduced.

[0103] Furthermore, in the case that the RF channel used with the baseband chip needs more coefficients of the equalization filter, less multiplier resources are left for the STAP anti-jamming. Since the poor channel consistency can seriously affect the anti-jamming performance, the importance of reducing the channel consistency to an acceptable level through channel equalization is a more priority target than improving the time degrees of freedom of the STAP. Therefore, the above trade-off is reasonable.

[0104] In the case that the RF channel used with the baseband chip has good consistency and needs less coefficients of the equalization filter, more multiplier resources are left for the STAP anti-jamming. In this way, the STAP algorithm can obtain higher time degrees of freedom and has stronger potential anti-jamming capability.

[0105] Therefore, with the saving of the FIR filter multiplier overhead, the cost and power consumption of the chip are reduced, thereby improving the market competitiveness of the chip.

[0106] Figure 4 A block diagram of some embodiments of the signal processing apparatus of the present disclosure is shown.

[0107] As shown in Figure 4 The signal processing apparatus 4 includes a selection unit 41 configured to select, in a filter set, a first number of filters capable of satisfying a required channel equalization performance as first number of equalization filters, and select, in the remaining filters of the filter set, a second number of filters capable of satisfying a required anti-jamming performance as second number of anti-jamming filters; and a processing unit 42 configured to process a multi-channel to-be-processed signal by using the equalization filters and the anti-jamming filters.

[0108] In some embodiments, the processing unit 42 processes the multi-channel calibration signal by using the first number of equalization filters to determine a channel equalization processing result, updates the first number according to the channel equalization processing result, and processes the multi-channel to-be-processed signal by using the equalization filters of the updated first number.

[0109] In some embodiments, the processing unit 42 processes the multi-channel calibration signal by using the first number of equalization filters to determine a channel equalization processing result, updates the first number and the second number in the case that the channel equalization processing result does not satisfy an equalization condition, repeats the above steps until the channel equalization processing result satisfies the equalization condition, and processes the multi-channel to-be-processed signal by using the equalization filters of the first number and the anti-jamming filters of the second number when the equalization condition is satisfied.

[0110] In some embodiments, the processing unit 42 calculates an equalization cancellation ratio of the channel equalization processing result, and increases the first number in a case where the equalization cancellation ratio is less than or equal to a threshold value, and updates the second number according to a number of remaining filters of the filter set after the first number is increased.

[0111] In some embodiments, the selection unit 41 determines a minimum number of equalization filters capable of satisfying a required channel equalization performance as the first number, and selects the first number of filters from the filter set.

[0112] In some embodiments, the processing unit 42 determines equalization filter coefficients of the equalization filters according to the first number, and processes the multi-channel correction signal by using the equalization filter coefficients.

[0113] In some embodiments, the processing unit 42 processes the multi-channel correction signal after power splitting by using a plurality of radio frequency channels to determine a multi-channel digital intermediate frequency sampling signal, and the selection unit calculates the minimum number according to the multi-channel digital intermediate frequency sampling signal.

[0114] In some embodiments, the filter set includes a plurality of FIR filters.

[0115] In some embodiments, the anti-interference filter is used to implement STAP.

[0116] Figure 5 A block diagram showing another embodiment of the signal processing apparatus of the present disclosure.

[0117] As shown in Figure 5 The signal processing apparatus 5 of this embodiment includes a memory 51 and a processor 52 coupled to the memory 51, and the processor 52 is configured to execute the signal processing method in any one of the embodiments of the present disclosure based on instructions stored in the memory 51.

[0118] The memory 51 may, for example, include a system memory, a fixed non-volatile storage medium, etc. The system memory may, for example, store an operating system, an application program, a Boot Loader, a database, and other programs, etc.

[0119] Figure 6 A block diagram showing still another embodiment of the signal processing apparatus of the present disclosure.

[0120] As shown in Figure 6 The signal processing apparatus 6 of this embodiment includes a memory 610 and a processor 620 coupled to the memory 610, and the processor 620 is configured to execute the signal processing method in any one of the preceding embodiments based on instructions stored in the memory 610.

[0121] The memory 610 can include, for example, a system memory, a fixed nonvolatile memory medium, and the like. The system memory stores, for example, an operating system, an application program, a Boot Loader, and other programs.

[0122] The signal processing apparatus 6 can further include an input / output interface 630, a network interface 640, a storage interface 650, and the like. These interfaces 630, 640, 650, and the memory 610 and the processor 620 can be connected, for example, through a bus 660. Among them, the input / output interface 630 provides a connection interface for display, mouse, keyboard, touch screen, microphone, speaker, and the like input / output devices. The network interface 640 provides a connection interface for various networking devices. The storage interface 650 provides a connection interface for external storage devices such as SD cards and U disks.

[0123] Those skilled in the art should understand that the embodiments of the present disclosure can be provided as a method, a system, or a computer program product. Therefore, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present disclosure can take the form of a computer program product implemented on one or more computer-usable non-transitory storage media including, but not limited to, disk storage, CD-ROMs, optical storage, and the like, containing computer-usable program code.

[0124] So far, the signal processing method, the signal processing apparatus, the chip, and the non-volatile computer readable storage medium according to the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein according to the above description.

[0125] The methods and systems of the present disclosure can be implemented in a number of ways. For example, the methods and systems of the present disclosure can be implemented using software, hardware, firmware, or any combination of software, hardware, and firmware. The above described order of steps for the methods is merely for illustration, and the steps of the methods of the present disclosure are not limited to the above specifically described order, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure can also be implemented as programs recorded in recording media, which include machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers recording media storing programs for executing the methods according to the present disclosure.

[0126] While certain embodiments of the disclosure have been described herein in detail as presently preferred, many modifications and variations thereof will be apparent to those skilled in the art, without departing from the scope and spirit of the disclosure. It is to be understood that those skilled in the art will be able to devise many embodiments of the disclosure which, while not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope. Accordingly, all such suitable modifications and equivalents should be considered as within the scope of the disclosure. The scope of the disclosure is to be indicated by the appended claims, rather than the foregoing description, and all changes that come within the meaning and range of equivalents are intended to be embraced therein.

Claims

1. A method for processing a signal, comprising: selecting, in a filter set, a first number of filters capable of satisfying a required channel equalization performance as a first number of equalization filters, and selecting, in remaining filters of the filter set, a second number of filters capable of satisfying a required anti-jamming performance as a second number of anti-jamming filters, the filters in the filter set having a same filter structure; processing a multi-channel to-be-processed signal using the equalization filters and the anti-jamming filters, wherein the processing the multi-channel to-be-processed signal using the equalization filters and the anti-jamming filters comprises: processing a multi-channel calibration signal using the first number of equalization filters to determine a channel equalization processing result; updating the first number and the second number in a case where the channel equalization processing result does not satisfy an equalization condition; repeating the above steps until the channel equalization processing result satisfies the equalization condition; processing the multi-channel to-be-processed signal using the first number of equalization filters and the second number of anti-jamming filters when the equalization condition is satisfied.

2. The treatment method of claim 1, wherein, the processing the multi-channel to-be-processed signal using the equalization filters and the anti-jamming filters comprises: processing a multi-channel calibration signal using the first number of equalization filters to determine a channel equalization processing result; updating the first number according to the channel equalization processing result; processing the multi-channel to-be-processed signal using the first number of equalization filters after being updated.

3. The treatment method according to claim 1 or 2, wherein, the updating the first number and the second number comprises: calculating an equalization cancellation ratio of the channel equalization processing result; increasing the first number in a case where the equalization cancellation ratio is less than or equal to a threshold value; updating the second number according to a number of remaining filters of the filter set after the first number is increased.

4. The treatment method according to claim 1 or 2, wherein, the selecting the first number of filters capable of satisfying the required channel equalization performance as the first number of equalization filters comprises: determining a minimum number of the equalization filters capable of satisfying the required channel equalization performance as the first number; selecting the first number of filters in the filter set.

5. The treatment method of claim 4, wherein, the processing the multi-channel calibration signal using the first number of equalization filters comprises: determining equalization filter coefficients of the equalization filters according to the first number; processing the multi-channel calibration signal using the equalization filter coefficients.

6. The treatment method of claim 4, wherein, the determining the minimum number of the equalization filters capable of satisfying the required channel equalization performance as the first number comprises: processing a multi-channel digital intermediate frequency sampling signal obtained by processing the multi-channel calibration signal using a plurality of radio frequency channels to determine the minimum number. calculating the minimum number according to the multi-channel digital intermediate frequency sampling signal.

7. The treatment method of claim 1, wherein, the filter set comprises a plurality of finite impulse response (FIR) filters.

8. The treatment method of claim 1, wherein, the anti-jamming filters are used to implement space-time adaptive processing (STAP).

9. An apparatus for processing a signal, comprising: The selecting unit is configured to select, in a filter set, a first number of filters capable of meeting a required channel equalization performance as first number of equalization filters, and select, in the remaining filters of the filter set, a second number of filters capable of meeting a required anti-interference performance as second number of anti-interference filters, the filters in the filter set having the same filter structure. The processing unit is configured to process a multi-channel to-be-processed signal by using the equalization filters and the anti-interference filters. In the processing unit, the first number of equalization filters are used to process a multi-channel correction signal to determine a channel equalization processing result, and in a case where the channel equalization processing result does not meet an equalization condition, the first number and the second number are updated, and the above steps are repeated until the channel equalization processing result meets the equalization condition, and the first number of equalization filters and the second number of anti-interference filters meeting the equalization condition are used to process the multi-channel to-be-processed signal.

10. The processing apparatus according to claim 9, wherein The processing unit uses the first number of equalization filters to process a multi-channel correction signal to determine a channel equalization processing result, and updates the first number according to the channel equalization processing result, and uses the equalization filters of the updated first number to process the multi-channel to-be-processed signal.

11. The processing apparatus according to claim 9 or 10, wherein The processing unit calculates an equalization cancellation ratio of the channel equalization processing result, and in a case where the equalization cancellation ratio is less than or equal to a threshold value, increases the first number, and updates the second number according to the number of the remaining filters of the filter set after the first number is increased.

12. A signal processing apparatus, comprising: a memory; and a processor coupled to the memory, configured to execute the signal processing method according to any one of claims 1-8 based on instructions stored in the memory.

13. A non-volatile computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the signal processing method according to any one of claims 1-8.

14. A chip, comprising: the signal processing apparatus according to any one of claims 9-12.

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