Optical synaptic transistor and method for manufacturing the same

Abstract

The present invention belongs to the technical field of semiconductor devices, and discloses an optical synaptic transistor and a manufacturing method thereof. Using the blend of P3HT and perovskite nanosheets as the semiconductor layer, it can be prepared by a simple solution spin-coating method. Benefiting from the high carrier transport efficiency and high light absorption coefficient of perovskite nanosheets, the single synaptic power consumption of this device is only 0.053 fJ under extremely low operating voltage (-0.0005 V), weak light pulse intensity (0.4 mW cm-2), and short illumination time (20 ms). The synaptic transistor provided by the present invention can achieve low power consumption under weak light conditions.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to an optical synapse transistor and a manufacturing method thereof. Background Art

[0002] In recent years, many advances have been made in the research of artificial synapses. For example, memristors, phase change memories and field effect transistors have been used to simulate synaptic behavior. The outstanding advantages of synaptic transistors based on light regulation (hereinafter referred to as photosynaptic transistors) in the field of simulating synaptic behavior include low operating power consumption, strong anti-interference ability and the ability to achieve functional diversity. However, although most of the current photosynaptic transistors have achieved low electrical power consumption, these photosynaptic transistors rely on high optical power, which limits the application field of artificial synapses, especially the application of photosynaptic transistors in weak light environments.

[0003] The light intensity required for the synaptic transistor based on light regulation in the existing technology is basically 10 2 ~10 3 mWcm -2 For example, the synaptic transistors fabricated in the public documents with DOI number 10.1002 / adma.201870287 and DOI number 10.1002 / admt.202000514 both rely on higher optical power.

[0004] In 2021, Ender Ercan et al. published a paper titled "Self-Assembled Nanostructures of Quantum Dot / Conjugated Polymer Hybrids for Photonic Synaptic Transistors with Ultralow Energy Consumption and Zero-Gate Bias", DOI: 10.1002 / adfm.202107925, which disclosed the preparation of perovskite (CsPbBr 3 ) quantum dot (QD) / poly (3-hexylthiophene) (P3HT) composite nanofiber film (CNFs) photonic synaptic transistor, although it achieved an ultra-low energy consumption of 0.18 fJ, the 10 mW cm -2The high optical power still cannot achieve low power consumption in the optical sense and is not suitable for weak light conditions. The construction of artificial synaptic devices under weak light conditions is the basis for realizing many bionic applications, such as the construction of artificial vision systems. Human vision has a high perception sensitivity to low illumination from moonlight to dusk at night, which gives people a survival advantage at night. Artificial vision devices have high sensitivity and low power consumption to weak night lighting, which can improve imaging contrast and realize energy-saving image information processing. They have broad application prospects, especially in biomimetic robots, night autopilots and next-generation night blindness medical technologies. Summary of the invention

[0005] In order to overcome the deficiencies of the above-mentioned prior art, the present invention provides an optical synaptic transistor having the advantages of both low power consumption and plasticity performance. The low power consumption specifically refers to two aspects: electrical power consumption and optical power consumption. The optical synaptic transistor provided by the present invention can be used for simulating synaptic plasticity functions under weak light conditions.

[0006] The technical solution adopted by the present invention is:

[0007] In a first aspect, the present invention provides a photosynaptic transistor, the synaptic transistor comprising, from bottom to top: a gate electrode, a gate insulating layer, an organic semiconductor layer, and a source-drain electrode;

[0008] The organic semiconductor layer is composed of a p-type organic polymer semiconductor P3HT and a perovskite nanosheet CsPbBr 3 NPLs mixed coating, the thickness of the organic semiconductor layer is 20-40nm; the molecular weight of the p-type organic polymer semiconductor P3HT is greater than 40000; the perovskite nanosheet CsPbBr 3 The average size of NPLs is about 50nm; among them, P3HT and CsPbBr 3 The volume ratio of NPLs was 2:1;

[0009] The gate electrode is made of a material selected from highly doped silicon, Al, Cu, Au, Ag or Pt;

[0010] The gate insulating layer covers the entire surface of the gate electrode, isolates the contact between the gate electrode and the semiconductor layer, and effectively reduces the gate leakage current; the gate insulating layer includes silicon oxide and polymethyl methacrylate PMMA, the thickness of the silicon oxide is preferably 300nm, the silicon oxide directly covers the gate electrode, and the thickness of the PMMA layer is 20-40nm;

[0011] The source-drain electrodes are grown on both sides of the conductive channel, and the material used is one of Cu, Au or Pt, and the thickness is 60-100nm. The length of the conductive channel between the source and the drain is 50-200μm, and the width of the conductive channel between the source and the drain is 1000-2000μm; preferably, the source-drain electrodes are prepared by vacuum evaporation or magnetron sputtering; further preferably, the source-drain electrode material is copper.

[0012] In a second aspect, the present invention provides a method for manufacturing the above-mentioned optical synapse transistor, comprising the following steps:

[0013] Step (1), first using hot injection method and then using solvent growth method to synthesize perovskite nanosheets CsPbBr 3 NPLs, and dispersed in an organic solvent; preferably, the perovskite nanosheets CsPbBr 3 The specific preparation process of NPLs includes the following steps: cesium carbonate and oleic acid with a mass ratio of 1:46 are reacted at 100 °C for 30 min under vacuum and then placed in N 2 The reaction was continued at 120°C for 30 min to obtain a cesium oleate precursor; lead bromide, octadecene, oleic acid and oleylamine in a mass ratio of 1:51:5.8:10.6 were reacted at 100°C for 1 h under vacuum conditions, and then N 2 , the temperature was raised to 120℃ and the cesium oleate precursor was quickly injected, kept for 1h and then cooled to obtain CsPbBr 3 NPLs crude solution; the prepared CsPbBr 3 The crude NPLs solution was centrifuged and washed to obtain high-purity CsPbBr 3 NPLs.

[0014] Step (2), weigh P3HT and PMMA respectively and dissolve them in an organic solvent, wherein the concentration of P3HT is 1 mg / mL; the concentration of PMMA is 5 mg / mL, and stir with a magnetic stirrer until they are completely dissolved;

[0015] Step (3) P3HT solution and CsPbBr 3 The NPLs solution was mixed in a volume ratio of 2:1 as the semiconductor layer solution;

[0016] Step (4), using acetone, ethanol and deionized water to ultrasonically clean the silicon wafer for 8 to 10 minutes respectively, then blowing the surface dry with high-purity nitrogen gas, and drying it in an electric blast drying oven;

[0017] Step (5), treating the dry and clean substrate covered with the silicon oxide gate insulating layer with ultraviolet ozone for 10 to 20 minutes;

[0018] Step (6), using a solution spin coating method, firstly spin-coating a PMMA gate insulating layer on the substrate cleaned in step (5), with a rotation speed of 3000 r / min and a spin coating time of 30 s, wherein the thickness of the gate insulating layer is controlled to be 20 to 40 nm; and then spin-coating P3HT / CsPbBr 3 NPLs mixed solution, the rotation speed is 1000r / min, the spin coating time is 50s, and the thickness is controlled at 20-40nm; the spin-coated sample is placed on a heating platform for annealing at 100℃ for 30min;

[0019] Step (7), vacuum evaporating source and drain electrodes on the sample annealed in step (6).

[0020] Preferably, in step (1), the centrifugal washing process comprises: first, centrifuging at 7000 r / min for 15 min, discarding the supernatant, then adding 2 mL of toluene and 3 mL of ethyl acetate to the precipitate, shaking evenly and centrifuging at 12000 r / min for 10 min, repeating twice, adding 2 mL of toluene to the precipitate, shaking evenly and standing for use.

[0021] Preferably, the organic solvent in step (2) is any one of ethyl acetate, toluene or chlorobenzene.

[0022] Preferably, the vacuum-deposited source and drain electrodes in step (7) are copper, and patterning is performed using a mask plate, the mask plate channel width is 1500 μm, the length is 150 μm, and the evaporation rate is controlled at The thickness is controlled at 60-100nm.

[0023] Further preferably, in order to obtain an electrode with a smooth pattern edge, the device after the top electrode is evaporated is further annealed for at least 20 minutes in the original vacuum thermal evaporation environment, so as to obtain a complete synaptic transistor device.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention proposes a simple optical synaptic transistor, which uses P3HT and perovskite nanosheets as a semiconductor layer and can be prepared by a simple solution spin coating method. Thanks to the high carrier transfer efficiency and high light absorption coefficient of the perovskite nanosheets, the device can operate at extremely low operating voltage (-0.0005V) and weak light pulse intensity (0.4mWcm -2 ) and a short illumination time (20ms), the power consumption of a single synapse is only 0.053fJ, which is lower than the power consumption level of most devices reported so far. Therefore, the low power consumption described in the present invention includes both electrical power consumption and optical power consumption, that is, the synaptic transistor described in the present invention can achieve low power consumption under weak light conditions;

[0026] The key points of realizing low power consumption of the synaptic transistor described in the present application are that, firstly, the size and morphology of the nanosheets in the present invention are specific, and the perovskite nanomaterials are widely used in optical transistors, solar cells, light-emitting diodes and memories due to their advantages of a large number of surface states, adjustable band gap, simple preparation and low cost. The perovskite nanosheet material described in the present invention has a high absorption cross section due to its unique two-dimensional structure, and thus has a high light absorption coefficient, so that the device has a good light responsiveness and can respond under weak light intensity, which is the basis for the device to achieve low light power consumption, and can be used to construct low-power optoelectronic storage and neuromorphic devices under weak light conditions; secondly, the present invention selects P3HT with a large molecular weight of >40,000 and perovskite nanosheets as semiconductor layers, mainly because the energy levels of the two are matched, effective charge transfer can occur, and the two-dimensional structure of the perovskite nanosheet makes it have a high carrier transfer efficiency, which enables the artificial synaptic device to operate at a lower operating voltage and have a faster write speed, which is the basis for the device to achieve electrical low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The CsPbBr 3 Transmission electron microscopy (TEM) images and high-resolution transmission electron microscopy (HRTEM) images of NPLs;

[0028] Figure 2 The present invention is based on P3HT / CsPbBr 3 Schematic diagram of the structure of NPLs' low-power synaptic transistor device;

[0029] Figure 3 The present invention is based on P3HT / CsPbBr 3 The low-power synaptic transistors of NPLs simulate the excitatory postsynaptic current (EPSC) under light pulses of different wavelengths for synaptic testing;

[0030] Figure 4 The present invention is based on P3HT / CsPbBr 3 The low-power synaptic transistor of NPLs simulates the long-term plasticity (LTP) of synaptic tests under different numbers of light pulses;

[0031] Figure 5 The present invention is based on P3HT / CsPbBr 3 NPLs' low-power synaptic transistor achieves 0.4 mW cm -2 , EPSC triggered by a light pulse with a width of 20 ms. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below in conjunction with the examples and drawings, but the embodiments of the present invention are not limited thereto. For process parameters not specifically noted, conventional techniques may be used.

[0033] Figure 2 The P3HT / CsPbBr 3 The schematic diagram of the structure of the low-power synaptic transistor of NPLs is shown in the figure, which includes source and drain electrodes, semiconductor layers, gate insulating layers and gate electrodes from top to bottom; wherein the material in the semiconductor layer is P3HT / CsPbBr 3 NPLs mixed solution, volume ratio P3HT:CsPbBr 3 NPLs = 2:1, thickness is about 30nm. During actual preparation, the laboratory room temperature is maintained at about 25°C, and the indoor humidity is maintained below 40%.

[0034] The main preparation steps are as follows:

[0035] 1. Preparation of perovskite nanosheets

[0036] 1.1. Preparation of precursor: 0.6 mmol cesium carbonate (Macklin, 99.9%) and 10 mL oleic acid (Aladdin, 85%) were added into a three-necked flask and reacted at 100 °C for 30 min under vacuum. 2 The reaction was continued at 120°C for 30 min to obtain a cesium oleate precursor;

[0037] 1.2 Preparation of CsPbBr 3 NPLs: 0.42 mmol of lead bromide (Macklin, 99.9%), 10 mL of octadecene (Macklin, ≥95%), 1 mL of oleic acid, and 2 mL of oleylamine (Aladdin, 80%-90%) were added to a three-necked flask and reacted at 100 °C for 1 h under vacuum. Then, N 2 , heat to 120℃ and quickly inject 1mL of precursor, keep for 1h and cool in cold water;

[0038] 1.3. Cleaning and centrifugation: Centrifuge the prepared liquid, first at 7000r / min for 15min, pour off the supernatant, then add 2mL toluene and 3mL ethyl acetate to the precipitate, shake evenly and centrifuge at 12000r / min for 10min, repeat twice, add 2mL toluene to the precipitate, shake evenly and let stand for use.

[0039] 2. Pretreatment of substrate

[0040] 2.1. Ultrasonic cleaning of heavily doped silicon substrate with 300nm silicon oxide on the surface was carried out with acetone, ethanol and deionized water for 8-10min in sequence, with the ultrasonic frequency of 100KHz;

[0041] 2.2. Use high-purity nitrogen to blow dry the surface liquid to make the substrate surface clean, put it into an electric heating blast drying oven, and dry it at 120℃ for 30 minutes;

[0042] 2.3. Treat the clean and dry substrate with UV ozone for 10 to 20 minutes;

[0043] 3. Preparation of gate insulation layer and semiconductor layer thin film by solution spin coating

[0044] 3.1. Preparation of P3HT (Mw>40000, p-OLED, 90–94% regioregular) solution and PMMA (M w ≈350000, Sigma-Aldrich) solution, the solvent used for P3HT solution was toluene, the concentration was 1 mg / mL, the solvent used for PMMA solution was ethyl acetate, the concentration was 5 mg / mL, a magnetic bar was added for stirring, and after the P3HT solution and CsPbBr were completely dissolved, 3 NPLs were mixed in a volume ratio of 2:1 for use;

[0045] 3.2. Spin coating was performed under nitrogen environment. The prepared solution was spin coated on the substrate. Two layers were required. First, the PMMA insulating layer was spin coated. 100 μL PMMA solution was evenly dropped on the substrate surface with a pipette. The speed was 3000 r / min and the spin coating time was 30 s. After annealing, P3HT / CsPbBr was continued to be spin coated. 3 The NPLs mixed solution was spin-coated at a speed of 1000 r / min and a time of 50 s, with the thickness controlled at about 30 nm;

[0046] 3.3. Place the spin-coated sample on a heating platform and anneal at 100°C for 30 minutes;

[0047] 4. Preparation of top electrode by vacuum evaporation coating technology

[0048] 4.1. Vacuum evaporation of source and drain electrode copper on the surface of the spin-coated film is performed using a mask plate for patterning. The mask plate channel width is 1500μm and the length is 150μm. The evaporation rate is controlled at The thickness is controlled at about 80nm;

[0049] 4.2. In order to obtain an electrode with a smooth pattern edge, the device after the top electrode is evaporated is further annealed in the original vacuum thermal evaporation environment for at least 20 minutes to obtain a complete synaptic transistor device.

[0050] Figure 1The CsPbBr prepared in this embodiment 3 Transmission electron microscopy (TEM) images and high-resolution transmission electron microscopy (HRTEM) images of NPLs, such as Figure 1 The average size of the nanosheets shown is about 50 nm, and the lattice fringe spacing is 0.5 nm.

[0051] Figure 3 The P3HT / CsPbBr 3 NPLs' low-power synaptic transistors simulate excitatory postsynaptic currents (EPSCs) under light pulses of different wavelengths for synaptic testing, such as Figure 3 As shown, the device has the strongest response to light at a wavelength of 405 nm and the weakest response to light at a wavelength of 650 nm.

[0052] Figure 4 The P3HT / CsPbBr 3 The low-power synaptic transistor of NPLs simulates the long-term plasticity (LTP) of synaptic tests under different numbers of light pulses. As shown in the figure, as the number of pulses increases from 10 to 50, the PSC gradually increases. As the light stimulation stops, the PSC gradually decreases and then stabilizes at a level higher than before the stimulation.

[0053] Figure 5 The P3HT / CsPbBr 3 NPLs' low-power synaptic transistor achieves 0.4 mW cm -2 , EPSC triggered by a 20ms light pulse, calculated according to the energy consumption formula of the synaptic transistor: E = I peak ×t×V, where I peak , t and V are EPSC, light pulse width and operating voltage respectively. The ultra-low power consumption of the synaptic transistor is calculated to be 0.053fJ.

[0054] In summary, the device not only successfully simulates the characteristics of photonic synapses such as excitatory postsynaptic currents, short-range and long-range plasticity, but also achieves ultra-low power consumption. At an extremely low operating voltage of -0.0005 V, the power consumption is 0.4 mW cm -2 With weak light stimulation for 20ms, the source-drain current of the device increased significantly, and the power consumption was only 0.053fJ, which is lower than the power consumption level of most synaptic transistor devices reported so far, which makes the application of neuromorphic computing possible.

Claims

1. A photosynaptic transistor, Features: From bottom to top, this includes: A gate electrode, a gate insulating layer, an organic semiconductor layer, a source electrode and a drain electrode; The organic semiconductor layer is composed of a p-type organic polymer semiconductor P3HT and a perovskite nanosheet CsPbBr 3 NPLs mixed coating, the thickness of the organic semiconductor layer is 20-40 nm; the molecular weight of the p-type organic polymer semiconductor P3HT is greater than 40000; the perovskite nanosheet CsPbBr 3 The average size of NPLs is 50 nm; among them, P3HT and CsPbBr 3 The volume ratio of NPLs was 2:1; The gate electrode is made of a material selected from highly doped silicon, Al, Cu, Au, Ag or Pt; The gate insulating layer covers the entire surface of the gate electrode. The gate insulating layer is made of silicon oxide and polymethyl methacrylate (PMMA). The silicon oxide directly covers the gate electrode. The thickness of the PMMA layer is 20-40 nm. The source electrode and the drain electrode are grown on both sides of the conductive channel. The material used is one of Cu, Au or Pt, and the thickness is 60-100 nm. The length of the conductive channel between the source electrode and the drain electrode is 50-200 μm, and the width of the conductive channel between the source electrode and the drain electrode is 1000-2000 μm.

2. The optical synapse transistor according to claim 1, Features: The source electrode and the drain electrode are prepared by vacuum evaporation or magnetron sputtering.

3. A method for manufacturing a photosynaptic transistor as claimed in claim 1 or 2, Features: The method for manufacturing the optical synapse transistor comprises the following steps: Step (1), first using hot injection method and then using solvent growth method to synthesize perovskite nanosheets CsPbBr 3 NPLs and dispersed in organic solvents; Step (2), weigh P3HT and PMMA respectively and dissolve them in an organic solvent, wherein the concentration of P3HT is 1 mg / mL; the concentration of PMMA is 5 mg / mL, and stir with a magnetic stirrer until they are completely dissolved; Step (3) P3HT solution and CsPbBr 3 The NPLs solution was mixed in a volume ratio of 2:1 as the semiconductor layer solution; Step (4), using acetone, ethanol and deionized water to ultrasonically clean the silicon wafer for 8 to 10 minutes, and then blowing the surface dry with high-purity nitrogen and then drying; Step (5), treating the dry and clean substrate covered with the silicon oxide gate insulating layer with ultraviolet ozone for 10 to 20 minutes; Step (6), using a solution spin coating method, first spin-coat a PMMA gate insulating layer on the substrate cleaned in step (5), with a rotation speed of 3000 r / min and a spin coating time of 30 s, wherein the thickness of the gate insulating layer is controlled to be 20-40 nm; and then spin-coat P3HT / CsPbBr after annealing. 3 NPLs mixed solution, the rotation speed is 1000 r / min, the spin coating time is 50 s, and the thickness is controlled at 20-40 nm; the spin-coated sample is placed on a heating platform for annealing at 100 °C for 30 min; Step (7), vacuum evaporating a source electrode and a drain electrode on the sample annealed in step (6).

4. The method for manufacturing a photosynaptic transistor according to claim 3, It is characterized in that The perovskite nanosheets CsPbBr 3 The specific preparation process of NPLs includes the following steps: cesium carbonate and oleic acid with a mass ratio of 1:46 are reacted at 100 °C for 30 min under vacuum and then placed in N 2 The reaction was continued at 120 °C for 30 min to obtain a cesium oleate precursor; lead bromide, octadecene, oleic acid and oleylamine in a mass ratio of 1:51:5.8:10.6 were reacted at 100 °C for 1 h under vacuum conditions, and then N 2 , the temperature was raised to 120 °C and the cesium oleate precursor was quickly injected, kept for 1 h and then cooled to obtain CsPbBr 3 NPLs crude solution; the prepared CsPbBr 3 The crude NPLs solution was centrifuged and washed to obtain high-purity CsPbBr 3 NPLs.

5. The method for manufacturing the optical synapse transistor according to claim 4, It is characterized in that The centrifugal cleaning process includes: first, centrifuging at 7000 r / min for 15 min, pouring off the supernatant, then adding 2 mL of toluene and 3 mL of ethyl acetate to the precipitate, shaking evenly and centrifuging at 12000 r / min for 10 min, repeating twice, adding 2 mL of toluene to the precipitate, shaking evenly and standing for use.

6. The method for manufacturing the optical synapse transistor according to claim 3, It is characterized in that The organic solvent in step (2) is any one of ethyl acetate, toluene or chlorobenzene.

7. The method for manufacturing a photosynaptic transistor according to claim 3, It is characterized in that The material of the vacuum-evaporated source electrode and drain electrode in step (7) is copper.

8. The method for manufacturing the optical synapse transistor according to claim 7, It is characterized in that The specific steps of vacuum evaporating the source electrode and the drain electrode on the sample in step (7) are as follows: patterning is performed using a mask plate, the mask plate channel width is 1500 μm, the length is 150 μm, the evaporation rate is controlled at 0.5 Å / s, and the thickness is controlled at 60~100 nm.

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