A method and device for measuring parasitic inductance

Abstract

The present application discloses a method and device for measuring parasitic inductance, relating to the field of power electronics technology. The method for measuring parasitic inductance includes: sending a double-pulse driving signal to a second power switching device, and measuring a first current waveform of the turn-on transient process of the second power switching device under a first bus voltage; adjusting the gate driving parameters of the second power switching device, wherein the turn-on speed of the adjusted second power switching device is higher than that of the second power switching device before adjustment; sending a double-pulse driving signal to the second power switching device, and measuring a second current waveform in the turn-on transient process of the second power switching device under the first bus voltage; and measuring the loop parasitic inductance in the parasitic inductance test circuit when the first current waveform and the second current waveform match. According to the embodiments of the present application, accurate measurement of the parasitic inductance in the loop can be effectively achieved.

Description

Technical Field

[0001] This application belongs to the field of power electronics technology, and particularly relates to a method and device for measuring parasitic inductance. Background Art

[0002] In various power electronic systems, such as inverters, DC step-up and step-down systems, etc., power semiconductor devices such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and Insulated Gate Bipolar Transistors (IGBTs) are widely used as switching elements to form topologies such as half-bridges, full-bridges, and three-phase bridges, and corresponding functions are realized through the switching of power semiconductor devices. During the switching process of the devices, the current path in the system changes significantly. The current increases on some paths and decreases on some paths to complete the "commutation" process. During this process, the current change rate on the path is very fast, reaching more than 2000 A / μs.

[0003] In an actual power electronic system, each part of the current path, such as copper bars, device pins, copper plating on a Printed Circuit Board (PCB), internal leads in the package, etc., cannot be regarded as an ideal wire and has corresponding parasitic inductance and resistance. Capacitors and resistors used in the system also cannot be regarded as ideal components and have equivalent parasitic inductance. These parasitic inductances will cause problems such as voltage overshoot, voltage-current oscillation, and increased switching losses during the commutation process of the system. Accurately evaluating and measuring the magnitude of parasitic inductance is of great significance for the design and optimization of power electronic systems.

[0004] However, the existing solutions for measuring and evaluating parasitic inductance generally have problems such as difficult accurate measurement, difficult solution, and low accuracy. Based on this, the industry still urgently needs a new solution to achieve accurate measurement of parasitic inductance. Summary of the Invention

[0005] The embodiments of this application provide a method and device for measuring parasitic inductance, which can effectively achieve accurate measurement of parasitic inductance in a loop.

[0006] In a first aspect, the embodiments of this application provide a method for measuring parasitic inductance. This method for measuring parasitic inductance is applied to a parasitic inductance test circuit, and this parasitic inductance test circuit includes:

[0007] A bus capacitor, a first power switch device, and a second power switch device connected in series in sequence through a DC bus bar, and a load inductance connected in parallel with the first power switch device; a DC voltage source is connected in parallel with the bus capacitor, and the DC voltage source outputs a first bus voltage;

[0008] The parasitic inductance measurement method includes:

[0009] By sending a double-pulse driving signal to the second power switching device, a first current waveform of the turn-on transient process of the second power switching device under the first bus voltage is measured. Among them, under the action of the double-pulse driving signal, the working process of the second power switching device includes the turn-on transient process;

[0010] Adjust the gate driving parameters of the second power switching device, where the turn-on speed of the adjusted second power switching device is higher than that of the second power switching device before adjustment;

[0011] By sending a double-pulse driving signal to the second power switching device, a second current waveform during the turn-on transient process of the second power switching device under the first bus voltage is measured;

[0012] When the first current waveform and the second current waveform match, measure the loop parasitic inductance in the parasitic inductance test circuit;

[0013] Among them, the matching of the first current waveform and the second current waveform means that the time of the linear current rise process in the first current waveform and the second current waveform is greater than a preset threshold.

[0014] In some possible implementation manners, measuring the loop parasitic inductance in the parasitic inductance test circuit includes:

[0015] Based on at least one of the first current waveform and the second current waveform, determine the current change rate of the second power switching device;

[0016] Determine the loop parasitic inductance in the parasitic inductance test circuit through a first calculation formula;

[0017] The first calculation formula is:

[0018]

[0019] Among them, is the current change rate of the second power switching device, L loop is the loop parasitic inductance, U DC is the first bus voltage, V S1 is the conduction voltage drop of the anti-parallel diode in the first power switching device, V S2 is the forward conduction voltage drop of the second power switching device.

[0020] In some possible implementation manners, when the first current waveform and the second current waveform match, measuring the loop parasitic inductance in the parasitic inductance test circuit includes:

[0021] Match the first current linear transformation segment in the first current waveform with the second current linear transformation segment in the second current waveform;

[0022] When the first current linear transformation segment matches the second current linear transformation segment, measure the loop parasitic inductance in the parasitic inductance test circuit.

[0023] In some possible implementation manners, after measuring the second current waveform during the turn-on transient process of the second power switch device under the first bus voltage, the parasitic inductance measurement method further includes:

[0024] When the first current waveform and the second current waveform do not match, adjust the target parameter, where the target parameter is: the bus voltage output by the DC voltage source; or, the gate drive parameter of the second power switch device;

[0025] By sending a double-pulse drive signal to the second power switch device, measure the third current waveform during the turn-on transient process of the second power switch device after the target parameter is adjusted;

[0026] Determine whether to measure the loop parasitic inductance in the parasitic inductance test circuit according to the third current waveform.

[0027] In some possible implementation manners, when the target parameter is the bus voltage output by the DC voltage source and the first current waveform and the second current waveform do not match, adjusting the target parameter includes:

[0028] When the first current waveform and the second current waveform do not match, adjust the first bus voltage output by the DC voltage source to the second bus voltage;

[0029] Determine whether to measure the loop parasitic inductance in the parasitic inductance test circuit according to the third current waveform, including:

[0030] Adjust the gate drive parameter of the second power switch device, where the turn-on speed of the second power switch device after adjustment is higher than that before adjustment;

[0031] By sending a double-pulse drive signal to the second power switch device, measure the fourth current waveform during the turn-on transient process of the second power switch device under the second bus voltage;

[0032] When the third current waveform and the fourth current waveform match, measure the loop parasitic inductance in the parasitic inductance test circuit.

[0033] In some possible implementation manners, when the first current waveform and the second current waveform do not match, adjusting the first bus voltage output by the DC voltage source to the second bus voltage includes:

[0034] When the first current waveform and the second current waveform do not match, and the difference between the turn-on speed of the second power switch device and the upper limit value of the turn-on speed of the second power switch device is less than the first threshold, the first bus voltage output by the DC voltage source is adjusted to the second bus voltage.

[0035] In some possible implementation manners, when the first current waveform and the second current waveform match, the parasitic inductance measurement method further includes:

[0036] Measuring a first voltage waveform across both ends of a branch to be measured in a parasitic inductance test circuit during a target time period, where the target time period is the time period corresponding to the turn-on transient process of the second power switch device under the first bus voltage; the branch to be measured does not include a bus capacitor;

[0037] Determining a first voltage value of a first voltage segment in the first voltage waveform; the difference between the voltage value corresponding to each moment in the first voltage segment and the first voltage value is less than a second threshold; the time period corresponding to the first voltage segment matches the time period corresponding to the current rising segment in the target current waveform; the target current waveform is determined based on the first current waveform and / or the second current waveform;

[0038] Determining the parasitic inductance of the branch to be measured through a second calculation formula;

[0039] The second calculation formula is:

[0040]

[0041] where L DUT is the parasitic inductance of the branch to be measured, is the current change rate of the second power switch device, and U DUT is the first voltage value.

[0042] In some possible implementation manners, when the first current waveform and the second current waveform match, the parasitic inductance measurement method further includes:

[0043] Measuring a second voltage waveform of the bus capacitor in the parasitic inductance test circuit during the target time period;

[0044] Determining a second voltage value of a second voltage segment in the second voltage waveform; the time period corresponding to the second voltage segment matches the time period corresponding to the current rising segment in the target current waveform; the difference between the voltage value corresponding to each moment in the second voltage segment and the second voltage value is less than a third threshold;

[0045] Determining the parasitic inductance of the bus capacitor through a third calculation formula;

[0046] The third calculation formula is:

[0047]

[0048] Among them, L1 is the parasitic inductance of the bus capacitor, is the rate of change of current of the second power switch device, U C is the second voltage value, U DC is the first bus voltage.

[0049] In some possible implementation manners, the range of the bus voltage output by the DC voltage source is between 10V and 50V.

[0050] In a second aspect, an embodiment of the present application provides a parasitic inductance measurement device, which is applied to a parasitic inductance test circuit, and the parasitic inductance test circuit includes:

[0051] A bus capacitor, a first power switch device, and a second power switch device connected in series in sequence through a DC busbar, and a load inductor connected in parallel with the first power switch device; a DC voltage source is connected in parallel with the bus capacitor, and the DC voltage source outputs a first bus voltage;

[0052] The parasitic inductance measurement device includes:

[0053] A first measurement module, configured to measure a first current waveform of the turn-on transient process of the second power switch device under the first bus voltage by sending a double-pulse drive signal to the second power switch device, where, under the action of the double-pulse drive signal, the working process of the second power switch device includes a turn-on transient process;

[0054] A first adjustment module, configured to adjust the gate drive parameters of the second power switch device, where the turn-on speed of the adjusted second power switch device is higher than that of the second power switch device before adjustment;

[0055] A second measurement module, configured to measure a second current waveform during the turn-on transient process of the second power switch device under the first bus voltage by sending a double-pulse drive signal to the second power switch device;

[0056] A third measurement module, configured to measure the loop parasitic inductance in the parasitic inductance test circuit when the first current waveform and the second current waveform match;

[0057] Among them, the matching of the first current waveform and the second current waveform means that the time of the linear rising process of the current in the first current waveform and the second current waveform is greater than a preset threshold.

[0058] In a third aspect, an embodiment of the present application provides a parasitic inductance measurement device, and the parasitic inductance measurement device includes:

[0059] A processor and a memory storing computer program instructions;

[0060] When the processor executes the computer program instructions, the parasitic inductance measurement method provided in any one of the above embodiments of the present application is implemented.

[0061] In a fourth aspect, an embodiment of the present application provides a computer storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the parasitic inductance measurement method provided in any one of the above embodiments of the present application is implemented.

[0062] In a fifth aspect, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device is caused to execute the parasitic inductance measurement method provided in any one of the above embodiments of the present application.

[0063] A parasitic inductance measurement method and device according to an embodiment of the present application first send a dual-pulse drive signal to a second power switch device, measure a first current waveform of the turn-on transient process of the second power switch device under a first bus voltage, and then adjust the gate drive parameters of the second power switch device and measure an adjusted second current waveform. In this way, the loop parasitic inductance in the parasitic inductance test circuit is measured based on the matching situation between the first current waveform and the second current waveform. The parasitic inductance measurement method and device provided in the embodiments of the present application can verify whether the characteristics of the first bus voltage and the gate drive parameters of the second power switch device match based on the matching situation between the first current waveform and the second current waveform, and measure the loop parasitic inductance when the characteristics of the first bus voltage and the gate drive parameters of the second power switch device match and the time of the linearly rising process of the current in both the first current waveform and the second current waveform is greater than a preset threshold, thereby effectively ensuring the accurate measurement of the parasitic inductance in the loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0065] Figure 1 is a schematic flowchart of a parasitic inductance measurement method provided by an embodiment of the present application;

[0066] Figure 2 is a schematic structural diagram of a parasitic inductance measurement circuit provided by an embodiment of the present application;

[0067] Figure 3 is provided by an embodiment of the present application Figure 2Schematic diagram of the circuit waveform of the parasitic inductance measurement circuit shown;

[0068] Figure 4 This is provided by an embodiment of the present application Figure 2 Schematic diagram of the voltage - current waveform of the parasitic inductance measurement circuit shown;

[0069] Figure 5 Another structural schematic diagram of the parasitic inductance measurement circuit provided by an embodiment of the present application;

[0070] Figure 6 Another structural schematic diagram of the parasitic inductance measurement circuit provided by an embodiment of the present application;

[0071] Figure 7 Another structural schematic diagram of the parasitic inductance measurement circuit provided by an embodiment of the present application;

[0072] Figure 8 This is provided by an embodiment of the present application Figure 7 Schematic diagram of the voltage - current waveform of the parasitic inductance measurement circuit shown;

[0073] Figure 9 Structural schematic diagram of the parasitic inductance measurement device provided by an embodiment of the present application;

[0074] Figure 10 Structural schematic diagram of the parasitic inductance measurement equipment provided by an embodiment of the present application. Detailed implementation manners

[0075] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below in combination with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0076] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0077] The inventor has found through research that since commutation in a power electronic system often occurs in a certain half-bridge circuit, the evaluation and measurement of parasitic inductance are often carried out for this system including bus capacitors, busbars, and power half-bridges. Regarding the evaluation of parasitic inductance, it specifically includes two methods: simulation calculation and experimental measurement. Among them, the simulation calculation method is based on the spatial geometric model of the current path, and uses methods such as theoretical formula approximation and finite element to calculate the parasitic inductance value of the current path. However, there are problems such as the calculation accuracy being affected by the modeling accuracy, being unable to fully correspond to the actual system, and being difficult to consider the parasitic inductance of passive devices such as capacitors and resistors. Generally, it requires comparison and verification with the experimental measurement results.

[0078] Therefore, the current methods for evaluating parasitic inductance through experimental measurement include solving based on the turn-off voltage spike and the rate of change of turn-off current, artificially exciting the system to oscillate to obtain the resonant frequency for solution, and solving based on the rate of change of current and voltage plateau during the turn-on process of the device under an inductive load. The first two have problems such as relying on transient signal testing and being affected by the change of junction capacitance, resulting in poor accuracy. Based on this, solving based on the rate of change of current and voltage plateau during the turn-on process is a commonly used method. However, the inventor further found through research that since the rate of change of current is jointly controlled by the gate charging process and the device output characteristics and is difficult to be stable for a long time, there is also a problem of difficult accurate measurement and solution. At the same time, this method is limited by the problem of the voltage measurement point and generally difficult to measure the parasitic inductance inside the package.

[0079] In view of the above, to solve the problems of the prior art, the embodiments of the present application provide a method, device, equipment, storage medium and computer program product for measuring parasitic inductance. It should be noted that the embodiments provided in the present application do not limit the scope of the disclosure of the present application.

[0080] First, the parasitic inductance measurement method provided by the embodiments of the present application will be introduced below.

[0081] Figure 1The flowchart of a parasitic inductance measurement method provided by an embodiment of the present application is shown. This parasitic inductance measurement method is applied to a parasitic inductance test circuit, which includes:

[0082] A bus capacitor, a first power switch device, and a second power switch device connected in series in sequence through a DC busbar, and a load inductor connected in parallel with the first power switch device; a DC voltage source is connected in parallel with the bus capacitor, and the DC voltage source outputs a first bus voltage;

[0083] This parasitic inductance measurement method may include:

[0084] S110, by sending a double-pulse driving signal to the second power switch device, measure a first current waveform during the turn-on transient process of the second power switch device under the first bus voltage. Among them, under the action of the double-pulse driving signal, the working process of the second power switch device may include a turn-on transient process;

[0085] S120, adjust the gate driving parameters of the second power switch device, where the turn-on speed of the adjusted second power switch device is higher than that of the second power switch device before adjustment;

[0086] S130, by sending a double-pulse driving signal to the second power switch device, measure a second current waveform during the turn-on transient process of the second power switch device under the first bus voltage;

[0087] S140, when the first current waveform and the second current waveform match, measure the loop parasitic inductance in the parasitic inductance test circuit; where the matching of the first current waveform and the second current waveform means that the time of the linear current rise process in the first current waveform and the second current waveform is greater than a preset threshold.

[0088] A parasitic inductance measurement method according to an embodiment of the present application first sends a double-pulse driving signal to the second power switch device to measure a first current waveform during the turn-on transient process of the second power switch device under the first bus voltage, and then adjusts the gate driving parameters of the second power switch device to measure the adjusted second current waveform. In this way, the loop parasitic inductance in the parasitic inductance test circuit is measured based on the matching situation of the first current waveform and the second current waveform.

[0089] A parasitic inductance measurement method provided by an embodiment of the present application can verify whether the characteristics of the first bus voltage and the gate drive parameters of the second power switch device match based on the matching situation between the first current waveform and the second current waveform. When the characteristics of the first bus voltage and the gate drive parameters of the second power switch device match, and the time of the current linear rise process in both the first current waveform and the second current waveform is greater than a preset threshold (the first current waveform and the second current waveform include a long stable current rise section), the loop parasitic inductance is measured, thereby effectively ensuring the accurate measurement of the parasitic inductance in the loop.

[0090] The specific implementation manners of the above steps 110 to 140 will be introduced in detail below.

[0091] To facilitate a better understanding of the following embodiments of the present application, first please refer to Figure 2 and Figure 3 , Figure 2 is a schematic structural diagram of a parasitic inductance measurement circuit provided by an embodiment of the present application; Figure 3 is provided by an embodiment of the present application Figure 2 is a schematic circuit waveform diagram of the parasitic inductance measurement circuit shown.

[0092] Figure 2 In, S1 is the first power switch device, S2 is the second power switch device, and the first / second power switch device can specifically be a MOSFET, IGBT, etc., C is the bus capacitor, I DS is a current sensor for measuring the current passing through the S2 element (which can be a Rogowski coil, a shunt resistor, a Hall sensor, etc.), L is the load inductance for double-pulse testing, and its inductance value is at the μH level, L1 is the parasitic inductance of the bus capacitor, L2 to L5 are the parasitic inductances corresponding to some current paths, and the inductance values of L1 to L5 are generally at the level of dozens of nH. The gate of the second power switch device S2 is connected to a double-pulse signal sending platform for conducting or turning off according to the double-pulse signal received by the gate.

[0093] Generally, to evaluate the characteristics of a power electronic system, it is generally necessary to measure the total loop parasitic inductance. Figure 2 The loop parasitic inductance L in the parasitic inductance measurement circuit shown loop The expression is as shown in Equation 1.

[0094] L loop = L1 + L2 + L3 + L4 + L5 Equation 1

[0095] Next, in combination with Figure 3 to Figure 2 the working process of the parasitic inductance measurement circuit in will be introduced.

[0096] In Figure 3 in, VGS(S2) is the gate-source voltage of component S2, I L is the current of load inductor L, I DS(S2) is the drain-source current passing through component S2, V DS(S2) is the drain-source voltage of source S2.

[0097] Combined with Figure 3 , in the specific test process, the first power switch device S1 always remains off.

[0098] At time t0, the second power switch device S2 turns on, causing the load inductor to generate a continuously rising current under the action of the bus voltage output by the DC voltage source. The current I DS(S2) passing through the second power switch device S2 then rises and remains consistent with the inductor current.

[0099] During the time period from t0 to t1, the voltage V DS(S2) across the S2 device drops to the conduction voltage drop (generally small, much smaller than the bus voltage). During this process, the current path in this circuit is as shown by the solid line in Figure 2 . By controlling the time from t0 to t1, the device current before time t1 can be controlled, that is, the test current I norm . The test current I norm is determined by Equation 2:

[0100]

[0101] where L is the inductance value of the load inductor, and U dc is the bus voltage.

[0102] At time t1, the second power switch device S2 turns off to form an open circuit. Since the load inductor current cannot change suddenly, the load inductor conducts freewheeling through the anti-parallel diode in the first switch power device S1. After that, the current path in this current is as shown by the dotted line in Figure 2 .

[0103] During the t1 - t2 stage, the freewheeling diode and the loop parasitic resistance in the first power switch device consume the inductor energy, causing the current to drop slightly, but the dropping speed and amplitude are much smaller than the current rising rate when S2 is turned on. Therefore, it can be considered that the inductor currents at times t1 and t2 are the same. And, during this stage, since the second power switch device S2 is turned off, the current I DS(S2) passing through the second power switch device S2 is zero, and the voltage V DS(S2) across the second power switch device S2 is equal to the bus voltage.

[0104] At time t2, the second power switch device S2 turns on again, and the current path changes back to Figure 2The solid line path in. At time t3, the second power switch device S2 is turned off again, and the current path becomes Figure 2 the virtual line path in, and continues until the inductor energy is exhausted.

[0105] For the turn-on process of the second power switch device at time t2, please refer to Figure 4 , Figure 4 which is provided by an embodiment of the present application Figure 2 a schematic diagram of the voltage and current waveforms of the parasitic inductance measurement circuit shown.

[0106] Figure 4 shows the turn-on transient process of the second power switch device S2 at the corresponding bus voltage measured at time t2, corresponding to the I DS(S2) current waveform, the V GS(S2) voltage waveform, and the V DS(S2) voltage waveform. Among them, please see Figure 4 the I DS(S2) current waveform shown. At the moment when the second power switch device is turned on at time t2, a current linear change segment of the order of nanoseconds will appear.

[0107] Next, return to the parasitic inductance measurement method provided by the present application. In S110, specifically, by sending a double-pulse drive signal to the second power switch device, the first current waveform of the turn-on transient process of the second power switch device under the first bus voltage at time t2 is measured. Among them, under the action of the double-pulse drive signal, the working process of the second power switch device includes the turn-on transient process.

[0108] When specifically measuring the waveform, a current sensor, such as a Rogowski coil, a shunt resistor, a Hall sensor, etc., can be arranged in the parasitic inductance measurement circuit, and then combined with an oscilloscope, etc. to obtain the first current waveform of the turn-on transient process of the second power switch device under the first bus voltage.

[0109] In S120, specifically, after measuring the above first current waveform, the gate drive parameters of the second power switch device are adjusted to improve the turn-on speed of the second power switch device. Among them, the turn-on speed of the adjusted second power switch device is higher than that of the second power switch device before adjustment, that is, when the second power switch device is turned on by using the adjusted gate drive parameters, the turn-on speed of the second power switch device is higher than when the second power switch device is turned on by using the gate drive parameters before adjustment.

[0110] The above adjustment of the gate drive parameters of the second power switch device can specifically be to reduce the turn-on gate resistance, increase the gate positive voltage value during turn-on, or reduce the gate capacitance value when there is an external gate capacitance, etc. The present application does not make specific limitations on this.

[0111] In S130, in specific implementation, after adjusting the gate drive parameters of the second power switch device to improve the turn-on speed of the second power switch device at time t2, a double-pulse drive signal is sent to the second power switch device again, and the second current waveform during the turn-on transient process of the second power switch device under the first bus voltage is measured.

[0112] The measurement method of the second current waveform is the same as that of the aforementioned first current waveform, the difference being that: the turn-on speed of the second power switch device corresponding to the second current waveform has been improved by adjusting the gate drive parameters.

[0113] In S140, in specific implementation, the measured first current waveform and second current waveform are matched. Specifically, for example, it can be verified whether the current change trends and the like corresponding to a certain time period in the first current waveform and the second current waveform are consistent. In this way, when it is determined that the first current waveform and the second current waveform match, the loop parasitic inductance in the parasitic inductance test circuit is measured again.

[0114] Since the matching of the first current waveform and the second current waveform indicates that the characteristics of the first bus voltage and the gate drive parameters of the second power switch device match, and the time of the linear current rise process in the first current waveform and the second current waveform is greater than a preset threshold (the first current waveform and the second current waveform include a long stable current rise section). At this time, when the loop parasitic inductance is specifically measured, the accurate measurement of the parasitic inductance in the loop can be effectively guaranteed.

[0115] In some possible implementation manners, measuring the loop parasitic inductance in the parasitic inductance test circuit may include:

[0116] Determining the current change rate of the second power switch device based on at least one of the first current waveform and the second current waveform;

[0117] Determining the loop parasitic inductance in the parasitic inductance test circuit through a first calculation formula;

[0118] The first calculation formula is as shown in Equation 3:

[0119]

[0120] Wherein, is the current change rate of the second power switch device, L loop is the loop parasitic inductance, U DC is the first bus voltage, V S1 is the conduction voltage drop of the anti-parallel diode in the first power switch device, V S2 is the forward conduction voltage drop of the second power switch device.

[0121] In specific implementation, exemplarily, it may be in the first current waveform, the second current waveform, or the current waveform obtained by fusing the first current waveform and the second current waveform by using relevant image processing means. An current linear transformation section where the current shows a stable linear increase is selected, so as to determine the current change rate of the second power switch device according to the current linear transformation section, and then the loop parasitic inductance in the parasitic inductance test circuit is specifically calculated in combination with the first calculation formula.

[0122] In this embodiment, considering that the conduction voltage drop of the anti-parallel diode changes relatively little with the current after it is fully turned on, the conduction voltage drop V of the device diode can be directly used F for approximate substitution, that is

[0123] V S1 =V F

[0124] wherein, the value of V F can be obtained from the device datasheet.

[0125] V S2 is the forward conduction voltage drop of the second power switch device S2. When the second power switch device S2 is a MOSFET, it can be approximated by the following formula

[0126] V S2 =I norm ·R DS(on)

[0127] wherein, I norm is the test current in the aforementioned formula 2, and R DS(on) is the on-resistance of the second power switch device S2.

[0128] When the second power switch device S2 is an IGBT, it can be approximated by the forward saturation voltage drop of the second power switch device S2, wherein the value of V CEsat can be obtained from the device datasheet.

[0129] V S2 =V CEsat

[0130] By using a parasitic inductance measurement method provided by the present application to measure the loop parasitic inductance as described above, since the first current waveform and the second current waveform match, the bus voltage of the DC voltage source matches the characteristics of the gate drive parameters of the second power switch device, the linearity of the current rising process is good, and the duration of the rising stage is relatively long, it is easy to extract a stable current change rate to obtain a high measurement accuracy.

[0131] In addition, when the parasitic inductance measurement method provided by this application is actually measured, only one current measurement probe is required, and no voltage probe is needed, which effectively reduces the measurement requirements and complexity. At the same time, by using the measurement method described in the present invention, the full-system parasitic inductance measurement including the internal parasitic inductance of the module can be completed without setting measurement points in the power module, improving the integrity of the measurement results.

[0132] In some possible implementation manners, considering the actual needs of parasitic inductance measurement, when the first current waveform and the second current waveform match, measuring the loop parasitic inductance in the parasitic inductance test circuit, that is, the above step S140, may include:

[0133] Matching the first current linear transformation section in the first current waveform with the second current linear transformation section in the second current waveform;

[0134] When the first current linear transformation section and the second current linear transformation section match, measuring the loop parasitic inductance in the parasitic inductance test circuit.

[0135] Among them, the first current linear transformation end in the first current waveform and the second current linear transformation section in the second current waveform can specifically refer to Figure 4 the marked current linear transformation section.

[0136] When specifically matching the first current linear transformation section and the second current linear transformation section, the current transformation rates (transformation section slopes) of the two can be specifically compared. If the current transformation rates of the two are the same or almost approach the same, it can be considered that the first current linear transformation section and the second current linear transformation section match, that is, the first current waveform and the second current waveform match. At this time, when measuring and calculating the loop parasitic inductance in the parasitic inductance measurement circuit, the accuracy of the measured loop parasitic inductance can be fully guaranteed.

[0137] In some possible implementation manners, for the case where the first current waveform and the second current waveform do not match, that is, the characteristics of the bus voltage and the gate drive parameters of the second power switch device do not match, it is necessary to adjust based on this parasitic capacitance measurement loop so that the characteristics of the final bus voltage and the gate drive parameters of the second power switch device match each other, so as to obtain a long-term stable current linear rising section in the current waveform of the turn-on transient process of the second power switch device. Therefore, after measuring the second current waveform in the turn-on transient process of the second power switch device under the first bus voltage, the parasitic inductance measurement method may further include:

[0138] When the first current waveform and the second current waveform do not match, adjusting the target parameter, where the target parameter is: the bus voltage output by the DC voltage source; or, the gate drive parameters of the second power switch device;

[0139] By sending a double-pulse driving signal to the second power switching device, a third current waveform of the turn-on transient process of the second power switching device after the target parameters are adjusted is measured;

[0140] According to the third current waveform, it is determined whether to measure the loop parasitic inductance in the parasitic inductance test circuit.

[0141] In specific implementation, the gate driving parameters of the DC bus source or the second power switching device can be adjusted, and the current waveform corresponding to the turn-on transient process of the adjusted second power switching device is measured, and based on this current waveform, it is determined whether the loop parasitic inductance in the parasitic inductance test circuit can be measured.

[0142] In some possible implementation manners, in order to achieve the rationality of target parameter adjustment to further ensure the accurate measurement of the loop parasitic inductance, when the target parameter is the gate driving parameter of the second power switching device, according to the third current waveform, determining whether to measure the loop parasitic inductance in the parasitic inductance test circuit may include:

[0143] When the third current waveform matches the second current waveform, measure the loop parasitic inductance in the parasitic inductance test circuit.

[0144] In some possible implementation manners, in order to achieve the rationality of target parameter adjustment to further ensure the accurate measurement of the loop parasitic inductance, when the target parameter is the bus voltage output by the DC voltage source, when the first current waveform and the second current waveform do not match, adjusting the target parameter may specifically include:

[0145] When the first current waveform and the second current waveform do not match, adjust the first bus voltage output by the DC voltage source to the second bus voltage;

[0146] According to the third current waveform, determining whether to measure the loop parasitic inductance in the parasitic inductance test circuit may include:

[0147] Adjust the gate driving parameter of the second power switching device, wherein the turn-on speed of the adjusted second power switching device is higher than that of the second power switching device before adjustment;

[0148] By sending a double-pulse driving signal to the second power switching device, a fourth current waveform of the turn-on transient process of the second power switching device under the second bus voltage is measured;

[0149] When the third current waveform matches the fourth current waveform, measure the loop parasitic inductance in the parasitic inductance test circuit.

[0150] In specific implementation, when the first current waveform and the second current waveform do not match, the first bus voltage output by the DC voltage source is adjusted to the second bus voltage, and the third current waveform of the turn-on transient process of the second power switch device under the second bus voltage is measured. At this time, the gate drive parameters of the second power switch device are adjusted to increase the turn-on speed of the second power switch device. After adjusting the gate drive parameters of the second power switch device, a double-pulse drive signal is sent to the second power switch device, and the fourth current waveform of the turn-on transient process of the second power switch device under the second bus voltage after adjustment is measured.

[0151] In this way, by judging whether the third current waveform and the fourth current waveform match, and when it is determined that the third current waveform and the fourth current waveform match, the loop parasitic inductance in the parasitic inductance test circuit is measured.

[0152] In some possible implementation manners, although the above target parameter can be the bus voltage of the DC voltage source or the gate drive parameter of the second power switch device, the inventors of the present application found through research in combination with the actual parasitic capacitance measurement experiment scenario that in order to reduce the experimental measurement error, direct adjustment of the bus voltage is avoided as much as possible. That is, when the first current waveform and the second current waveform do not match, the gate drive parameters of the second power switch device are preferentially adjusted to increase its turn-on speed.

[0153] However, for a power switch device, its turn-on speed has an upper limit value. If the turn-on speed is too fast, it often causes the device to be damaged or burned out. Based on this, in order to achieve more reasonable adjustment of the target parameter, the above adjustment of the first bus voltage output by the DC voltage source to the second bus voltage when the first current waveform and the second current waveform do not match may include:

[0154] When the first current waveform and the second current waveform do not match, and the difference between the turn-on speed of the second power switch device and the upper limit value of the turn-on speed of the second power switch device is less than the first threshold, the first bus voltage output by the DC voltage source is adjusted to the second bus voltage.

[0155] It should be noted that the upper limit value of the turn-on speed of the second power switch device can be determined by checking the device datasheet.

[0156] In a parasitic inductance measurement method of the present application, when introducing by taking Figure 2 as an example above, S2 is used as the second power switch device for double-pulse testing to measure the parasitic inductance. However, in some other embodiments, see Figure 5 , Figure 5It is another schematic structural diagram of the parasitic inductance measurement circuit provided by an embodiment of the present application. It can also be a double-pulse test with S1 as the second power switch device in this solution to similarly measure the parasitic inductance.

[0157] In addition to measuring the parasitic inductance of the loop as described above, the parasitic inductance measurement method provided by the present application can also be used to measure the parasitic inductance of a specific part of the current path. In some possible implementation manners, specifically, when the first current waveform and the second current waveform match, the parasitic inductance measurement method may further include:

[0158] Measuring the first voltage waveform across both ends of the branch to be measured in the parasitic inductance test circuit during the target time period. The target time period is the time period corresponding to the turn-on transient process of the second power switch device under the first bus voltage. The branch to be measured shall not include the bus capacitor;

[0159] Determining the first voltage value of the first voltage segment in the first voltage waveform. The difference between the voltage values corresponding to each moment in the first voltage segment and the first voltage value is less than the second threshold. The time period corresponding to the first voltage segment matches the time period corresponding to the current rising segment in the target current waveform. The target current waveform is determined based on the first current waveform and / or the second current waveform;

[0160] Determining the parasitic inductance of the branch to be measured through the second calculation formula;

[0161] The second calculation formula can be:

[0162]

[0163] where L DUT is the parasitic inductance of the branch to be measured, is the current change rate of the second power switch device, and U DUT is the first voltage value.

[0164] Please refer to Figure 6 , Figure 6 which is another schematic structural diagram of the parasitic inductance measurement circuit provided by an embodiment of the present application. As Figure 6 shown, a voltage probe can be connected across the current path to be measured (the branch to be measured), and record the first voltage waveform U DUT (t) across both ends of the current path to be measured during the turn-on transient process of the second power switch device S2 at time t2.

[0165] During the rising process of the current I ds of the second switching power device, a voltage plateau (the first voltage segment) will appear in the first voltage waveform U DUT (t). Record the voltage value U DUT(The first voltage value), the parasitic inductance of this part of the current path can be calculated using the second calculation formula.

[0166] In some possible implementation manners, similarly, the parasitic inductance measurement method provided in this application can also be used for measuring the parasitic inductance of a bus capacitor. Specifically, when the first current waveform and the second current waveform match, the parasitic inductance measurement method may further include:

[0167] Measuring the second voltage waveform of the bus capacitor in the parasitic inductance test circuit during the target time period;

[0168] Determining the second voltage value of the second voltage segment in the second voltage waveform; the time period corresponding to the second voltage segment matches the time period corresponding to the current rising segment in the target current waveform; the difference between the voltage value corresponding to each moment in the second voltage segment and the second voltage value is less than the third threshold;

[0169] Determining the parasitic inductance of the bus capacitor through the third calculation formula;

[0170] The third calculation formula may be:

[0171]

[0172] where L1 is the parasitic inductance of the bus capacitor, is the current change rate of the second power switch device, U C is the second voltage value, U DC is the first bus voltage.

[0173] Please refer to Figure 7 , Figure 7 which is another schematic structural diagram of the parasitic inductance measurement circuit provided by an embodiment of this application. As Figure 7 shown, a voltage probe is used to record the voltage waveform U C (t) at both ends of the measured current path during the transient process of turning on the second power switch device S2 at time t2. Specifically, please refer to Figure 8 , Figure 8 which is a schematic diagram of the voltage and current waveforms of the parasitic inductance measurement circuit provided by an embodiment of this application. Referring to Figure 7 it can be seen that during the rising process of the current I Figure 8 of the second switching power device S2, a voltage plateau (the second voltage segment) will appear in the second voltage waveform U DS (t). Recording the voltage value U C (the second voltage value) of this plateau, the parasitic inductance of the bus capacitor can be calculated using the third calculation formula. C

[0174] In some possible embodiments, in order to further improve the accuracy of parasitic inductance measurement, the range of the bus voltage output by the DC voltage source is between 10V and 50V. It should be noted that in the foregoing embodiments, the first bus voltage or the second bus voltage output by the DC voltage source may both be within the range of 10V to 50V.

[0175] The inventors of the present application have realized that in the parasitic inductance measurement scheme applied to the parasitic inductance measurement circuit, if the bus voltage output by the DC voltage source is too low, the proportion of the conduction voltage of the second power switch device in the actual loop parasitic inductance calculation step will be too large, which will affect the accuracy of parasitic inductance measurement. If the bus voltage output by the DC voltage source is too high, it is not easy to measure the long current stable linear rising section of the second power switch device during the turn-on transient process, which is not conducive to the subsequent actual calculation of the parasitic capacitance.

[0176] Therefore, considering the above comprehensively, the inventors of the present application have restricted the range of the bus voltage output by the DC voltage source in this case to between 10V and 50V after research, so as to further achieve accurate measurement of the parasitic inductance.

[0177] It should be added that the parasitic inductance measurement method provided by the present application can be applied to, but not limited to, power electronic systems with low on-resistance and large rated current, preferably for a rated current of not less than 80A and a rated on-state voltage drop of not more than 2.5V.

[0178] Under this prerequisite, only by providing a large test current can a longer current rise time during turn-on be obtained under the same test conditions, making the measurement process more accurate. In addition, if the rated current of the second power switch device is small and cannot withstand large current tests, a relatively low bus voltage can also be selected as much as possible to reduce the current change rate during the turn-on process and increase the current rise time when the second power switch device is turned on.

[0179] Based on the parasitic inductance measurement method provided in the above embodiments, the present application also provides a parasitic inductance measurement device corresponding to the above parasitic inductance measurement method. The following is through Figure 9 a detailed introduction to the parasitic inductance measurement device.

[0180] Figure 9 shows a schematic structural diagram of a parasitic inductance measurement device provided by an embodiment of the present application.

[0181] Figure 9 The shown parasitic inductance measurement device 900 includes:

[0182] This parasitic inductance measurement device is applied to a parasitic inductance test circuit, and this parasitic inductance test circuit includes:

[0183] A bus capacitor, a first power switch device, and a second power switch device connected in series in sequence through a DC busbar, and a load inductor connected in parallel with the first power switch device; a DC voltage source is connected in parallel with the bus capacitor, and the DC voltage source outputs a first bus voltage;

[0184] The parasitic inductance measuring device may include:

[0185] A first measurement module 910, configured to measure a first current waveform of the turn-on transient process of the second power switch device under the first bus voltage by sending a double-pulse driving signal to the second power switch device, wherein, under the action of the double-pulse driving signal, the operating process of the second power switch device includes a turn-on transient process;

[0186] A first adjustment module 920, configured to adjust the gate driving parameters of the second power switch device, wherein the turn-on speed of the adjusted second power switch device is higher than that of the second power switch device before adjustment;

[0187] A second measurement module 930, configured to measure a second current waveform during the turn-on transient process of the second power switch device under the first bus voltage by sending a double-pulse driving signal to the second power switch device;

[0188] A third measurement module 940, configured to measure the loop parasitic inductance in the parasitic inductance test circuit when the first current waveform and the second current waveform match;

[0189] Wherein, the matching of the first current waveform and the second current waveform means that the time of the linear rising process of the current in the first current waveform and the second current waveform is greater than a preset threshold.

[0190] In some possible implementation manners, the third measurement module 940 may include:

[0191] A first determination sub-module, configured to determine the current change rate of the second power switch device based on at least one of the first current waveform and the second current waveform;

[0192] A second determination sub-module, configured to determine the loop parasitic inductance in the parasitic inductance test circuit through a first calculation formula;

[0193] The first calculation formula is:

[0194]

[0195] Wherein, is the current change rate of the second power switch device, L loop is the loop parasitic inductance, U DC is the first bus voltage, V S1is the conduction voltage drop of the anti-parallel diode in the first power switch device, V S2 is the forward conduction voltage drop of the second power switch device.

[0196] In some possible implementation manners, the third measurement module 940 may include:

[0197] A matching sub-module, which can be used to match the first current linear transformation segment in the first current waveform with the second current linear transformation segment in the second current waveform;

[0198] A first measurement sub-module, which can be used to measure the loop parasitic inductance in the parasitic inductance test circuit when the first current linear transformation segment matches the second current linear transformation segment.

[0199] In some possible implementation manners, after measuring the second current waveform in the turn-on transient process of the second power switch device under the first bus voltage, the parasitic inductance measuring device may further include:

[0200] A second adjustment module, which can be used to adjust the target parameter when the first current waveform and the second current waveform do not match, and the target parameter is: the bus voltage output by the DC voltage source; or, the gate drive parameter of the second power switch device;

[0201] A fourth measurement module, which can be used to measure the third current waveform in the turn-on transient process of the second power switch device after the target parameter is adjusted by sending a double-pulse drive signal to the second power switch device;

[0202] A first determination module, which can be used to determine whether to measure the loop parasitic inductance in the parasitic inductance test circuit according to the third current waveform.

[0203] In some possible implementation manners, when the target parameter is the bus voltage output by the DC voltage source, the second adjustment module may specifically include:

[0204] A first adjustment sub-module, which can be used to adjust the first bus voltage output by the DC voltage source to a second bus voltage when the first current waveform and the second current waveform do not match;

[0205] The above-mentioned first determination module may include:

[0206] A second adjustment sub-module, which can be used to adjust the gate drive parameter of the second power switch device, where the turn-on speed of the second power switch device after adjustment is higher than the turn-on speed of the second power switch device before adjustment;

[0207] The second measurement sub-module can be used to measure the fourth current waveform of the turn-on transient process of the second power switch device under the second bus voltage by sending a double-pulse drive signal to the second power switch device;

[0208] The third measurement sub-module can be used to measure the loop parasitic inductance in the parasitic inductance test circuit when the third current waveform and the fourth current waveform match.

[0209] In some possible implementation manners, the above first adjustment sub-module may include:

[0210] When the first current waveform and the second current waveform do not match, and the difference between the turn-on speed of the second power switch device and the upper limit value of the turn-on speed of the second power switch device is less than the first threshold, adjust the first bus voltage output by the DC voltage source to the second bus voltage.

[0211] In some possible implementation manners, when the first current waveform and the second current waveform match, the parasitic inductance measuring device may further include:

[0212] The fifth measurement module can be used to measure the first voltage waveform across both ends of the branch to be measured in the parasitic inductance test circuit during the target time period. The target time period is the time period corresponding to the turn-on transient process of the second power switch device under the first bus voltage; the branch to be measured may not include the bus capacitor;

[0213] The second determination module can be used to determine the first voltage value of the first voltage segment in the first voltage waveform; the difference between the voltage values corresponding to each moment in the first voltage segment and the first voltage value is less than the second threshold; the time period corresponding to the first voltage segment matches the time period corresponding to the current rising segment in the target current waveform; the target current waveform is determined based on the first current waveform and / or the second current waveform;

[0214] The third determination module can be used to determine the parasitic inductance of the branch to be measured through the second calculation formula;

[0215] The second calculation formula can be:

[0216]

[0217] Where L DUT is the parasitic inductance of the branch to be measured, is the current change rate of the second power switch device, and U DUT is the first voltage value.

[0218] In some possible implementation manners, when the first current waveform and the second current waveform match, the parasitic inductance measuring device may further include:

[0219] The sixth measurement module can be used to measure the second voltage waveform of the bus capacitor in the parasitic inductance test circuit during the target time period;

[0220] The fourth determination module can be used to determine the second voltage value of the second voltage segment in the second voltage waveform; the time period corresponding to the second voltage segment matches the time period corresponding to the current rising segment in the target current waveform; the difference between the voltage values corresponding to each moment in the second voltage segment and the second voltage value is less than the third threshold;

[0221] The fifth determination module can be used to determine the parasitic inductance of the bus capacitor through the third calculation formula;

[0222] The third calculation formula is:

[0223]

[0224] where L1 is the parasitic inductance of the bus capacitor, is the current change rate of the second power switch device, U C is the second voltage value, U DC is the first bus voltage.

[0225] In some possible implementation manners, the range of the bus voltage output by the DC voltage source can be between 10V and 50V.

[0226] Figure 10 is a schematic structural diagram of a parasitic inductance measurement device provided by an embodiment of the present application.

[0227] The parasitic inductance measurement device may include a processor 1001 and a memory 1002 storing computer program instructions.

[0228] Specifically, the above-mentioned processor 1001 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0229] The memory 1002 may include a mass storage for data or instructions. By way of example and not limitation, the memory 1002 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 1002 may include removable or non-removable (or fixed) media. Where appropriate, the memory 1002 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, the memory 1002 is a non-volatile solid-state memory.

[0230] The memory may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage media device, an optical storage media device, a flash memory device, an electrical, optical, or other physical / tangible memory storage device. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to an aspect of the present disclosure.

[0231] The processor 1001 reads and executes the computer program instructions stored in the memory 1002 to implement any of the parasitic inductance measurement methods in the above embodiments.

[0232] In one example, the data parasitic inductance measurement device may further include a communication interface 1003 and a bus 1010. Among them, as Figure 10 shown, the processor 1001, the memory 1002, and the communication interface 1003 are connected through the bus 1010 and complete communication with each other.

[0233] The communication interface 1003 is mainly used to implement communication between the modules, devices, units, and / or devices in the embodiments of the present application.

[0234] The bus 1010 includes hardware, software, or both, and couples the components of the parasitic inductance measurement device to each other. By way of example and not limitation, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a MicroChannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, the bus 1010 may include one or more buses. Although embodiments of the present application describe and illustrate specific buses, the present application contemplates any suitable bus or interconnect.

[0235] The parasitic inductance measurement device executes the parasitic inductance measurement method in the embodiments of the present application, thereby implementing Figure 1 the described parasitic inductance measurement method.

[0236] In addition, in combination with the parasitic inductance measurement method in the above embodiments, embodiments of the present application may provide a computer storage medium for implementation. Computer program instructions are stored on the computer storage medium; when the computer program instructions are executed by a processor, any one of the parasitic inductance measurement methods in the above embodiments is implemented.

[0237] Based on the parasitic inductance measurement method in the above embodiments, embodiments of the present application provide a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device is caused to execute the parasitic inductance measurement method provided in any one of the above embodiments of the present application.

[0238] It should be clear that the present application is not limited to the specific configurations and processes described above and illustrated in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and illustrated as examples. However, the method process of the present application is not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications, and additions, or change the order between steps after understanding the spirit of the present application.

[0239] The functional blocks shown in the above-described structural block diagrams can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, and so on. When implemented in software, the elements of the present application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium or transmitted over a transmission medium or communication link via a data signal carried in a carrier wave. A "machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical discs, hard disks, fiber optic media, radio frequency (RF) links, and so on. The code segment can be downloaded via a computer network such as the Internet, an intranet, and so on.

[0240] It should also be noted that the exemplary embodiments mentioned in the present application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps, that is, the steps can be executed in the order mentioned in the embodiments, can be different from the order in the embodiments, or several steps can be executed simultaneously.

[0241] Aspects of the present disclosure have been described above with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block in the flowcharts and / or block diagrams, and the combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the functions / actions specified in one or more blocks of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It can also be understood that each block in the block diagram and / or flowchart, and the combinations of blocks in the block diagram and / or flowchart, can also be implemented by dedicated hardware that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0242] As described above, this is only the specific implementation manner of the present application. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein. It should be understood that the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application.

Claims

1. A method for measuring parasitic inductance, characterized in that Applied to a parasitic inductance test circuit, the parasitic inductance test circuit comprising: A bus capacitor, a first power switch device, and a second power switch device connected in series in sequence through a DC busbar, and a load inductor connected in parallel with the first power switch device; the bus capacitor is connected in parallel with a DC voltage source, and the DC voltage source outputs a first bus voltage; The parasitic inductance measurement method comprising: By sending a double-pulse drive signal to the second power switch device, measuring a first current waveform during the turn-on transient process of the second power switch device under the first bus voltage, wherein, under the action of the double-pulse drive signal, the operating process of the second power switch device includes the turn-on transient process; Adjusting the gate drive parameters of the second power switch device, wherein the turn-on speed of the adjusted second power switch device is higher than that of the second power switch device before adjustment; By sending a double-pulse drive signal to the second power switch device, measuring a second current waveform during the turn-on transient process of the second power switch device under the first bus voltage; When the first current waveform and the second current waveform match, measuring the loop parasitic inductance in the parasitic inductance test circuit; Wherein, the matching of the first current waveform and the second current waveform means that: the time of the linearly rising process of the current in the first current waveform and the second current waveform is greater than a preset threshold.

2. The parasitic inductance measurement method according to claim 1, wherein The measuring the loop parasitic inductance in the parasitic inductance test circuit includes: Based on at least one of the first current waveform and the second current waveform, determining the current change rate of the second power switch device; Determining the loop parasitic inductance in the parasitic inductance test circuit through a first calculation formula; The first calculation formula is: Among them, is the rate of change of current of the second power switch device, L loop is the parasitic inductance of the loop, U DC is the first bus voltage, V S1 is the conduction voltage drop of the anti-parallel diode in the first power switch device, V S2 is the forward conduction voltage drop of the second power switch device.

3. The parasitic inductance measurement method according to claim 1, wherein, The measuring the loop parasitic inductance in the parasitic inductance test circuit when the first current waveform and the second current waveform match includes: Matching the first current linear transformation section in the first current waveform with the second current linear transformation section in the second current waveform; When the first current linear transformation section and the second current linear transformation section match, measuring the loop parasitic inductance in the parasitic inductance test circuit.

4. The parasitic inductance measurement method according to claim 1, wherein After measuring the second current waveform during the turn-on transient process of the second power switch device under the first bus voltage, the method further includes: When the first current waveform and the second current waveform do not match, adjusting a target parameter, the target parameter being: the bus voltage output by the DC voltage source; or, the gate drive parameters of the second power switch device; By sending a double-pulse drive signal to the second power switch device, measuring a third current waveform during the turn-on transient process of the second power switch device after the target parameter is adjusted; According to the third current waveform, determining whether to measure the loop parasitic inductance in the parasitic inductance test circuit.

5. The parasitic inductance measurement method according to claim 4, wherein, When the target parameter is the bus voltage output by the DC voltage source, in the case where the first current waveform and the second current waveform do not match, adjusting the target parameter includes: In the case where the first current waveform and the second current waveform do not match, adjusting the first bus voltage output by the DC voltage source to a second bus voltage; Determining whether to measure the loop parasitic inductance in the parasitic inductance test circuit according to the third current waveform includes: Adjusting the gate drive parameter of the second power switch device, wherein the turn-on speed of the adjusted second power switch device is higher than that of the second power switch device before adjustment; By sending a double-pulse drive signal to the second power switch device, measuring a fourth current waveform of the turn-on transient process of the second power switch device under the second bus voltage; When the third current waveform and the fourth current waveform match, measuring the loop parasitic inductance in the parasitic inductance test circuit.

6. The parasitic inductance measurement method according to claim 5, characterized in that In the case where the first current waveform and the second current waveform do not match, adjusting the first bus voltage output by the DC voltage source to a second bus voltage includes: In the case where the first current waveform and the second current waveform do not match, and the difference between the turn-on speed of the second power switch device and the upper limit value of the turn-on speed of the second power switch device is less than a first threshold, adjusting the first bus voltage output by the DC voltage source to the second bus voltage.

7. The parasitic inductance measurement method according to claim 1, wherein When the first current waveform and the second current waveform match, the method further includes: Measuring a first voltage waveform across both ends of a branch to be measured in the parasitic inductance test circuit during a target time period, where the target time period is the time period corresponding to the turn-on transient process of the second power switch device under the first bus voltage; the branch to be measured does not include the bus capacitor; Determining a first voltage value of a first voltage segment in the first voltage waveform; the difference between the voltage values corresponding to each moment in the first voltage segment and the first voltage value is less than a second threshold; the time period corresponding to the first voltage segment matches the time period corresponding to the current rising segment in the target current waveform; the target current waveform is determined based on the first current waveform and / or the second current waveform; Determining the parasitic inductance of the branch to be measured through a second calculation formula; The second calculation formula is: Among them, L DUT is the parasitic inductance of the branch to be measured, is the current change rate of the second power switch device, and U DUT is the first voltage value.

8. The parasitic inductance measurement method according to claim 7, wherein When the first current waveform and the second current waveform match, the method further includes: Measuring a second voltage waveform of the bus capacitor in the parasitic inductance test circuit during the target time period; Determining a second voltage value of a second voltage segment in the second voltage waveform; the time period corresponding to the second voltage segment matches the time period corresponding to the current rising segment in the target current waveform; the difference between the voltage values corresponding to each moment in the second voltage segment and the second voltage value is less than a third threshold; Determining the parasitic inductance of the bus capacitor through a third calculation formula; The third calculation formula is: Among them, L1 is the parasitic inductance of the bus capacitor, is the rate of change of current of the second power switch device, U C is the second voltage value, U DC is the first bus voltage.

9. The parasitic inductance measurement method according to any one of claims 1-8, characterized in that The bus voltage output by the DC voltage source ranges from 10V to 50V.

10. A parasitic inductance measurement device, characterized in that, Applied to a parasitic inductance test circuit, the parasitic inductance test circuit includes: A bus capacitor, a first power switch device, and a second power switch device connected in series in sequence through a DC busbar, and a load inductor connected in parallel with the first power switch device; the bus capacitor is connected in parallel with a DC voltage source, and the DC voltage source outputs a first bus voltage; The parasitic inductance measuring device includes: A first measurement module for measuring a first current waveform of the turn-on transient process of the second power switch device under the first bus voltage by sending a double-pulse drive signal to the second power switch device, wherein, under the action of the double-pulse drive signal, the working process of the second power switch device includes the turn-on transient process; A first adjustment module for adjusting the gate drive parameters of the second power switch device, wherein the turn-on speed of the adjusted second power switch device is higher than that of the second power switch device before adjustment; A second measurement module for measuring a second current waveform during the turn-on transient process of the second power switch device under the first bus voltage by sending a double-pulse drive signal to the second power switch device; A third measurement module for measuring the loop parasitic inductance in the parasitic inductance test circuit when the first current waveform and the second current waveform match; Wherein, the matching of the first current waveform and the second current waveform means that the time of the linear rising process of the current in the first current waveform and the second current waveform is greater than a preset threshold.

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