Test signal generation circuit, test chip and test system

Abstract

The present disclosure provides a test signal generation circuit, a test chip and a test system, which adds an optimization circuit (i.e. a test signal generation circuit) of a to-be-tested signal waveform on the basis of an original circuit, the test signal generation circuit performs filtering and optimization processing on the to-be-tested signal to generate an excitation signal, and the excitation signal is used to detect the accuracy of the flip threshold of the test chip. When the to-be-tested signal waveform oscillates, it can be ensured that the output waveform detected by the back-end functional test machine connected to the test chip is always in a low state. However, when the to-be-tested signal is a stable waveform after complete flipping, the functional test machine can timely detect the high level after the excitation signal flips. Thus, the present disclosure can improve the premature false triggering of the original test system and improve the test accuracy and precision of the test signal generation circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor integrated circuit technology, specifically to a test signal generation circuit, a test chip, and a test system. Background Technology

[0002] Many threshold-flipping chips, such as logic chips, undergo functional testing (FT, primarily used in the final stage of surface-mount semiconductor device manufacturing, involving fully automated testing of electrical parameters, classification and storage, laser marking, marking detection, and dimensional inspection) to determine the accuracy of their electrical performance. When the input voltage approaches VIH / VIL (VIL being the maximum input voltage that can be interpreted as logic "0," and VIH being the minimum input voltage that can be interpreted as logic "1"), the output may exhibit incomplete flipping and oscillation. When using FT to test the VIH / VIL parameters, output oscillation (glitch) can cause the test system to prematurely trigger, resulting in inaccurate test results and reduced precision, thus severely impacting product performance.

[0003] The original test plan, such as Figure 1a As shown, the test chip generates a test signal (DUT) based on the input signal Vin and directly connects it to the voltage detection interface of the functional test equipment. Taking VIH as an example, the waveform of the chip's output voltage Vo changing with the input voltage Vin is as follows. Figure 1b As shown, when the input voltage Vin approaches VIH, the output voltage Vo will oscillate for a period of time. Detecting such a waveform will cause the test system to trigger prematurely, resulting in a large error in the test results.

[0004] One existing solution involves continuously sampling multiple output voltage points. If all the sampled points are the flipped voltage values, the input voltage is considered to be at the VIH / VIL point. However, this method has a drawback: if the high-level duration of the oscillation voltage is long, and if the sampled points happen to all be at the high level during oscillation, the test results will be inaccurate. Another solution involves determining VIH / VIL by testing the average value of the output voltage. However, this method has a drawback: as the input voltage approaches the VIH / VIL value, the average value of the output oscillation voltage gets closer to the flipped voltage value. Therefore, this method can also lead to premature triggering and inaccurate test results, resulting in errors. Therefore, it is not directly used in I / O circuits. Summary of the Invention

[0005] To address the aforementioned technical issues, this disclosure provides a test signal generation circuit, a test chip, and a test system, which can improve the situation of premature triggering in the original test system and enhance test accuracy and precision.

[0006] On one hand, this disclosure provides a test signal generation circuit for providing excitation signals to a test chip, wherein the test signal generation circuit includes:

[0007] The control unit is configured to generate a first level signal based on the signal to be measured and a preset reference signal, and to output a selection signal under the control of a timing control signal. The selection signal is one of the aforementioned first level signal and the inverted signal of the first level signal.

[0008] A logic unit is used to receive a reset signal and, in response to the reset signal, change the state detection logic of a first level signal or the inverted signal of the first level signal to generate a second level signal.

[0009] The shaping unit is used to process the aforementioned second-level signal to generate a third-level signal;

[0010] The output unit is used to adjust its own circuit state according to the aforementioned third-level signal and generate an excitation signal.

[0011] This excitation signal is used to detect the accuracy of the flip threshold of the test chip.

[0012] Preferably, the aforementioned control unit includes:

[0013] The comparator has the aforementioned test signal connected to its non-inverting input, the aforementioned reference signal connected to its inverting input, the operating voltage connected to its positive power supply, grounded its negative power supply, and provides the aforementioned first level signal at its output.

[0014] The selection module is connected between the output of the comparator and the logic unit, and is controlled by the timing control signal to output the aforementioned selection signal.

[0015] Preferably, the aforementioned timing control signals include a first control signal and a second control signal that are inverses of each other, and the aforementioned selection module includes:

[0016] A first switch and a first inverter are connected in series between the output of the comparator and the input of the logic unit, and are controlled by the first control signal to provide the inverted signal of the aforementioned first level signal through the first inverter;

[0017] The second switch has its first end connected to the output of the comparator along with the first end of the first switch. The second end of the second switch is connected to the input of the logic unit along with the output of the first inverter. The second switch is controlled by the second control signal to provide the first level signal.

[0018] Preferably, the aforementioned logic unit includes:

[0019] The first flip-flop is used to detect the falling edge of the aforementioned selection signal and, in response to the aforementioned reset signal, outputs a first pulse signal by dividing the frequency by two.

[0020] The second trigger is used to detect the rising edge of the aforementioned selection signal and, in response to the aforementioned reset signal, outputs a second pulse signal by dividing the frequency by two.

[0021] The third flip-flop has a set terminal connected to a first pulse signal, a clock terminal connected to a second pulse signal, a reset terminal connected to the aforementioned reset signal, and an output terminal providing a third pulse signal.

[0022] A NOT gate, which is connected to the output of the aforementioned third flip-flop, outputs the inverted signal of the third pulse signal;

[0023] The AND gate has its inputs connected to the output of the NOT gate and the output of the aforementioned selection module, respectively, and its output provides the aforementioned second-level signal.

[0024] Preferably, the aforementioned logic unit further includes:

[0025] A reset signal generation module is provided. Based on the detection of the transition of the input signal, the reset signal generation module is triggered to generate the aforementioned reset signal and synchronously outputs the reset signal to the first flip-flop, the second flip-flop, and the third flip-flop respectively.

[0026] Preferably, the aforementioned shaping unit includes:

[0027] A high-pass filter includes a first resistor and a first capacitor connected in series between the output of a logic AND gate and ground, and provides a second-level signal that filters out high-frequency components through the connection node of the first resistor and the first capacitor.

[0028] An operational amplifier is provided with the second-level signal (filtered out for high-frequency components) connected to its positive input terminal, and its output terminal connected to ground via a third resistor and a second resistor connected in series. The negative input terminal is connected to the connection node of the third resistor and the second resistor. The positive power supply terminal is connected to the aforementioned operating voltage, the negative power supply terminal is grounded, and the output terminal provides the aforementioned third-level signal.

[0029] Preferably, the aforementioned output unit includes:

[0030] A first switching transistor and a fifth resistor are connected in series between the output terminal of the aforementioned selection module and ground. The control terminal of the first switching transistor is connected to the output terminal of the aforementioned operational amplifier through a fourth resistor.

[0031] The sixth resistor has its first end connected to the connection node between the first switch and the fifth resistor, and its second end serves as the output terminal of the test signal generation circuit to provide the aforementioned excitation signal.

[0032] On the other hand, this disclosure also provides a test chip, wherein the test chip integrates the aforementioned test signal generation circuit, the test chip generates a test signal based on the input signal, and the test signal generation circuit filters and shapes the aforementioned test signal to output an excitation signal.

[0033] This excitation signal is used to detect the accuracy of the flip threshold of the aforementioned test chip.

[0034] On the other hand, this disclosure also provides a testing system, which includes:

[0035] As described above, the test chip generates an excitation signal based on the input signal, and the excitation signal is used to detect the accuracy of the test chip's flip threshold.

[0036] The functional testing machine has a voltage detection interface adapted to the output port of the aforementioned test chip. Based on the excitation signal provided by the aforementioned test chip, the functional testing machine performs accuracy detection on the flip threshold of the test chip and outputs the detection result.

[0037] The beneficial effects of this disclosure are as follows: This disclosure provides a test signal generation circuit, a test chip, and a test system. The test signal generation circuit utilizes a control unit to generate a first-level signal based on the signal under test and a preset reference signal, and is controlled by a timing control signal to output a selection signal, which is one of the aforementioned first-level signal and its inverted signal. A logic unit then receives a reset signal and, in response to the reset signal, changes the state detection logic of the first-level signal or its inverted signal to generate a second-level signal. A shaping unit then processes the second-level signal to generate a third-level signal. Finally, an output unit adjusts its own circuit state based on the third-level signal to generate an excitation signal, which is used for the accuracy detection of the test chip's flip threshold. This application adds an optimization circuit (i.e., a test signal generation circuit) to the existing circuit to optimize the waveform of the signal under test. The waveform of the signal under test is filtered and optimized to generate an excitation signal. This excitation signal is used to detect the accuracy of the flip-threshold of the test chip. When the waveform of the signal under test oscillates, it can ensure that the output waveform detected by the back-end functional test equipment is always in a low-level state. However, when the signal under test is a steady-state waveform after complete flip-through, the functional test equipment can detect the high level after flip-through in time. This improves the situation of premature false triggering in the original test system and improves the test accuracy and precision of the test chip. Attached Figure Description

[0038] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings.

[0039] Figure 1a A schematic block diagram of a testing scheme in the prior art is shown;

[0040] Figure 1b Show Figure 1a The diagram shows the working waveforms of the test scheme.

[0041] Figure 2 This diagram illustrates a test chip in a test system provided by an embodiment of the present disclosure;

[0042] Figure 3 Show Figure 2 A schematic block diagram of the test signal generation circuit in the test chip shown.

[0043] Figure 4 Show Figure 2 The diagram shows a signal waveform of the test system in one embodiment.

[0044] Figure 5 Show Figure 2 The diagram shows a signal waveform of the test system in another implementation. Detailed Implementation

[0045] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the contents of this disclosure.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0047] Traditional test circuits cannot filter out the oscillation glitches of the DUT signal, which can cause errors in the threshold detection of the output by the functional test equipment when the input voltage is close to VIH / VIL, resulting in output jumps and premature triggering, inaccurate test results, and thus seriously affecting product performance.

[0048] The present disclosure will now be described in detail with reference to the accompanying drawings.

[0049] Figure 2 This diagram illustrates a test chip in a test system provided by an embodiment of the present disclosure. Figure 3Show Figure 2 The diagram shows a schematic block diagram of the test signal generation circuit in the test chip.

[0050] refer to Figure 2 and Figure 3 This disclosure provides a test chip 10, which integrates a test signal generation circuit 100. The test chip 10 generates a test signal (DUT) based on an input signal Vin. This disclosure adds an optimization circuit (i.e., the test signal generation circuit 100) to the existing circuit to filter and optimize the waveform of the DUT, generating an excitation signal V4. This excitation signal V4 is used to detect the accuracy of the flip threshold of the test chip 10, thereby improving the premature triggering of the original test system and enhancing the test accuracy and precision of the test chip 10. The test signal generation circuit 100 includes a control unit 110, a logic unit 120, a shaping unit 130, and an output unit 140. Since the test signal generation circuit 100 is a functional circuit added to the existing test system, the circuitry for generating the DUT based on the input signal Vin can be understood by those skilled in the art in conjunction with existing disclosed technical solutions, and will not be elaborated upon here.

[0051] In this embodiment, the control unit 110 is used to generate a first level signal a based on the signal under test (DUT) and a preset reference signal ref, and is controlled by timing control signals (S1 and S2) to output a selection signal V1 (the selection signal V1 is one of the first level signal a and the inverted signal of the first level signal a, the same below); the logic unit 120 is used to receive a reset signal Rest, and in response to the reset signal Rest, change the state detection logic of the first level signal a or the inverted signal of the first level signal a, and generate a second level signal V2; the shaping unit 130 is used to perform signal processing on the aforementioned second level signal V2 to generate a third level signal V3; the output unit 140 is used to adjust its own circuit state based on the third level signal V3 to generate an excitation signal V4, and the excitation signal V4 is used for the accuracy detection of the flip threshold of the test chip 10, wherein the flip threshold is VIH / VIL (VIL is the maximum input voltage that can be interpreted as logic "0", and VIH is the minimum input voltage that can be interpreted as logic "1").

[0052] Further, refer to Figure 3In this embodiment, the aforementioned control unit 110 includes a comparator 111 and a selection module 112. The non-inverting input of the comparator 111 is connected to the signal under test (DUT), the inverting input is connected to the aforementioned reference signal (ref), the positive power supply is connected to the operating voltage VCC, the negative power supply is grounded, and the output provides the aforementioned first level signal a. The selection module 112 is connected between the output of the comparator 111 and the logic unit 120, and is controlled by timing control signals (S1 and S2) to output one of the aforementioned first level signal a and the inverted signal of the first level signal a.

[0053] Further, in this embodiment, the aforementioned timing control signals (S1 and S2) include a first control signal S1 and a second control signal S2 that are inverses of each other. The aforementioned selection module 112 includes a first switch K1, a first inverter 1121, and a second switch K2. The first switch K1 and the first inverter 1121 are connected in series between the output of the comparator 111 and the input of the logic unit 120, and are controlled by the first control signal S1 to provide an inverted signal of the first level signal a through the first inverter 1121. The first end of the second switch K2 is connected to the output of the comparator 111 along with the first end of the first switch K1. The second end of the second switch K2 is connected to the input of the logic unit 120 along with the output of the first inverter 1121. The second switch K2 is controlled by the aforementioned second control signal S2 to provide the aforementioned first level signal a.

[0054] Further, in this embodiment, the aforementioned logic unit 120 includes: a first flip-flop 121, a second flip-flop 122, a third flip-flop 123, a NOT gate 125, and an AND gate 126. The first flip-flop 121 is a falling-edge divide-by-two flip-flop, used to detect the falling edge of the aforementioned selection signal V1, and in response to the aforementioned reset signal Rest, outputs a first pulse signal b through a frequency divider. The second flip-flop 122 is a rising-edge divide-by-two flip-flop, used to detect the rising edge of the aforementioned selection signal V1, and in response to the aforementioned reset signal Rest, outputs a second pulse signal b through a frequency divider. The pulse signal c; the third flip-flop 123 is, for example, an RS flip-flop, with the set terminal of the third flip-flop 123 connected to the first pulse signal b, the clock terminal connected to the second pulse signal c, the reset terminal connected to the aforementioned reset signal Rest, and the output terminal providing the third pulse signal d; the logic NOT gate 125 is an inverter structure, which is connected to the output terminal of the aforementioned third flip-flop 123 and outputs the inverted signal e of the third pulse signal d; the input terminal of the logic AND gate 126 is connected to the output terminal of the logic NOT gate 125 and the output terminal of the aforementioned selection module 112 respectively, and the output terminal of the logic AND gate 126 provides the aforementioned second level signal V2.

[0055] Furthermore, in this embodiment, the aforementioned logic unit 120 further includes a reset signal generation module 124, wherein the reset signal generation module 124 triggers the generation of the aforementioned reset signal Rest based on the detection of the transition of the input signal Vin, and synchronously outputs the reset signal Rest to the first flip-flop 121, the second flip-flop 122 and the third flip-flop 123 respectively.

[0056] Further, in this embodiment, the aforementioned shaping unit 130 includes: a high-pass filter and an operational amplifier 131 and their associated circuitry. The high-pass filter includes a first resistor R1 and a first capacitor C1 connected in series between the output of the AND gate 126 and ground. The connection node of the first resistor R1 and the first capacitor C1 provides a second-level signal V2 that filters out high-frequency components. The positive input terminal of the operational amplifier 131 is connected to the second-level signal V2 that filters out high-frequency components. The output terminal is connected to ground through a third resistor R3 and a second resistor R2 connected in series. The negative input terminal is connected to the connection node of the third resistor R3 and the second resistor R2. The positive power supply terminal is connected to the aforementioned operating voltage VCC, the negative power supply terminal is grounded, and the output terminal provides the aforementioned third-level signal V3.

[0057] Further, in this embodiment, the aforementioned output unit 140 includes: a first switch Q1, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The first switch Q1 and the fifth resistor R5 are connected in series between the output terminal of the aforementioned selection module 112 and ground. The control terminal of the first switch Q1 is connected to the output terminal of the aforementioned operational amplifier 131 through the fourth resistor R4. The first end of the sixth resistor R6 is connected to the connection node of the aforementioned first switch Q1 and the fifth resistor R5, and the second end serves as the output terminal of the test signal generation circuit 100 to provide the aforementioned excitation signal V4.

[0058] Furthermore, in this embodiment, in order to improve the testing accuracy and precision of the test chip in high-frequency circuits, the aforementioned comparator 111 is a high-speed comparator, the operational amplifier 131 is a high-speed operational amplifier, and the aforementioned first switching transistor Q1 is an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET, abbreviated as NMOS transistor).

[0059] Of course, this disclosure is not limited thereto. In other alternative embodiments, the aforementioned first switch Q1 may also be a PMOS transistor. Accordingly, the circuit of the output unit 140 requires adaptive replacement of components and adjustment of structure.

[0060] In this embodiment, the test signal generation circuit 100 is added to the original circuit. It is used to filter and optimize the waveform of the output voltage (DUT) when the input voltage Vin is close to VIH / VIL, and generate an excitation signal V4. When the DUT oscillates, it ensures that the waveform of the excitation signal V4 detected by the functional test equipment 20 at the back end of the test chip 10 is always at a low level. However, when the DUT is a fully flipped steady-state waveform, the corresponding excitation signal V4 is a fully flipped steady-state waveform. At this time, the functional test equipment 20 can detect the high level after the flip in time, thereby improving the situation of premature false triggering of the original test system and improving the test accuracy and precision.

[0061] Figure 4 Show Figure 2 The diagram shows a signal waveform of the test system in one embodiment. Figure 5 Show Figure 2 The diagram shows a signal waveform of the test system in another implementation.

[0062] Combination Figures 3 to 5 The specific working principle of the test signal generation circuit 100 is as follows:

[0063] For example, when testing the input voltage Vin near VIH, the reference signal ref is set to 0.7Vo; when testing the input voltage Vin near VIL, the reference signal ref is set to 0.3Vo, where Vo is the output detection threshold voltage.

[0064] 1. When the signal under test (DUT) is an incompletely flipped oscillating waveform, it first passes through a high-speed comparator 111 to convert the irregular oscillation waveform of the DUT into a first-level signal a (square wave signal), while also filtering out waveforms with low oscillation amplitude. When testing VIH, the second control signal S2 closes the second switch K2; when testing VIL, the first control signal S1 closes the first switch K1, inverting the signal to obtain the selection signal V1. The resulting square wave signal (i.e., the selection signal V1) is divided into two paths in the logic unit 120 for signal processing. One path is triggered by the falling edge of the first flip-flop 121 and divided by two to obtain the first pulse signal b. The other path is triggered by the rising edge of the second flip-flop 122 and divided by two to obtain the second pulse signal c. Of the two signals, the first pulse signal b serves as the data input, and the second pulse signal c serves as the clock signal, valid on the falling edge, passing through the third flip-flop 123 to obtain the third pulse signal d. Each change in the input voltage Vi... The value of n triggers a reset signal Rest to the test signal generation circuit 100 in the system, re-triggering it. The third pulse signal d is then inverted by the NOT gate 125, and the resulting signal e is logically ANDed with the selection signal V1 output by the selection module 112. The resulting second-level signal V2 only contains the first high-level square wave output by the comparator 111. This second-level signal V2 is filtered by the RC filter in the high-frequency filter, and then filtered out by the high-speed operational amplifier 131. The first pulse pps is then provided to the control terminal of the NMOS transistor Q1 connected to the next stage. At this time, the NMOS transistor Q1 is not turned on, and the functional test instrument 20 always detects a low level with logic "0", which does not trigger the VIH / VIL test program interruption. Its waveform is as follows. Figure 4 As shown.

[0065] 2. When the signal under test (DUT) has a fully inverted waveform, similarly, after processing by the test signal generation circuit 100, the NMOS transistor Q1 turns on at the instant of inversion. The functional test instrument 20 detects a high level of logic "1", triggering the VIH / VIL test program interrupt, thereby obtaining the VIH / VIL value, the waveform of which is as follows: Figure 5 As shown.

[0066] Therefore, the test signal generation circuit 100 provided in this embodiment can improve the situation of premature triggering in the original test system and improve the test accuracy and precision of the test chip 10.

[0067] On the other hand, this embodiment of the present disclosure also provides a test chip 10, wherein the test chip 10 integrates the aforementioned test signal generation circuit 100. The test chip 10 generates a test signal DUT based on the input signal Vin. The test signal generation circuit 100 filters and shapes the aforementioned test signal DUT and outputs an excitation signal V4. The excitation signal V4 is used for the accuracy detection of the flip threshold (VIH / VIL) of the aforementioned test chip 10, such as... Figure 2 As shown.

[0068] On the other hand, embodiments of this disclosure also provide a testing system, such as Figure 2 As shown. The testing system includes:

[0069] The aforementioned test chip 10 generates an excitation signal V4 based on the input signal Vin. The excitation signal V4 is used for the accuracy detection of the flip threshold (VIH / VIL) of the test chip 10.

[0070] The functional test equipment 20 has a voltage detection interface adapted to the output port of the aforementioned test chip 10. The functional test equipment 20 performs accuracy detection on the flip threshold (VIH / VIL) of the test chip 10 according to the excitation signal V4 provided by the aforementioned test chip 10, and outputs the detection result.

[0071] In summary, the test signal generation circuit 100, the test chip 10 with the test signal generation circuit 100, and the test system with the test chip 10 provided in this embodiment of the present disclosure add an optimization circuit (i.e., test signal generation circuit 100) to the waveform of the signal under test (DUT) on the basis of the original circuit. The DUT waveform is filtered and optimized to generate an excitation signal V4. The excitation signal V4 is used to detect the accuracy of the flip threshold (VIH / VIL) of the test chip 10. When the waveform of the DUT oscillates, it can ensure that the output waveform detected by the back-end functional test equipment 20 is always in a low-level state. However, when the DUT is a steady-state waveform after complete flipping, the functional test equipment 20 can detect the high level after flipping in time. This improves the situation of premature false triggering in the original test system and improves the test accuracy and precision of the test chip 10.

[0072] It should be noted that, in the description of this disclosure, the terms "upper," "lower," "inner," etc., which indicate orientation or positional relationship, are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0073] Furthermore, throughout this document, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0074] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this disclosure and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of this disclosure.

Claims

1. A test signal generation circuit for providing an excitation signal to a test chip, wherein, The test signal generation circuit includes: The control unit is configured to generate a first level signal based on the signal to be measured and a preset reference signal, and to output a selection signal under the control of a timing control signal, wherein the selection signal is one of the first level signal and its inverted signal. A logic unit is configured to receive a reset signal and, in response to the reset signal, change the logic control of the state detection of the first level signal or the inverted signal of the first level signal to generate a second level signal. The shaping unit is used to process the second level signal to generate a third level signal; The output unit is used to adjust its own circuit state according to the third level signal to generate the excitation signal. The excitation signal is used for the accuracy detection of the flip threshold of the test chip. The logic unit includes: The first trigger is used to detect the falling edge of the selection signal and, in response to the reset signal, outputs a first pulse signal by dividing the frequency by two. The second trigger is used to detect the rising edge of the selection signal and, in response to the reset signal, outputs a second pulse signal by dividing the frequency by two. The third flip-flop has a set terminal connected to the first pulse signal, a clock terminal connected to the second pulse signal, a reset terminal connected to the reset signal, and an output terminal providing the third pulse signal. A NOT gate is connected to the output of the third flip-flop to output the inverted signal of the third pulse signal; The AND gate has its inputs connected to the output of the NOT gate and the selection signal, respectively, and its output provides the second level signal.

2. The test signal generation circuit according to claim 1, wherein, The control unit includes: The comparator has the non-inverting input terminal connected to the signal to be measured, the inverting input terminal connected to the reference signal, the positive power supply terminal connected to the operating voltage, the negative power supply terminal grounded, and the output terminal providing the first level signal. The selection module is connected between the output of the comparator and the logic unit, and outputs the selection signal under the control of the timing control signal.

3. The test signal generation circuit according to claim 2, wherein, The timing control signals include a first control signal and a second control signal that are inverses of each other, and the selection module includes: A first switch and a first inverter are connected in series between the output of the comparator and the input of the logic unit, and are controlled by the first control signal to provide an inverted signal of the first level signal through the first inverter. The second switch has its first end connected to the output of the comparator along with the first end of the first switch, and its second end connected to the input of the logic unit along with the output of the first inverter. The second switch is controlled by the second control signal to provide the first level signal.

4. The test signal generation circuit according to claim 3, wherein, The logic unit further includes: A reset signal generation module is provided, which generates a reset signal based on the detection of a transition in the input signal, and synchronously outputs the reset signal to the first flip-flop, the second flip-flop, and the third flip-flop respectively.

5. The test signal generation circuit according to claim 4, wherein, The shaping unit includes: A high-pass filter includes a first resistor and a first capacitor connected in series between the output of the AND gate and ground, and provides a second level signal that filters out high-frequency components through the connection node of the first resistor and the first capacitor; An operational amplifier is provided, wherein the positive input terminal is connected to the second level signal after filtering out high-frequency components, the output terminal is connected to ground through a third resistor and a second resistor connected in series, the negative input terminal is connected to the connection node of the third resistor and the second resistor, the positive power supply terminal is connected to the operating voltage, the negative power supply terminal is grounded, and the output terminal provides the third level signal.

6. The test signal generation circuit according to claim 5, wherein, The output unit includes: A first switching transistor and a fifth resistor are connected in series between the output terminal of the selection module and ground. The control terminal of the first switching transistor is connected to the output terminal of the operational amplifier through a fourth resistor. The sixth resistor has its first end connected to the connection node between the first switch and the fifth resistor, and its second end serves as the output terminal of the test signal generation circuit to provide the excitation signal.

7. A test chip, wherein, The test chip integrates a test signal generation circuit as described in any one of claims 1 to 6. The test chip generates a test signal based on the input signal, and the test signal generation circuit filters and shapes the test signal to output an excitation signal. The excitation signal is used to detect the accuracy of the flip threshold of the test chip.

8. A testing system, wherein, include: The test chip as described in claim 7, wherein the test chip generates an excitation signal based on an input signal, and the excitation signal is used for the accuracy detection of the test chip's flip threshold; The functional testing machine has a voltage detection interface adapted to the output port of the test chip. The functional testing machine performs accuracy detection on the flip threshold of the test chip according to the excitation signal provided by the test chip and outputs the detection result.

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