Reference voltage generation circuit

Abstract

An embodiment of the present disclosure provides a reference voltage generating circuit, which includes: a bias circuit, first and second transistors, first and second feedback circuits, first and second sampling circuits, and first and second current amplifying circuits. The bias circuit generates first and second bias voltages at first and second nodes respectively according to the bias current. The control electrode of the first transistor is coupled to the first node. The first electrode of the first transistor is coupled to the reference voltage output terminal and the first electrode of the second transistor. The control electrode of the second transistor is coupled to the second node. The first sampling circuit samples a first current flowing through the first transistor. The second sampling circuit samples a second current flowing through the second transistor. The first feedback circuit generates a first feedback current according to the first current. The second feedback circuit generates a second feedback current according to the second current. The first current amplifying circuit amplifies the first current into a first amplified current. The second current amplifying circuit amplifies the second current into a second amplified current.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a reference voltage generating circuit. Background Art

[0002] Reference voltage generating circuits are often used in various integrated circuits to provide reference voltages. The reference voltage needs to remain stable as a comparison benchmark in the integrated circuit. However, when the reference voltage generating circuit is loaded, the reference voltage generating circuit may need to provide a pull current to the load, or may need to absorb a sink current from the load. Therefore, in some application scenarios, it is hoped that the reference voltage generating circuit has a push-pull output capability. Furthermore, it is hoped that the reference voltage output by the reference voltage generating circuit is also stable when the load current increases. Summary of the invention

[0003] Embodiments described herein provide a reference voltage generating circuit.

[0004] According to a first aspect of the present disclosure, a reference voltage generating circuit is provided. The reference voltage generating circuit includes: a bias circuit, a first transistor, a second transistor, a first feedback circuit, a second feedback circuit, a first sampling circuit, a second sampling circuit, a first current amplifying circuit, and a second current amplifying circuit. The bias circuit is configured to generate a first bias voltage at a first node and a second bias voltage at a second node according to a bias current from a bias current source. The control electrode of the first transistor is coupled to the first node. The first electrode of the first transistor is coupled to a reference voltage output terminal. The second electrode of the first transistor is coupled to a third node. The control electrode of the second transistor is coupled to the second node. The first electrode of the second transistor is coupled to the reference voltage output terminal. The second electrode of the second transistor is coupled to a fourth node. The first sampling circuit is configured to sample a first current flowing through the first transistor via the third node. The second sampling circuit is configured to sample a second current flowing through the second transistor via the fourth node. The first feedback circuit is configured to generate a first feedback current according to the first current. The first feedback current is used to adjust the first bias voltage to stabilize the reference voltage output from the reference voltage output terminal. The second feedback circuit is configured to generate a second feedback current according to the second current. The second feedback current is used to adjust the second bias voltage to stabilize the reference voltage. The first current amplification circuit is configured to amplify the first current into a first amplified current. The second current amplification circuit is configured to amplify the second current into a second amplified current. Wherein, when the reference voltage generation circuit provides a pull current to the load, the first transistor is turned on, the second transistor is turned off, and the pull current includes the first current and the first amplified current. When the reference voltage generation circuit absorbs a sink current from the load, the first transistor is turned off, the second transistor is turned on, and the sink current includes the second current and the second amplified current.

[0005] In some embodiments of the present disclosure, the reference voltage generating circuit further includes: a first compensation circuit and a second compensation circuit. The first compensation circuit is configured to: generate a first compensation current to compensate for the increment of the first current when the source current is greater than or equal to the first current threshold. The second compensation circuit is configured to: generate a second compensation current to compensate for the increment of the second current when the sink current is greater than or equal to the second current threshold.

[0006] In some embodiments of the present disclosure, the bias circuit includes: a first resistor, a second resistor, a third resistor, a third transistor, and a fourth transistor. The first end of the first resistor is coupled to the bias current source and the control electrode of the third transistor. The second end of the first resistor is coupled to the first node and the first end of the second resistor. The second end of the second resistor is coupled to the second electrode of the third transistor. The first electrode of the third transistor is coupled to the first electrode of the fourth transistor. The control electrode of the fourth transistor is coupled to the second electrode of the fourth transistor and the second node. The first end of the third resistor is coupled to the second node. The second end of the third resistor is coupled to the second voltage terminal.

[0007] In some embodiments of the present disclosure, the first feedback circuit includes: a fifth transistor, and a fourth resistor. The control electrode of the fifth transistor is coupled to the third node. The first electrode of the fifth transistor is coupled to the first end of the fourth resistor. The second electrode of the fifth transistor is coupled to the bias current source. The second end of the fourth resistor is coupled to the first voltage end.

[0008] In some embodiments of the present disclosure, the first sampling circuit includes: a sixth transistor, and a fifth resistor, wherein the control electrode of the sixth transistor is coupled to the second electrode and the third node of the sixth transistor, the first electrode of the sixth transistor is coupled to the first end of the fifth resistor, and the second end of the fifth resistor is coupled to the first voltage end.

[0009] In some embodiments of the present disclosure, the first current amplifying circuit includes: a seventh transistor, wherein a control electrode of the seventh transistor is coupled to the third node, a first electrode of the seventh transistor is coupled to the first voltage terminal, and a second electrode of the seventh transistor is coupled to the reference voltage output terminal.

[0010] In some embodiments of the present disclosure, the second feedback circuit includes: an eighth transistor, and a sixth resistor. The control electrode of the eighth transistor is coupled to the fourth node. The first electrode of the eighth transistor is coupled to the first end of the sixth resistor. The second electrode of the eighth transistor is coupled to the second node. The second end of the sixth resistor is coupled to the second voltage end.

[0011] In some embodiments of the present disclosure, the second sampling circuit includes: a ninth transistor, and a seventh resistor, wherein the control electrode of the ninth transistor is coupled to the second electrode and the fourth node of the ninth transistor, the first electrode of the ninth transistor is coupled to the first end of the seventh resistor, and the second end of the seventh resistor is coupled to the second voltage end.

[0012] In some embodiments of the present disclosure, the second current amplifying circuit includes: a tenth transistor, wherein a control electrode of the tenth transistor is coupled to the fourth node, a first electrode of the tenth transistor is coupled to the second voltage terminal, and a second electrode of the tenth transistor is coupled to the reference voltage output terminal.

[0013] In some embodiments of the present disclosure, the first compensation circuit includes: an eleventh transistor. The second compensation circuit includes: a twelfth transistor. The control electrode of the eleventh transistor is coupled to the third node. The first electrode of the eleventh transistor is coupled to the first voltage terminal. The second electrode of the eleventh transistor is coupled to the reference voltage output terminal. The control electrode of the twelfth transistor is coupled to the fourth node. The first electrode of the twelfth transistor is coupled to the second voltage terminal. The second electrode of the twelfth transistor is coupled to the reference voltage output terminal. The threshold voltage of the eleventh transistor and the threshold voltage of the twelfth transistor are higher than the threshold voltages of other transistors in the reference voltage generating circuit.

[0014] According to a second aspect of the present disclosure, a reference voltage generating circuit is provided. The reference voltage generating circuit includes: a first transistor to a twelfth transistor, and a first resistor to a seventh resistor. The control electrode of the first transistor is coupled to the first node. The first electrode of the first transistor is coupled to the reference voltage output terminal. The second electrode of the first transistor is coupled to the third node. The control electrode of the second transistor is coupled to the second node. The first electrode of the second transistor is coupled to the reference voltage output terminal. The second electrode of the second transistor is coupled to the fourth node. The first end of the first resistor is coupled to the bias current source and the control electrode of the third transistor. The second end of the first resistor is coupled to the first node and the first end of the second resistor. The second end of the second resistor is coupled to the second electrode of the third transistor. The first electrode of the third transistor is coupled to the first electrode of the fourth transistor. The control electrode of the fourth transistor is coupled to the second electrode and the second node of the fourth transistor. The first end of the third resistor is coupled to the second node. The second end of the third resistor is coupled to the second voltage terminal. The control electrode of the fifth transistor is coupled to the third node. The first electrode of the fifth transistor is coupled to the first end of the fourth resistor. The second electrode of the fifth transistor is coupled to the bias current source. The second end of the fourth resistor is coupled to the first voltage terminal. The control electrode of the sixth transistor is coupled to the second electrode of the sixth transistor and the third node. The first electrode of the sixth transistor is coupled to the first end of the fifth resistor. The second end of the fifth resistor is coupled to the first voltage end. The control electrode of the seventh transistor is coupled to the third node. The first electrode of the seventh transistor is coupled to the first voltage end. The second electrode of the seventh transistor is coupled to the reference voltage output end. The control electrode of the eighth transistor is coupled to the fourth node. The first electrode of the eighth transistor is coupled to the first end of the sixth resistor. The second electrode of the eighth transistor is coupled to the second node. The second end of the sixth resistor is coupled to the second voltage end. The control electrode of the ninth transistor is coupled to the second electrode of the ninth transistor and the fourth node. The first electrode of the ninth transistor is coupled to the first end of the seventh resistor. The second end of the seventh resistor is coupled to the second voltage end. The control electrode of the tenth transistor is coupled to the fourth node. The first electrode of the tenth transistor is coupled to the second voltage end. The second electrode of the tenth transistor is coupled to the reference voltage output end. The first electrode of the eleventh transistor is coupled to the first voltage end. The second electrode of the eleventh transistor is coupled to the reference voltage output end. The control electrode of the twelfth transistor is coupled to the fourth node. The first electrode of the twelfth transistor is coupled to the second voltage end. The second electrode of the twelfth transistor is coupled to the reference voltage output terminal. The threshold voltage of the eleventh transistor and the threshold voltage of the twelfth transistor are higher than the threshold voltages of other transistors in the reference voltage generating circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0016] Figure 1is a schematic block diagram of a reference voltage generating circuit according to an embodiment of the present disclosure;

[0017] Figure 2 is another schematic block diagram of a reference voltage generating circuit according to an embodiment of the present disclosure; and

[0018] Figure 3 yes Figure 2 An exemplary circuit diagram of a reference voltage generating circuit is shown.

[0019] It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0022] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle end of the MOS transistor is referred to as a control electrode, and the remaining two ends of the MOS transistor are referred to as a first electrode and a second electrode, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0023] Figure 1A schematic block diagram of a reference voltage generating circuit 100 according to an embodiment of the present disclosure is shown. The reference voltage generating circuit 100 may include: a bias circuit 110, a first transistor M1, a second transistor M2, a first feedback circuit 120, a second feedback circuit 150, a first sampling circuit 130, a second sampling circuit 160, a first current amplifying circuit 140, and a second current amplifying circuit 170.

[0024] The bias circuit 110 may be coupled to a bias current source IB via a fifth node. In some embodiments of the present disclosure, the bias current source IB may be a bias current source IB outside the reference voltage generating circuit 100. In other embodiments of the present disclosure, the bias current source IB may be a part of the reference voltage generating circuit 100. The bias circuit 110 may be coupled to a control electrode of the first transistor M1 via a first node N1. The bias circuit 110 may be coupled to a control electrode of the second transistor M2 and a second feedback circuit 150 via a second node N2. The bias circuit 110 may also be coupled to a first feedback circuit 120 and a second voltage terminal V2. The bias circuit 110 may be configured to generate a first bias voltage at a first node N1 and a second bias voltage at a second node N2 according to a bias current IB from the bias current source IB. In some embodiments of the present disclosure, the first bias voltage is higher than the second bias voltage.

[0025] The control electrode of the first transistor M1 is coupled to the first node N1. The first electrode of the first transistor M1 is coupled to the reference voltage output terminal VREF. The second electrode of the first transistor M1 is coupled to the third node N3. The second electrode of the first transistor M1 can be coupled to the first feedback circuit 120, the first sampling circuit 130, and the first current amplifier circuit 140 via the third node N3.

[0026] The control electrode of the second transistor M2 is coupled to the second node N2. The first electrode of the second transistor M2 is coupled to the reference voltage output terminal VREF. The second electrode of the second transistor M2 is coupled to the fourth node N4. The second electrode of the second transistor M2 can be coupled to the second feedback circuit 150, the second sampling circuit 160, and the second current amplifier circuit 170 via the fourth node N4.

[0027] The first sampling circuit 130 may be coupled to the second electrode of the first transistor M1 via the third node N3. The first sampling circuit 130 may also be coupled to the first voltage terminal V1. The first sampling circuit 130 may be configured to: sample the first current I1 flowing through the first transistor M1 via the third node N3.

[0028] The second sampling circuit 160 may be coupled to the second electrode of the second transistor M2 via the fourth node N4. The second sampling circuit 160 may also be coupled to the second voltage terminal V2. The second sampling circuit 160 may be configured to: sample the second current I2 flowing through the second transistor M2 via the fourth node N4.

[0029] The first feedback circuit 120 may be coupled to the second electrode of the first transistor M1 via the third node N3. The first feedback circuit 120 may be coupled to the first voltage terminal V1. The first feedback circuit 120 may also be coupled to the bias current source IB and the bias circuit 110 via the fifth node N5. The first feedback circuit 120 may be configured to generate a first feedback current If1 according to the first current I1. The first feedback current If1 may be used to adjust the first bias voltage to stabilize the reference voltage VREF output from the reference voltage output terminal VREF. In some embodiments of the present disclosure, the first feedback current If1 may be positively correlated with the first current I1. In the case where the reference voltage generating circuit 100 provides the source current Isource to the load, the first transistor M1 is turned on and the second transistor M2 is turned off. When the source current Isource increases, the reference voltage VREF decreases and the first current I1 increases, thereby increasing the first feedback current If1. The increased first feedback current If1 may raise the voltage of the first node N1, thereby raising the reference voltage VREF, thereby offsetting a portion of the voltage value of the reference voltage VREF that decreases as the source current Isource increases. Therefore, the first feedback circuit 120 can realize the function of stabilizing the reference voltage VREF when the reference voltage generating circuit 100 provides the source current Isource to the load.

[0030] The second feedback circuit 150 may be coupled to the second electrode of the second transistor M2 via the fourth node N4. The second feedback circuit 150 may be coupled to the second voltage terminal V2. The second feedback circuit 150 may also be coupled to the bias circuit 110 and the control electrode of the second transistor M2 via the second node N2. The second feedback circuit 150 may be configured to generate a second feedback current If2 according to the second current I2. The second feedback current If2 may be used to adjust the second bias voltage to stabilize the reference voltage VREF. In some embodiments of the present disclosure, the second feedback current If2 may be positively correlated with the second current I2. In the case where the reference voltage generating circuit 100 absorbs the sink current Isink from the load, the first transistor M1 is turned off and the second transistor M2 is turned on. When the sink current Isink increases, the reference voltage VREF increases and the second current I2 increases, thereby increasing the second feedback current If2. The increased second feedback current If2 may pull down the voltage of the second node N2, thereby pulling down the reference voltage VREF, thereby offsetting a portion of the voltage value of the reference voltage VREF that increases with the increase of the sink current Isink. Therefore, the second feedback circuit 150 can realize the function of stabilizing the reference voltage VREF when the reference voltage generating circuit 100 absorbs the sink current Isink from the load.

[0031] The first current amplifier circuit 140 may be coupled to the second electrode of the first transistor M1 via the third node N3. The first current amplifier circuit 140 may also be coupled to the first voltage terminal V1. The first current amplifier circuit 140 may be configured to amplify the first current I1 into a first amplified current Ia1. In the case where the reference voltage generating circuit 100 provides a source current Isource to the load, the first amplified current Ia1 may be a part of the source current Isource.

[0032] The second current amplifier circuit 170 may be coupled to the second electrode of the second transistor M2 via the fourth node N4. The second current amplifier circuit 170 may also be coupled to the second voltage terminal V2. The second current amplifier circuit 170 may be configured to amplify the second current I2 into a second amplified current Ia2. In the case where the reference voltage generating circuit 100 absorbs the sink current Isink from the load, the second amplified current Ia2 may be a part of the sink current Isink.

[0033] When the reference voltage generating circuit 100 provides the source current Isource to the load, the first transistor M1 is turned on, the second transistor M2 is turned off, and the source current Isource includes the first current I1 and the first amplified current Ia1. Since the first current I1 is smaller than the first amplified current Ia1, the change rate of the first current I1 is smaller than the change rate of the source current Isource, so that the change rate of the reference voltage VREF is also smaller than the change rate of the source current Isource.

[0034] When the reference voltage generating circuit 100 absorbs the sink current Isink from the load, the first transistor M1 is turned off, the second transistor M2 is turned on, and the sink current Isink includes the second current I2 and the second amplified current Ia2. Since the second current I2 is smaller than the second amplified current Ia2, the change rate of the second current I2 is smaller than the change rate of the sink current Isink, so that the change rate of the reference voltage VREF is also smaller than the change rate of the sink current Isink.

[0035] Figure 2 FIG. 2 shows another schematic block diagram of a reference voltage generating circuit 200 according to an embodiment of the present disclosure. Figure 2 Based on the example, the reference voltage generating circuit 200 may further include: a first compensation circuit 280 and a second compensation circuit 290 .

[0036] The first compensation circuit 280 may be coupled to the second electrode of the first transistor M1 via the third node N3. The first compensation circuit 280 may also be coupled to the first voltage terminal V1. The first compensation circuit 280 may be configured to generate a first compensation current Ihv1 to compensate for the increment of the first current I1 when the source current Isource is greater than or equal to the threshold value of the first current I1. In this case, the source current Isource includes the first current I1, the first amplified current Ia1, and the first compensation current Ihv1. In some embodiments of the present disclosure, the first compensation current Ihv1 is greater than the first current I1. In this way, even if the source current Isource continues to increase, the rate of change of the first current I1 is still less than the rate of change of the source current Isource, so that the rate of change of the reference voltage VREF is also less than the rate of change of the source current Isource.

[0037] The second compensation circuit 290 may be coupled to the second electrode of the second transistor M2 via the fourth node N4. The second compensation circuit 290 may also be coupled to the second voltage terminal V2. The second compensation circuit 290 may be configured to generate a second compensation current Ihv2 to compensate for the increment of the second current I2 when the injection current Isink is greater than or equal to the second current I2 threshold. In this case, the injection current Isink includes the second current I2, the second amplified current Ia2, and the second compensation current Ihv2. In some embodiments of the present disclosure, the second compensation current Ihv2 is greater than the second current I2. In this way, even if the leakage current continues to increase, the rate of change of the second current I2 is still less than the rate of change of the injection current Isink, so that the rate of change of the reference voltage VREF is also less than the rate of change of the injection current Isink.

[0038] Figure 3 Show Figure 2 1 is an exemplary circuit diagram of a reference voltage generating circuit 300 shown in FIG. 1 . The bias circuit 310 may include: a first resistor R1, a second resistor R2, a third resistor R3, a third transistor M3, and a fourth transistor M4. The first end of the first resistor R1 is coupled to the bias current source IB and the control electrode of the third transistor M3. The second end of the first resistor R1 is coupled to the first node N1 and the first end of the second resistor R2. The second end of the second resistor R2 is coupled to the second electrode of the third transistor M3. The first electrode of the third transistor M3 is coupled to the first electrode of the fourth transistor M4. The control electrode of the fourth transistor M4 is coupled to the second electrode of the fourth transistor M4 and the second node N2. The first end of the third resistor R3 is coupled to the second node N2. The second end of the third resistor R3 is coupled to the second voltage terminal V2.

[0039] The first feedback circuit 320 may include: a fifth transistor M5 and a fourth resistor R4. The control electrode of the fifth transistor M5 is coupled to the third node N3. The first electrode of the fifth transistor M5 is coupled to the first end of the fourth resistor R4. The second electrode of the fifth transistor M5 is coupled to the bias current source IB. The second end of the fourth resistor R4 is coupled to the first voltage terminal V1.

[0040] The first sampling circuit 330 may include: a sixth transistor M6, and a fifth resistor R5. The control electrode of the sixth transistor M6 is coupled to the second electrode of the sixth transistor M6 and the third node N3. The first electrode of the sixth transistor M6 is coupled to the first end of the fifth resistor R5. The second end of the fifth resistor R5 is coupled to the first voltage terminal V1.

[0041] The first current amplifier circuit 340 may include a seventh transistor M7 , wherein a control electrode of the seventh transistor M7 is coupled to the third node N3 , a first electrode of the seventh transistor M7 is coupled to the first voltage terminal V1 , and a second electrode of the seventh transistor M7 is coupled to the reference voltage output terminal VREF .

[0042] The second feedback circuit 350 may include an eighth transistor M8 and a sixth resistor R6. The control electrode of the eighth transistor M8 is coupled to the fourth node N4. The first electrode of the eighth transistor M8 is coupled to the first end of the sixth resistor R6. The second electrode of the eighth transistor M8 is coupled to the second node N2. The second end of the sixth resistor R6 is coupled to the second voltage terminal V2.

[0043] The second sampling circuit 360 may include: a ninth transistor M9 and a seventh resistor R7. The control electrode of the ninth transistor M9 is coupled to the second electrode of the ninth transistor M9 and the fourth node N4. The first electrode of the ninth transistor M9 is coupled to the first end of the seventh resistor R7. The second end of the seventh resistor R7 is coupled to the second voltage terminal V2.

[0044] The second current amplifying circuit 370 may include: a tenth transistor M10. A control electrode of the tenth transistor M10 is coupled to the fourth node N4. A first electrode of the tenth transistor M10 is coupled to the second voltage terminal V2. A second electrode of the tenth transistor M10 is coupled to the reference voltage output terminal VREF.

[0045] The first compensation circuit 380 may include an eleventh transistor M11. A first electrode of the eleventh transistor M11 is coupled to the first voltage terminal V1. A second electrode of the eleventh transistor M11 is coupled to the reference voltage output terminal VREF.

[0046] The second compensation circuit 390 includes a twelfth transistor M12. The control electrode of the eleventh transistor M11 is coupled to the third node N3. The control electrode of the twelfth transistor M12 is coupled to the fourth node N4. The first electrode of the twelfth transistor M12 is coupled to the second voltage terminal V2. The second electrode of the twelfth transistor M12 is coupled to the reference voltage output terminal VREF.

[0047] In some embodiments of the present disclosure, the threshold voltage of the eleventh transistor M11 and the threshold voltage of the twelfth transistor M12 are higher than the threshold voltages of other transistors in the reference voltage generating circuit 300. In some embodiments of the present disclosure, the eleventh transistor M11 and the twelfth transistor M12 are high turn-on threshold (VTH) devices.

[0048] In some embodiments of the present disclosure, the resistance values ​​of the first resistor R1, the second resistor R2, and the third resistor R3 may be set to a suitable ratio so that the first transistor and the second transistor can maintain a small current at zero load, thereby reducing static power consumption. In some embodiments of the present disclosure, the resistance value of the fifth resistor R5 may be equal to the resistance value of the seventh resistor R7. In some embodiments of the present disclosure, R4=R5 / α, wherein R4 represents the resistance value of the fourth resistor R4, and R5 represents the resistance value of the fifth resistor. In some embodiments of the present disclosure, R6=R7 / α, wherein R6 represents the resistance value of the sixth resistor R6, and R7 represents the resistance value of the seventh resistor R7. In some embodiments of the present disclosure, the ratio of the width-to-length ratio of the sixth transistor M6 to the width-to-length ratio of the fifth transistor M5 is 1:α. In some embodiments of the present disclosure, the ratio of the width-to-length ratio of the ninth transistor M9 to the width-to-length ratio of the eighth transistor M8 is 1:α. In some embodiments of the present disclosure, α is less than 0.1. In some embodiments of the present disclosure, α is less than 0.1 and greater than 0.01.

[0049] In some embodiments of the present disclosure, the ratio of the width-to-length ratio of the seventh transistor M7 to the width-to-length ratio of the sixth transistor M6 is n: 1. In some embodiments of the present disclosure, the ratio of the width-to-length ratio of the tenth transistor M10 to the width-to-length ratio of the ninth transistor M9 is n:1.

[0050] exist Figure 3 In the example, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1, the third transistor M3, the eighth transistor M8 to the tenth transistor M10, and the twelfth transistor M12 are NMOS transistors. The second transistor M2, the fourth transistor M4 to the seventh transistor M7, and the eleventh transistor M11 are PMOS transistors. Those skilled in the art should understand that based on the above inventive concept, Figure 3 Variations of the circuit shown in the figure should also fall within the scope of protection of the present disclosure. In this variation, the transistor and the voltage terminal may also have the same Figure 3 Examples of different setups are shown.

[0051] In the case where the reference voltage generating circuit 300 absorbs the sink current Isink from the load, if the reference voltage generating circuit 300 operates in a zero-load state, Isink is equal to 0. Q satisfy:

[0052] I Q =IB+I2+Ia2 (1)

[0053] When the sink current Isink increases, but the voltage of the fourth node N4 has not yet risen to the level that turns on the twelfth transistor M12,

[0054] Isink= I2+Ia2 (2)

[0055]

[0056]

[0057] V can be set TH_M10 =V TH_M9 , substituting formula (3) into formula (4) yields:

[0058]

[0059] Among them, V TH_M9 represents the threshold voltage of the ninth transistor M9, V GS_M9 represents the gate-source voltage of the ninth transistor M9, V TH_M10 represents the threshold voltage of the tenth transistor M10, n represents the ratio of the width-to-length ratio of the tenth transistor M10 to the width-to-length ratio of the ninth transistor M9, R7 represents the resistance value of the seventh resistor, represents the current coefficient of the ninth transistor M9. Among them, μ n_M9 represents the carrier mobility of the ninth transistor M9, C ox_M9 represents the gate oxide capacitance of the ninth transistor M9, represents the width-to-length ratio of the ninth transistor M9.

[0060] According to the proportional relationship between I2 and Ia2 in formula (5), it can be seen that the change rate of I2 is smaller than Isink.

[0061] For the second transistor M2, V S_M2 =V G_M2 +V GS_M2 (6)

[0062] Among them, V S_M2 represents the source voltage of the second transistor M2, V G_M2represents the gate voltage of the second transistor M2, V GS_M2 V represents the gate-source voltage of the second transistor M2. S_M2 = VREF(7).

[0063] Since IB=I5+If2 (I5 represents the current value flowing through the third resistor R3), the gate voltage V of the second transistor M2 is G_M2 = (IB-If2)×R3, where R3 represents the resistance value of the third resistor R3. Since the ratio of the width-to-length ratio of the ninth transistor M9 to the width-to-length ratio of the eighth transistor M8 is 1:α, and R6=R7 / α, therefore, If2=α×I2. V G_M2 =(IB-α×I2)×R3(8).

[0064] Since the current flowing through the second transistor M2 is equal to the second current I2 flowing through the ninth transistor M9,

[0065] Among them, V TH_M2 represents the threshold voltage of the second transistor M2, represents the current coefficient of the second transistor M2. Among them, μ n_M2 represents the carrier mobility of the second transistor M2, C ox_M2 represents the gate oxide capacitance of the second transistor M2, represents the width-to-length ratio of the second transistor M2.

[0066] Substituting equations (7), (8) and (9) into equation (6) yields:

[0067]

[0068] According to formula (10), the reference voltage VREF rises with the second current I2. When the change rate of the second current I2 is less than the sink current Isink, the change rate of the reference voltage VREF is also less than the sink current Isink.

[0069] When the sink current Isink continues to increase and the voltage of the fourth node N4 rises to the point where the twelfth transistor M12 is turned on,

[0070] Isink=I2+Ia2+Ihv2 (11)

[0071] in,

[0072] in, represents the current coefficient of the twelfth transistor M12, R7 represents the resistance value of the seventh resistor R7, V GS_M9 represents the gate-source voltage of the ninth transistor M9, VTH_M12 represents the threshold voltage of the twelfth transistor M12. By setting The second compensation current Ihv2 can be made larger than the second current I2 , so the increment of the sink current Isink mostly falls on the twelfth transistor M12 , the growth rate of the second current I2 slows down, and the reference voltage VREF also tends to rise more slowly.

[0073] In the case where the reference voltage generating circuit 100 provides a source current Isource to the load, if the reference voltage generating circuit 300 operates in a zero-load state, Isource is equal to 0. Q satisfy:

[0074] I Q =IB+If1+I1+Ia1=IB+(1+α)×I1+Ia1 (13)

[0075] When the source current Isource increases, but the voltage of the third node N3 has not yet dropped to the point where the eleventh transistor M11 is turned on,

[0076] Isource= I1+Ia1 (14)

[0077] Due to the proportional relationship between I1 and Ia1 (similar to the proportional relationship between I2 and Ia2), the change rate of I1 is smaller than that of Isource. The reference voltage VREF decreases as the first current I1 increases.

[0078] When the source current Isource continues to increase and the voltage of the third node N3 drops to the point where the eleventh transistor M11 is turned on,

[0079] Isource=I1+Ia1+Ihv1 (15)

[0080] The current coefficient of the eleventh transistor M11 can be set so that the first compensation current Ihv1 is greater than the first current I1. Therefore, most of the increase of the source current Isource falls on the eleventh transistor M11, the first current I1 increases more slowly, and the reference voltage VREF decreases more slowly.

[0081] In summary, the reference voltage generating circuit according to the embodiment of the present disclosure has a simple overall structure, a small static current, and a push-pull output capability. In addition, the reference voltage generating circuit according to the embodiment of the present disclosure has current compensation when the load current is large, and can output a stable voltage, and its output voltage is suitable for use as a relative reference voltage.

[0082] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0083] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0084] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A reference voltage generating circuit, comprising: a bias circuit, a first transistor, a second transistor, a first feedback circuit, a second feedback circuit, a first sampling circuit, a second sampling circuit, a first current amplifying circuit, and a second current amplifying circuit, wherein the bias circuit is configured to generate a first bias voltage at a first node and a second bias voltage at a second node according to a bias current from a bias current source; A control electrode of the first transistor is coupled to the first node, a first electrode of the first transistor is coupled to a reference voltage output terminal, and a second electrode of the first transistor is coupled to a third node; A control electrode of the second transistor is coupled to the second node, a first electrode of the second transistor is coupled to the reference voltage output terminal, and a second electrode of the second transistor is coupled to a fourth node; The first sampling circuit is configured to sample a first current flowing through the first transistor via the third node; The second sampling circuit is configured to sample a second current flowing through the second transistor via the fourth node; The first feedback circuit is configured to generate a first feedback current according to the first current, and the first feedback current is used to adjust the first bias voltage to stabilize the reference voltage output from the reference voltage output terminal; The second feedback circuit is configured to generate a second feedback current according to the second current, and the second feedback current is used to adjust the second bias voltage to stabilize the reference voltage; The first current amplifying circuit is configured to amplify the first current into a first amplified current; The second current amplifying circuit is configured to amplify the second current into a second amplified current; Among them, when the reference voltage generating circuit provides a source current to the load, the first transistor is turned on, the second transistor is turned off, and the source current includes the first current and the first amplified current; when the reference voltage generating circuit absorbs a sink current from the load, the first transistor is turned off, the second transistor is turned on, and the sink current includes the second current and the second amplified current.

2. The reference voltage generating circuit according to claim 1, further comprising: a first compensation circuit, and a second compensation circuit, Wherein, the first compensation circuit is configured to: generate a first compensation current to compensate for an increase in the first current when the source current is greater than or equal to a first current threshold; The second compensation circuit is configured to generate a second compensation current to compensate for an increase in the second current when the sink current is greater than or equal to a second current threshold.

3. The reference voltage generating circuit according to claim 1 or 2, wherein: The bias circuit includes: a first resistor, a second resistor, a third resistor, a third transistor, and a fourth transistor. Wherein, a first end of the first resistor is coupled to the bias current source and the control electrode of the third transistor, and a second end of the first resistor is coupled to the first node and a first end of the second resistor; The second end of the second resistor is coupled to the second electrode of the third transistor; The first electrode of the third transistor is coupled to the first electrode of the fourth transistor; The control electrode of the fourth transistor is coupled to the second electrode of the fourth transistor and the second node; A first terminal of the third resistor is coupled to the second node, and a second terminal of the third resistor is coupled to a second voltage terminal.

4. The reference voltage generating circuit according to claim 1 or 2, wherein: The first feedback circuit includes: a fifth transistor and a fourth resistor, Wherein, a control electrode of the fifth transistor is coupled to the third node, a first electrode of the fifth transistor is coupled to the first end of the fourth resistor, and a second electrode of the fifth transistor is coupled to the bias current source; The second terminal of the fourth resistor is coupled to the first voltage terminal.

5. The reference voltage generating circuit according to claim 1 or 2, wherein: The first sampling circuit includes: a sixth transistor and a fifth resistor, Wherein, the control electrode of the sixth transistor is coupled to the second electrode of the sixth transistor and the third node, and the first electrode of the sixth transistor is coupled to the first end of the fifth resistor; The second terminal of the fifth resistor is coupled to the first voltage terminal.

6. The reference voltage generating circuit according to claim 1 or 2, wherein: The first current amplifying circuit comprises: a seventh transistor, The control electrode of the seventh transistor is coupled to the third node, the first electrode of the seventh transistor is coupled to the first voltage terminal, and the second electrode of the seventh transistor is coupled to the reference voltage output terminal.

7. The reference voltage generating circuit according to claim 1 or 2, wherein: The second feedback circuit includes: an eighth transistor and a sixth resistor, Wherein, the control electrode of the eighth transistor is coupled to the fourth node, the first electrode of the eighth transistor is coupled to the first end of the sixth resistor, and the second electrode of the eighth transistor is coupled to the second node; The second terminal of the sixth resistor is coupled to the second voltage terminal.

8. The reference voltage generating circuit according to claim 1 or 2, wherein: The second sampling circuit includes: a ninth transistor and a seventh resistor. Wherein, the control electrode of the ninth transistor is coupled to the second electrode of the ninth transistor and the fourth node, and the first electrode of the ninth transistor is coupled to the first end of the seventh resistor; The second terminal of the seventh resistor is coupled to the second voltage terminal.

9. The reference voltage generating circuit according to claim 1 or 2, wherein: The second current amplifying circuit comprises: a tenth transistor, The control electrode of the tenth transistor is coupled to the fourth node, the first electrode of the tenth transistor is coupled to the second voltage terminal, and the second electrode of the tenth transistor is coupled to the reference voltage output terminal.

10. The reference voltage generating circuit according to claim 2, wherein: The first compensation circuit includes: an eleventh transistor, and the second compensation circuit includes: a twelfth transistor, Wherein, the control electrode of the eleventh transistor is coupled to the third node, the first electrode of the eleventh transistor is coupled to the first voltage terminal, and the second electrode of the eleventh transistor is coupled to the reference voltage output terminal; The control electrode of the twelfth transistor is coupled to the fourth node, the first electrode of the twelfth transistor is coupled to the second voltage terminal, and the second electrode of the twelfth transistor is coupled to the reference voltage output terminal; The threshold voltage of the eleventh transistor and the threshold voltage of the twelfth transistor are higher than the threshold voltages of other transistors in the reference voltage generating circuit.

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