Voltage generation circuit and semiconductor device

Abstract

The present application provides a voltage generation circuit and a semiconductor device that can suppress a leakage current without using a deep power-down mode. The voltage generation circuit of the present application includes a reference voltage generation section that generates a reference voltage; a leakage current monitoring section that generates a leakage current corresponding to a leakage current of a peripheral circuit; an output voltage control section that controls the reference voltage according to the leakage current and outputs the controlled reference voltage; a backup voltage generation section that supplies an internal supply voltage to the peripheral circuit according to the controlled reference voltage; and a voltage drop detection section that detects a case where the controlled reference voltage has dropped to a certain level. The output voltage control section controls the controlled reference voltage according to a detection result of the voltage drop detection section.

Description

Technical Field

[0001] This invention relates to a voltage generating circuit and a semiconductor device for generating voltage, and more particularly to a voltage generating circuit and a semiconductor device for suppressing leakage current. Background Technology

[0002] In semiconductor devices, a temperature-compensated voltage corresponding to the operating temperature is typically generated to enable circuit operation and maintain circuit reliability. For example, in memory, if the read current decreases due to temperature changes during data readout, the read margin decreases, making accurate data readout impossible. Therefore, using a temperature-compensated voltage for data readout prevents the decrease in read current. For instance, Japanese Patent Application Publication No. 2021-82094 discloses a voltage generation circuit that reduces circuit size by eliminating the need for an on-chip temperature sensor or logic for calculating the temperature-compensated voltage based on its result.

[0003] Semiconductor devices such as resistive variable memory (RVMs) can operate at low voltages and constant currents, making them suitable for mobile devices such as those used in the Internet of Things (IoT). As their applications in mobile devices expand, so too does the operating temperature range. Therefore, voltage generation circuits typically integrated into semiconductor devices can generate temperature-compensated voltages.

[0004] Figure 1 This is a diagram of an example of a conventional temperature-compensated voltage generation circuit. The voltage generation circuit 10 includes: a bandgap reference circuit (BGR) 20, which generates a reference voltage Vref independent of variations in the external power supply voltage; and an internal voltage generation circuit 30, which generates an internal supply voltage INTVDD based on the reference voltage Vref output from the BGR circuit 20.

[0005] The internal voltage generation circuit 30 includes an operational amplifier OP, a positive-channel metal-oxide-semiconductor (PMOS) transistor Q1, a reference voltage Vref input to the inverting input terminal (-) of the operational amplifier OP, and the voltage VN at node N input to the non-inverting input terminal (+) via negative feedback. The output of the operational amplifier OP is connected to the gate of transistor Q1, and the load of the peripheral circuit 40 is connected to node N. The operational amplifier OP controls the gate voltage of transistor Q1 to make the voltage VN at node N equal to the reference voltage Vref (VN = Vref). Thus, the current flowing through transistor Q1 becomes a constant current independent of the variation of the supply voltage VDD, thereby supplying a constant internal supply voltage INTVDD (INTVDD = VN) to the peripheral circuit 40.

[0006] When a flash memory is in standby mode, if the operating temperature becomes high, the leakage current flowing to the peripheral circuitry 40 increases. The peripheral circuitry 40 contains various integrated circuits using complementary metal-oxide-semiconductor (CMOS) transistors, etc. The leakage current of these circuits' positive-negative junctions (PN junctions) and the threshold leakage current of the transistors increase with rising temperature. Furthermore, leakage current is voltage-dependent; therefore, when external factors cause an increase in the internal supply voltage INTVDD, the leakage current also increases.

[0007] To suppress leakage current, some semiconductor devices employ Deep Power Down (DPD) mode, which further reduces power consumption compared to standby mode. In DPD mode, the operation of the internal voltage generation circuit 30 is stopped. For example, a switch is placed between the supply voltage VDD and transistor Q1, and Q1 is turned off during the shutdown phase of the internal voltage generation circuit 30, thereby cutting off the power supply to the supply voltage VDD.

[0008] However, the DPD mode has the following problem: when the supply voltage VDD is cut off through the DPD mode, the peripheral circuit 40 becomes floating. When recovering from the DPD mode, the capacitors of the circuit components and lines of the peripheral circuit 40 must be charged, which takes time and prevents the next action from being performed quickly.

[0009] To address the aforementioned problems, this invention provides a voltage generation circuit that can suppress leakage current without using DPD mode. Summary of the Invention

[0010] The voltage generation circuit of the present invention includes: a reference voltage generation unit for generating a reference voltage; a leakage current monitoring unit for generating a monitoring leakage current corresponding to the leakage current of the internal circuit of a semiconductor device; a control unit for controlling the reference voltage based on the monitoring leakage current; and an internal voltage generation unit for receiving the reference voltage controlled by the control unit and supplying an internal voltage to the internal circuit based on the controlled reference voltage.

[0011] The semiconductor device of the present invention may include a voltage generation circuit according to any embodiment of the present invention, and includes the ability to supply internal voltage to internal circuits in standby mode when operating at low power consumption.

[0012] According to the present invention, a reference voltage is controlled based on the leakage current of the internal circuit, and an internal voltage is supplied to the internal circuit based on the controlled reference voltage. Therefore, a temperature-compensated reference voltage can be generated autonomously, thereby minimizing the leakage current of the internal circuit. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of an existing voltage generation circuit;

[0014] Figure 2 This is a schematic diagram of the voltage generation circuit according to the first embodiment of the present invention;

[0015] Figure 3 This is a block diagram of the voltage generation circuit according to the second embodiment of the present invention;

[0016] Figure 4A (A) Figure 4A (B) Figure 4A (C) Figure 4A (D) is a schematic diagram of the leakage current monitoring unit according to an embodiment of the present invention;

[0017] Figure 4B (A) Figure 4B (B) is a schematic diagram of the leakage current monitoring unit according to an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of the voltage generation circuit according to the second embodiment of the present invention;

[0019] Figure 6 This is a block diagram of the voltage generation circuit according to the third embodiment of the present invention;

[0020] Figure 7 This is a schematic diagram of a first example of the voltage generation circuit according to the third embodiment of the present invention;

[0021] Figure 8 This is a schematic diagram of a second example of the voltage generation circuit according to the third embodiment of the present invention;

[0022] Figure 9 This is a schematic diagram of a third example of the voltage generation circuit according to the third embodiment of the present invention;

[0023] Figure 10 This is a schematic diagram of the voltage generation circuit according to the fourth embodiment of the present invention;

[0024] Figure 11 This is a schematic diagram of the voltage generation circuit according to the fifth embodiment of the present invention.

[0025] Explanation of symbols

[0026] 10: Voltage generation circuit

[0027] 100, 200, 200A, 400, 500: Voltage generation circuit

[0028] 110: Reference Voltage Generation Circuit (BGR Circuit)

[0029] 112: Operational amplifier

[0030] 20: Bandgap Reference Circuit (BGR Circuit)

[0031] 210, 210A: Reference voltage generation unit

[0032] 220: Leakage Current Monitoring Unit

[0033] 230, 310, 310A, 310B, 410: Output voltage control unit

[0034] 240: Backup voltage generation unit

[0035] 250: Peripheral Circuits

[0036] 260: Active voltage generation unit

[0037] 300: Voltage Drop Detection Section

[0038] 320: Voltage offset section

[0039] 40: Peripheral Circuits

[0040] BP1, BP2: Bipolar Transistors (PNP Bipolar Transistors)

[0041] I A I B I C I N Leakage current

[0042] iBGR: The current flowing in the BGR circuit.

[0043] I LEAK Leakage current

[0044] IN: Inverter

[0045] INTVDD: Internal supply voltage

[0046] I PMOS I NMOS Off-state leakage current (leakage current)

[0047] N, N1, N2, N3, N4, N5: Nodes

[0048] OP: Operational amplifier

[0049] OP1: Unity-gain buffer

[0050] Q1, Q3, Q5, Q10, Q20: Transistors (PMOS transistors)

[0051] Q2: Transistor

[0052] Q4: Transistor (NMOS transistor)

[0053] R1, R2, R3, R4, Rf: Resistors

[0054] Trim: Trimming signal

[0055] VDD: Supply voltage

[0056] Vref, Vref_NTc: Reference voltage

[0057] Vref_C: The reference voltage after control Detailed Implementation

[0058] The voltage generation circuit of the present invention can be incorporated into semiconductor memories such as flash memory, dynamic memory, static memory, resistance-varying memory, and magnetic memory, or into semiconductor devices such as logic and signal processing devices.

[0059] Reference Figure 2 The voltage generation circuit 100 in this embodiment includes a reference voltage generation circuit (BGR circuit) 110 and an internal voltage generation circuit 120. The voltage generation circuit 100 is, for example, mounted in a flash memory, and supplies an internal supply voltage INTVDD to the peripheral circuit 40 when the flash memory is in a standby state. During this period, the peripheral circuit 40 enters a low-power mode, but will operate in response to external input commands, etc.

[0060] BGR circuit 110 utilizes the physical properties of silicon, specifically its bandgap voltage, to generate a stable reference voltage with low dependence on temperature and supply voltage variations. BGR circuit 110 includes first and second current paths between the supply voltage VDD and ground (GND). The first current path includes a series-connected PMOS transistor Q10, resistor R1, and positive-negative-positive (PNP) bipolar transistor BP1. The second current path includes a series-connected PMOS transistor Q11 (with the same structure as transistor Q10), resistor R2 (with the same resistance value as resistor R1), resistor Rf, and PNP bipolar transistor BP2. BGR circuit 110 also includes operational amplifier 112, where the connection node N1 between resistor R1 and bipolar transistor BP1 is connected to the inverting input terminal (-) of operational amplifier 112, the connection node N2 between resistor R2 and resistor Rf is connected to the non-inverting input terminal (+) of operational amplifier 112, and the output terminals of operational amplifier 112 are all connected to the gates of transistors Q10 and Q11.

[0061] The emitter area ratio of bipolar transistors BP1 and BP2 is 1:n (where n is a number greater than 1), and the current density of bipolar transistor BP1 is n times that of bipolar transistor BP2. Although a bipolar transistor is illustrated here, a diode with an area ratio of 1:n can also be used instead of a bipolar transistor.

[0062] Operational amplifier 112 controls the gate voltages of transistors Q10 and Q11 to make the voltage at node N1 equal to the voltage at node N2, thereby allowing equal currents I to flow in the first and second current paths. B The voltage V between the terminals of resistor Rf Rf It is expressed by the following formula.

[0063] V Rf = kT / qIn(n)

[0064] k is Boltzmann's constant, T is the absolute temperature, and q is the charge of the electron.

[0065] The current I flowing through resistor Rf B It is expressed by the following formula.

[0066] I B =V Rf / Rf=T / Rf×k / qln(n)

[0067] The temperature-dependent factor is T / Rf, and the current is I. B It has a positive temperature coefficient.

[0068] In addition, if the resistance of the selected tap position of resistor R2 is set as resistor R2', then the reference voltage Vref_NTc is expressed by the following formula.

[0069] Vref_NTc = V N2 +I B R2'

[0070] V N2 Let N be the voltage at node N2.

[0071] In a preferred embodiment, resistor R2 comprises a semiconductor material with a negative temperature coefficient. That is, the resistance decreases as the temperature increases, and vice versa. Resistor R2 is, for example, composed of a conductive polycrystalline silicon layer doped with a high concentration of dopant and an N+ diffusion region. The reference voltage Vref_NTc can have a desired negative temperature coefficient by appropriately selecting the tap position of resistor R2. The tap position or negative temperature coefficient is determined based on how large a reference voltage is supplied to the internal voltage generation circuit 120 at the desired maximum temperature.

[0072] Internal voltage generation circuit 120 and Figure 1 The internal voltage generation circuit 30 shown has the same configuration. (Refer to...) Figure 2 The reference voltage Vref_NTc generated by the BGR circuit 110 is input to the inverting input terminal (-) of the operational amplifier OP of the internal voltage generation circuit 120, and the voltage VN at node N is input to the non-inverting input terminal (+) through negative feedback. The internal voltage generation circuit 120 supplies the internal supply voltage INTVDD generated according to the reference voltage Vref_NTc from node N to the peripheral circuit 40.

[0073] In this embodiment, the flash memory does not employ DPD mode; that is, it does not switch from standby mode to DPD mode. Instead, in standby mode, the leakage current generated in the peripheral circuitry 40 is minimized. During standby mode, when the operating temperature becomes high, the reference voltage Vref_NTc generated in the BGR circuit 110 decreases due to its negative temperature coefficient. The decrease in reference voltage Vref_NTc causes a similar decrease in the internal supply voltage INTVDD generated by the internal voltage generation circuitry 120. Leakage currents generated by PN junction leakage in the peripheral circuitry 40, transistor off-state leakage, etc., increase with rising operating temperature. However, these leakage currents are related to the internal supply voltage INTVDD; if the internal supply voltage INTVDD decreases, the leakage current also decreases accordingly.

[0074] In this embodiment, since the reference voltage Vref_NTc has a negative temperature coefficient, if the temperature rises, the reference voltage Vref_NTc decreases, offsetting the increased leakage current of the surrounding circuit 40. Furthermore, since DPD mode is not used, the next active operation can be performed without considering the delay time of recovery from DPD mode.

[0075] In the first embodiment, resistor R2 must be adjusted during manufacturing or shipping to ensure that the reference voltage Vref_NTc falls within a certain voltage range as the operating temperature rises. However, in reality, the increase in leakage current is not linear but increases exponentially with respect to a certain temperature, making adjustment extremely complex. Furthermore, if the operating temperature exceeds the intended temperature, the reference voltage Vref_NTc will deviate from the predetermined voltage range. As a result, for example, when the reference voltage Vref_NTc falls below the minimum operating voltage of the CMOS transistor in the peripheral circuit 40, the peripheral circuit 40 can no longer respond to commands input in standby mode. Therefore, the second embodiment provides a voltage generation circuit that can autonomously generate a temperature-compensated reference voltage Vref without adjusting the reference voltage generation unit 110.

[0076] Reference Figure 3 The voltage generation circuit 200 of the second embodiment includes: a reference voltage generation unit 210 that generates a reference voltage Vref; and a leakage current monitoring unit 220 that monitors the leakage current I of the peripheral circuit 250 in standby mode. LEAK_PERI And the corresponding leakage current I is generated. LEAK The output voltage control unit 230 receives the reference voltage Vref and outputs the leakage current I generated by the leakage current monitoring unit 220. LEAK The reference voltage Vref_C is controlled; and the standby voltage generation unit 240 generates an internal supply voltage INTVDD based on the controlled reference voltage Vref_C. The peripheral circuit 250 operates with low power consumption in standby mode using the internal supply voltage INTVDD generated by the standby voltage generation unit 240, and operates in active mode using the internal supply voltage INTVDD generated by the active voltage generation unit 260.

[0077] The reference voltage generation unit 210 includes, for example, a Figure 2 The BGR circuit shown provides a reference voltage Vref to the output voltage control unit 230. The leakage current monitoring unit 220 generates a leakage current If generated in the peripheral circuitry 250 in standby mode. LEAK_PERI Leakage current I with a certain ratio LEAKThe peripheral circuitry 250 includes various circuits using CMOS transistors, etc. When the flash memory is in standby mode, these circuits operate under an internal supply voltage INTVDD from the standby voltage generation unit 240. On the other hand, the reduction in the threshold voltage of transistors and the miniaturization of transistors increase the off-state leakage current (including PN junction leakage and gate leakage) flowing between the source and drain of transistors. Therefore, the leakage current of the peripheral circuitry 250 in standby mode must be minimized.

[0078] In one embodiment, the leakage current monitoring unit 220 includes a CMOS transistor consisting of at least one PMOS transistor and an NMOS transistor connected in series to monitor the leakage current of the peripheral circuit 250. The channel width of each PMOS transistor and NMOS transistor has a certain ratio R relative to the combined channel width of the PMOS and NMOS transistors in the overall CMOS transistor of the peripheral circuit 250. In other words, the off-state leakage current I of the CMOS transistor in the leakage current monitoring unit 220 is monitored. LEAK ×R approximates the off-state leakage current I of the peripheral circuit 250. LEAK_PERI .

[0079] In order to further improve the leakage current I generated by the leakage current monitoring unit 220 LEAK The accuracy can also be considered in relation to the structure of the CMOS transistor in the surrounding circuitry 250. That is, in the off-state leakage of the CMOS transistor, there are... Figure 4A Figure (A) shows the off-state leakage current I when the input signal is high (High, H), with the PMOS transistor off and the NMOS transistor on. PMOS and such Figure 4A Figure (B) shows the off-state leakage current I when the input signal is low (Low, L), with the PMOS transistor on and the NMOS transistor off. NMOS Off-state leakage current I PMOS With off-state leakage current I NMOS The sizes are different, therefore the total number S_P of the PMOS transistors and the total number S_N of the NMOS transistors in the peripheral circuit 250 that are disconnected are calculated. The leakage current monitoring unit 220 includes leakage circuit A and leakage circuit B, wherein leakage circuit A, relative to... Figure 4A The total channel widths of the PMOS transistors S_P shown in (C) are combined to form a certain ratio, and the PMOS transistor becomes an off-state leakage transistor. In the leakage circuit B, relative to... Figure 4AThe total channel width of the NMOS transistors S_N, as shown in (D), is represented by a certain ratio, making the NMOS transistor a non-leaking transistor. When leakage circuit A and leakage circuit B are connected in parallel, the leakage current I... PMOS With leakage current I NMOS The sum of these becomes the leakage current I. LEAK .

[0080] The leakage current monitoring unit 220 may also include various leakage circuits to generate a leakage current I that takes into account more leakage characteristics of the surrounding circuit 250. LEAK The peripheral circuitry 250 contains various logic circuits utilizing CMOS transistors (inverters, AND gates, NAND gates, etc.), each resulting in different leakage current magnitudes. Therefore, as... Figure 4B As shown in (A), various leakage circuits A, B, C to N with different leakage characteristics can be prepared, and the leakage circuit selected by the trimming signal Trim can be operated according to the structure of the peripheral circuit 250.

[0081] For example, leakage circuit A generates off-state leakage current for the PMOS transistor, leakage circuit B generates off-state leakage current for the NMOS transistor, leakage circuit C generates off-state leakage current for both the PMOS and NMOS transistors, and leakage circuit N generates off-state leakage current for the PMOS transistor in the NAND gate. The trimming signal Trim, for example, enables leakage circuits A through N, selected by a blown fuse, to operate.

[0082] Furthermore, each of the leakage circuits A, B, C, ..., N scales the leakage current ratio of the corresponding logic circuit in the peripheral circuit 250, thus incorporating multiple sets of CMOS transistors, and causing a selected number of CMOS transistors to operate. This selection is performed by a trimming signal (Trim). For example, in the case of P sets of leakage circuits A connected in parallel, to obtain a certain ratio relative to the leakage current of the corresponding CMOS inverter in the peripheral circuit 250, a number of leakage circuits A selected from the P sets are operated by the trimming signal (Trim). For example, a number of leakage circuits A selected by blowing a fuse using the trimming signal (Trim) are operated.

[0083] Leakage circuits A, B, C, ..., N are connected in parallel. The leakage current I generated by each leakage circuit... A Leakage current I B Leakage current I C Leakage current I N The sum of these becomes the leakage current I. LEAK As the operating temperature increases, the leakage current I...LEAK Increase, as the operating temperature decreases, the leakage current I LEAK reduce.

[0084] Thus, the leakage current monitoring unit 220 generates the leakage current I of the peripheral circuit 250 in standby mode. LEAK_PERI Leakage current I obtained by monitoring LEAK and the generated leakage current I LEAK Provided to the output voltage control unit 230.

[0085] The output voltage control unit 230 controls the output voltage based on the leakage current I. LEAK This controls the reference voltage Vref. Specifically, when the leakage current I... LEAK When the voltage increases, the output voltage control unit 230 lowers the reference voltage Vref_C, and when the leakage current I... LEAK When the voltage decreases, the output voltage control unit 230 increases the reference voltage Vref_C. The reference voltage Vref_C controlled by the output voltage control unit 230 is then provided to the standby voltage generation unit 240.

[0086] Backup voltage generation unit 240, for example, with Figure 2 The internal voltage generation circuit 120 shown has the same configuration. The standby voltage generation unit 240 receives the reference voltage Vref_C and provides an internal supply voltage INTVDD, which becomes equal to the reference voltage Vref_C, to the peripheral circuit 250. When the operating temperature of the peripheral circuit 250 rises, the reference voltage Vref_C decreases, and consequently, the internal supply voltage INTVDD decreases, thus reducing the leakage current I of the peripheral circuit 250. LEAK_PERI This is suppressed, thereby saving power. When switching from standby mode to active mode, the internal supply voltage INTVDD is supplied from the active voltage generation unit 260 to the peripheral circuit 250.

[0087] Figure 5 This is a detailed circuit diagram of the voltage generation circuit 200 according to the second embodiment. The reference voltage generation unit 210 uses a BGR circuit to generate a reference voltage Vref and provides the reference voltage Vref to the output voltage control unit 230. Furthermore, unlike the reference voltage Vref_NTc in the first embodiment, the reference voltage Vref has a positive temperature coefficient.

[0088] Similar to the backup voltage generation unit 240, the output voltage control unit 230 includes a constant current circuit (unity-gain buffer OP1, transistor Q2) and generates a voltage Vref at node N3 that is independent of fluctuations in the external power supply voltage VDD. Resistor R3 is connected between node N3 and node N4, generating a constant current I at node N4. C Constant current I C Compared to the constant current I generated by the backup voltage generation unit 240C_PERI It has a certain ratio (I) LEAK_PERI :I LEAK =I C_PERI :I C That is, the channel width of transistor Q2 is adjusted to a certain ratio relative to the channel width of transistor Q1.

[0089] The leakage current monitoring unit 220 is connected to node N4 of the output voltage control unit 230. An example of the leakage current monitoring unit 220 including a leakage circuit A is shown here. A constant current I is generated at node N4. C Because of the leakage current I generated by the leakage current monitoring unit 220 LEAK The current flows to GND, resulting in the generation of a constant current I at node N4. C With leakage current I LEAK The difference (I) C -I LEAK The reference voltage Vref_C is controlled by the temperature rise. That is, when the leakage current I... LEAK When the reference voltage Vref_C increases, the leakage current I decreases due to the decrease in temperature. LEAK When the temperature decreases, the reference voltage Vref_C increases, thereby autonomously generating a controlled reference voltage Vref_C that corresponds to the temperature change.

[0090] In the second embodiment, the reference voltage Vref_C is automatically adjusted based on temperature changes. However, since the leakage current increases sharply at a certain temperature, there is a risk that the reference voltage Vref_C may fall below the minimum operating voltage of the CMOS in the surrounding circuitry 250. Therefore, in the third embodiment, feedback control is implemented to prevent the reference voltage Vref_C from falling below the minimum operating voltage of the CMOS.

[0091] Reference Figure 6 The voltage generation circuit 200A of the third embodiment includes a voltage drop detection unit 300 and an output voltage control unit 310. The reference voltage generation unit 210, leakage current monitoring unit 220, and standby voltage generation unit 240 are the same as those in the second embodiment.

[0092] The voltage drop detection unit 300 monitors the temperature-compensated reference voltage Vref_C output by the output voltage control unit 310, detects the case where the reference voltage Vref_C drops to the threshold voltage Vth near the minimum operating voltage Vmin of CMOS (Vref_C-Vmin≦th threshold voltage Vth), and provides the detection result to the output voltage control unit 310.

[0093] Similar to the second embodiment, the output voltage control unit 310 outputs the leakage current I of the leakage current monitoring unit 220. LEAKThe corresponding reference voltage Vref_C is used, but when it is detected that the reference voltage Vref_C has dropped to the threshold voltage Vth, the reference voltage Vref_C is controlled to make the reference voltage Vref_C greater than the threshold voltage Vth. In one embodiment, the output voltage control unit 310 increases the constant current I flowing from the external power supply voltage VDD to node N3. C To offset leakage current I LEAK This increases the reference voltage Vref_C. In another embodiment, the output voltage control unit 310 increases the reference voltage Vref_C by shifting the direct current (DC) voltage. This prevents the internal supply voltage INTVDD of the backup voltage generation unit 240 from falling below the minimum operating voltage of the CMOS, ensuring the operation of the peripheral circuitry 250.

[0094] Figure 7 The diagram illustrates a first structural example of the voltage generation circuit 200A according to the third embodiment of the present invention. Figure 5 Structures with the same structure are labeled with the same reference symbol. The voltage drop detection unit 300 monitors the temperature-compensated reference voltage Vref_C at node N4. The voltage drop detection unit 300 includes a PMOS transistor Q3 with its source connected to node N4, a constant current resistor R4 connected between transistor Q3 and ground, and an inverter IN at node N5 connected between transistor Q3 and resistor R4. The gate of transistor Q3 is grounded, and transistor Q3 is in the on state.

[0095] When the reference voltage Vref_C is sufficiently high compared to the minimum operating voltage of the CMOS, transistor Q3 is strongly turned on, causing node N5 to become H level and the output of inverter IN to become L level. When the reference voltage Vref_C decreases to Vref_C-Vmin≦Vth, the gate-source voltage V of transistor Q3... GS The drain current of transistor Q3 decreases, node N5 becomes L level, and the output of inverter IN becomes H level.

[0096] The output voltage control unit 310 includes an NMOS transistor Q4 connected in parallel with transistor Q2 between the external supply voltage VDD and node N3. The gate of transistor Q4 is connected to the output of the inverter IN of the voltage drop detection unit 300. When the reference voltage Vref_C decreases and the output of inverter IN becomes H, transistor Q4 turns on, supplying current I to node N3. ADD The dimensions of transistor Q4 are adjusted as follows: Current I ADD To counteract the sharp increase in leakage current I as temperature rises. LEAK Furthermore, the reference voltage Vref_C becomes higher than the level detected by the voltage drop detection unit 300.

[0097] When the reference voltage Vref_C increases sufficiently relative to the minimum operating voltage of the CMOS, the output of the inverter IN of the voltage drop detection unit 300 becomes L level, stopping the current I. ADD The supply. Furthermore, the current I ADD The supply method is not limited to the method described above, and may also be carried out by other methods.

[0098] Figure 8 The diagram illustrates a second structural example of the voltage generation circuit 200A according to the third embodiment of the present invention. Figure 7 Structures with the same structure are labeled with the same reference symbol. In the second structural example, the output voltage control unit 310A includes a voltage offset unit 320, which increases the reference voltage Vref_C in the positive direction based on the output of the inverter IN of the voltage drop detection unit 300. The voltage offset unit 320 includes, for example, a pull-up transistor for connecting the reference voltage Vref_C to the external power supply voltage VDD, which is turned on in response to the H-level output of the inverter IN, thus offsetting the reference voltage Vref_C in the positive direction.

[0099] When the reference voltage Vref_C increases sufficiently relative to the minimum operating voltage of the CMOS, the output of the inverter IN of the voltage drop detection unit 300 becomes L level, and the voltage offset performed by the voltage offset unit 320 stops. Furthermore, the voltage offset method is not limited to the method described above, and other methods may also be used.

[0100] Figure 9 The diagram illustrates a third structural example of the voltage generation circuit 200A according to the third embodiment of the present invention. Figure 7 and Figure 8 Structures with the same structure are labeled with the same reference symbol. In the third structural example, the output voltage control unit 310B includes... Figure 7 The shown is used to supply current I ADD transistor Q4 and Figure 8 The voltage offset section 320 shown is used to shift the reference voltage Vref_C in the positive direction. Transistor Q4 and voltage offset section 320 increase the reference voltage Vref_C in response to a drop in the reference voltage Vref_C detected by voltage drop detection section 300, to avoid it falling below the minimum operating voltage of the CMOS. According to the third structural example, compared with the first and second structural examples, the reference voltage Vref_C can be increased in a shorter time.

[0101] Next, the fourth embodiment of the present invention will be described. Figure 10 This is a schematic diagram of the voltage generation circuit in the fourth embodiment. Figure 9Structures with the same structure are labeled with the same reference symbol. In the voltage generation circuit 400 of this embodiment, the output voltage generation unit 410 includes transistor Q10, which is part of the BGR circuit of the reference voltage generation unit 210, and PMOS transistor Q5, which forms a current mirror with transistor Q20. Transistor Q5 is connected between the external power supply voltage VDD and transistor Q2, and the gate of transistor Q5 is connected to the gates of transistors Q10 and Q20.

[0102] Transistor Q5 is configured with a current mirror ratio K relative to transistors Q10 / Q20, and the current I flowing to the output voltage control unit 410 is... C It is K times iBGR (K is a value greater than or equal to 1). Furthermore, the current (iBGR) flowing in the BGR circuit has a positive temperature coefficient, therefore the current I flowing to the output voltage control unit 410... C It also has a positive temperature coefficient. Therefore, as the temperature rises, the current I... C Increase, and at the same time, the leakage current I generated by the leakage current monitoring unit 220 LEAK This also increases the current, thus preventing a sharp drop in the reference voltage Vref_C. Furthermore, although the output voltage control unit 410 includes an additional current I in response to the detection result of the voltage drop detection unit 300... ADD The transistor Q4 and voltage offset section 320 are included, but the structure may also include either one.

[0103] Next, the fifth embodiment of the present invention will be described. Figure 11 To illustrate the voltage generation circuit of the fifth embodiment, a schematic diagram is provided for... Figure 10 Structures with the same structure are labeled with the same reference symbol. In the voltage generation circuit 500 of this embodiment, the reference voltage generation unit 210A has the same configuration as in the first embodiment. That is, the reference voltage generation unit 210A provides a reference voltage Vref_NTc with a negative temperature coefficient to the output voltage control unit 410.

[0104] In this embodiment, as the temperature rises, the reference voltage Vref_NTc decreases, and on the other hand, the current I... C Increase, leakage current I LEAK It also increases. If the current I C The increase in leakage current I LEAK When this is canceled out, the reference voltage Vref_C decreases due to the decrease in the reference voltage Vref_NTc, and the leakage current of the peripheral circuit 250 is suppressed. Furthermore, although the output voltage control unit 410 includes an additional current I in response to the detection result of the voltage drop detection unit 300... ADD The transistor Q4 and voltage offset section 320 are included, but the structure may also include either one.

[0105] The features of the voltage generation circuit in this embodiment are summarized as follows.

[0106] 1. The internal supply voltage INTVDD of the backup voltage generation unit 240 ensures the minimum operating voltage of the CMOS throughout the temperature compensation range.

[0107] 2. At the highest temperature within the temperature compensation range, the internal supply voltage INTVDD of the standby voltage generation unit 240 is controlled at a minimum DC level.

[0108] 3. By using a lower internal supply voltage INTVDD, the junction leakage current, gate leakage current, and off-state leakage current of the integrated circuits in the peripheral circuit 250 can be minimized.

[0109] 4. By maintaining a lower level of internal supply voltage INTVDD instead of cutting off power supply in deep power-down mode (DPD), the time to recover to active operation can be shortened compared to deep power-down mode.

[0110] Furthermore, while the voltage generation circuit in this embodiment is used in the standby state of the flash memory, this is just one example. The present invention can be applied to the voltage supply to internal circuits regardless of the standby state. Moreover, the present invention can be applied to voltage generation circuits that provide desired internal voltages to the internal circuits of other semiconductor devices besides flash memory.

[0111] The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments, and various modifications and alterations can be made within the scope of the spirit of the present invention as set forth in the claims.

Claims

1. A voltage generation circuit, comprising: The reference voltage generation unit generates a reference voltage. The leakage current monitoring unit generates a monitoring leakage current corresponding to the leakage current of the internal circuit of the semiconductor device; The control unit controls the reference voltage based on the monitoring leakage current; and An internal voltage generation unit receives a reference voltage controlled by the control unit and supplies an internal voltage to the internal circuit based on the controlled reference voltage. The control unit includes a constant current circuit that generates a constant current. The output node of the constant current circuit is connected to the leakage current monitoring unit, and the controlled reference voltage is output from the output node.

2. The voltage generation circuit according to claim 1 further includes a detection unit, which detects that the controlled reference voltage has dropped to a certain level. The control unit controls the reference voltage after control based on the detection results of the detection unit.

3. The voltage generation circuit according to claim 2, wherein, The specified voltage level is a voltage higher than the minimum operating voltage of the complementary metal-oxide-semiconductor transistor in the internal circuit.

4. The voltage generation circuit according to claim 1 or 2, wherein, The leakage current monitoring unit includes a monitoring transistor for generating a monitoring leakage current and performing off-state leakage. The channel width of the monitoring transistor is configured to have a certain ratio relative to the total channel width of the internal circuit's off-state leakage transistors.

5. The voltage generation circuit according to claim 1 or 2, wherein, The leakage current monitoring unit includes a variety of monitoring transistors that monitor leakage in the off-state. The channel width of each monitoring transistor is configured to have a certain ratio relative to the total channel width of the corresponding transistors that monitor leakage in the off-state in the internal circuit.

6. The voltage generation circuit according to claim 4, wherein, The monitoring transistor is a complementary metal-oxide-semiconductor transistor formed by connecting a positive-channel metal-oxide-semiconductor transistor and a negative-channel metal-oxide-semiconductor transistor in series.

7. The voltage generation circuit according to claim 1 or 2, wherein, The leakage current monitoring unit includes multiple leakage circuits, and generates a monitoring leakage current by operating a leakage circuit selected from these multiple leakage circuits.

8. The voltage generation circuit according to claim 7, wherein, The leakage current monitoring unit selects the leakage circuit based on the adjustment signal input from the outside.

9. The voltage generation circuit according to claim 1, wherein, When the leakage current for monitoring increases, the controlled reference voltage decreases; when the leakage current for monitoring decreases, the controlled reference voltage increases.

10. The voltage generation circuit according to claim 1, wherein, The constant current circuit generates the constant current based on a reference voltage with a negative temperature coefficient.

11. The voltage generation circuit according to claim 1, wherein, The constant current circuit generates the constant current based on a reference voltage with a positive temperature coefficient.

12. The voltage generation circuit according to claim 2, wherein, When the detection unit detects that the controlled voltage has dropped to a certain level, the control unit increases the controlled voltage.

13. The voltage generation circuit according to claim 12, wherein, The control unit adds an additional current to the constant current based on the detection result of the detection unit.

14. The voltage generation circuit according to claim 12, wherein, The control unit increases the controlled reference voltage in the positive direction based on the detection result of the detection unit.

15. A semiconductor device comprising a voltage generation circuit as claimed in any one of claims 1 to 14.

16. The semiconductor device of claim 15, comprising a standby mode for low-power operation, wherein the voltage generation circuit supplies an internal voltage to the internal circuitry in the standby mode.

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