Bandgap reference circuit and chip

Abstract

The application discloses a band gap reference circuit and a chip, and the band gap reference circuit comprises a first MOS transistor, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor, an amplifier and an adjustable resistor unit. Compared with a traditional band gap reference circuit structure, the circuit structure of the application is simple, the output voltage precision is high, the noise of a power supply and ground is well inhibited, the interference of a reference voltage caused by a large ground noise in a DCDC converter and the like can be well solved, and the application can be widely applied to a semiconductor integrated circuit as a high-performance reference circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a bandgap reference circuit and chip. Background Technology

[0002] Bandgap reference circuits have become an indispensable basic module in semiconductor integrated circuits, widely used in amplifiers, analog-to-digital converters, digital-to-analog converters, radio frequency (RF) devices, sensors, and power management chips. Traditional bandgap reference circuits include various implementations such as voltage references based on the reverse breakdown characteristics of Zener diodes, voltage references based on the forward conduction characteristics of PN junctions, and bandgap references. Due to their advantages such as low temperature drift and high voltage accuracy, bandgap references have gained widespread application.

[0003] In the design of power management chips and chips such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), dynamic memory (DRAM), and flash memory, the design of a bandgap reference with low temperature coefficient, low power consumption, and high anti-interference is crucial.

[0004] In existing bandgap reference circuits, the circuit's anti-interference design mainly focuses on optimizing the power supply rejection ratio (PSSR), but it does not have a good ability to suppress ground noise. Ground noise is generally quite high in power management chips, especially DC-DC converter chips. This noise can significantly interfere with the output voltage of the bandgap reference circuit, thereby affecting the overall performance of the chip.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a bandgap reference circuit that can improve the suppression of ground noise.

[0007] To achieve the above objectives, embodiments of the present invention provide a bandgap reference circuit, comprising: a first MOS transistor, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor, an amplifier, and an adjustable resistor unit.

[0008] The source of the first MOSFET is connected to the power supply voltage. The drain of the first MOSFET is connected to the collector and base of the first transistor and the collector and base of the second transistor and is used to output a reference voltage. The emitter of the first transistor is connected to the first terminal of the third resistor and the first input terminal of the amplifier. The emitter of the second transistor is connected to the first terminal of the first resistor. The second terminal of the first resistor is connected to the second input terminal of the amplifier and the first terminal of the second resistor. The output terminal of the amplifier is connected to the gate of the first MOSFET. The second terminal of the third resistor and the second terminal of the second resistor are connected to the first terminal of the adjustable resistor unit. The second terminal of the adjustable resistor unit is connected to ground voltage.

[0009] In one or more embodiments of the present invention, the adjustable resistor unit includes a fourth resistor and a plurality of resistor units, wherein the fourth resistor and the resistor units are connected in series.

[0010] In one or more embodiments of the present invention, the resistor unit includes a fifth resistor and a second MOS transistor, the drain of the second MOS transistor is connected to a first terminal of the fifth resistor, the source of the second MOS transistor is connected to a second terminal of the fifth resistor, and the gate of the second MOS transistor is used to receive a control signal.

[0011] In one or more embodiments of the present invention, the bandgap reference circuit further includes a startup circuit for switching the bandgap reference circuit from a degenerate state to a normal operating state.

[0012] In one or more embodiments of the present invention, the startup circuit includes an eighth resistor, a ninth resistor, a third MOSFET, and a fourth MOSFET;

[0013] The first end of the eighth resistor and the first end of the ninth resistor are connected to the power supply voltage. The second end of the eighth resistor is connected to the gate of the third MOS transistor and the drain of the fourth MOS transistor. The second end of the ninth resistor is connected to the drain of the third MOS transistor. The gate of the fourth MOS transistor and the source of the third MOS transistor are connected to the collectors of the first transistor and the second transistor. The source of the fourth MOS transistor is connected to the ground voltage.

[0014] In one or more embodiments of the present invention, the bandgap reference circuit further includes a filter circuit for filtering the reference voltage.

[0015] In one or more embodiments of the present invention, the bandgap reference circuit further includes a BG_OK generation circuit for outputting a BG_OK signal when the reference voltage is higher than a preset value.

[0016] In one or more embodiments of the present invention, the BG_OK generation circuit includes a tenth resistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a first inverter, a second inverter, and a third inverter;

[0017] The gates of the fifth and sixth MOS transistors are connected to receive a reference voltage. The first terminal of the tenth resistor is connected to the power supply voltage. The second terminal of the tenth resistor is connected to the input terminal of the first inverter and the drain of the fifth MOS transistor. The source of the fifth MOS transistor is connected to the drain of the sixth and seventh MOS transistors. The sources of the sixth and seventh MOS transistors are connected to ground. The output terminal of the first inverter is connected to the gate of the seventh MOS transistor and the input terminal of the second inverter. The output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is used to output the BG_OK signal.

[0018] In one or more embodiments of the present invention, the bandgap reference circuit further includes a first capacitor, a first terminal of which is connected to the gate of a first MOS transistor, and a second terminal of which is connected to the drain of the first MOS transistor.

[0019] The present invention also discloses a chip, comprising: the aforementioned bandgap reference circuit.

[0020] Compared with the prior art, the bandgap reference circuit and chip according to the embodiments of the present invention have a simpler circuit structure, higher output voltage accuracy, and better suppression of power supply and ground noise compared with the traditional bandgap reference circuit structure. It can effectively solve the interference of the reference voltage caused by the large ground noise in circuits such as DC-DC converters, and can be widely used as a high-performance reference circuit in semiconductor integrated circuits. Attached Figure Description

[0021] Figure 1 This is a circuit schematic diagram of a bandgap reference circuit according to an embodiment of the present invention.

[0022] Figure 2 This is a graph showing the change of reference voltage as a function of temperature generated by a bandgap reference circuit according to an embodiment of the present invention.

[0023] Figure 3 This is a graph showing the ability of a bandgap reference circuit, according to an embodiment of the present invention, to suppress power supply noise.

[0024] Figure 4 This is a graph showing the ability of a bandgap reference circuit, according to an embodiment of the present invention, to suppress ground noise. Detailed Implementation

[0025] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0026] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0027] like Figure 1 As shown, a bandgap reference circuit includes: a core circuit 10 composed of a first MOS transistor MP1, a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, an amplifier AMP, a first capacitor C1, and an adjustable resistor unit; a startup circuit 20; a filter circuit 30; and a BG_OK generation circuit 40.

[0028] In this configuration, the source of the first MOSFET MP1 is connected to the power supply voltage VDD. The drain of the first MOSFET MP1 is connected to the collector and base of the first transistor Q1 and the collector and base of the second transistor Q2, and is used to output the reference voltage VBG1. The first terminal of the first capacitor C1 is connected to the gate of the first MOSFET MP1, and the second terminal of the first capacitor C1 is connected to the drain of the first MOSFET MP1. The emitter of the first transistor Q1 is connected to the first terminal of the third resistor R3 and the first input terminal of the amplifier AMP, forming node A. The emitter of the second transistor Q2 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the second input terminal of the amplifier AMP and the first terminal of the second resistor R2, forming node B. The output terminal of the amplifier AMP is connected to the gate of the first MOSFET MP1. The second terminals of the third resistor R3 and the second resistor R2 are connected to the first terminal of the adjustable resistor unit, and the second terminal of the adjustable resistor unit is connected to ground voltage GND. The first input terminal of the amplifier AMP is the positive input terminal, and the second input terminal of the amplifier AMP is the negative input terminal.

[0029] The adjustable resistor unit includes a fourth resistor R4 and several resistor units. The first end of the fourth resistor R4 is connected to the second end of the third resistor R3 and the second end of the second resistor R2. The fourth resistor R4 and the resistor units are connected in series. In this embodiment, there are two resistor units 11, namely a first resistor unit 11 and a second resistor unit 12. In other embodiments, the number of resistor units 11 can be provided as needed, such as four, five, seven, etc.

[0030] The first resistor unit 11 includes a fifth resistor R5 and a second MOSFET MN1. The drain of the second MOSFET MN1 is connected to the first terminal of the fifth resistor R5 and the second terminal of the fourth resistor, the source of the second MOSFET MN1 is connected to the second terminal of the fifth resistor R5, and the gate of the second MOSFET MN1 is used to receive the control signal VTM1.

[0031] The second resistor unit 12 includes a sixth resistor R6 and an eighth MOSFET MN2. The drain of the eighth MOSFET MN2 is connected to the first terminal of the sixth resistor R6 and the second terminal of the fifth resistor R5. The source of the eighth MOSFET MN2 is connected to ground voltage GND. The gate of the eighth MOSFET MN2 is used to receive the control signal VTM2.

[0032] By adjusting control signals VTM1 and VTM2, the second MOSFET MN1 and / or the eighth MOSFET MN2 can be turned on, thereby causing the adjustable resistor unit to exhibit different resistance values. Adjusting the resistance value of the adjustable resistor unit can improve the accuracy of the reference voltage VBG1.

[0033] In this embodiment, by making the resistance values ​​of the second resistor R2 and the third resistor R3 equal, we can obtain:

[0034] Among them, V BE1 V BE2 I1 = ΔV is the voltage between the base and emitter of transistors Q1 and Q2. BE / R1, ΔV BE =

[0035] V BE1 -V BE2 ;R Trim This is the resistance value of the adjustable resistor unit.

[0036] Based on the characteristics of the amplifier AMP, it can ensure that the voltages at nodes A and B are equal, and at the same time, it can effectively shield the noise generated at the ground terminal from being transmitted to the reference voltage VBG1. Compared with the traditional bandgap reference voltage structure, this structure greatly improves the circuit's ability to suppress ground noise while ensuring the power supply voltage rejection ratio PSSR. The amplifier AMP can adopt a traditional 5-transistor operational amplifier structure or a folded common source common gate structure, etc.

[0037] like Figure 1 As shown, the startup circuit 20 is used to switch the bandgap reference circuit from the degenerate state to the normal operating state.

[0038] In this embodiment, the startup circuit 20 includes an eighth resistor R8, a ninth resistor R9, a third MOSFET MN3, and a fourth MOSFET MN4.

[0039] Specifically, the first terminal of the eighth resistor R8 and the first terminal of the ninth resistor R9 are connected to the power supply voltage VDD. The second terminal of the eighth resistor R8 is connected to the gate of the third MOSFET MN3 and the drain of the fourth MOSFET MN4. The second terminal of the ninth resistor R9 is connected to the drain of the third MOSFET MN3. The gate of the fourth MOSFET MN4 and the source of the third MOSFET MN3 are connected to the collectors of the first transistor Q1 and the second transistor Q2. The source of the fourth MOSFET MN4 is connected to the ground voltage GND.

[0040] During the power supply voltage VDD, the core circuit 10 may be in a degenerate state. At this time, the reference voltage VBG1 remains at a low level. The fourth MOSFET MN4 is turned off, and the third MOSFET MN3 is turned on, allowing current to flow into the core circuit 10. This causes the core circuit 10 to leave the degenerate state and allows the reference voltage VBG1 to maintain its normal operating voltage. At this time, the fourth MOSFET MN4 is turned on, the third MOSFET MN3 is turned off, and the core circuit 10 enters its normal operating state.

[0041] like Figure 1 As shown, the filter circuit 30 is used to filter the reference voltage VBG1 to output the final reference voltage VBG, further improving the noise suppression capability of the bandgap reference circuit.

[0042] In this embodiment, the filter circuit 30 includes a seventh resistor R7 and a second capacitor C2. The first end of the seventh resistor R7 is connected to the collector of the first transistor Q1 and the second transistor Q2, the second end of the seventh resistor R7 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to ground voltage GND.

[0043] like Figure 1 As shown, the BG_OK generation circuit 40 is used to output the BG_OK signal when the reference voltage VBG is higher than a preset value.

[0044] In this embodiment, the BG_OK generation circuit 40 includes a tenth resistor R10, a fifth MOSFET MN5, a sixth MOSFET MN6, a seventh MOSFET MN7, a first inverter INV1, a second inverter INV2, and a third inverter INV3.

[0045] Specifically, the gate of the fifth MOSFET MN5 and the gate of the sixth MOSFET MN6 are connected to receive the reference voltage. The first terminal of the tenth resistor R10 is connected to the power supply voltage VDD, and the second terminal of the tenth resistor R10 is connected to the input terminal of the first inverter INV1 and the drain of the fifth MOSFET MN5. The source of the fifth MOSFET MN5 is connected to the drain of the sixth MOSFET MN6 and the drain of the seventh MOSFET MN7. The sources of the sixth MOSFET MN6 and the seventh MOSFET MN7 are connected to the ground voltage GND. The output terminal of the first inverter INV1 is connected to the gate of the seventh MOSFET MN7 and the input terminal of the second inverter INV2. The output terminal of the second inverter INV2 is connected to the input terminal of the third inverter INV3. The output terminal of the third inverter INV3 is used to output the BG_OK signal.

[0046] When the final reference voltage VBG output by the core circuit 10 is less than the preset value, the BG_OK signal is a low-level signal; when the reference voltage VBG is higher than the preset value, the BG_OK signal is a high-level signal, which is used to enable subsequent related circuits.

[0047] This embodiment also discloses a chip, including the above-described bandgap reference circuit.

[0048] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A bandgap reference circuit, characterized in that, include: First MOSFET, first transistor, second transistor, first resistor, second resistor, third resistor, amplifier, and adjustable resistor unit; The source of the first MOSFET is connected to the power supply voltage. The drain of the first MOSFET is connected to the collector and base of the first transistor and the collector and base of the second transistor and is used to output a reference voltage. The emitter of the first transistor is connected to the first terminal of the third resistor and the first input terminal of the amplifier. The emitter of the second transistor is connected to the first terminal of the first resistor. The second terminal of the first resistor is connected to the second input terminal of the amplifier and the first terminal of the second resistor. The output terminal of the amplifier is connected to the gate of the first MOSFET. The second terminal of the third resistor and the second terminal of the second resistor are connected to the first terminal of the adjustable resistor unit. The second terminal of the adjustable resistor unit is connected to ground voltage. The adjustable resistor unit includes a fourth resistor and several resistor units, wherein the fourth resistor and the resistor units are connected in series. The bandgap reference circuit further includes a first capacitor, the first terminal of which is connected to the gate of the first MOS transistor, and the second terminal of which is connected to the drain of the first MOS transistor.

2. The bandgap reference circuit as described in claim 1, characterized in that, The resistor unit includes a fifth resistor and a second MOS transistor. The drain of the second MOS transistor is connected to the first end of the fifth resistor, the source of the second MOS transistor is connected to the second end of the fifth resistor, and the gate of the second MOS transistor is used to receive control signals.

3. The bandgap reference circuit as described in claim 1, characterized in that, The bandgap reference circuit also includes a startup circuit, which is used to switch the bandgap reference circuit from a degenerate state to a normal operating state.

4. The bandgap reference circuit as described in claim 3, characterized in that, The startup circuit includes an eighth resistor, a ninth resistor, a third MOSFET, and a fourth MOSFET; The first end of the eighth resistor and the first end of the ninth resistor are connected to the power supply voltage. The second end of the eighth resistor is connected to the gate of the third MOS transistor and the drain of the fourth MOS transistor. The second end of the ninth resistor is connected to the drain of the third MOS transistor. The gate of the fourth MOS transistor and the source of the third MOS transistor are connected to the collectors of the first transistor and the second transistor. The source of the fourth MOS transistor is connected to the ground voltage.

5. The bandgap reference circuit as described in claim 1, characterized in that, The bandgap reference circuit also includes a filter circuit, which is used to filter the reference voltage.

6. The bandgap reference circuit as described in claim 1, characterized in that, The bandgap reference circuit also includes a BG_OK generation circuit, which is used to output a BG_OK signal when the reference voltage is higher than a preset value.

7. The bandgap reference circuit as described in claim 6, characterized in that, The BG_OK generation circuit includes a tenth resistor, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, a first inverter, a second inverter, and a third inverter; The gates of the fifth and sixth MOS transistors are connected to receive a reference voltage. The first terminal of the tenth resistor is connected to the power supply voltage. The second terminal of the tenth resistor is connected to the input terminal of the first inverter and the drain of the fifth MOS transistor. The source of the fifth MOS transistor is connected to the drain of the sixth and seventh MOS transistors. The sources of the sixth and seventh MOS transistors are connected to ground. The output terminal of the first inverter is connected to the gate of the seventh MOS transistor and the input terminal of the second inverter. The output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is used to output the BG_OK signal.

8. A chip, characterized in that, include: The bandgap reference circuit as described in any one of claims 1 to 7.

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