Waveform Output Method and Related Device Based on Dual-RAM Reading of FPGA and SDRAM

Abstract

In an embodiment of the present invention, a waveform output method based on dual-RAM reading of FPGA and SDRAM is provided. By utilizing the non-self-refresh characteristic of the internal RAM resources of the FPGA, this method first reads out a part of the previous data and gives it to the DAC, and at the same time caches the data of the SDRAM into the FIFO inside the FPGA, and then reads the subsequent data from the FIFO and splices it to the DAC output; thus, waveform instant output can be achieved. At the same time, since the number of data points cached in the FIFO is always greater than the number of data points interrupted by the self-refresh of the SDRAM, the waveform can be guaranteed to be continuous, and it can meet the high synchronization and low latency requirements of Qubit manipulation.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum measurement and control, and particularly relates to a waveform output method and related device based on dual-RAM reading of FPGA and SDRAM. Background Art

[0002] Quantum computing utilizes basic principles such as the superposition and coherence of quantum states to perform exponential parallel operations. For example, if there are N ideal Qubits, 2^N parallel operations can be achieved. Quantum computing is expected to solve some application problems that are currently difficult or impossible to complete with classical computing, such as the Shor algorithm for prime factorization, etc., and has broad application prospects in the fields of information security, finance, medicine, materials, etc.

[0003] Taking superconducting quantum computing as an example, several Qubits are integrated on a superconducting quantum bit chip. By precisely adjusting the frequency, amplitude, and phase of the microwave pulses input to the chip, the Qubits can be controlled to be in any quantum state, and by collecting and analyzing the information carried by the detection microwave pulses, the current quantum state can be measured. However, since a Qubit is an artificial two-level quantum system, the lifetime of the quantum state is extremely short, and the quantum state is very fragile and extremely vulnerable to interference such as thermal noise and environmental coupled electromagnetic radiation. Therefore, in order to operate the Qubit to quickly maintain it in a definite state, it is necessary to collect, process, and judge the measurement results within an extremely short time and quickly generate correction microwave pulses. During this process, it is necessary to read relevant waveform data through the FPGA and transmit it to the DAC, and the DAC directly outputs the waveform to the Qubit or the DAC combines with the RF radio frequency unit to output the waveform to the Qubit. If the waveform data is stored in an external SDRAM device, due to the self-refresh problem of the SDRAM device, in order to avoid interruption of the output waveform, after the start signal arrives, N points need to be read into the FIFO first (the value of N is equal to the self-refresh time t, the memory bit width width, and the user clock userclk), and then the data is output to the DAC. That is, there is a delay of N points from the start signal to the DAC output waveform, which is difficult to meet the low-delay requirements of Qubit feedback control. When facing the scenario of multi-channel waveform output, due to the uncertainty of the refresh time between different SDRAM devices, it will bring great uncertainty to the synchronization of multi-channel waveform output. And when storing the waveform data in the internal storage block of the FPGA, although there is no self-refresh problem of the SDRAM device, the space of the internal storage block of the FPGA is limited and cannot be fully used to store waveform files, resulting in limited waveform file size and directly affecting the control of Qubits.

[0004] Therefore, there is a need to design a waveform data storage and reading solution that can meet the high synchronization and low latency requirements for Qubit control. Summary of the Invention

[0005] In view of the deficiencies of the above-mentioned prior art, the object of the present invention is to provide a waveform output method based on dual-RAM reading of FPGA and SDRAM. By utilizing the non-self-refresh characteristic of the internal RAM resources of the FPGA, a part of the data in the front is first read out and given to the DAC, and at the same time, the data in the SDRAM is cached into the internal FIFO of the FPGA for caching, and then the data in the back is read from the FIFO and spliced to the DAC output. Therefore, waveform instant output can be realized. At the same time, since the number of data points cached in the FIFO is always greater than the number of data points interrupted by the self-refresh of the SDRAM, the waveform can be ensured to be continuous, and it can meet the high synchronization and low latency requirements for Qubit control.

[0006] In the first aspect of the present invention, there is provided a waveform output method based on dual-RAM reading of FPGA and SDRAM, which includes:

[0007] Configuring the FPGA to write the received waveform file completely into the external SDRAM, and writing the first n data points of the received waveform file into the RAM resources inside the FPGA; where n ≤ N, and N is the number of data points interrupted by the DAC reception during the self-refresh of the SDRAM;

[0008] Configuring the FPGA to, after receiving a trigger signal, sequentially read the first n data points of the waveform file stored in the RAM resources and output them to the DAC, and sequentially read the data of the waveform file starting from the (n + 1)-th data point stored in the SDRAM and output them to the internal FIFO of the FPGA for caching;

[0009] And, configuring the FPGA to, when detecting that the first n data points of the waveform file have been read, read the data cached in the FIFO and output it to the DAC, and when detecting that the number of data points cached in the FIFO is lower than a preset value, sequentially read the data in the SDRAM that has not been cached in the FIFO and output it to the FIFO for caching, so that the number of data points cached in the FIFO is always greater than N.

[0010] According to a specific embodiment, the waveform output method based on dual-RAM reading of FPGA and SDRAM provided by the present invention includes: configuring the FPGA to, after receiving a trigger signal, if the number of data points of the waveform file does not exceed N, only read the data points stored in the RAM resources and output them to the DAC.

[0011] According to a specific embodiment, the waveform output method based on dual-RAM reading of FPGA and SDRAM provided by the present invention includes: configuring the FPGA to generate a first status indication signal and a first enable signal; wherein, if there is data stored in the RAM resource to be output to the DAC, the first status indication signal is valid; the first enable signal is obtained by inverting the first status indication signal and ANDing it with the non-empty flag signal of the FIFO; if the first enable signal is valid, the data cached in the FIFO is read and output to the DAC.

[0012] According to a specific embodiment, the waveform output method based on dual-RAM reading of FPGA and SDRAM provided by the present invention includes: configuring the write bandwidth of the SDRAM to the FIFO to be at least 2 times the read bandwidth of the DAC from the FIFO, and the depth of the FIFO to be at least 2N.

[0013] In a second aspect of the present invention, a waveform generating device is provided, which includes:

[0014] A DAC unit configured to generate a corresponding waveform signal according to the input waveform data;

[0015] An SDRAM unit configured to store waveform files;

[0016] An FPGA unit configured to write the received waveform file completely into the SDRAM unit, and write the first n data points of the received waveform file into the RAM resource inside the FPGA unit; where n ≤ N, and N is the number of data points received by the DAC unit during the self-refresh of the SDRAM unit; and sequentially read the first n data points of the waveform file stored in the RAM resource and output them to the DAC unit, and sequentially read the data of the waveform file stored in the SDRAM unit starting from the (n + 1)-th data point and output them to the FIFO inside the FPGA for caching; and when it is detected that the first n data points of the waveform file have been read, read the data cached in the FIFO and output it to the DAC unit, and when it is detected that the number of data points cached in the FIFO is lower than a preset value, sequentially read the data of the waveform file stored in the SDRAM unit that has not been cached in the FIFO and output it to the FIFO for caching, so that the number of data points cached in the FIFO is always greater than N.

[0017] According to a specific embodiment, in the waveform generating device provided by the present invention, the FPGA unit is further configured to, after receiving a trigger signal, if the number of data points of the waveform file does not exceed N, only read the data points stored in the RAM resource and output them to the DAC unit.

[0018] According to a specific embodiment, in the waveform generating device provided by the present invention, the FPGA unit is further configured to generate a first status indication signal and a first enabling signal; wherein, if there is data stored in the RAM resource output to the DAC, the first status indication signal is valid; the first enabling signal is obtained by inverting the first status indication signal and ANDing it with the non-empty flag signal of the FIFO; if the first enabling signal is valid, the data cached in the FIFO is read out and output to the DAC.

[0019] According to a specific embodiment, in the waveform generating device provided by the present invention, the write bandwidth of the SDRAM unit to the FIFO is at least twice the read bandwidth of the DAC unit to the FIFO, and the depth of the FIFO is at least 2N.

[0020] According to a specific embodiment, in the waveform generating device provided by the present invention, the FPGA unit is further configured to, when receiving a waveform file, cache and output the data points of the received waveform file through a FIFO, and then write them into the SDRAM unit and the RAM resource respectively.

[0021] In a third aspect of the present invention, a quantum measurement and control system is provided, which includes:

[0022] At least one waveform generating device provided in the second aspect of the present invention;

[0023] A trigger source for providing a trigger signal to each of the waveform generating devices respectively;

[0024] A host computer for sending a waveform file to each of the waveform generating devices.

[0025] Compared with the prior art, the beneficial effects of the present invention are:

[0026] Based on the waveform output method of double RAM reading of FPGA and SDRAM, the present invention first reads out a part of the data in front and gives it to the DAC by using the non-self-refresh characteristic of the RAM resource inside the FPGA, and at the same time caches the data in the SDRAM into the FIFO inside the FPGA for caching, and then reads the subsequent data from the FIFO and splices it to the DAC output; thus, real-time waveform output can be realized, and at the same time, since the number of data points cached in the FIFO is always greater than the number of data points interrupted by the self-refresh of the SDRAM, the waveform can be guaranteed to be continuous, and it can meet the high synchronization and low latency requirements of Qubit control. Description of the Drawings

[0027] Figure 1 It is a schematic flowchart of the FPGA receiving a waveform file provided in the embodiment of the present invention;

[0028] Figure 2Schematic diagram of the process for an FPGA to read a waveform file provided in an embodiment of the present invention;

[0029] Figure 3 Timing relationship diagram provided in an embodiment of the present invention;

[0030] Figure 4 Schematic diagram of the structure of a waveform generating device provided in an embodiment of the present invention;

[0031] Figure 5 Schematic diagram of the internal structure of an FPGA provided in an embodiment of the present invention;

[0032] Figure 6 Schematic diagram of the internal structure of an FPGA provided in another embodiment of the present invention;

[0033] Figure 7 Schematic diagram of the structure of a quantum measurement and control system provided in an embodiment of the present invention. Detailed implementation manners

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. However, this should not be construed as limiting the scope of the above-mentioned subject matter of the present invention to the following embodiments. Any technology implemented based on the content of the present invention belongs to the scope of the present invention.

[0035] In an embodiment of the present invention, a waveform output method based on dual-RAM reading of an FPGA and an SDRAM is provided, which includes:

[0036] Configure the FPGA to write the received waveform file completely into an external SDRAM, and write the first n data points of the received waveform file into the RAM resource inside the FPGA; where n ≤ N, and N is the number of data points received by the DAC during self-refresh of the SDRAM;

[0037] Configure the FPGA to, after receiving a trigger signal, sequentially read the first n data points of the waveform file stored in the RAM resource and output them to the DAC, and sequentially read the data of the waveform file starting from the (n + 1)-th data point stored in the SDRAM and output them to the FIFO inside the FPGA for caching;

[0038] And, configure the FPGA to, when detecting that the first n data points of the waveform file have been read, read the data cached in the FIFO and output it to the DAC, and when detecting that the number of data points cached in the FIFO is lower than a preset value, sequentially read the data not cached in the FIFO and stored in the SDRAM and output it to the FIFO for caching, so that the number of data points cached in the FIFO is always greater than N.

[0039] In this embodiment, the above configuration of the FPGA is performed through Verilog HDL, enabling the FPGA to jointly implement the corresponding data writing and reading processes with the SDRAM and DAC respectively, and finally generating a waveform determined by the waveform file through the DAC.

[0040] Since the internal RAM resources of the FPGA include BRAM and other DRAMs that can be formed by logic blocks, in this embodiment, taking the BRAM in the internal RAM resources of the FPGA and the SDRAM device using DDR4 as an example, the self-refresh time is 100 data clock cycles, that is, t = 100, the memory bit width width = 256 bit, the clock frequency userclk is 500 MHz, and the DAC has a 16-bit resolution. Therefore, the number of points interrupted during the self-refresh of the SDRAM device is: N = t * width / 16; then, N = 1600.

[0041] As Figure 1 shown, the control process for the FPGA to receive the waveform file is as follows: After establishing an Ethernet network connection between the FPGA and the host computer, the FPGA receives the waveform file sent by the host computer; the FPGA configures itself into a FIFO storage unit with a FIFO interface by invoking internal RAM resources, logic block resources and other storage resources to cache the waveform data. At the same time, the waveform data is written into the BRAM and DDR4.

[0042] Among them, when writing to the BRAM, if the number of data points File_num in the waveform file is less than 1600, continuously judge whether the write address WR_ADDR of the BRAM is less than File_num. If it is less than File_num, increment the write address WR_ADDR of the BRAM by one, otherwise the BRAM write ends; in addition, if the number of data points File_num in the waveform file is greater than or equal to 1600, continuously judge whether the write address WR_ADDR of the BRAM is less than 1600. If it is less than 1600, increment WR_ADDR by one, otherwise the BRAM write process ends;

[0043] When writing to the DDR4, judge whether the write address WR_ADDR of the DDR4 is less than File_num. If it is less than File_num, increment the write address WR_ADDR of the DDR4 by one, otherwise the DDR4 write process ends;

[0044] As Figure 2 shown, the control process for the FPGA to read the waveform data is as follows: Continuously judge whether a trigger signal is received in real time. If a trigger signal is received, read the waveform data from the BRAM and DDR4 simultaneously.

[0045] Among them, the waveform data read by the BRAM is directly output to the DAC. If the number of data points File_num in the waveform file is less than 1600, it continuously judges whether the read address RD_ADDR of the BRAM is less than File_num. If it is less than File_num, the read address RD_ADDR of the BRAM is incremented by one, otherwise the entire waveform output process ends. Additionally, if the number of data points File_num in the waveform file is greater than or equal to 1600, it continuously judges whether the read address RD_ADDR of the BRAM is less than 1600. If it is less than 1600, RD_ADDR is incremented by one, otherwise the BRAM reading process ends;

[0046] While reading the BRAM, waveform data is read from the DDR4. If the number of data points File_num in the waveform file is less than 1600, the entire waveform output process can be directly achieved by reading the waveform data through the BRAM. In this case, there is no need for the DDR4 to perform the reading operation. Generally, however, the number of data points in the waveform file is definitely greater than 1600. When the DDR4 is performing the reading operation, although the entire waveform file data is written into the DDR4, since the waveform data read by the BRAM is directly output to the DAC and the first part of the waveform is generated first, the initial read address RD_ADDR of the DDR4 is assigned 1600, then the read length is set to File_num - 1600, and the waveform data read from the DDR4 is automatically output to the FIFO for caching. Then, it judges whether the FIFO is non-empty. If it is non-empty, it detects whether the BRAM reading is completed. If the BRAM reading is completed, the waveform data is output from the FIFO to the DAC to generate the subsequent waveform.

[0047] Meanwhile, during the process of the FIFO continuously outputting waveform data, when it is detected that the number of data points cached in the FIFO is lower than the preset value, the DDR4 is triggered to read data and output it to the FIFO, so that the number of data points cached in the FIFO is always greater than N.

[0048] In this embodiment, the write bandwidth of the SDRAM to the FIFO is configured to be at least twice the read bandwidth of the DAC to the FIFO, and the depth of the FIFO is at least 2N. In this way, it can be ensured that the data cached in the FIFO can always meet the reading of the FIFO, avoiding the occurrence of waveform interruption. At the same time, the depth of the FIFO is at least 2N, and even if the SDRAM has a self-refresh at any time, the occurrence of waveform interruption can be avoided.

[0049] In order to ensure that the data directly output from the BRAM reading and the data read from the DDR4 and output through the FIFO can be accurately spliced, precise timing control needs to be ensured. Therefore, provided as Figure 3The timing diagram shown; configure the FPGA to generate a first status indication signal BRAM_data_valid and a first enable signal FIFO_data_valid; wherein, if there is data stored in the BRAM output to the DAC, the first status indication signal is valid BRAM_data_valid; the first enable signal FIFO_data_valid is obtained by inverting the first status indication signal BRAM_data_valid and ANDing it with the non-empty flag signal of the FIFO. If the first enable signal is valid, read the data cached in the FIFO and output it to the DAC; thus avoiding the situation where the FIFO is emptied and causing waveform interruption, so that the DA_data input data is continuous, and thus the waveform output by the DAC is also continuous.

[0050] Therefore, the waveform output method based on dual-RAM reading of FPGA and SDRAM of the present invention, by utilizing the non-self-refresh characteristic of the RAM resources inside the FPGA, first reads out a part of the previous data and gives it to the DAC, and at the same time caches the data of the SDRAM into the internal FIFO of the FPGA for caching, and then reads the subsequent data from the FIFO and splices it to the DAC output; thus, real-time waveform output can be achieved. At the same time, since the number of data points cached in the FIFO is always greater than the number of data points interrupted by the self-refresh of the SDRAM, the waveform can be guaranteed to be continuous, and it can meet the high synchronization and low latency requirements of Qubit control.

[0051] In one embodiment, there is provided a waveform generating device 100 as shown in Figure 4 and it includes:

[0052] A DAC 130 configured to generate a corresponding waveform signal according to the input waveform data;

[0053] An SDRAM 120 configured to store waveform files;

[0054] An FPGA 110 configured to include:

[0055] A write control unit 111 for completely writing the received waveform file into the SDRAM 120 and writing the first n data points of the received waveform file into the internal BRAM 114 of the FPGA; wherein, n ≤ N, and N is the number of data points interrupted by the DAC 130 during the self-refresh of the SDRAM 120;

[0056] A read control unit 112, which is configured to, after receiving a trigger signal (i.e., a waveform playback signal), sequentially read the first n data points of the waveform file stored in the BRAM 114 and output them to the DAC, and sequentially read the data of the waveform file starting from the (n + 1)-th data point stored in the SDRAM 120 and output them to the FIFO 115 inside the FPGA for caching;

[0057] A FIFO control unit 113, which is configured to, when detecting that the first n data points of the waveform file have been read, read the data cached in the FIFO 115 and output them to the DAC 130, and when detecting that the number of data points cached in the FIFO 115 is lower than a preset value, sequentially read the unread data stored in the SDRAM 120 and output them to the FIFO 115 for caching, so that the number of data points cached in the FIFO 115 is always greater than N.

[0058] Specifically, when the BRAM and FIFO resources inside the FPGA 110 meet the actual conditions, by setting corresponding storage addresses for different DACs, the waveform data corresponding to different DACs can be independently read, thereby realizing multi-channel waveform output.

[0059] In this embodiment, the FPGA 110 is further configured to, after receiving a trigger signal (i.e., a waveform playback signal), if the number of data points of the waveform file does not exceed N, only read the data points stored in the BRAM and output them to the DAC unit. Actually, since the waveform file is small, the data can be directly cached by the BRAM.

[0060] In this embodiment, the FPGA 110 is further configured to generate a first status indication signal and a first enable signal; among them, when the read control unit 112 controls to read the data of the BRAM 114 and output them to the DAC 130, if there is data stored in the BRAM 114 output to the DAC 130, the generated first status indication signal is valid; at the same time, the FIFO control unit 113 obtains the first enable signal by taking the inverse of the first status indication signal and ANDing it with the non-empty flag signal of the FIFO 115; if the first enable signal is valid, the FIFO control unit 113 controls to read the data cached in the FIFO 115 and output them to the DAC 130. In this way, the situation that the FIFO is emptied and causes waveform interruption is avoided, so that the data input to the DAC is continuous, and thus the waveform output by the DAC is also continuous.

[0061] In this embodiment, the write bandwidth of the SDRAM 120 to the FIFO 115 is at least twice the read bandwidth of the DAC 130 to the FIFO 115, and the depth of the FIFO is at least 2N.

[0062] In another embodiment, the FPGA 110 is further configured to, when receiving a waveform file, cache the data points of the received waveform file through a FIFO 116 and then write them into the SDRAM 120 and the BRAM 114 respectively after output.

[0063] In one embodiment, there is provided a quantum measurement and control system as Figure 7 shown, which includes:

[0064] At least one waveform generating device 100 provided in the embodiments of the present invention;

[0065] A trigger source 200 for providing a trigger signal to each of the waveform generating devices 100;

[0066] A host computer 300 for sending a waveform file to each of the waveform generating devices 100.

[0067] In this embodiment, the host computer 300 communicates with each waveform generating device 100 through a switch 400 to send the corresponding waveform file to each waveform generating device 100. The trigger source 200 is directly connected to each waveform generating device 100 to transmit a trigger signal (i.e., a waveform playback signal). Combining with Figure 4 , the host computer 300 is communicatively connected to the FPGA 110 in the waveform generating device 100 through the switch 400, and the FPGA 110 is communicatively connected to the switch 400 through a configured Ethernet network interface.

[0068] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A waveform output method based on dual-RAM reading of FPGA and SDRAM, characterized in that Comprising: Configuring the FPGA to write the received waveform file completely into an external SDRAM, and write the first n data points of the received waveform file into the RAM resource inside the FPGA; where n ≤ N, and N is the number of data points received by the DAC during self-refresh of the SDRAM; Configuring the FPGA to, after receiving a trigger signal, sequentially read the first n data points of the waveform file stored in the RAM resource and output them to the DAC, and sequentially read the data of the waveform file stored in the SDRAM starting from the (n + 1)-th data point and output them to the FIFO inside the FPGA for caching; And, configuring the FPGA to, when detecting that the first n data points of the waveform file have been read, read the data cached in the FIFO and output it to the DAC, and when detecting that the number of data points cached in the FIFO is lower than a first preset value, sequentially read the data stored in the SDRAM that has not been cached in the FIFO and output it to the FIFO for caching, so that the number of data points cached in the FIFO is always greater than N.

2. The waveform output method based on dual-RAM reading of FPGA and SDRAM according to claim 1, wherein Comprising: Configuring the FPGA to generate a first status indication signal and a first enable signal; where, if there is data stored in the RAM resource output to the DAC, the first status indication signal is valid; the first enable signal is obtained by taking the inverse of the first status indication signal and ANDing it with the non-empty flag signal of the FIFO; if the first enable signal is valid, read the data cached in the FIFO and output it to the DAC.

3. The waveform output method based on dual-RAM reading of FPGA and SDRAM according to claim 2, wherein, Comprising: Configuring the FPGA to generate a second status indication signal; where, if the amount of data cached in the FIFO reaches a second set value, the second status indication signal is valid; If the second status indication signal is valid, pause reading the data stored in the SDRAM and output it to the FIFO for caching.

4. The waveform output method based on dual-RAM reading of FPGA and SDRAM according to claim 1, wherein Configuring the write bandwidth of the SDRAM to the FIFO to be at least 2 times the read bandwidth of the DAC from the FIFO, and the depth of the FIFO to be at least 2N.

5. A waveform generating device, characterized in that, Comprising: A DAC configured to generate a corresponding waveform signal according to the input waveform data; An SDRAM configured to store a waveform file; An FPGA configured to include: A write control unit for writing the received waveform file completely into the SDRAM, and writing the first n data points of the received waveform file into the RAM resource inside the FPGA; where n ≤ N, and N is the number of data points received by the DAC unit during self-refresh of the SDRAM; A read control unit for, after receiving a trigger signal, sequentially reading the first n data points of the waveform file stored in the RAM resource and outputting them to the DAC, and sequentially reading the data of the waveform file stored in the SDRAM starting from the (n + 1)-th data point and outputting them to the FIFO inside the FPGA for caching; A FIFO control unit, which is configured to read the data cached in the FIFO and output it to the DAC when it detects that the first n data points of the waveform file have been read, and when it detects that the number of data points in the FIFO cache is lower than a preset value, sequentially read the unread data stored in the SDRAM and output it to the FIFO for caching, so that the number of data points cached in the FIFO is always greater than N.

6. The waveform generating device according to claim 5, characterized in that, The FPGA is further configured to, after receiving a trigger signal, if the number of data points of the waveform file does not exceed N, only read the data points stored in the RAM resource and output them to the DAC unit.

7. The waveform generating device according to claim 5, wherein The FPGA is further configured to generate a first status indication signal and a first enable signal; wherein, if there is data stored in the RAM resource output to the DAC, the first status indication signal is valid; the first enable signal is obtained by inverting the first status indication signal and ANDing it with the non-empty flag signal of the FIFO; if the first enable signal is valid, read the data cached in the FIFO and output it to the DAC.

8. A waveform generating device according to claim 5, characterized in that, The write bandwidth of the SDRAM to the FIFO is at least twice the read bandwidth of the DAC unit to the FIFO, and the depth of the FIFO is at least 2N.

9. A waveform generating device according to claim 5, characterized in that, The FPGA unit is further configured to, when receiving a waveform file, after caching and outputting the data points of the received waveform file through a FIFO, write them into the SDRAM unit and the RAM resource respectively.

10. A quantum measurement and control system, characterized in that, Comprising: At least one waveform generating device according to any one of claims 5 to 9; A trigger source, which is configured to provide a trigger signal for each of the waveform generating devices respectively; A host computer, which is configured to send a waveform file to each of the waveform generating devices.

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