CGRA-oriented multi-precision small-area simd operation system, method, medium and device

Abstract

The application provides a CGRA-oriented multi-precision small-area SIMD operation system, method, medium and equipment, which comprises an encoding module, an accumulation module and an overflow processing module, the encoding module is composed of an encoding unit, a selector and a decoding selection unit, an encoding operation is performed based on a Booth algorithm, and decoding of data is performed based on mode selection to obtain a partial product result; the accumulation module is composed of multiple partial product compression blocks, and partial product compression results of different blocks are summed and spliced based on mode selection; and the overflow processing module performs overflow processing on the result of the accumulation module to obtain final truncated data. The working precision of the application can be configured, can support high-speed deployment work of current mainstream 32-bit and 8-bit neural network applications, has high resource utilization, and through three-stage pipelining, the data operation processing is ensured at a working frequency of 1GHz.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, in particular to a CGRA-oriented multi-precision small-area SIMD operation system, method, medium and equipment. BACKGROUND

[0002] Reconfigurable computing CGRA belongs to a class of coarse-grained heterogeneous reconfigurable architecture, and its basic unit is PE, LSE, LC and LSU, wherein the PE processes coarse-grained arithmetic operations and is a configurable processing unit to adapt to different application scenarios and can flexibly deal with general calculations such as Fast Fourier transform (FFT).

[0003] SIMD stands for Single Instruction Multiple Data, which can copy multiple operands and pack them in a set of instructions in a large register.

[0004] In order to improve the computing utilization of the computing unit, a special low-precision computing unit is often designed, and high-precision calculation is performed through combination, that is, a high-precision multiplier (32 bits) is decomposed into several low-precision multipliers (8 bits), and the computing unit can be configured to different computing precisions.

[0005] The basic computing unit is composed of partial product generation, partial product compression and carry propagation adder. The specific implementation of the three parts is also various. The commonly used method for generating partial products is AND gate operation, Baugh-Wooley algorithm and Booth algorithm, wherein the Booth algorithm reduces the number of generated partial products through coding, greatly reducing the area, power consumption and delay of subsequent compression logic. The commonly used means of partial product compression is array multiplier and tree multiplier, wherein Wallace tree as a typical tree multiplier has become a commonly used technology due to low delay and high wiring resource demand. The carry propagation adder as the last step of the multiplier plays a crucial role in the delay. For the optimization of the adder, the commonly used methods are traveling wave carry adder and advanced carry adder.

[0006] Patent document CN113794552A (application number: CN202111074292.X) discloses a SIMD-based SM3 parallel data encryption operation method and system, a plurality of to-be-processed data are obtained; if each piece of to-be-processed data is equal in length, the to-be-processed data are grouped, each group is equal in length, and a CF function operation is performed on the grouping; after completing a plurality of rounds of CF function operations, the last grouping is judged; if the data length is less than or equal to a first threshold value, a bit string representing the data length is placed at the end of the current grouping, and a last round of CF function operation is performed; if the data length is greater than the first threshold value, the CF function operation is first performed on the current grouping, the bit string representing the length is placed in the next grouping, and the CF function operation is performed again, until the final operation result is obtained.

[0007] Due to the different accuracies of different neural networks at present, the use of fixed-precision calculation units often leads to a large waste of computing resources and brings unnecessary additional cost overhead. Especially in resource-constrained ASIC design, how to design a configurable processing unit has become a problem to be solved. SUMMARY

[0008] In view of the defects in the prior art, the purpose of the present application is to provide a CGRA-oriented multi-precision small-area SIMD operation system, method, medium and equipment.

[0009] The CGRA-oriented multi-precision small-area SIMD operation system provided by the present application comprises an encoding module, an accumulation module and an overflow module.

[0010] The encoding module comprises an encoding unit, a selector Mux and a decoding selection unit Select.

[0011] The encoding unit is used to obtain S, D and N parameters through Booth encoding operation of the original multiplicand X.

[0012] The selector is used to select the data direction of the encoding module in different precision and sign modes.

[0013] The decoding unit is used to perform decoding operation on the obtained S, D and N parameters and the multiplier Y to obtain the partial product result of each row part.

[0014] The S, D and N parameters are the encoding results of the multiplicand X, wherein S represents 32-bit single-precision format Single, and the output result is ±1; D is 64-bit double-precision format Double, and the output result is ±2; N is negation, which represents the sign bit of the operation.

[0015] The accumulation module is used to accumulate the multiplication partial product and the multiplication result after encoding according to a preset timing.

[0016] The overflow processing module is used to perform low-order truncation, high-order truncation and saturation truncation according to preset rules.

[0017] Preferably, in the coding unit, X is the multiplicand, Y is the multiplier, and the expression of the Single signal is X 2i-1 ^X 2i ; The expression of Double signal is ~(~(X 2i-1 &X 2i &~X wi+1 )&~(~X 2i-1 &~X 2i &X 2i ); Negation signal is ~X 2i+1 ;

[0018] The Booth algorithm of base-4 is selected. For the encoding module, the multiplicand X is encoded every 3 bits. The parameter i is introduced to represent the number of data groups. Each group of data is represented as X 2i+1 、X 2i 、X 2i-1 , the value range is 0, 1, 2 and 3, a total of four integers, when i = 0, X -1 =0.

[0019] Preferably, the selector is a 2to1 selector.

[0020] Preferably, the input signal of the decoding unit is a combination of S, D, N and multiplier Y, and a 32-bit Booth multiplication operation is multiplexed with four 8-bit Booth multiplication operations. In the 8-bit Booth operation, a selector is provided at the boundary coding unit to select whether to perform a 32-bit operation.

[0021] Preferably, the process of generating partial products by the encoding module is:

[0022] After the data direction is selected by the selector, the data is grouped, and then the encoding results S, D and N parameters and the multiplier Y are put into the decoding module to obtain the partial product PP. The parameter j is introduced to represent each bit of the partial product PP, where j is an integer from 0 to 7.

[0023] The relationship between the partial product PP and the encoding result and the multiplier Y is expressed as: PP j =~(~(Y j &D)&~(Y j-1 &S))^N, where PP0=~(S&Y0)^N.

[0024] Preferably, the partial integrals generated by the encoding module are divided into 8 parts, wherein Part 1, 2, 5 and 6 are all single accumulation units for generating 8-bit multiplication results, and Part 3 and 7 and Part 4 and 8 are cut blocks for pipeline;

[0025] For the low 32-bit output result, first, the corresponding 17-bit and 23-bit accumulation results generated by Part 1, 2 and 3 are added together with Part 4 to generate a 36-bit output result, and finally the mode is determined according to the control signal:

[0026] If it is an 8-bit multiplication mode, the 16-bit results of Part 1 and 2 are spliced to generate a 32-bit result;

[0027] If it is a 32-bit multiplication mode, the low 32-bit result of the 32-bit multiplier is taken from the low 32 bits of the generated 36-bit output result, and the remaining high 4 bits are used as the carry for the high 32-bit output result;

[0028] For the high 32-bit output result, the corresponding 17-bit and 26-bit accumulation results generated by Part 5, 6 and 7 are added together with Part 8 and the 4-bit number from the low 32-bit output result to generate a 32-bit accumulation result, and finally the mode is determined according to the control signal:

[0029] If it is an 8-bit multiplication mode, the 16-bit results of Part 3 and 4 are spliced to generate a 32-bit result;

[0030] If it is a 32-bit multiplication mode, the high 32-bit result of the 32-bit multiplier is taken from the generated 32-bit output result;

[0031] The 32-bit numbers generated by the low 32-bit output result and the high 32-bit output result are directly spliced to generate a 64-bit result, which is the output result of the 32-bit multiplier.

[0032] Preferably, the low bit truncation: for 32-bit operation, the low 32 bits are reserved, and for 8-bit operation, the low 8 bits are reserved;

[0033] The high bit truncation: for 32-bit operation, the high 32 bits are reserved, and for 8-bit operation, the high 8 bits are reserved;

[0034] The saturation truncation: for 32-bit operation and 8-bit operation, it is divided into signed and unsigned, positive and negative saturation truncation. Unsigned overflow only needs to judge whether the high bit is 1 or not, if it is 1, then overflow; signed positive overflow judges whether the high bit is 1 or not, if it is 1, then overflow; signed negative overflow judges whether the high bit is 0 or not, if it is 0, then overflow.

[0035] The CGRA-oriented multi-precision small-area SIMD operation method comprises the following steps:

[0036] Step 1: after a group of input data and mode selection data are input, signals S, D and N required by the current group of data Select are generated by working of 16 encoders;

[0037] Step 2: all encoding units corresponding to the low 32 bits of the output start to work, input quantities are S, D and N and the multiplier input data of the current group, the result of the decoding selection is put into the accumulation unit to be accumulated, and finally the output result is 36-bit data, wherein the high 4-bit data is used as the addition of the next period, and the low 32 bits are the low 32-bit data corresponding to the 32-bit multiplier;

[0038] Step 3: the multiplier B in the input data, all control signals, the signals S / D / N obtained in step 1, the 36-bit data obtained in step 2 and the addend C are put into the register to be cached, and the first time period is ended;

[0039] Step 4: the cached S / D / N and the multiplier B are used as input data of the high 32-bit encoding unit to obtain the corresponding result;

[0040] Step 5: the cached S / D / N, the multiplier B and the high 4-bit data of the 36-bit data are put into the accumulation unit to be accumulated, and finally the high 32-bit data is obtained;

[0041] Step 6: all control signals in step 3, the addend C, the low 32-bit data in the 36-bit data and the high 32-bit data obtained in step 5 are put into the register to be cached, and the second time period is ended;

[0042] Step 7: the low 32-bit data and the high 32-bit data cached in step 6 are spliced to obtain 64-bit output data of the 32-bit multiplier, the addend C is accumulated according to the control signals cached in step 6, and 64-bit result is obtained;

[0043] Step 8: the 64-bit result obtained in step 7 is overflowed according to the control signals cached in step 6, an overflow mode is selected, and finally 32-bit output result is obtained.

[0044] The computer readable storage medium storing the computer program provided by the application, when the computer program is executed by the processor, the steps of the CGRA-oriented multi-precision small-area SIMD operation method are realized.

[0045] The application provides an electronic device, which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, and the computer program is used for realizing the steps of the CGRA-oriented multi-precision small-area SIMD operation method when the processor executes the computer program.

[0046] Compared with the prior art, the application has the following beneficial effects:

[0047] (1) The working precision of the application can be configured, and the application can support the high-speed deployment work of the current mainstream 32-bit and 8-bit neural network application, has high resource utilization, and in addition, the application performs data operation processing through a three-stage pipeline mode, and ensures a working frequency of 1GHz.

[0048] (2) The application is designed for the CGRA project design requirement, is based on an application-specific integrated circuit (ASIC), utilizes Booth algorithm and Wallace compression mode, and through control logic, satisfies multiple working modes, realizes multi-precision SIMD operation with multiple functions, high performance and low resource consumption. BRIEF DESCRIPTION OF DRAWINGS

[0049] Other characteristics, objects and advantages of the application will become more apparent through reading the following detailed description of the non-restrictive embodiments with reference to the accompanying drawings:

[0050] Figure 1 Fig. 1 is a schematic diagram of the overall structure of a circuit;

[0051] Figure 2 Fig. 2 is a schematic diagram of the structure of an encoding module;

[0052] Figure 3 Fig. 3 is a schematic diagram of the structure of a decoding module;

[0053] Figure 4 Fig. 4 is a schematic diagram of a partial product of a conventional 8-bit Booth unsigned multiplication operation;

[0054] Figure 5 Fig. 5 is a schematic diagram of a partial product of an optimized 8-bit Booth signed / unsigned multiplication operation;

[0055] Fig. 6 is a schematic diagram of a partial product structure; Figure 6a Fig. 7 is a schematic diagram of X0; Figure 6b Fig. 8 is a schematic diagram of X1; Figure 6c Fig. 9 is a schematic diagram of X6;

[0056] Figure 7 Fig. 10 is a schematic diagram of partial product block compression;

[0057] Figure 8 Fig. 11 is a flowchart of an overflow processing module;

[0058] Figure 9The accumulated module diagram is cut according to the flow. DETAILED DESCRIPTION

[0059] The application will be described in detail below with specific examples. The following examples will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the application. These are within the scope of the application.

[0060] Embodiment:

[0061] The application proposes a multi-precision small-area SIMD operation device based on Booth algorithm, and the overall structure of the circuit is as shown in Figure 1 The circuit mainly includes an encoding module, an accumulated module, an overflow processing module and a mode selection module.

[0062] 1. Encoding module

[0063] The encoding module is composed of an encoding (Encode) unit, a selector (Mux) and a decoding selection (Select) unit, and the structure of the encoding module is as shown in Figure 2 . Among them, X is the multiplicand, Y is the multiplier, the expression of Single signal is X 2i-1 ^X 2i , the expression of Double signal is ~(~(X 2i-1 &X 2i &~X wi+1 )&~(~X 2i-1 &~X 2i &X 2i ), and the Negative signal is ~X 2i+1 . The selector is a 2to 1 selector; the input signal of the decoding unit is composed of Single, Double, Negative and the multiplier Y, and the structure is as shown in Figure 3 .

[0064] In the application, the 8-bit signed / unsigned Booth multiplication is composed of Select and Mux units, and the 32-bit is based on 8-bit multiplication unit for multiplexing. Figure 4 is a partial product diagram of the traditional 8-bit Booth unsigned multiplication operation, Figure 5 is a partial product array diagram of the improved 8-bit multiplier. The structure of X2 is the same as that of X1, and the input pp 09 becomes pp 0_10 . The structure of X3 is the same as that of X1, and the three inputs are different, pp 09 becomes pp 0_11 , N0 is negated, and pp 08X4 is exactly the same as X0, X5 structure is similar to X3 structure, input from becomes X6 result is not affected by the sign bit, only switching between 32-bit and 8-bit operation. X7 is exactly the same as X0, X8 structure is similar to X5 structure, input from becomes X9 structure is similar to X6 structure, input from pp 0_10 becomes pp 2_10 , X0, X1 and X6 structure are shown in Figure 6a , Figure 6b , Figure 6c

[0065] In the encoding module, 32-bit Booth multiplication operation is multiplexed with 4 8-bit Booth multiplication operations. In the improved 8-bit Booth operation, the encoding unit at the boundary has a Mux to select whether to perform 32-bit operation. The design of the encoding module is compatible with signed and unsigned budget, and facilitates the SIMD operation to switch between 4 8-bit multiplication and 32-bit multiplication mode, reducing resource and power waste.

[0066] The Booth algorithm of base-4 is selected. For the encoding module, the multiplier X is encoded every 3 bits. Taking an 8-bit multiplier X as an example, X7, X6, X5, X4, X3, X2, X1 and X0 are used to represent the 8-bit multiplier X. Before encoding, the multiplier X is divided into X7, X6, X5; X5, X4, X3; X3, X2, X1 and X1, X0, 0, a total of four groups of data, each group of data consisting of 3 bits of data. In order to facilitate description, the parameter i is introduced to represent the group number of data, and each group of data is represented as X 2i+1 , X 2i , X 2i-1 , the value range is 0, 1, 2 and 3, a total of four integers, in particular, when i = 0, X -1 = 0.

[0067] 2, Accumulation module

[0068] The accumulation module is divided into encoding multiplication partial product accumulation and multiplication result accumulation. After the partial product is generated, it needs to be added and accumulated in blocks. In order to meet the timing requirements, the generated partial product also needs to be accumulated in a certain order.

[0069] After completing data grouping, there are four groups of data. Based on the correct data direction selected by the selector, the grouped data is used as the input of the encoding module, and the S, D and N signals corresponding to each group of data can be obtained, wherein the relationship between S, D and N and the multiplier X is: the expression of S signal is X 2i-1 ^X 2i ​, the expression of D signal is ~ (~ (X 2i-1 & X 2i & ~ X 2i+1 )& ~ (~ X 2i-1 & ~ X 2i & X 2i ), the N signal is ~ X 2i+1 Where i is the group number i in the supplement of question 2.

[0070] After completing the four groups of encoding process, the encoding results S, D and N signal and the multiplier Y are put into the decoding module to obtain four groups of partial products PP. Taking the first group of partial products as an example, Y is also an 8-bit data, which can be represented as Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0. After being put into the decoding module together with the encoding results, PP7, PP6, PP5, PP4, PP3, PP2, PP1, PP0 can be obtained. In order to facilitate description, parameter j is introduced to represent each bit of partial product PP, where j takes integer value of 0-7. The relationship expression of partial product PP, encoding result and multiplier Y is PP j = ~ (~ (Y j &D)& ~ (Y j-1 &S))^N, in particular, PP0 = ~ (S&Y0)^N. After passing through the four decoding modules, four groups of partial product data can be obtained.

[0071] In order to meet the timing requirements, the pipeline-based design puts forward certain requirements for the accumulation part. The entire multiplier is divided into Figure 7 , where Part1, 2, 5 and 6 are single accumulation units for generating 8-bit multiplication results, and Part3 and 7 as well as Part4 and 8 are cut and divided for meeting the pipeline.

[0072] The calculation sequence is shown in Figure 8 For the right half (low 32-bit output result), first, part1, 2 and 3 generate corresponding 17-bit and 23-bit accumulation results, which are accumulated together with part4 to generate 36-bit output result. Finally, the mode needs to be determined according to the control signal:

[0073] (1) If it is 8-bit multiplication mode, the results of part1 and 2 (each 16 bits) are spliced to generate 32-bit result;

[0074] (2) If it is 32-bit multiplication mode, the low 32 bits of the generated 36-bit output result are taken as the low 32-bit result of 32-bit multiplier (total 64 bits), and the remaining high 4 bits are taken as the carry, which is used as the addend of the left half (high 32-bit output result).

[0075] Next is the left half (high 32-bit output result) accumulation calculation, which is also the corresponding 17-bit and 26-bit accumulation results generated by parts 5, 6 and 7, and is accumulated with part 8 and the 4-bit number from the right half, to generate a 32-bit accumulation result, which also needs to be determined according to the control signal to determine the mode:

[0076] (1) If it is an 8-bit multiplication mode, the results (each 16-bit) of parts 3 and 4 are spliced to generate a 32-bit result;

[0077] (2) If it is a 32-bit multiplication mode, the generated 32-bit output result is the high 32-bit result (a total of 64 bits) of the 32-bit multiplier.

[0078] Finally, the 32-bit numbers generated by the left and right parts are directly spliced to generate a 64-bit result, which is the output result of the 32-bit multiplier, for input to the overflow processing module.

[0079] The multiplication result accumulation is commonly used for adding a 64-bit input to a 32-bit multiplication result, adding a 16-bit input to an 8-bit multiplication result, and adding a 16-bit multiplication accumulation number to four 8-bit multiplication results. The addition of two 8-bit numbers can be understood as one 8-bit multiplied by 1 plus one 8-bit input, and the addition of two 32-bit numbers can be understood as one 32-bit multiplied by 1 plus one 32-bit input. The addition operation can reuse the resources and control logic of the multiplication operation, reducing the complexity of the logic and saving resources.

[0080] 3. Overflow processing module

[0081] The overflow processing module includes low-bit truncation, high-bit truncation and saturation truncation, and the specific flowchart is as shown in Figure 8 The low-bit truncation is to retain the low 32 bits for 32-bit operation and retain the low 8 bits for 8-bit operation; the high-bit truncation is to retain the high 32 bits for 32-bit operation, at which time the high bits are slightly different due to the different bit widths of the 32-bit multiplication and 32-bit addition output results, and to retain the high 8 bits for 8-bit operation, and the high bits of the 8-bit multiplication and 8-bit addition are also slightly different; the saturation truncation needs to be divided into signed and unsigned saturation truncation for 32-bit operation and 8-bit operation, and the judgment flowchart is as shown in Figure 8 Unsigned overflow only needs to judge whether the high bits are 1 or not, if 1, overflow; signed positive overflow also judges whether the high bits are 1 or not; signed negative overflow judges whether the high bits are 0 or not, if 0, overflow.

[0082] 4. Pipeline control

[0083] Considering that both the 8-bit multiplication and the 33-bit adder challenge the timing of the 1GHz working frequency, the pipeline cutting position is particularly important.

[0084] The pipeline control mainly controls the data to be cached in the register by means of gate-level cut pipeline, ensures the entire multiplier to support the pipeline working mode, and improves the working efficiency. Figure 9 Through the pipeline control, the overall delay can be evenly distributed to each time period, which lays a foundation for satisfying the timing in subsequent synthesis work. The core content of the pipeline control is the overall timing control of the encoding module, the accumulation module and the overflow module.

[0085] The pipeline control flow of the control encoding module, the accumulation module and the overflow module is as follows:

[0086] (1) after a group of input data and mode selection data are input, 16 encoders start to work to generate the signals S, D and N required by the current group of data Select.

[0087] S, D and N represent the encoding results of the multiplicand X, that is, different operations to be performed on the multiplier Y, as shown in the following table, wherein S represents Single, that is, the output result is ±1; D is Double, that is, the output result is ±2; and N is Negation, representing the sign bit of the operation.

[0088] x 2i+1 x 2i x 2i-1 ]]> S D N OP 000 0 0 0 +0 001 1 0 0 +Y 010 1 0 0 +Y 011 0 1 0 +2Y 100 0 1 1 -2Y 101 1 0 1 -Y 110 1 0 1 -Y 111 0 0 1 -0

[0089] (2) all encoding units corresponding to the low 32 bits start to work, the input quantity is S, D and N in (1) and the multiplicand input data of the current group. The result of the decoding selection is put into the accumulation unit for accumulation, and the final output result is 36-bit data, wherein the high 4-bit data is used as the addition of the next period, and the low 32-bit data is the low 32-bit data corresponding to the 32-bit multiplier.

[0090] (3) the multiplier B in the input data, all control signals, S / D / N obtained in (1), 36-bit data obtained in (2) and the addend C are put into the register for caching, and the first time period of the current group of data ends.

[0091] (4) S / D / N and the multiplier B cached in (3) are used as the input data of the high 32-bit encoding unit to obtain the corresponding result.

[0092] (5) the data in (4) and the high 4-bit of the 36-bit data cached in (3) are put into the accumulation unit for accumulation, and the high 32-bit data is finally obtained.

[0093] (6) all control signals in (3), the addend C, the low 32-bit data in the 36-bit data, and the high 32-bit data obtained in (5) are put into the register for caching, and the second time period of the current group of data ends.

[0094] (7) The low 32-bit data and the high 32-bit data cached in (6) are spliced to obtain 64-bit output data of the 32-bit multiplier, and the accumulated value C is accumulated according to the control signal cached in (6) to obtain a 64-bit result.

[0095] (8) The 64-bit result obtained in (7) is overflow processed according to the control signal cached in (6), an overflow mode is selected, and a final 32-bit output result is obtained.

[0096] Among them, (1)-(3) are the first period, (4)-(6) are the second period, and (7)-(8) are the third period.

[0097] The present application has the following advantages:

[0098] (1) Good multiplexing. On the basis of being able to complete 32-bit, four groups of 8-bit signed / unsigned multiplication and addition operations, 32-bit and four groups of 8-bit signed / unsigned addition operations are also supported to support the existing neural network 4 8-bit multiplication result accumulation operation.

[0099] (2) Low resource consumption. The circuit structure of the present application is simple, only 300 FFs are used to realize the pipeline structure, and 33*16 decoding modules are used.

[0100] (3) Low delay, based on the 28nm library of Huali, the 1GHz working frequency requirement is realized.

[0101] (4) Support for multiple truncation mode applications in different actual scenarios, support for three high, low and saturation truncation modes.

[0102] (5) Regular structure, good back-end compatibility, and layout utilization rate can reach more than 85%.

[0103] Those skilled in the art know that, in addition to implementing the system, device and each module thereof provided by the present application in a pure computer readable program code manner, the same program can be realized in the form of logic gates, switches, special integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and each module thereof provided by the present application can be considered as a hardware component, and the modules included therein for realizing various programs can also be considered as structures within the hardware component; the modules for realizing various functions can also be considered as both software programs for realizing methods and structures within hardware components.

[0104] The specific embodiments of the present application are described above. It needs to be understood that the present application is not limited to the specific embodiments described above, and various changes or modifications can be made by those skilled in the art within the scope of the claims, which does not affect the essential content of the present application. The embodiments of the present application and the features in the embodiments can be combined with each other at will without conflict.

Claims

1. A multi-precision small-area SIMD computing system for CGRA, characterized by: Including encoding module, accumulation module and overflow module; The encoding module includes an encoding unit, a selector Mux and a decoding unit Select; The encoding unit is used to obtain S, D and N parameters by Booth encoding operation on the original multiplicand X; The selector is used to select the data direction of the encoding module in the mode with different precision and symbol mode; The decoding unit is used to perform a decoding operation on the S, D and N parameters obtained by encoding and the multiplier Y to obtain a partial product result of each row; The S, D, and N parameters are the encoding results of the multiplicand X, where S represents the 32-bit single-precision format Single, and the output result is ±1; D is the 64-bit double-precision format Double, and the output result is ±2; N is the negation symbol, representing the sign bit of the operation; The accumulation module is used to accumulate the multiplication partial products and the multiplication results after encoding according to a preset time sequence; The overflow module is used to perform low-order truncation, high-order truncation and saturation truncation according to preset rules; The input signal of the decoding unit is a combination of S, D, N and multiplier Y. 32-bit Booth multiplication operation is multiplexed with four 8-bit Booth multiplication operations. In the 8-bit Booth operation, a selector is provided at the boundary coding unit to select whether to perform 32-bit operation; The process of generating partial products in the encoding module is: After the data direction is selected by the selector, the data is grouped, and then the encoding results S, D and N parameters and the multiplier Y are put into the decoding module to obtain the partial product PP. The parameter j is introduced to represent each bit of the partial product PP, where j is an integer from 0 to 7. The relationship between the partial product PP and the encoding result and the multiplier Y is expressed as: PP j =~(~(Y j &D)&~(Y j-1 &S))^N, where PP0=~(S&Y0)^N.

2. The CGRA-oriented multi-precision small-area SIMD computing system according to claim 1, characterized in that: In the coding unit, X is the multiplicand, Y is the multiplier, and the expression of the Single signal is X 2i-1 ^X 2i ; The expression of Double signal is ~(~(X 2i-1 &X 2i &~X wi+1 )&~(~X 2i-1 &~X 2i &X 2i ); Negation signal is ~X 2i+1 ; The Booth algorithm of base-4 is selected. For the encoding module, the multiplicand X is encoded every 3 bits. The parameter i is introduced to represent the number of data groups. Each group of data is represented as X 2i+1 、X 2i 、X 2i-1 , the value range is 0, 1, 2 and 3, a total of four integers, when i = 0, X -1 =0.

3. The CGRA-oriented multi-precision small-area SIMD computing system according to claim 1, characterized in that: The selector is a 2to1 selector.

4. The CGRA-oriented multi-precision small-area SIMD computing system according to claim 1, characterized in that: The partial products generated by the encoding module are divided into 8 parts, where Parts 1, 2, 5, and 6 are single accumulation units for generating 8-bit multiplication results, and Parts 3 and 7 as well as Parts 4 and 8 are cut and blocked to meet the pipeline requirements; For the lower 32-bit output result, first, Parts 1, 2, and 3 generate the corresponding 17-bit and 23-bit cumulative results, which are then added together with Part 4 to produce a 36-bit output result. Finally, the mode is determined according to the control signal: If it is 8-bit multiplication mode, the 16-bit results of Part 1 and Part 2 are concatenated to produce a 32-bit result; If the mode is 32-bit multiplication, the lower 32 bits of the 36-bit output result are used as the lower 32-bit result of the 32-bit multiplier, and the remaining upper 4 bits are the carry bit, which is used as the addend of the upper 32-bit output result. For the high 32-bit output result, the corresponding 17-bit and 26-bit cumulative results generated by Parts 5, 6, and 7 are accumulated and added with Part 8 and the 4-bit number from the low 32-bit output result to generate a 32-bit cumulative result. Finally, the mode is determined according to the control signal: If it is 8-bit multiplication mode, the 16-bit results of Part 3 and Part 4 are concatenated to produce a 32-bit result; If it is 32-bit multiplication mode, the 32-bit output result generated is the high 32-bit result of the 32-bit multiplier; The 32-bit numbers generated by the lower 32-bit output result and the upper 32-bit output result are directly concatenated, and the resulting 64-bit result is the output result of the 32-bit multiplier.

5. The CGRA-oriented multi-precision small-area SIMD computing system according to claim 1, characterized in that: The low-order truncation: for 32-bit operation, the low-order 32 bits are retained; for 8-bit operation, the low-order 8 bits are retained; The high-order truncation: for 32-bit operation, the high-order 32 bits are retained; for 8-bit operation, the high-order 8 bits are retained; The saturation truncation: for 32-bit operations and 8-bit operations, it is divided into signed and unsigned, positive and negative saturation truncation. For unsigned overflow, it is only necessary to judge whether the high-bit bitwise OR is 1. If it is 1, overflow occurs; for signed positive overflow, it is necessary to judge whether the high-bit bitwise OR is 1. If it is 1, overflow occurs; for signed negative overflow, it is necessary to judge whether the high-bit bitwise AND is 0. If it is 0, overflow occurs.

6. A multi-precision small-area SIMD computing method for CGRA, characterized in that: The CGRA-oriented multi-precision small-area SIMD computing system according to any one of claims 1 to 5 comprises the following steps: Step 1: After a set of input data and mode selection data are input, 16 encoders work to generate the signals S, D, and N required for the current set of data Select; Step 2: All encoding units corresponding to the lower 32 bits of the output start working. The input is S, D, and N as well as the multiplicand input data of this group. The result of the decoding selection is put into the accumulation unit for accumulation. The final output result is 36-bit data, of which the upper 4 bits are used for addition in the next cycle, and the lower 32 bits are the lower 32 bits corresponding to the 32-bit multiplier. Step 3: The multiplier B in the input data, all control signals, the signals S / D / N obtained in step 1, the 36-bit data obtained in step 2, and the addend C are cached in the register, ending the first time cycle. Step 4: Use the cached S / D / N and multiplier B as input data for the high 32-bit encoding unit to obtain the corresponding result; Step 5: The cached S / D / N, multiplier B, and the upper 4 bits of the 36-bit data are placed in the accumulation unit for accumulation, and finally the upper 32 bits of data are obtained; Step 6: Put all control signals in step 3, addend C, the lower 32 bits of the 36-bit data, and the upper 32 bits of the data obtained in step 5 into the register cache, ending the second time period; Step 7: Concatenate the lower 32-bit data and the upper 32-bit data cached in step 6 to obtain the 64-bit output data of the 32-bit multiplier, and accumulate the addend C according to the control signal cached in step 6 to obtain a 64-bit result; Step 8: Perform overflow processing on the 64-bit result obtained in step 7 according to the control signal cached in step 6, select the overflow mode, and obtain the final 32-bit output result.

7. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the CGRA-oriented multi-precision small-area SIMD operation method according to claim 6 are implemented.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the computer program is executed by a processor, the steps of the CGRA-oriented multi-precision small-area SIMD operation method according to claim 6 are implemented.

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