Control method and controller based on AXI synchronous read-write single-port SRAM

Abstract

The application provides a control method and device based on AXI synchronous read-write single-port SRAM. After receiving the synchronous read-write information sent by the AXI bus at the current time, the read data address, read operation indication, write data address and write operation indication are stored in the configured signal storage space. If it is detected that the read data address and write data address corresponding to the current time both access the target SRAM, the to-be-written data is stored in the configured data storage space. Based on the read data address and read operation indication corresponding to the current time in the signal storage space, the read operation is performed, and the obtained read data is uploaded to the AXI bus through the configured read data channel. After the read operation is performed, based on the write data address and write operation indication corresponding to the current time in the signal storage space, the to-be-written data is written into the target SRAM. The method enables the single-port SRAM to have the function of being read and written at the same time, and improves the read-write efficiency.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and more specifically, to a control method and controller based on AXI synchronous read / write of single-port SRAM. Background Technology

[0002] According to the Advanced eXtensible Interface (AXI) bus protocol, the master connected to the AXI bus has the function of concurrent reading and writing to the slave. In order to best support the characteristics of the AXI bus and give full play to its performance, it is usually necessary to ensure that the slave connected to the AXI bus has the function of being read and written at the same time during the design stage.

[0003] Currently, the following schemes allow for read and write operations on Static Random-Access Memory (SRAM) connected to the Advanced eXtensible Interface (AXI) bus:

[0004] Option 1 involves connecting a dual-ended SRAM to the AXI bus. This option places no special requirements on the chip design; it only requires setting the appropriate size of the dual-ended SRAM based on the chip's storage needs. This method is simple to design and can achieve concurrent read and write operations. The disadvantage is that the dual-ended SRAM requires a larger area, necessitating more masks during chip manufacturing, significantly increasing manufacturing costs.

[0005] Option 2 involves connecting a single-ended SRAM (or "single-port SRAM") to the AXI bus. Compared to Option 1, this option has advantages in terms of cost and area control. However, simultaneous read and write operations on the single-ended SRAM will cause conflicts, meaning it cannot support the concurrent read and write characteristics of the AXI bus, resulting in wasted AXI bus performance. Summary of the Invention

[0006] The purpose of this application is to provide a control method and controller for synchronous reading and writing of single-port SRAM based on AXI, so as to solve the above-mentioned problems existing in the prior art, enabling single-port SRAM to have the function of simultaneous reading and writing, and having the advantages of fast reading and writing speed and low resource consumption.

[0007] Firstly, a control method based on AXI synchronous read / write of single-port SRAM is provided, applied to a controller connected to an AXI bus and multiple single-port SRAMs respectively. This method may include:

[0008] Receive synchronous read / write information sent by the AXI bus at the current moment. The synchronous read / write information includes read data address, read operation instruction, write data address, write operation instruction, and corresponding data to be written.

[0009] The read data address, read operation instruction, write data address, and write operation instruction are stored in the configured signal storage space;

[0010] If it is detected that both the read data address and the write data address corresponding to the current time access the target SRAM, then the data to be written is stored in the configured data storage space; the target SRAM is any one of the plurality of single-port SRAMs.

[0011] Based on the read data address and read operation instruction corresponding to the current moment in the signal storage space, the read operation is performed, and the obtained read data is uploaded to the AXI bus through the configured read data path;

[0012] After the read operation is completed, the data to be written is written to the target SRAM based on the write data address and write operation instruction corresponding to the current time in the signal storage space.

[0013] In one possible implementation, the method further includes:

[0014] If it is detected that the read data address corresponding to the current time in the signal storage space accesses the first SRAM and the write data address corresponding to the current time accesses the second SRAM, then a read operation is performed on the first SRAM based on the read data address corresponding to the current time and the read operation instruction.

[0015] Simultaneously, based on the write data address and write operation instruction corresponding to the current moment, the data to be written is written into the second SRAM;

[0016] Wherein, the first SRAM and the second SRAM are two different SRAMs among the plurality of single-port SRAMs.

[0017] In one possible implementation, the controller further includes a first selector and a second selector;

[0018] If it is detected that both the read data address and the write data address corresponding to the current time are accessing the target SRAM, then the data to be written is stored in the configured data storage space, including:

[0019] If it is detected that both the read data address and the write data address corresponding to the current time are accessing the target SRAM, then the first selector is controlled to store the data to be written in the configured data storage space.

[0020] The obtained read data is uploaded to the AXI bus through the configured read data path, including:

[0021] The second selector is controlled to upload the obtained read data to the AXI bus through the configured read data path.

[0022] In one possible implementation, detecting that both the read data address and the write data address corresponding to the current time are accessing the target SRAM includes:

[0023] It is detected that the read data address and write data address corresponding to the current time both access the same address in the target SRAM; or, it is detected that the read data address and write data address corresponding to the current time both access different addresses in the target SRAM.

[0024] In one possible implementation, the method further includes:

[0025] If it is detected that the read data address and write data address corresponding to the current time both access the same address in the target SRAM, then the first selector is controlled to store the data to be written in the configured data storage space, and then the second selector is controlled to read the stored data to be written from the data storage space.

[0026] In one possible implementation, the method further includes:

[0027] If it is detected that the read data address and write data address corresponding to the current time both access different addresses in the target SRAM, then the first selector is controlled to store the data to be written in the configured data storage space.

[0028] Based on the read data address and read operation instruction corresponding to the current moment in the signal storage space, the second selector is controlled to perform a read operation on the target SRAM.

[0029] In one possible implementation, the method further includes:

[0030] Real-time capacity detection of the signal storage space;

[0031] If no free capacity is detected in the signal storage space, or if the occupied free capacity in the signal storage space reaches a preset capacity threshold, an instruction to pause the write operation is sent to the AXI bus.

[0032] In one possible implementation, a read operation is performed based on the read data address and read operation instruction corresponding to the current moment in the signal storage space, including:

[0033] If it is detected that the signal storage space converts the address format of the read data address and write data address corresponding to the current time into the address format corresponding to the SRAM to be accessed, then a read operation is performed based on the read data address and read operation indication corresponding to the current time in the signal storage space.

[0034] Secondly, a controller based on AXI synchronous read / write single-port SRAM is provided, which may include:

[0035] A data receiver connected to the AXI bus is used to receive synchronous read / write information sent by the AXI bus at the current moment. The synchronous read / write information includes read data address, read operation instruction, write data address, write operation instruction, and corresponding data to be written.

[0036] A signal buffer is used to store the read data address, read operation instruction, write data address, and write operation instruction in its own configured signal storage space;

[0037] A logic control unit is configured to send storage control information to the data buffer if it is detected that both the read data address and the write data address corresponding to the current time access the target SRAM. The storage control information includes the data to be written. The target SRAM is any one of at least one single-port SRAM.

[0038] Based on the read data address and read operation instruction corresponding to the current time in the signal storage space, a read operation is performed, and the obtained read data is sent to the read data path; after the read operation is completed, based on the write data address and write operation instruction corresponding to the current time in the signal storage space, the data to be written is written to the target SRAM;

[0039] A data buffer is used to receive the storage control information sent by the logic control unit and store the data to be written in its own configured data storage space;

[0040] The read data path is used to receive the read data sent by the logic control unit and upload the read data to the AXI bus.

[0041] Fourthly, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when executed by a processor, the computer program implements the steps of any of the methods described in the first aspect above.

[0042] The AXI synchronous read / write control method for single-port SRAM provided in this application receives synchronous read / write information sent by the AXI bus at the current moment. This synchronous read / write information includes a read data address, a read operation instruction, a write data address, a write operation instruction, and corresponding data to be written. The read data address, read operation instruction, write data address, and write operation instruction are stored in a configured signal storage space. If it is detected that both the read data address and write data address at the current moment access the target SRAM, the data to be written is stored in the configured data storage space. The target SRAM can be any one of multiple single-port SRAMs. Based on the read data address and read operation instruction at the current moment in the signal storage space, a read operation is performed, and the obtained read data is uploaded to the AXI bus through a configured read data path. After the read operation is completed, the data to be written is written to the target SRAM based on the write data address and write operation instruction at the current moment in the signal storage space. This method, through reasonable control of the read / write data information sent by the AXI bus, enables a single-port SRAM to have the function of simultaneous read and write operations, and has the advantages of fast read / write speed and low resource consumption. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A system architecture diagram of a control method based on AXI synchronous read / write of single-port SRAM provided in this application embodiment;

[0045] Figure 2 A schematic diagram of the controller structure for an application of a control method based on AXI synchronous read / write of single-port SRAM provided in this application embodiment;

[0046] Figure 3 This is a schematic diagram illustrating the address format conversion of a signal buffer provided in an embodiment of this application;

[0047] Figure 4 This is a flowchart illustrating a control method for synchronous reading and writing of single-port SRAM based on AXI, provided in an embodiment of this application. Detailed Implementation

[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0049] The control method based on AXI synchronous read / write single-port SRAM provided in this application embodiment can be applied to... Figure 1 In the system architecture shown, such as Figure 1 As shown, the system may include: an AXI bus, a controller, and multiple single-port SRAMs.

[0050] The AXI bus connects to multiple hosts, and the controller connects to both the AXI bus and multiple single-port SRAMs. This controller can be integrated into the chip's digital module. When the AXI bus needs to read or write data from the SRAM, the controller can control the data flow of the read / write operation to assist in achieving synchronous read / write functionality.

[0051] Each single-port SRAM contains stored data;

[0052] The AXI bus is used to receive read data information, write data information, and synchronous read / write information from the same or different hosts, and to send the received information to the controller. Read data information may include a read data address and a read operation instruction; write data information may include a write data address, a write operation instruction, and the corresponding data to be written; synchronous read / write information may include a read data address, a read operation instruction, a write data address, a write operation instruction, and the corresponding data to be written, i.e., information for simultaneous read and write operations.

[0053] The controller receives information from the AXI bus and performs read and / or write operations based on that information. Specifically:

[0054] If the information is read data information or write data information, then a read operation is performed based on the read data address and read operation instruction in the read data information, or a write operation is performed based on the write data address, write operation instruction and corresponding data to be written in the write data information.

[0055] If the information is synchronous read / write information, then the control method for synchronous read / write of single-port SRAM based on AXI provided in the embodiments of this application can be executed to complete the task of enabling the single-port SRAM to be read and written simultaneously, and has the advantages of faster read / write speed and less resource consumption.

[0056] like Figure 2 As shown, the controller may include a data receiver connected to the AXI bus, a signal buffer, a logic control unit, a data buffer, and a read data path;

[0057] The logic control unit can be a data flow control circuit, and the specific circuit structure is not limited in this application embodiment.

[0058] The data receiver is used to receive synchronous read and write information sent by the AXI bus at the current moment. The synchronous read and write information may include read data address, read operation instruction, write data address, write operation instruction and corresponding data to be written.

[0059] A signal buffer is used to store the read data address, read operation instruction, write data address, and write operation instruction in its own configured signal storage space;

[0060] Furthermore, the signal buffer stores the received read data address and write data address in its own read address queue and write address queue, respectively, and then... Figure 3 After the address format conversion shown, the address formats in the read address queue and write address queue are converted into the address formats corresponding to the single-port SRAM to be accessed, and stored in the corresponding queues in its own address sending space, such as the read address sending queue and the write address sending queue. The required addresses are then extracted from the address sending space when subsequent read and write operations are performed.

[0061] The logic control unit is used to send storage control information to the data buffer if it is detected that both the read data address and the write data address corresponding to the current time are accessing the target SRAM; wherein, the storage control information may include the data to be written; the target SRAM is any one of multiple single-port SRAMs;

[0062] Based on the read data address and read operation instruction corresponding to the current moment in the signal storage space, the read operation is executed, and the obtained read data is sent to the read data path;

[0063] After the read operation is completed, the data to be written is written to the target SRAM based on the write data address and write operation instruction corresponding to the current moment in the signal storage space.

[0064] The data buffer is used to receive storage control information sent by the logic control unit and store the data to be written in its own configured data storage space.

[0065] The read data path is used to receive read data sent by the logic control unit and upload the read data to the AXI bus.

[0066] Furthermore, the controller may also include a first selector and a second selector.

[0067] The logic control unit can control the first selector to store the data to be written in the configured data storage space; and the logic control unit can control the second selector to upload the obtained read data to the AXI bus through the configured read data path.

[0068] Furthermore, during the read operation, based on the read data address and read operation indication corresponding to the current moment in the signal storage space, the logic control unit may control the second selector to read data from the single-port SRAM to be accessed, or the logic control unit may control the second selector to read data from the data storage space of the data buffer.

[0069] As can be seen, the controller provided in this application embodiment adds a built-in data flow control circuit and uses multiple single-ended SRAMs with contiguous addresses instead of the existing single SRAM. The controller includes a data storage space, i.e., a data buffer, set within a data buffer to cache data to be written to the SRAM.

[0070] When concurrent read and write operations are performed on the AXI bus, if concurrent read and write operations involve the same SRAM, the write data is buffered in a data buffer. A read operation is then performed on that SRAM, and the obtained data is directly read onto the AXI bus. After the read operation is completed, the data to be written is retrieved from the data buffer, and a write operation is initiated simultaneously, writing the data to the corresponding SRAM. This controller enables concurrent read and write operations on the same SRAM, significantly reducing cost and area overhead. Furthermore, because this control method conforms to the standard AXI protocol, it has good versatility.

[0071] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict.

[0072] Figure 4 This is a flowchart illustrating a control method for synchronous reading and writing of single-port SRAM based on AXI, provided in an embodiment of this application. Figure 4 As shown, the method may include:

[0073] Step S410: Receive the synchronous read / write information sent by the AXI bus at the current moment.

[0074] The synchronous read / write information may include the read data address, read operation instruction, write data address, write operation instruction, and corresponding data to be written.

[0075] In practice, synchronous read / write information can be received from the same host to the AXI bus; or, synchronous read / write information can be received from different hosts; or, while receiving read operation data from one host, write operation data from another host can be received simultaneously, thus constituting synchronous read / write information.

[0076] Step S420: Store the read data address, read operation instruction, write data address, and write operation instruction in the configured signal storage space.

[0077] In practice, the read data address and write data address are stored in the read address queue and write address queue, respectively. The address formats of the read data address and write data address are converted into the address formats corresponding to the SRAM to be accessed, and the corresponding addresses after conversion are stored in the address sending space.

[0078] Correspondingly, read operation indicators and write operation indicators can be stored in the corresponding signal queues configured within the signal buffer for later retrieval.

[0079] Step S430: Determine the order of read and write operations based on the detection of the SRAM accessed by the read data address and write data address corresponding to the current time.

[0080] In practice, the SRAM accessed by the read data address and write data address corresponding to the current moment is detected, and the detection results can include the following situations:

[0081] Case 1: The read data address and write data address at the current moment both access the same address of the same target SRAM; where the target SRAM is any one of multiple single-port SRAMs.

[0082] Case 2: The read data address and write data address at the current moment access different addresses of the same target SRAM.

[0083] Case 3: The read data address and write data address at the current moment access different SRAMs, that is, the read data address accesses the first SRAM and the write data address accesses the second SRAM. The first SRAM and the second SRAM are two different SRAMs among multiple single-port SRAMs.

[0084] (1) Based on situation 1 above, determine the order of read and write operations, specifically including:

[0085] If it is detected that the read data address and write data address corresponding to the current time both access the same address in the target SRAM, then the first selector is controlled to store the data to be written in the configured data storage space.

[0086] Subsequently, based on the read data address and read operation indication corresponding to the current moment in the signal storage space, the control and the second selector read the data to be written corresponding to the read data address from the data storage space of the data buffer, thereby obtaining the read data, and uploading the obtained read data to the AXI bus through the configured read data path; wherein, after reading the data from the data storage space at this time, the data is still stored in the data storage space.

[0087] After the read operation is completed, based on the write data address and write operation indication corresponding to the current moment in the signal storage space, the first selector is controlled to write the data to be written into the target SRAM.

[0088] It is understandable that in (1) above, the corresponding data to be written in the data storage space will disappear from the data storage space only after the write operation is completed. Therefore, for (1) above, the read operation must be performed first and then the write operation.

[0089] (2) Based on situation 2 above, determine the order of read and write operations, specifically including:

[0090] If it is detected that the read data address and write data address corresponding to the current time both access different addresses in the target SRAM, then the first selector is controlled to store the data to be written in the configured data storage space.

[0091] Subsequently, based on the read data address and read operation indication corresponding to the current moment in the signal storage space, the second selector is controlled to perform a read operation on the target SRAM, obtain the read data, and upload the obtained read data to the AXI bus through the configured read data path;

[0092] After the read operation is completed, based on the write data address and write operation indication corresponding to the current moment in the signal storage space, the first selector is controlled to write the data to be written into the target SRAM.

[0093] It should be noted that in (2) above, the write operation can be performed first and the read operation can be performed later according to actual needs. This application embodiment does not limit this.

[0094] (3) Based on situation 3 above, determine the order of read and write operations, specifically including:

[0095] If it is detected that the read data address corresponding to the current moment in the signal storage space accesses the first SRAM and the write data address corresponding to the current moment accesses the second SRAM, then based on the read data address and read operation instruction corresponding to the current moment, a read operation is performed on the first SRAM, and the second selector is controlled to upload the obtained read data to the AXI bus through the configured read data path.

[0096] While performing a read operation, the first selector can be controlled based on the write data address and write operation instruction corresponding to the current moment to write the data to be written into the second SRAM.

[0097] In other words, as can be seen from the execution process described in (3) above, for information involving concurrent reading and writing, read and write operations can be performed simultaneously or sequentially, depending on business needs. Simultaneous reading and writing operations can improve read and write efficiency.

[0098] In some embodiments, since the AXI bus and the controller are connected via the AXI protocol and there is a handshake mechanism in the AXI protocol, the host will send read / write operation information only after the controller sends a ready signal to the host via the AXI bus. In order to receive the read / write operation information sent by the host via the AXI bus, the logic control unit in the controller can detect the capacity of the signal storage space in real time.

[0099] If free capacity is detected in the signal storage space, or if the free capacity occupied in the signal storage space does not reach the preset capacity threshold, it indicates that read and write operations can be performed normally, that is, the control method described above in this application is executed.

[0100] If no free capacity is detected in the signal storage space, or if the occupied free capacity in the signal storage space reaches a preset capacity threshold, an instruction to pause write operations can be sent to the AXI bus to notify the AXI bus to stop sending read and write operation information.

[0101] As can be seen, the control method for synchronous reading and writing of single-port SRAM based on AXI provided in this application avoids the limitation that a single-port SRAM cannot be read and written simultaneously due to having only one read / write port by reasonably controlling the read and write data information sent by the AXI bus, thereby realizing support for AXI read and write concurrency function and improving read and write efficiency.

[0102] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform any of the control methods for reading and writing single-port SRAM based on AXI synchronously as described in the above embodiments.

[0103] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the control methods for reading and writing single-port SRAM based on AXI synchronously as described in the above embodiments.

[0104] Those skilled in the art will understand that the embodiments in this application can be provided as methods, systems, or computer program products. Therefore, the embodiments in this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, the embodiments in this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0105] This application describes embodiments of methods, apparatus (systems), and computer program products according to embodiments of this application with reference to flowchart illustrations and / or block diagrams. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0106] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0107] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0108] Although preferred embodiments have been described in this application, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of this application.

[0109] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims in this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A control method for synchronous reading and writing of single-port SRAM based on AXI, characterized in that, The method, applied in a controller connected to an AXI bus and multiple single-port SRAMs respectively, includes: Receive synchronous read / write information sent by the AXI bus at the current moment. The synchronous read / write information includes read data address, read operation instruction, write data address, write operation instruction, and corresponding data to be written. The read data address, read operation instruction, write data address, and write operation instruction are stored in the configured signal storage space; If it is detected that both the read data address and the write data address corresponding to the current time access the target SRAM, then the data to be written is stored in the configured data storage space; the target SRAM is any one of the plurality of single-port SRAMs; the controller includes the data storage space for caching the data to be written; Based on the read data address and read operation instruction corresponding to the current moment in the signal storage space, the read operation is performed, and the obtained read data is uploaded to the AXI bus through the configured read data path; After the read operation is completed, the data to be written is retrieved from the data storage space, and the data to be written is written to the target SRAM based on the write data address and write operation instruction corresponding to the current time in the signal storage space.

2. The method as described in claim 1, characterized in that, The method further includes: If it is detected that the read data address corresponding to the current time in the signal storage space accesses the first SRAM and the write data address corresponding to the current time accesses the second SRAM, then a read operation is performed on the first SRAM based on the read data address corresponding to the current time and the read operation instruction. Simultaneously, based on the write data address and write operation instruction corresponding to the current moment, the data to be written is written into the second SRAM; Wherein, the first SRAM and the second SRAM are two different SRAMs among the plurality of single-port SRAMs.

3. The method as described in claim 1, characterized in that, The controller also includes a first selector and a second selector; If it is detected that both the read data address and the write data address corresponding to the current time are accessing the target SRAM, then the data to be written is stored in the configured data storage space, including: If it is detected that both the read data address and the write data address corresponding to the current time are accessing the target SRAM, then the first selector is controlled to store the data to be written in the configured data storage space. The obtained read data is uploaded to the AXI bus through the configured read data path, including: The second selector is controlled to upload the obtained read data to the AXI bus through the configured read data path.

4. The method as described in claim 3, characterized in that, The detection that both the read data address and the write data address corresponding to the current time are accessing the target SRAM includes: It was detected that both the read data address and the write data address corresponding to the current time are accessing the same address in the target SRAM; or, It was detected that both the read data address and the write data address corresponding to the current time were accessing different addresses in the target SRAM.

5. The method as described in claim 4, characterized in that, The method further includes: If it is detected that the read data address and write data address corresponding to the current time both access the same address in the target SRAM, then the first selector is controlled to store the data to be written in the configured data storage space, and then the second selector is controlled to read the stored data to be written from the data storage space.

6. The method as described in claim 4, characterized in that, The method further includes: If it is detected that the read data address and write data address corresponding to the current time both access different addresses in the target SRAM, then the first selector is controlled to store the data to be written in the configured data storage space. Based on the read data address and read operation instruction corresponding to the current moment in the signal storage space, the second selector is controlled to perform a read operation on the target SRAM.

7. The method as described in claim 1, characterized in that, The method further includes: Real-time capacity detection of the signal storage space; If no free capacity is detected in the signal storage space, or if the occupied free capacity in the signal storage space reaches a preset capacity threshold, an instruction to pause the write operation is sent to the AXI bus.

8. The method as described in claim 1, characterized in that, Based on the read data address and read operation instruction corresponding to the current moment in the signal storage space, a read operation is performed, including: If it is detected that the signal storage space converts the address format of the read data address and write data address corresponding to the current time into the address format corresponding to the SRAM to be accessed, then a read operation is performed based on the read data address and read operation indication corresponding to the current time in the signal storage space.

9. A controller based on AXI synchronous read / write single-port SRAM, characterized in that, The controller includes: A data receiver connected to the AXI bus is used to receive synchronous read / write information sent by the AXI bus at the current moment. The synchronous read / write information includes read data address, read operation instruction, write data address, write operation instruction, and corresponding data to be written. A signal buffer is used to store the read data address, read operation instruction, write data address, and write operation instruction in its own configured signal storage space; A logic control unit is configured to send storage control information to a data buffer if it is detected that both the read data address and the write data address corresponding to the current time access the target SRAM. The storage control information includes the data to be written. The target SRAM is any one of at least one single-port SRAM. Based on the read data address and read operation instruction corresponding to the current time in the signal storage space, a read operation is performed, and the obtained read data is sent to the read data path; after the read operation is completed, the data to be written is retrieved from the data storage space, and based on the write data address and write operation instruction corresponding to the current time in the signal storage space, the data to be written is written into the target SRAM; A data buffer is used to receive the storage control information sent by the logic control unit and store the data to be written in its own configured data storage space; The read data path is used to receive the read data sent by the logic control unit and upload the read data to the AXI bus.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-8.

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