Physical unclonable function circuit and signature information generating apparatus

Abstract

The application discloses a physical unclonable function circuit and a signature information generation device, relates to the field of encryption, and aims to improve the stability of a response signal generated by a PUF circuit. The PUF circuit comprises a first comparison circuit, N first delay circuits connected in series, and N second delay circuits connected in series. For the first delay circuit, a first delay device is coupled with a first capacitive device and a first end of a first selector, and a second delay device is coupled with a second capacitive device and a second end of the first selector. For the second delay circuit, a third delay device is coupled with a third capacitive device and a first end of a second selector, and a fourth delay device is coupled with a fourth capacitive device and a second end of the second selector. The N first delay circuits input an excitation signal and output a first signal. The N second delay circuits input the excitation signal and output a second signal. The first comparison circuit outputs a response signal according to a time delay difference between the first signal and the second signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of cryptography, and in particular to a physical unclonable function (PUF) circuit and a signature information generation apparatus. BACKGROUND

[0002] Storing signature information (such as identity authentication information or encryption keys) of a chip in a non-volatile memory (NVM) is at risk of being tampered with or stolen. An improved way is to use the uncertainty in the manufacturing process of a PUF circuit to generate a response signal based on a stimulus signal, thereby generating unique signature information for each chip, so that the resulting signature information has the characteristics of unpredictability, non-replicability and tamper resistance.

[0003] However, current PUF circuits mostly generate response signals based on the time delay difference of active devices or the difference of certain characteristic parameters (such as the threshold voltage difference of a static random-access memory (SRAM) PUF), and these differences are easily affected by factors such as voltage and temperature and thus change, resulting in the response signal generated by the PUF circuit being easily changed and having the problem of low stability. SUMMARY

[0004] Embodiments of the present application provide a PUF circuit and a signature information generation apparatus for improving the stability of the response signal generated by the PUF circuit.

[0005] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a PUF circuit is provided, comprising: a first comparison circuit, N first delay circuits in series, and N second delay circuits in series; the first delay circuit comprises a first delay device, a first capacitive device, a second delay device, a second capacitive device, and a first selector; the second delay circuit comprises a third delay device, a third capacitive device, a fourth delay device, a fourth capacitive device, and a second selector; N is a positive integer; for each first delay circuit, the first delay device is coupled to the first capacitive device and a first end of the first selector, and the second delay device is coupled to the second capacitive device and a second end of the first selector; for each second delay circuit, the third delay device is coupled to the third capacitive device and a first end of the second selector, and the fourth delay device is coupled to the fourth capacitive device and a second end of the second selector; the N first delay circuits in series are configured to input an excitation signal and output a first signal; the N second delay circuits in series are configured to input the excitation signal and output a second signal; the first comparison circuit is configured to output a response signal according to a time delay difference between the first signal and the second signal, the response signal being configured to indicate that the first signal is earlier or later than the second signal.

[0007] The PUF circuit provided by the embodiments of the present application comprises N first delay circuits in series, N second delay circuits in series, and a comparison circuit. For the first delay circuit or the second delay circuit, each comprises a selector, two delay devices, and two sets of capacitive devices. Each delay device is coupled to a set of capacitive devices. The selector selects one delay device to transmit the excitation signal. Since the time delay caused by the capacitive device as the load capacitance of the transmission path of the delay device is much larger than the time delay caused by the transmission of the signal by the delay device, and the capacitance parameter of the capacitive device is less affected by factors such as voltage and temperature, the overall time delay of the N first delay circuits and the N second delay circuits is less affected by factors such as voltage and temperature. Then, the comparison circuit compares the time delay difference between the transmission of the excitation signal through the Nth first delay circuit and the transmission of the excitation signal through the Nth second delay circuit, and outputs a response signal. The stability of the response signal is less affected by factors such as voltage and temperature, thereby improving the stability of the response signal generated by the PUF circuit.

[0008] In a possible implementation, the PUF circuit further comprises a fifth delay device and a second comparison circuit; an output terminal of an Nth first delay circuit in the N first delay circuits is coupled to a first input terminal of the second comparison circuit through the fifth delay device, and an output terminal of an Nth second delay circuit in the N second delay circuits is coupled to a second input terminal of the second comparison circuit, and the second comparison circuit is configured to output a first indication signal, and the first indication signal is configured to indicate whether the time delay difference of the first signal from the second signal is greater than a first threshold value, and the first threshold value is equal to a time delay generated by the fifth delay device. When the time delay difference of the first signal from the second signal is greater than the first threshold value, it indicates that the time delay difference can be stably maintained over time, so that the value 0 of the response signal can also be stably maintained, and therefore the response signal has higher credibility; otherwise, it indicates that the time delay difference is difficult to be stably maintained, so that the value 0 of the response signal is also difficult to be stably maintained, and therefore the response signal has lower credibility.

[0009] In a possible implementation, the PUF circuit further comprises a seventh delay device, and a time delay generated by the seventh delay device is less than a time delay generated by the fifth delay device; the output terminal of the Nth second delay circuit is coupled to the second input terminal of the second comparison circuit through the seventh delay device, and the first threshold value is equal to the time delay generated by the fifth delay device minus the time delay generated by the seventh delay device. When the time delay difference of the first signal from the second signal is greater than the first threshold value, it indicates that the time delay difference can be stably maintained over time, so that the value 0 of the response signal can also be stably maintained, and therefore the response signal has higher credibility; otherwise, it indicates that the time delay difference is difficult to be stably maintained, so that the value 0 of the response signal is also difficult to be stably maintained, and therefore the response signal has lower credibility.

[0010] In a possible implementation, the second comparison circuit comprises a NAND gate latch or a NOR gate latch. The NAND gate latch can compare the time delay difference of two signals by comparing the speed of rising edges of the two signals, and the NOR gate latch can compare the time delay difference of two signals by comparing the speed of falling edges of the two signals.

[0011] In a possible implementation, the PUF circuit further comprises a sixth delay device and a third comparison circuit; an output terminal of an Nth second delay circuit in the N second delay circuits is coupled to a first input terminal of the third comparison circuit through the sixth delay device, an output terminal of an Nth first delay circuit in the N first delay circuits is coupled to a second input terminal of the third comparison circuit, and the third comparison circuit is configured to output a second indication signal, where the second indication signal is used to indicate whether a time delay difference of the second signal from the first signal is greater than a second threshold value, and the second threshold value is equal to a time delay generated by the sixth delay device. When the time delay difference of the second signal from the first signal is greater than the second threshold value, it indicates that the time delay difference can be stably maintained over time, so that the value 1 of the response signal can also be stably maintained, and therefore the response signal has a higher credibility; otherwise, it indicates that the time delay difference is difficult to be stably maintained, so that the value 1 of the response signal is also difficult to be stably maintained, and therefore the response signal has a lower credibility.

[0012] In a possible implementation, the PUF circuit further comprises an eighth delay device, and a time delay generated by the eighth delay device is less than a time delay generated by the sixth delay device; an output terminal of the Nth first delay circuit is coupled to the second input terminal of the third comparison circuit through the eighth delay device, and the second threshold value is equal to the time delay generated by the sixth delay device minus the time delay generated by the eighth delay device. When the time delay difference of the second signal from the first signal is greater than the second threshold value, it indicates that the time delay difference can be stably maintained over time, so that the value 1 of the response signal can also be stably maintained, and therefore the response signal has a higher credibility; otherwise, it indicates that the time delay difference is difficult to be stably maintained, so that the value 1 of the response signal is also difficult to be stably maintained, and therefore the response signal has a lower credibility.

[0013] In a possible implementation, the third comparison circuit comprises a NAND gate latch or a NOR gate latch. The NAND gate latch can compare the time delay difference of two signals by comparing the speed of rising edges of the two signals, and the NOR gate latch can compare the time delay difference of two signals by comparing the speed of falling edges of the two signals.

[0014] In a possible implementation, the first comparison circuit comprises a NAND gate latch or a NOR gate latch. The NAND gate latch can compare the time delay difference of two signals by comparing the speed of rising edges of the two signals, and the NOR gate latch can compare the time delay difference of two signals by comparing the speed of falling edges of the two signals.

[0015] In a possible implementation, for the nth first delay circuit and the nth second delay circuit, 1≤n≤N, and n is a positive integer: when the first selector selects the first delay device to transmit the excitation signal, the second selector selects the third delay device to transmit the excitation signal; the first delay device and the third delay device are the same in device, and the first capacitive device and the third capacitive device are the same in device. When the first selector selects the second delay device to transmit the excitation signal, the second selector selects the fourth delay device to transmit the excitation signal; the second delay device and the fourth delay device are the same in device, and the second capacitive device and the fourth capacitive device are the same in device. The same in device can include at least one of the same in type, number, parameter, and the like of the device. Since the bit control signals are independent of each other, the randomness of the time delay difference generated by the nth first delay circuit and the nth second delay circuit is independent of each other. Therefore, the N first delay circuits in series and the N second delay circuits in series also generate time delay differences when transmitting the excitation signal due to process deviation, and the more the number of the first delay circuit and the second delay circuit, the greater the randomness of the time delay difference, which is more difficult to predict, copy, or tamper.

[0016] In a possible implementation, for any two first delay circuits in the N first delay circuits in series: the first delay devices are independent of each other in device, the second delay devices are independent of each other in device, the first capacitive devices are independent of each other in device, and the second capacitive devices are independent of each other in device. In the embodiment of the application, the devices independent of each other means that the devices can be the same or different. The same in device can include at least one of the same in type, number, parameter, and the like of the device, and the different in device can include at least one of the different in type, number, parameter, and the like of the device.

[0017] In a possible implementation, for any two second delay circuits in the N second delay circuits in series: the third delay devices are independent of each other in device, the fourth delay devices are independent of each other in device, the third capacitive devices are independent of each other in device, and the fourth capacitive devices are independent of each other in device. In the embodiment of the application, the devices independent of each other means that the devices can be the same or different. The same in device can include at least one of the same in type, number, parameter, and the like of the device, and the different in device can include at least one of the different in type, number, parameter, and the like of the device.

[0018] In a second aspect, a signature information generation apparatus is provided, which comprises the PUF circuit and the processor as described in the first aspect and any of its possible implementation forms; the processor is configured to output an excitation signal to the PUF circuit; the processor is further configured to receive a response signal corresponding to the excitation signal from the PUF circuit; and the processor is further configured to output signature information according to the response signal, the signature information being used for encrypting information output by the processor. The signature information generation apparatus provided by the embodiments of the present application has the PUF circuit as described above, which improves the stability of the generated response signal, and thus the signature information generation apparatus can improve the reliability of the signature information according to the response signal. In addition, the PUF circuit can generate one bit of the response signal in each clock cycle, which can be used as one bit of the signature information, thereby improving the efficiency of the signature information generation apparatus in generating the signature information.

[0019] In a possible implementation form, the processor is further configured to receive a first indication signal or a second indication signal from the PUF circuit, the first indication signal being used for indicating whether the time delay difference of the first signal being earlier than the second signal is greater than the first threshold value, and the second indication signal being used for indicating whether the time delay difference of the second signal being earlier than the first signal is greater than the second threshold value; and obtain the signature information according to one of the first indication signal or the second indication signal and the response signal, each bit of the signature information being taken from one valid bit of the response signal, the one valid bit of the response signal being one bit of the response signal when the first indication signal indicates that the time delay difference of the first signal being earlier than the second signal is greater than the first threshold value, or when the second indication signal indicates that the time delay difference of the second signal being earlier than the first signal is greater than the second threshold value. The first indication signal or the second indication signal can further output an indication of the stability of each bit of the response signal, so that one stable bit of the response signal can be used as one bit of the signature information, thereby improving the stability of the signature information.

[0020] In a possible implementation form, the processor is further configured to obtain a third indication signal according to one of the first indication signal or the second indication signal, the third indication signal being used for indicating whether each bit of the response signal is valid, and when the response signal has M bits, the third indication signal also has M bits. When the third indication signal indicates that one bit of the response signal is valid, the one bit of the response signal can be used as one bit of the signature information. Otherwise, the one bit of the response signal cannot be used as one bit of the signature information. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A circuit schematic diagram of the signature information generation apparatus provided by the embodiments of the present application;

[0022] Figure 2A circuit schematic diagram of a PUF circuit provided for an embodiment of the present application is shown in FIG. 1.

[0023] Figure 3 A circuit schematic diagram of another PUF circuit provided for an embodiment of the present application is shown in FIG. 2.

[0024] Figure 4 A circuit schematic diagram of still another PUF circuit provided for an embodiment of the present application is shown in FIG. 3.

[0025] Figure 5 A circuit schematic diagram of yet another PUF circuit provided for an embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0026] In an encrypted chip such as a passport chip, an identity card chip, a subscriber identity module (SIM), etc., signature information needs to be stored. The traditional way of storing signature information in an NVM will face the risk of being tampered with or stolen. A current improved way is to use the uncertainty in the manufacturing process of a PUF circuit to generate a response signal based on an excitation signal, thereby generating unique signature information for each chip. Since a PUF is a hardware function implementation circuit that depends on chip features, it has uniqueness and randomness, and by extracting the process parameter deviation inevitably introduced in the chip manufacturing process, the function of uniquely corresponding the excitation signal and the response signal is realized. Therefore, the signature information obtained based on the PUF circuit has the characteristics of unpredictability, non-replicability and non-tamperability.

[0027] One way to obtain signature information through a PUF circuit is to connect multiple delay circuits in series, each delay circuit selects a different delay device to transmit an excitation signal, and the output end of the last delay circuit is fed back to the input end of the first delay circuit, so that multiple delay circuits output an oscillation signal. By comparing the number of oscillations in the same time window of the two transmission paths through a counter, one bit of signature information is generated. By changing the excitation signal, multiple bits of signature information can be obtained. This way mainly has the following shortcomings:

[0028] First, the time delay generated by the delay device is easily affected by factors such as voltage and temperature, and thus changes easily, thereby causing the response signal generated by the PUF circuit to change easily, and having the problem of low stability. Secondly, the above PUF circuit takes a long time to generate one bit of signature information. Depending on the degree of dispersion of the time delay generated by each delay device, it can take up to 2 15 to 2 17 clock cycles to generate one bit of signature information.

[0029] The PUF circuit provided by the embodiment of the present application drives the capacitive device through the delay device, and uses the capacitive device to introduce time delay which is not easily affected by factors such as voltage and temperature to improve the stability of the overall time delay, thereby improving the stability of the output response signal of the PUF circuit. In addition, the signature information generation device provided by the embodiment of the present application uses the PUF circuit to improve the stability of the generated response signal, and the signature information generation device generates signature information according to the response signal, so that the reliability of the signature information can be improved. In addition, the PUF circuit can generate a bit of the response signal in each clock cycle, and the bit can be used as a bit of the signature information, thereby improving the efficiency of generating the signature information. Further, the PUF circuit can also output a signal indicating the stability of each bit of the response signal, so that a stable bit of the response signal can be used as a bit of the signature information, thereby improving the efficiency of the signature information generation device in generating the signature information.

[0030] As shown in Figure 1 The embodiment of the present application provides a signature information generation device based on a PUF circuit. The signature information generation device can be a device for realizing identity authentication and key management, such as an encryption chip of a passport chip, an identity card chip, a SIM card, or an electronic device such as an Internet of Things (IoT) device and a wearable device. The signature information generation device includes a processor 11, a PUF circuit 12, a non-volatile memory 13, an interface circuit 14, and a random sequence generator 15.

[0031] The processor 11 can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processing circuit (DSP), a micro controller unit (MCU), a programmable logic device (PLD), etc.

[0032] The non-volatile memory 13 can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), or a flash memory.

[0033] The interface circuit 14 can provide power supply for the signature information generation device or be used for communication with external devices, and can include a power supply interface, a wired communication interface (such as an Internet interface, a USB interface, a serial interface, etc.), or a wireless communication interface (such as a radio frequency identification (RFID), an equal radio frequency circuit, etc.).

[0034] The random sequence generator 15 is used to generate M N-bit control signals (control signal 1 to control signal N) based on a random seed and output to the PUF circuit 12, where M and N are positive integers. For example, M = 256 and N = 10. The random seed can be a fixed value or come from the processor 11 or the non-volatile memory 13. The random sequence generator 15 can be a linear feedback shift register (LFSR).

[0035] The processor 11 can load and run a program from the non-volatile memory 13, output an excitation signal to the PUF circuit 12, receive an M-bit response signal from the PUF circuit 12, generate signature information according to the response signal, and output the signature information (which can be encrypted) and a validation signal (indicating that the signature information is valid). Optionally, the processor 11 can also receive an M-bit first indication signal or an M-bit second indication signal from the PUF circuit 12, generate signature information according to one of the first indication signal or the second indication signal and the response signal, obtain a third indication signal according to one of the first indication signal or the second indication signal, and output the third indication signal. The processor 11 can output these information or signals to the non-volatile memory 13, the interface circuit 14, etc. When the processor 11 outputs these information or signals to the non-volatile memory 13, these information or signals will not be lost due to power failure, and the processor 11 can directly obtain these information or signals from the non-volatile memory 13 when it is started next time; when the processor 11 outputs these information or signals to the interface circuit 14, these information or signals can be output to other devices through the interface circuit 14. The processor 11 can also output an enable signal to the random sequence generator 15 to control whether the random sequence generator 15 outputs the control signal. These signals involved above will be described in detail hereinafter.

[0036] It should be noted that the figure only shows one structure of a signature information generation device based on PUF circuit, and the signature information generation device may also include more or fewer devices.

[0037] The following is combined with Figures 2-4 The structure and working principle of the PUF circuit are described.

[0038] like Figures 2-4 As shown, the PUF circuit includes N first delay circuits 21 connected in series, N second delay circuits 22 connected in series, and a first comparator circuit 23. Here, N and... Figure 1 The N in them is the same.

[0039] The first first delay circuit 21 of the N series-connected first delay circuits 21 and the first second delay circuit 22 of the N series-connected second delay circuits 22 are used to receive excitation signals, which can be pulse signals, such as clock signals, clock divider signals, etc. One excitation signal is transmitted through the N series-connected first delay circuits 21 and then output through the Nth first delay circuit 21; this transmission path can be called the first transmission path. Another excitation signal is transmitted through the N series-connected second delay circuits 22 and then output through the Nth second delay circuit 22; this transmission path can be called the second transmission path.

[0040] The first delay circuit 21 includes a first delay device D1, a first capacitive device L1, a second delay device D2, a second capacitive device L2, and a first selector S1. The second delay circuit 22 includes a third delay device D3, a third capacitive device L3, a fourth delay device D4, a fourth capacitive device L4, and a second selector S2. This application does not limit the form of the delay device and the capacitive device. For example, the delay device can be an active device, an inverter, etc., and the capacitive device can be an active device, a passive capacitor, an inverter, etc. The difference between the delay device and the capacitive device is that the delay device is used to transmit the excitation signal, providing a smaller transmission delay for the transmission of the excitation signal; the capacitive device acts as the load capacitor in the transmission path of the coupled delay device, providing a larger transmission delay for the transmission of the excitation signal in that transmission path. In addition, the delay device or the capacitive device is not limited to a single device and can be obtained by coupling multiple devices.

[0041] For each first delay circuit 21, a first delay device D1 is coupled with a first capacitive device L1 and a first end of a first selector S1, a second delay device D2 is coupled with a second capacitive device L2 and a second end of a second selector S2, and the first selector S1 is configured to select one of the first delay device D1 or the second delay device D2 to transmit the excitation signal. For the nth(1≤n≤N, and n is a positive integer) first delay circuit 21, the first selector S1 is configured to select one of the first delay device D1 or the second delay device D2 to transmit the excitation signal based on an nth bit of the N-bit control signal. For example, as shown in Figure 2 FIG. 1, when the control end of the first selector S1 inputs a control signal of 0, the first delay device D1 is selected to transmit the excitation signal, and when the control end inputs a control signal of 1, the second delay device D2 is selected to transmit the excitation signal. Alternatively, when the control end of the first selector S1 inputs a control signal of 1, the first delay device D1 is selected to transmit the excitation signal, and when the control end inputs a control signal of 0, the second delay device D2 is selected to transmit the excitation signal.

[0042] The present application does not limit the coupling relationship between the first selector S1 and the first delay device D1, the first capacitive device L1, the second delay device D2, and the second capacitive device L2, as long as the first capacitive device L1 and the second capacitive device L2 are not directly coupled. For example, as shown in Figure 2 FIG. 2, the input end of the first delay device D1 and the input end of the second delay device D2 are configured to receive the excitation signal, the output end of the first delay device D1 and the first capacitive device L1 are coupled to one input end of the first selector S1, and the output end of the second delay device D2 and the second capacitive device L2 are coupled to another input end of the first selector S1. Alternatively, as shown in Figure 3 FIG. 3, the input end of the first selector S1 is configured to receive the excitation signal, one output end of the first selector S1 is coupled to the input end of the first delay device D1 and the first capacitive device L1, and another output end of the first selector S1 is coupled to the input end of the second delay device D2 and the second capacitive device L2, and the output end of the first delay device D1 is coupled to the output end of the second delay device D2.

[0043] For each second delay circuit 22, a third delay device D3 is coupled with a third capacitive device L3 and a first end of a second selector S2, a fourth delay device D4 is coupled with a fourth capacitive device L4 and a second end of the second selector S2, and the second selector S2 is configured to select one of the third delay device D3 or the fourth delay device D4 to transmit the excitation signal. For the nth (1≤n≤N, and n is a positive integer) second delay circuit 22, the second selector S2 is configured to select one of the third delay device D3 or the fourth delay device D4 to transmit the excitation signal based on the nth bit of the N-bit control signal. For example, as shown in FIG. 3, when the control end of the second selector S2 inputs a control signal of 0, the third delay device D3 is selected to transmit the excitation signal, and when the control end of the second selector S2 inputs a control signal of 1, the fourth delay device D4 is selected to transmit the excitation signal. Alternatively, when the control end of the second selector S2 inputs a control signal of 1, the third delay device D3 is selected to transmit the excitation signal, and when the control end of the second selector S2 inputs a control signal of 0, the fourth delay device D4 is selected to transmit the excitation signal. Figure 2

[0044] The application does not limit the coupling relationship between the second selector S2 and the third delay device D3, the third capacitive device L3, the fourth delay device D4 and the fourth capacitive device L4, as long as the third capacitive device L3 and the fourth capacitive device L4 are not directly coupled. For example, as shown in FIG. 3, the input end of the third delay device D3 and the input end of the fourth delay device D4 are configured to receive the excitation signal, the output end of the third delay device D3 and the third capacitive device L3 are coupled to one input end of the second selector S2, and the output end of the fourth delay device D4 and the fourth capacitive device L4 are coupled to another input end of the second selector S2. Alternatively, as shown in FIG. 4, the input end of the second selector S2 is configured to receive the excitation signal, one output end of the second selector S2 is coupled to the input end of the third delay device D3 and the third capacitive device L3, and another output end of the second selector S2 is coupled to the input end of the fourth delay device D4 and the second capacitive device L2, and the output end of the third delay device D3 is coupled to the output end of the fourth delay device D4. Figure 2 Figure 3

[0045] It should be noted that each of the M N-bit control signals and each bit of the same control signal are independent of each other. Each control signal will select a unique pair of first transmission path and second transmission path, and M control signals will select M pairs of first transmission path and second transmission path, and each pair of first transmission path and second transmission path will cause the PUF circuit to output a bit of response signal, so M control signals will cause the PUF circuit to output M bits of response signal.

[0046] ​​​The capacitive devices and the delay devices in each delay circuit are used to generate time delay, but the principles of generating time delay are different. The delay device itself generates time delay when it is turned on (i.e. turn-on delay). The capacitive device is coupled with the delay device, and when the excitation signal transmitted by the delay device changes, the capacitive device presents a capacitive characteristic (i.e. behaves as a load capacitance of the transmission path where the delay device is located) to hinder the change of the excitation signal, so the capacitive device also generates time delay. Moreover, by increasing the number of capacitive devices, the time delay generated by the capacitive devices can be much greater than the time delay generated by the delay device transmitting the signal. Since the capacitance parameter of the capacitive device is less affected by factors such as voltage and temperature, the time delay generated by the capacitive device is very stable. Even though the time delay generated by the delay device is easily affected by factors such as voltage and temperature, the proportion of the time delay generated by the delay device is very small compared to the time delay generated by the capacitive device. The time delay generated by the capacitive device is the main factor that determines the time delay of the delay circuit, so the factors such as voltage and temperature have little effect on the time delay of each delay circuit.

[0047] For the nth first delay circuit and the nth second delay circuit, when the first selector S1 selects the first delay device D1 to transmit the excitation signal, the second selector S2 selects the third delay device D3 to transmit the excitation signal; when the first selector S1 selects the second delay device D2 to transmit the excitation signal, the second selector S2 selects the fourth delay device D4 to transmit the excitation signal. At this time, the first delay device D1 and the third delay device D3 adopt the same device, the second delay device D2 and the fourth delay device D4 adopt the same device, the first capacitive device L1 and the third capacitive device L3 adopt the same device, and the second capacitive device L2 and the fourth capacitive device L4 adopt the same device. That is, for the nth first delay circuit and the nth second delay circuit, the selected delay devices are the same, and the selected capacitive devices are also the same, so as to prevent the first transmission path and the second transmission path from generating systematic time delay difference due to different devices, so that the time delay difference between the first transmission path and the second transmission path is mainly generated by the process deviation of the same device, which has great randomness and is difficult to be predicted, copied or tampered with.

[0048] For any two of the N first delay circuits 21 connected in series: the devices adopted by the first delay device D1 are independent of each other, the devices adopted by the second delay device D2 are independent of each other, the devices adopted by the first capacitive device L1 are independent of each other, the devices adopted by the second capacitive device L2 are independent of each other, i.e., the devices adopted by each first delay circuit 21 are independent of each other. For any two of the N second delay circuits 22 connected in series: the devices adopted by the third delay device D3 are independent of each other, the devices adopted by the fourth delay device D4 are independent of each other, the devices adopted by the third capacitive device L3 are independent of each other, the devices adopted by the fourth capacitive device L4 are independent of each other, i.e., the devices adopted by each second delay circuit 22 are independent of each other.

[0049] It should be noted that in the embodiments of the present application, the devices independent of each other means that the devices can be the same or different. The devices being the same can include at least one of the type, number, and parameter of the devices being the same, and the devices being different can include at least one of the type, number, and parameter of the devices being different.

[0050] Since the bit control signals are independent of each other, the randomness of the time delay difference generated by the nth first delay circuit 21 and the nth second delay circuit 22 is independent of each other. Therefore, the N first delay circuits 21 connected in series and the N second delay circuits 22 connected in series also generate time delay differences when transmitting the excitation signal due to process deviation, and the more the number of the first delay circuits 21 and the second delay circuits 22, the greater the randomness of the time delay difference, which is more difficult to be predicted, copied, or tampered with.

[0051] The first comparison circuit 23 is configured to output a response signal according to the time delay difference between the first signal and the second signal. The first signal is the signal after the excitation signal is transmitted through the N first delay circuits 21 (i.e., the first transmission path), i.e., the N first delay circuits 21 input the excitation signal and output the first signal; the second signal is the signal after the excitation signal is transmitted through the N second delay circuits 22 (i.e., the second transmission path), i.e., the N second delay circuits 22 input the excitation signal and output the second signal. The response signal is used to indicate that the first signal is earlier or later than the second signal. It should be noted that the first comparison circuit involved in the present application can realize the comparison of the time delay difference between two signals through a NAND gate latch, or an NOR gate latch. The NAND gate latch can realize the comparison of the time delay difference between two signals by comparing the fast and slow arrival of the rising edges of the two signals, and the NOR gate latch can realize the comparison of the time delay difference between two signals by comparing the fast and slow arrival of the falling edges of the two signals. For example, the present application is described by taking the NAND gate latch as an example, but is not intended to be limited thereto.

[0052] For example, as shown in FIG. 2, the first delay circuit 21 and the second delay circuit 22 are connected in series to form a first transmission path, and the third delay circuit 23 and the fourth delay circuit 24 are connected in series to form a second transmission path. The first transmission path and the second transmission path are connected in parallel to form a transmission path of the excitation signal. The first signal is the signal after the excitation signal is transmitted through the first transmission path, i.e., the first signal is the signal after the excitation signal is transmitted through the N first delay circuits 21 connected in series; the second signal is the signal after the excitation signal is transmitted through the second transmission path, i.e., the second signal is the signal after the excitation signal is transmitted through the N second delay circuits 22 connected in series. Figures 2-4As shown, the first comparison circuit 23 comprises a first NAND-SR1 and optionally a first flip flop (FF) FF1. The first NAND-SR1 comprises a first NAND gate NAND1 and a second NAND gate NAND2.

[0053] The output of the Nth first delay circuit 21 is coupled to the first input of the first NAND gate NAND1, and the output of the Nth second delay circuit 22 is coupled to the first input of the second NAND gate NAND2. The output of the first NAND gate NAND1 is coupled to the second input of the second NAND gate NAND2, and the output of the second NAND gate NAND2 is coupled to the second input of the first NAND gate NAND1. The output of the first NAND gate NAND1 is used to output a response signal. The first NAND gate NAND1 and the second NAND gate NAND2 form a latch, thereby forming a NAND-SR1.

[0054] Optionally, the output of the first NAND gate NAND1 can also be coupled to the data input D of the first flip flop FF1, and the data output Q of the first flip flop FF1 is used to output a response signal synchronized with a clock signal. That is, when one clock signal pulse is input to the clock signal end CLK of the first flip flop FF1, the data output Q of the first flip flop FF1 outputs a bit of the response signal.

[0055] The principle of the first NAND-SR1 outputting a response signal according to the time delay difference between the first signal and the second signal is as follows:

[0056] Suppose that initially the Nth first delay circuit 21 and the Nth second delay circuit 22 both output 0, and the first NAND gate NAND1 and the second NAND gate NAND2 both output 1, forming a stable latch state. The excitation signal is a signal changing from low level (or digital 0) to high level (or digital 1). In addition, suppose that the excitation signal is transmitted through N first delay circuits 21 (i.e. the first transmission path) to obtain the first signal, and the excitation signal is transmitted through N second delay circuits 22 (i.e. the second transmission path) to obtain the second signal.

[0057] When the first signal is earlier than the second signal, the Nth first delay circuit 21 outputs 1, and the Nth second delay circuit 22 still outputs 0. Therefore, the first input and the second input of the first NAND gate NAND1 both input 1, so that the first NAND gate NAND1 outputs 0, and the first input and the second input of the second NAND gate NAND2 both input 0, so that the second NAND gate NAND2 outputs 1, and a stable latch state is formed again. At this time, the response signal output by the first NAND gate NAND1 is 0.

[0058] When the first signal is later than the second signal, the Nth first delay circuit 21 still outputs 0, the Nth second delay circuit 22 outputs 1, the first input end and the second input end of the second NAND gate NAND2 both input 1, so the second NAND gate NAND2 outputs 0, the first input end and the second input end of the first NAND gate NAND1 both input 0, so the first NAND gate NAND1 outputs 1, and a stable interlocking state is formed. At this time, the response signal output by the first NAND gate NAND1 is 1.

[0059] That is, when the first signal after the excitation signal is transmitted through the first transmission path is faster than the second signal after the excitation signal is transmitted through the second transmission path, the response signal is 0, and when the first signal is slower than the second signal, the response signal is 1.

[0060] In summary, the PUF circuit and the signature information generation device provided by the embodiments of the present application, the PUF circuit includes N first delay circuits in series, N second delay circuits in series and a comparison circuit. For the first delay circuit or the second delay circuit, it includes a selector, two delay devices and two groups of capacitive devices. Each delay device is coupled to a group of capacitive devices, and the selector selects one delay device to transmit the excitation signal. Since the time delay caused by the capacitive device as the load capacitance of the transmission path of the delay device is much larger than the time delay caused by the transmission of the signal by the delay device itself, and the capacitance parameter of the capacitive device is less affected by factors such as voltage and temperature, the overall time delay of the N first delay circuits and the N second delay circuits is less affected by factors such as voltage and temperature. Then the comparison circuit compares the time delay difference between the excitation signal transmitted through the Nth first delay circuit and the excitation signal transmitted through the Nth second delay circuit to output the response signal. The stability of the response signal is less affected by factors such as voltage and temperature, thereby improving the stability of the response signal generated by the PUF circuit.

[0061] As shown in Figure 4 , on the basis of Figure 2 , the PUF circuit can further include a fifth delay device D5, a sixth delay device D6, a second comparison circuit 24 and a third comparison circuit 25. Optionally, as shown in Figure 5 , on the basis of Figure 4 , the PUF circuit can further include at least one of a seventh delay device D7 and an eighth delay device D8, wherein the time delay generated by the seventh delay device D7 is less than the time delay generated by the fifth delay device D5, and the time delay generated by the eighth delay device D8 is less than the time delay generated by the sixth delay device D6. It should be noted that Figure 4 or Figure 5 the added devices can also be applied to Figure 2 . Figure 3 .

[0062] like Figure 4 As shown, the output of the Nth first delay circuit 21 is coupled to the first input of the second comparator circuit 24 via the fifth delay device D5. The output of the Nth second delay circuit 22 is coupled to the second input of the second comparator circuit 24. The second comparator circuit 24 outputs a first indication signal, which indicates whether the time delay difference between the first signal and the second signal is greater than a first threshold. At this time, the first threshold is equal to the time delay generated by the fifth delay device D5. Optionally, as... Figure 5 As shown, the output of the Nth second delay circuit 22 can also be coupled to the second input of the second comparator circuit 24 through the seventh delay device D7. In this case, the first threshold is equal to the delay generated by the fifth delay device D5 minus the delay generated by the seventh delay device D7. When the delay difference between the first signal and the second signal is greater than the first threshold, it indicates that the delay difference can be stably maintained over time, thus ensuring that the response signal's value of 0 is also stably maintained, resulting in higher reliability of the response signal. Otherwise, it indicates that this delay difference is difficult to maintain stably, making it difficult to maintain the response signal's value of 0 stably maintained, thus resulting in lower reliability of the response signal.

[0063] like Figure 4 As shown, the output of the Nth second delay circuit 22 is coupled to the first input of the third comparator circuit 25 via the sixth delay device D6. The output of the Nth first delay circuit 22 is coupled to the second input of the third comparator circuit 25. The third comparator circuit 25 outputs a second indication signal, which indicates whether the time delay difference between the second signal and the first signal is greater than a second threshold. At this time, the second threshold is equal to the time delay generated by the sixth delay device D6. Optionally, as... Figure 5 As shown, the output of the Nth first delay circuit 21 can also be coupled to the second input of the third comparator circuit 25 through the eighth delay device D8. In this case, the second threshold is equal to the delay generated by the sixth delay device D6 minus the delay generated by the eighth delay device D8. When the delay difference between the second signal and the first signal is greater than the second threshold, it indicates that this delay difference can be stably maintained over time, thus ensuring the value of the response signal (1) remains stable, resulting in higher reliability of the response signal. Otherwise, it indicates that this delay difference is difficult to maintain stably, making it difficult to maintain the value of the response signal (1) stable, resulting in lower reliability of the response signal.

[0064] It should be noted that, similar to the first comparison circuit 23, the second comparison circuit 24 and the third comparison circuit 25 involved in the present application can also realize the comparison of the time delay difference of two signals through NAND latch, or NOR latch. Exemplarily, the present application takes NAND latch as an example for illustration, but is not intended to be limited thereto. In addition, the PUF circuit shown in the following is taken as an example for illustration, but is not intended to be limited thereto, which can also be applied to the PUF circuit shown in Figure 4 Figure 5

[0065] Exemplarily, the second comparison circuit 24 comprises a second NAND latch NAND-SR2, and optionally, can further comprise a second flip-flop FF2. The second NAND latch NAND-SR2 comprises a third NAND gate NAND3 and a fourth NAND gate NAND4. The third comparison circuit 25 comprises a third NAND latch NAND-SR2, and optionally, can further comprise a third flip-flop FF3. The third NAND latch NAND-SR3 comprises a fifth NAND gate NAND5 and a sixth NAND gate NAND6.

[0066] The output end of the Nth first delay circuit 21 is coupled to the first input end of the third NAND gate NAND3 through a fifth delay device D5, and the output end of the fourth NAND gate NAND4 is coupled to the second input end of the third NAND gate NAND3; the output end of the Nth second delay circuit 22 is coupled to the first input end of the fourth NAND gate NAND4, and the output end of the third NAND gate NAND3 is coupled to the second input end of the fourth NAND gate NAND4; wherein the output end of the third NAND gate NAND3 is used to output a first indication signal. The third NAND gate NAND3 and the fourth NAND gate NAND4 form a mutual lock, thereby forming a NAND latch.

[0067] Optionally, the output end of the third NAND gate NAND3 can also be coupled to the data input end D of the second flip-flop FF2, and the data output end Q of the second flip-flop FF2 is used to output the first indication signal synchronized with the clock signal. That is, every time the clock signal end CLK of the second flip-flop FF2 inputs a pulse of the clock signal, the data output end Q of the second flip-flop FF2 will output a bit of the first indication signal.

[0068] ​​The output terminal of the Nth second delay circuit 22 is coupled to the first input terminal of the fifth NAND gate NAND5 through the sixth delay device D6, and the output terminal of the sixth NAND gate NAND6 is coupled to the second input terminal of the fifth NAND gate NAND5; the output terminal of the Nth first delay circuit 21 is coupled to the first input terminal of the sixth NAND gate NAND6, and the output terminal of the fifth NAND gate NAND5 is coupled to the second input terminal of the sixth NAND gate NAND6; wherein the output terminal of the fifth NAND gate NAND5 is used to output the second indication signal. The fifth NAND gate NAND5 and the sixth NAND gate NAND6 form interlocking, thereby forming a NAND gate latch.

[0069] Alternatively, the output terminal of the fifth NAND gate NAND5 can also be coupled to the data input terminal D of the third flip-flop FF3. The data output terminal Q of the third flip-flop FF3 is used to output the second indication signal synchronized with the clock signal. That is, every time a clock signal pulse is input to the clock signal terminal CLK of the third flip-flop FF3, the data output terminal Q of the third flip-flop FF3 outputs a bit of the second indication signal.

[0070] The principle of outputting the first indication signal by the above-mentioned second NAND gate latch NAND-SR2 and outputting the second indication signal by the third NAND gate latch NAND-SR3 is as follows:

[0071] Suppose that in the initial state, the Nth first delay circuit 21 and the Nth second delay circuit 22 both output 0, then the third NAND gate NAND3, the fourth NAND gate NAND4, the fifth NAND gate NAND5 and the sixth NAND gate NAND6 all output 1, forming a stable interlocking state. The excitation signal is a signal changing from low level (or digital 0) to high level (or digital 1). In addition, suppose that the excitation signal is transmitted through the N first delay circuits 21 (i.e. the first transmission path) to obtain the first signal, and the excitation signal is transmitted through the N second delay circuits 22 (i.e. the second transmission path) to obtain the second signal.

[0072] As described above, when the first signal is earlier than the second signal, the response signal is 0. In this condition:

[0073] Case one: when the time delay difference between the first signal and the second signal is greater than the first threshold value, the first signal is delayed through the fifth delay device D5, and the Nth second delay circuit 22 still outputs 0, then the first input terminal and the second input terminal of the third NAND gate NAND3 both input 1, so the output terminal of the third NAND gate NAND3 outputs 0, making the first input terminal and the second input terminal of the fourth NAND gate NAND4 both input 0, so the fourth NAND gate NAND4 outputs 1, and a stable interlocking state is formed. At this time, the first indication signal output by the third NAND gate NAND3 is 0.

[0074] Case two: when the time delay difference between the first signal and the second signal is less than the first threshold, the first signal is delayed by the fifth delay device D5, the Nth second delay circuit 22 outputs 1 first, the first input and the second input of the fourth NAND gate NAND4 are both input 1, so the output of the fourth NAND gate NAND4 outputs 0, the first input and the second input of the third NAND gate NAND3 are both input 0, so the third NAND gate NAND3 outputs 1, and a stable interlocking state is formed. At this time, the first indication signal output by the third NAND gate NAND1 is 1.

[0075] And no matter case one or case two, the first input of the fifth NAND gate NAND5 is input 0, so the second indication signal output by the output of the fifth NAND gate NAND5 is always 1, which is not used to indicate whether the value 0 of the response signal is valid.

[0076] In summary, when the response signal is 0, the first indication information is 0, and the value 0 of the response signal is valid; when the first indication information is 1, the value 0 of the response signal is invalid.

[0077] As described above, when the second signal is earlier than the first signal, the response signal is 1. Under this condition:

[0078] Case three: when the time delay difference between the second signal and the first signal is greater than the second threshold, the second signal is delayed by the sixth delay device D6, the Nth first delay circuit 21 still outputs 0, the first input and the second input of the fifth NAND gate NAND5 are both input 1, so the output of the fifth NAND gate NAND5 outputs 0, the first input and the second input of the sixth NAND gate NAND6 are both input 0, so the sixth NAND gate NAND6 outputs 1, and a stable interlocking state is formed. At this time, the second indication signal output by the fifth NAND gate NAND5 is 0.

[0079] Case four: when the time delay difference between the second signal and the first signal is less than the second threshold, the second signal is delayed by the sixth delay device D6, the Nth first delay circuit 21 outputs 1 first, the first input and the second input of the sixth NAND gate NAND6 are both input 1, so the output of the sixth NAND gate NAND6 outputs 0, the first input and the second input of the fifth NAND gate NAND5 are both input 0, so the fifth NAND gate NAND5 outputs 1, and a stable interlocking state is formed. At this time, the second indication signal output by the fifth NAND gate NAND5 is 1.

[0080] And no matter case three or case four, the first input of the third NAND gate NAND3 is input 0, so the first indication signal output by the output of the third NAND gate NAND3 is always 1, which is not used to indicate whether the value 1 of the response signal is valid.

[0081] In summary, when the response signal is 1, the second indication information is 0, the value 1 of the response signal is valid, and when the second indication information is 1, the value 1 of the response signal is invalid.

[0082] In addition, the clock signal terminals CLK of the first flip-flop FF1, the second flip-flop FF2 and the third flip-flop FF3 input the same clock signal. As described above, when the clock signal terminal CLK of the first flip-flop FF1 inputs one pulse of the clock signal, the data output terminal Q of the first flip-flop FF1 outputs one bit of the response signal; when the clock signal terminal CLK of the second flip-flop FF2 inputs one pulse of the clock signal, the data output terminal Q of the second flip-flop FF2 outputs one bit of the first indication signal; and when the clock signal terminal CLK of the third flip-flop FF3 inputs one pulse of the clock signal, the data output terminal Q of the third flip-flop FF3 outputs one bit of the second indication signal. That is, the response signal, the first indication signal and the second indication signal correspond to each bit, and when the response signal has M bits, the first indication signal and the second indication signal also have M bits, and each bit of the first indication signal and the second indication signal indicates the reliability of one bit of the response signal.

[0083] In summary, Figure 4 The PUF circuit shown can also output the first indication signal and the second indication signal, the first indication signal is used to indicate whether the time delay difference of the first signal earlier than the second signal is greater than the first threshold value, the second indication signal is used to indicate whether the time delay difference of the second signal earlier than the first signal is greater than the second threshold value, the first signal is the signal of the excitation signal transmitted through the N first delay circuits in series in the PUF circuit, and the second signal is the signal of the excitation signal transmitted through the N second delay circuits in series in the PUF circuit. The two indication signals actually indicate whether the value of each bit of the response signal is stable, so that each stable bit of the response signal can be used as one bit of the signature information, thereby improving the efficiency of generating the signature information.

[0084] The following describes how the processor 11 obtains the signature information according to the response signal, wherein each bit of the signature information is taken from one bit of the response signal.

[0085] In a possible implementation, the processor 11 can select any bit of the response signal to obtain the signature information, for example, when the response signal output by the PUF circuit has M bits, the first M / 2 bits can be combined to obtain the signature information, and when M = 256, the signature information can have 128 bits.

[0086] In another possible implementation, the processor 11 can obtain the signature information according to one of the first indication signal or the second indication signal and the response signal. In addition, the processor 11 can obtain the third indication signal according to one of the first indication signal or the second indication signal, the third indication signal being used to indicate whether each bit of the response signal is valid, when the response signal has M bits, the third indication signal also has M bits.

[0087] As described above, when the first signal is earlier than the second signal, the response signal is 0. Further, for case one, when the first indication signal indicates that the time delay difference of the first signal being earlier than the second signal is greater than the first threshold, the first indication signal is 0, the second indication signal is 1, then the third indication signal indicates that this one bit of the response signal is valid (for example, the third indication signal takes value 1), this one bit of the response signal can be used as one bit of the signature information. Otherwise for case two, when the first indication signal indicates that the time delay difference of the first signal being earlier than the second signal is not greater than the first threshold, the first indication signal is 1, the second indication signal is 1, then the third indication signal indicates that this one bit of the response signal is invalid (for example, the third indication signal takes value 0), this one bit of the response signal cannot be used as one bit of the signature information.

[0088] As described above, when the second signal is earlier than the first signal, the response signal is 1. Further, for case three, when the second indication signal indicates that the time delay difference of the second signal being earlier than the first signal is greater than the second threshold, the second indication signal is 0, the first indication signal is 1, then the third indication signal indicates that this one bit of the response signal is valid (for example, the third indication signal takes value 1), this one bit of the response signal can be used as one bit of the signature information; otherwise for case four, when the second indication signal indicates that the time delay difference of the second signal being earlier than the first signal is not greater than the second threshold, the second indication signal is 1, the first indication signal is 1, then the third indication signal indicates that this one bit of the response signal is invalid (for example, the third indication signal takes value 0), this one bit of the response signal cannot be used as one bit of the signature information.

[0089] When the response signal outputted by the PUF circuit has M bits, the signature information can be obtained by taking the first M / 2 valid bit combinations. For example, when M=256, the signature information can have 128 bits.

[0090] The value of each bit of the above-mentioned response signal, the first indication signal, the second indication signal, the third indication signal and the signature information can refer to the truth table shown in Table 1. Wherein X represents that the bit of the response signal is not used as one bit of the signature information.

[0091] Table 1

[0092] Response signal First indication signal Second indication signal Third indication signal Signature information Case one 0 0 1 1 (valid) 0 Case two 0 1 1 0 (invalid) X Case three 1 1 0 1 (valid) 1 Case four 1 1 1 0 (invalid) X

[0093] The division of the modules is only a logical function division, and in actual implementation, there can be another division manner, for example, multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the modules or components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or modules, and can be electrical or other forms.

[0094] The modules described as separate components can or can not be physically separated, and the components shown as modules can or can not be physical modules, that is, can be located in one device, or can be distributed to multiple devices. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0095] In addition, the functional modules in each embodiment of the present application can be integrated in one device, or each module can exist physically alone, or two or more modules can be integrated in one device.

[0096] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A physically unclonable function, PUF, circuit, characterized by, The PUF circuit comprises: a first comparison circuit, N first delay circuits connected in series, and N second delay circuits connected in series; the first delay circuit comprises a first delay device, a first capacitive device, a second delay device, a second capacitive device, and a first selector; the second delay circuit comprises a third delay device, a third capacitive device, a fourth delay device, a fourth capacitive device, and a second selector; N is a positive integer; for each first delay circuit, the first delay device is coupled to the first capacitive device and a first terminal of the first selector, and the second delay device is coupled to the second capacitive device and a second terminal of the first selector; for each second delay circuit, the third delay device is coupled to the third capacitive device and a first terminal of the second selector, and the fourth delay device is coupled to the fourth capacitive device and a second terminal of the second selector; the N first delay circuits are used to input an excitation signal and output a first signal; the N second delay circuits are used to input the excitation signal and output a second signal; the first comparison circuit is used to output a response signal according to a time delay difference between the first signal and the second signal, and the response signal is used to indicate whether the first signal is earlier or later than the second signal.

2. The PUF circuit of claim 1, wherein, The PUF circuit further comprises a fifth delay device and a second comparison circuit; an output terminal of an Nth first delay circuit in the N first delay circuits is coupled to a first input terminal of the second comparison circuit through the fifth delay device, and an output terminal of an Nth second delay circuit in the N second delay circuits is coupled to a second input terminal of the second comparison circuit, and the second comparison circuit is used to output a first indication signal, and the first indication signal is used to indicate whether the time delay difference by which the first signal is earlier than the second signal is greater than a first threshold value.

3. The PUF circuit of claim 2, wherein, The PUF circuit further comprises a seventh delay device, and a time delay generated by the seventh delay device is less than a time delay generated by the fifth delay device; the output terminal of the Nth second delay circuit is coupled to the second input terminal of the second comparison circuit through the seventh delay device.

4. The PUF circuit according to any one of claims 1-3, characterized in that, The PUF circuit further comprises a sixth delay device and a third comparison circuit; an output terminal of the Nth second delay circuit in the N second delay circuits is coupled to a first input terminal of the third comparison circuit through the sixth delay device, and an output terminal of the Nth first delay circuit in the N first delay circuits is coupled to a second input terminal of the third comparison circuit, and the third comparison circuit is used to output a second indication signal, and the second indication signal is used to indicate whether the time delay difference by which the second signal is earlier than the first signal is greater than a second threshold value.

5. The PUF circuit of claim 4, wherein, The PUF circuit further comprises an eighth delay device, and a time delay generated by the eighth delay device is less than a time delay generated by the sixth delay device; the output terminal of the Nth first delay circuit is coupled to the second input terminal of the third comparison circuit through the eighth delay device.

6. The PUF circuit according to any one of claims 1-5, characterized in that, The first comparison circuit comprises a NAND gate latch or a NOR gate latch.

7. The PUF circuit according to any one of claims 1-6, characterized in that, For the nth first delay circuit and the nth second delay circuit, 1≤n≤N, and n is a positive integer: When the first selector selects the first delay device to transmit the excitation signal, the second selector selects the third delay device to transmit the excitation signal; the first delay device and the third delay device adopt the same device, and the first capacitive device and the third capacitive device adopt the same device; When the first selector selects the second delay device to transmit the excitation signal, the second selector selects the fourth delay device to transmit the excitation signal; the second delay device and the fourth delay device adopt the same device, and the second capacitive device and the fourth capacitive device adopt the same device.

8. The PUF circuit according to any one of claims 1-7, characterized in that, For any two first delay circuits in the series of N first delay circuits: the first delay devices adopt mutually independent devices, the second delay devices adopt mutually independent devices, the first capacitive devices adopt mutually independent devices, and the second capacitive devices adopt mutually independent devices.

9. The PUF circuit according to any one of claims 1-8, characterized in that, For any two second delay circuits in the series of N second delay circuits: the third delay devices adopt mutually independent devices, the fourth delay devices adopt mutually independent devices, the third capacitive devices adopt mutually independent devices, and the fourth capacitive devices adopt mutually independent devices.

10. A signature information generating apparatus characterized by comprising: A physical unclonable function (PUF) circuit and a processor comprising the PUF circuit according to any one of claims 1-9; The processor is configured to output an excitation signal to the PUF circuit; The processor is further configured to receive a response signal corresponding to the excitation signal from the PUF circuit; The processor is further configured to output signature information according to the response signal, the signature information being used for encrypting information output by the processor.

11. The signature information generating apparatus according to claim 10, wherein The processor is further configured to: receive a first indication signal or a second indication signal from the PUF circuit, the first indication signal being used for indicating whether a time delay difference of the first signal being earlier than the second signal is greater than a first threshold value, and the second indication signal being used for indicating whether a time delay difference of the second signal being earlier than the first signal is greater than a second threshold value; obtain the signature information according to one of the first indication signal or the second indication signal and the response signal, each bit of the signature information being taken from an effective bit in the response signal, the effective bit in the response signal being a bit in the response signal when the first indication signal indicates that the time delay difference of the first signal being earlier than the second signal is greater than the first threshold value, or when the second indication signal indicates that the time delay difference of the second signal being earlier than the first signal is greater than the second threshold value.

12. The signature information generating apparatus according to claim 11, wherein The processor is further configured to: obtain a third indication signal according to one of the first indication signal or the second indication signal, the third indication signal being used for indicating whether each bit of the response signal is effective.

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