Circuit partitioning method, equivalence verification method, and storage medium

Abstract

The application discloses a circuit partitioning method, an equivalence verification method, and a storage medium. The circuit partitioning method comprises the following steps: firstly, equivalence verification is performed on the combination logic of a reference circuit and an implementation circuit to obtain registers with matching failure and registers failing in combination logic equivalence verification; the registers with matching failure and the registers failing in combination logic equivalence verification are taken as possible partition nodes, and all cone tops of the possible partition nodes are searched; when any two possible partition nodes have the same cone top, the two possible partition nodes are divided into a group; and the reference circuit and the corresponding implementation circuit are divided in a group unit, and the registers in the group and the corresponding combination circuit are divided into a local circuit. The application can simplify the complexity of large-scale netlist circuit equivalence verification and improve the efficiency of large-scale netlist circuit equivalence verification.

Description

Technical Field

[0001] This invention relates to the technical field of equivalence verification of sequential circuits, and more particularly to a method for dividing circuits, namely, a method for identifying and segmenting locally time-equivalent circuits. Background Technology

[0002] Equivalence verification, a type of formal verification, refers to the mathematically complete proof or verification of whether a circuit implementation achieves the functionality described in the circuit design. Equivalence verification is often used for functional consistency verification between lower-level circuits, such as verification between the RTL level and gate-level netlists before and after synthesis. With the rapid increase in the scale of integrated circuits, verification has become increasingly difficult, and traditional simulation and modeling methods have revealed drawbacks such as long processing times and low verification coverage. Compared to traditional methods, equivalence verification uses mathematical methods to directly compare the implemented circuit with the reference circuit, eliminating the need to develop test vectors, significantly reducing verification time, and achieving 100% verification coverage.

[0003] Traditional verification of the functional equivalence of combinational circuits involves constructing the canonical representations of two circuits, such as truth tables or binary decision graphs (BDDS). Two circuits are functionally equivalent if and only if their canonical forms are isomorphic. To verify the equivalence of two sequential circuits, it is typically necessary to treat them as finite state machines and construct their product automata. Brand calls this computational model Miter. It works by concatenating each pair of primitive inputs of the two state machines together and each pair of primitive outputs together to an XOR gate, which constitutes the output of the product automaton. If for every input sequence, every primitive output of the product automaton is always 0, then the two sequential circuits are equivalent. In other words, for any input vector and reachable state, the primitive output response of the product automaton is always 0. Typically, the first step in proving the equivalence of state machines is to start from the initial state and compute all reachable states. This is a typical algorithm based on finite state machine traversal.

[0004] Therefore, to verify the equivalence of two combinational circuits, we can construct their output miter circuits (sharing a common input signal and connecting their outputs with XOR gates), and then use the SAT solver (Satisfiability Problem Solver) to solve the miter circuits. If the SAT solver cannot find a set of inputs that makes the miter circuit's output 1, then the two circuits are proven to be equivalent. For sequential circuits, it is necessary to divide the circuit into multiple combinational logic blocks along the registers, map each of the divided combinational logic blocks to create miter circuits, and then use the SAT solver to solve them.

[0005] However, due to the optimization strategies of synthesis tools, the synthesized gate-level netlist may have some inequivalent matching points with its RTL-level netlist during combinational logic equivalence verification, but they will be equivalent when performing temporal equivalence verification. However, performing temporal equivalence verification on two complete netlists has high requirements, necessitating a sufficiently small netlist size. When the netlist size is large, the time required to complete the temporal equivalence verification becomes unacceptable.

[0006] Therefore, how to provide a method for partitioning circuits to cut large netlists into local circuits is a technical problem to be solved. Summary of the Invention

[0007] To address the unacceptable time required for timing equivalence verification of large-scale netlists in existing technologies, this invention proposes a circuit partitioning method, an equivalence verification method, and a storage medium.

[0008] The circuit partitioning method proposed in this invention includes:

[0009] First, perform equivalence verification on the combinational logic of the reference circuit and the implementation circuit to obtain the registers that fail to match and / or the registers that fail the combinational logic equivalence verification.

[0010] The registers that fail to match and / or fail the combinational logic equivalence verification are taken as possible partition nodes, and all cone vertices of each possible partition node are found.

[0011] If any two possible partitioning nodes have the same cone vertices, they are partitioned into one group;

[0012] The reference circuit and its corresponding implementation circuit are divided into groups, and the registers and corresponding combinational circuits within a group are divided into local circuits.

[0013] Furthermore, the implementation circuit is a timing-optimized circuit.

[0014] Furthermore, the cone apex is the D terminal of the load-direction register and / or the main output of the top-level module.

[0015] The circuit equivalence verification method proposed in this invention uses the circuit partitioning method described in the above technical solution to partition the reference circuit and its corresponding implementation circuit, thereby obtaining the local circuit of the reference circuit and the local circuit of the implementation circuit.

[0016] Determine whether the inputs and outputs of the reference circuit and its corresponding implementation circuit are equal and matched. If so, perform equivalence verification on the local circuits of the reference circuit and the corresponding implementation circuit. Otherwise, specify the inputs and outputs of the reference circuit and its corresponding implementation circuit to make them equal and matched before performing equivalence verification.

[0017] The present invention proposes a computer-readable storage medium for storing a computer program, which, when executed, performs the circuit partitioning method described in the above technical solution.

[0018] This invention enables the correct identification and segmentation of potential local timing equivalence circuits after combinatorial equivalence verification results are obtained, and then performs timing equivalence verification on the segmented local circuits. This invention solves the problem that when synthesis tools perform local timing optimizations on the circuit, combinatorial equivalence verification of RTL-level and gate-level circuits fails, while global timing equivalence verification is too complex. The application of this invention in the formal verification of RTL-level and gate-level circuits will significantly reduce verification time. Attached Figure Description

[0019] The present invention will now be described in detail with reference to the embodiments and accompanying drawings, wherein:

[0020] Figure 1 This is a flowchart of an embodiment of the present invention. Detailed Implementation

[0021] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0022] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0023] A reference circuit is a circuit used as a reference standard in equivalence verification. The implementation circuit needs to be proven to be equivalent to the reference circuit. The reference circuit is usually RTL-level Verilog code, and the implementation circuit is usually a synthesized gate-level circuit. The equivalence verification referred to in this invention refers to the equivalence verification of two sequential circuits, namely the reference circuit and the implementation circuit. Sequential circuits contain registers and related combinational logic circuits. Equivalence verification is divided into combinational logic equivalence verification and timing equivalence verification. Combinational logic equivalence verification refers to verifying the equivalence of two circuits that only contain combinational logic. Timing equivalence verification refers to verifying the equivalence of two circuits that contain sequential logic, i.e., registers and related combinational logic. Therefore, combinational logic does not contain registers. Combinational logic equivalence verification essentially involves matching the registers of the two sequential circuits one by one, then cutting out a pair of combinational logic circuits that drive this pair of registers, and finally performing combinational logic equivalence verification on this pair of combinational logic circuits.

[0024] like Figure 1 As shown, the circuit partitioning method proposed in this invention mainly includes the following steps.

[0025] The combinational logic of the reference circuit and its implementation circuit is subjected to equivalence verification to obtain registers that fail to match and / or registers that fail the combinational logic equivalence verification. That is, registers are first matched to obtain registers that fail to match; then, the combinational logic corresponding to the successfully matched registers is subjected to equivalence verification to obtain registers that fail the combinational logic equivalence verification. Registers that fail to match are not subjected to combinational logic equivalence verification because there is no corresponding register and the combinational logic circuit driving that register for comparison.

[0026] The registers that fail to match and / or fail the combinational logic equivalence verification are taken as possible partition nodes, and all cone vertices of each possible partition node are found.

[0027] If any two possible partitioning nodes have the same cone vertices, they are partitioned into one group;

[0028] The reference circuit and its corresponding implementation circuit are divided into groups, and the registers and corresponding combinational circuits within a group are divided into local circuits.

[0029] In one embodiment, the process of finding the apex of a cone includes the following steps.

[0030] First, collect the registers that failed the combinational logic equivalence verification and the registers that failed the matching. These registers will be referred to as possible split nodes.

[0031] Starting from the output of these possible nodes, perform a depth-first traversal, that is, from the input of a gate to the output of the same gate. When the traversal reaches the output port of the top-level module or the D terminal of a register that has passed the combinational logic equivalence verification in the first round, stop the traversal and record the traversed register as the cone apex, that is, the output of the top-level module.

[0032] For example, after the steps described above for finding the cone vertices, we find that register A's cone vertices include register 2, register B's cone vertices include register 2 and register 3, and register C's cone vertices include register 3. Therefore, registers A, B, and C are all grouped into the same group. Since registers A and B share a common cone vertices—register 2—they are initially grouped together. At this point, there are two registers in the group, and the union of the cone vertices of these two registers constitutes the cone vertices of the group. That is, if register A's cone vertices are 2, then the cone vertices of the group containing register A are 2 and 3. If the set of cone vertices of a register to be grouped intersects with the set of cone vertices of a certain group, then that register is assigned to that group. The set of cone vertices of that group is then the union of the sets of cone vertices of all registers within that group.

[0033] In one embodiment, timing optimization can be performed on the implementation circuit, and then the combinational logic of the timing-optimized implementation circuit and the reference circuit can be verified for equivalence to obtain the registers that fail to match and / or the registers that fail the combinational logic equivalence verification.

[0034] In one embodiment, the cone apex may be the D terminal of the load-direction register and / or the main output of the top-level module.

[0035] The load direction is the direction from the input terminal of a gate to its output terminal. A top-level module refers to the module at the very top of a hierarchical structure. Circuit design typically consists of a top-level module containing several sub-modules.

[0036] The circuit equivalence verification method of the present invention divides a reference circuit and its corresponding implementation circuit using the aforementioned circuit partitioning method, obtaining local circuits of the reference circuit and local circuits of the implementation circuit. It then determines whether the inputs and outputs of the local circuits of the reference circuit and the corresponding local circuits of the implementation circuit are equal and matched. If the number of inputs and outputs are equal and matched, the local circuits of the reference circuit and the corresponding local circuits of the implementation circuit are subjected to equivalence verification. Otherwise, the inputs and outputs of the mismatched local circuits are specified manually or by other means, so that the local circuits of the reference circuit and the corresponding local circuits of the implementation circuit can satisfy the input and output conditions for equivalence verification.

[0037] The inputs and outputs of the partitioned local circuits are not necessarily equal in number or matched. Only local circuits with equal and matched input and output numbers can undergo timing equivalence verification. Generally, if timing optimization of the implementation circuit results in a large proportion of mismatched registers, the number of inputs and outputs of the partitioned local circuits may be unequal or mismatched. In this case, manual intervention is required to specify the inputs and outputs of the local circuits so that the local circuits can be partitioned according to the specified inputs and outputs and timing equivalence verification can be performed.

[0038] The circuit partitioning method of this invention can divide a large-scale netlist circuit into local circuits, thereby reducing the complexity of verification, reducing the verification time of the circuit, and improving the verification efficiency of the circuit.

[0039] The present invention also protects a computer-readable storage medium for storing a computer program that, when executed, performs the circuit partitioning method of the above-described technical solution of the present invention.

[0040] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for dividing a circuit, characterized in that, include: First, perform equivalence verification on the combinational logic of the reference circuit and the implementation circuit to obtain the registers that fail to match and / or the registers that fail the combinational logic equivalence verification. The registers that fail to match and / or fail the combinational logic equivalence verification are taken as possible partition nodes, and all cone vertices of each possible partition node are found. If any two possible partitioning nodes have the same cone vertices, they are partitioned into one group; The reference circuit and its corresponding implementation circuit are divided into groups, and the registers and corresponding combinational circuits within a group are divided into local circuits.

2. The circuit partitioning method as described in claim 1, characterized in that, The implementation circuit is a timing-optimized circuit.

3. The circuit partitioning method as described in claim 1, characterized in that, The cone apex is the D terminal of the load-direction register and / or the main output of the top-level module.

4. The circuit partitioning method as described in claim 1, characterized in that, The vertex of any set is the union of the vertices of all possible split nodes within that set.

5. The circuit partitioning method as described in claim 1, characterized in that, The process of finding all cone vertices of each possible segmentation node includes: The traversal starts from the output of each possible node and stops when the traversal reaches the output port of the top-level module or the D end of the register that has passed the verification in the first round of combinational logic equivalence verification. The traversed register is recorded as the cone apex.

6. A method for verifying the equivalence of a circuit, characterized in that, The reference circuit and its corresponding implementation circuit are divided using the circuit division method described in any one of claims 1 to 5 to obtain a local circuit of the reference circuit and a local circuit of the implementation circuit. Determine whether the inputs and outputs of the reference circuit and its corresponding implementation circuit are equal and matched. If so, perform equivalence verification on the local circuits of the reference circuit and the corresponding implementation circuit. Otherwise, specify the inputs and outputs of the reference circuit and its corresponding implementation circuit to make them equal and matched before performing equivalence verification.

7. A computer-readable storage medium for storing a computer program, characterized in that, When the computer program is executed, it performs the circuit partitioning method as described in any one of claims 1 to 5.

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