Gate driving circuit and display device including the same

Abstract

A gate drive circuit and a display device including the same are provided. The gate drive circuit includes: a first output unit for outputting a first scan pulse that swings between a gate-on voltage and a first gate-off voltage; a second output unit for outputting a second scan pulse that swings between the gate-on voltage and a second gate-off voltage; and a controller for controlling the first and second output units. The first gate-off voltage is set to be higher or lower than the second gate-off voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0130033, filed on September 30, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit. Background Art

[0004] Depending on the material of the emission layer, electroluminescent display devices may include inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices include organic light-emitting diodes (hereinafter referred to as "OLEDs") that emit light by themselves, and have the advantages of fast response speed, high luminous efficiency, high brightness, and wide viewing angle. In an organic light-emitting display device, an OLED (organic light-emitting diode) is formed in each pixel. The organic light-emitting display device has a fast response speed, excellent luminous efficiency, brightness, and viewing angle, and because the black grayscale can be expressed as full black, it also has excellent contrast and color reproducibility.

[0005] The pixel circuit of an organic light-emitting display device may include a light-emitting element serving as a light-emitting element, a driver element for driving the light-emitting element, a capacitor for storing the gate-source voltage of the driver element, and multiple switching elements. In the pixel circuit, leakage current may occur through the switching element connected to the capacitor in the off state, thereby discharging the voltage of the capacitor. As a result, the brightness and retention characteristics of the pixel may be reduced. Summary of the Invention

[0006] An object of the present disclosure is to meet the above-mentioned needs and / or solve the above-mentioned problems.

[0007] The present disclosure provides a gate driving circuit for preventing a decrease in pixel luminance due to leakage current in a switching element and improving a retention characteristic of a pixel, and a display device including the gate driving circuit.

[0008] Aspects of the present disclosure are not limited thereto, and other aspects not described herein will be clearly understood by those of ordinary skill in the art from the following description.

[0009] According to an embodiment of the present disclosure, the gate driving circuit includes: an (N-1)th signal transmitter, to which a start pulse or a carry signal, a shift clock, a gate-on voltage, a first gate-off voltage, and a second gate-off voltage are applied, where N is a natural number; and an Nth signal transmitter, to which the carry signal from the (N-1)th signal transmitter, the shift clock, the gate-on voltage, the first gate-off voltage, and the second gate-off voltage are applied.

[0010] Each of the (N-1)th signal transmitter and the Nth signal transmitter includes: a first output portion configured to output a first scanning pulse swinging between the gate-on voltage and the first gate-off voltage; a second output portion configured to output a second scanning pulse swinging between the gate-on voltage and the second gate-off voltage; and a controller configured to control the first output portion and the second output portion.

[0011] The first gate-off voltage is set to be higher or lower than the second gate-off voltage.

[0012] A display device according to an embodiment of the present disclosure includes: a pixel array including a plurality of data lines, a plurality of gate lines, a plurality of power lines to which a constant voltage is applied, and a plurality of sub-pixels; a data driver configured to apply a data voltage to the plurality of data lines; and a gate driver configured to sequentially provide scan pulses to the plurality of gate lines using a shift register.

[0013] The shift register includes the (N-1)th signal transmitter and the Nth signal transmitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0015] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure;

[0016] Figure 2 yes Figure 1 A cross-sectional view of the display panel shown;

[0017] Figure 3 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

[0018] Figure 4 is a circuit diagram of various pixel circuits applicable to the pixel circuit of the present disclosure;

[0019] Figure 5 It shows Figure 4A waveform diagram of a driving method for a pixel circuit;

[0020] Figure 6 shows a gate driving circuit according to an embodiment of the present disclosure;

[0021] Figure 7A and Figure 7B is a graph showing gate-off voltages of scan pulses having different voltages;

[0022] Figure 8 yes Figure 6 A circuit diagram of an example of the (N-1)th signal transmitter shown; and

[0023] Figure 9 yes Figure 6 The waveforms of the input and output signals and the control node voltage of the signal transmitter are shown. DETAILED DESCRIPTION

[0024] The advantages and features of the present disclosure and their implementation methods will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in a variety of different forms. On the contrary, the present disclosure is intended to complete the disclosure and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0025] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, similar reference numerals generally represent similar elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0026] Terms such as "including," "comprising," "having," and "consisting of" used herein are generally intended to allow the addition of other components unless these terms are used with the term "only." Any reference to the singular may include the plural unless expressly stated otherwise.

[0027] Even if not explicitly stated, components are interpreted as including the usual margin of error.

[0028] When terms such as "on," "over," "below," and "adjacent" are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used with the terms "immediately" or "directly."

[0029] Although "first," "second," and the like are used to describe various components in the embodiments, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component described below may be referred to as the second component without departing from the technical scope of the present disclosure.

[0030] Throughout the specification, the same reference numerals refer to the same components.

[0031] The features of the various embodiments may be partially or fully combined with each other, or implemented technically in association with each other in various ways, and the embodiments may be implemented independently of each other or together.

[0032] The pixel circuit and gate drive unit formed on the display panel of the present disclosure may include a plurality of transistors. Each transistor may be embodied as an oxide thin film transistor (TFT) including an oxide semiconductor, a low-temperature polysilicon (LTPS) TFT including low-temperature polysilicon (LTPS), or the like. Each transistor may be embodied as a p-channel TFT or an n-channel TFT.

[0033] A transistor is a three-electrode component consisting of a gate, a source, and a drain. The source is the electrode through which charge carriers are supplied to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers exit the transistor. In a transistor, charge carriers flow from the source to the drain. In an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In a p-channel transistor, since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, the present disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as first and second electrodes.

[0034] The gate pulse can swing between a gate-on voltage and a gate-off voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be a gate high voltage VGH and VEH, and the gate-off voltage can be a gate low voltage VGL and VEL.

[0035] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be mainly described as an organic light emitting display device, but the present disclosure is not limited thereto.

[0036] refer to Figure 1 and Figure 2 The display device according to an embodiment of the present disclosure includes a display panel 100, display panel drivers 110 and 120 for writing pixel data of an input image into pixels of the display panel 100, a timing controller 130 for controlling the display panel drivers 110 and 120, and a power supply 150 for generating power required to drive the display panel 100.

[0037] The display panel 100 includes a pixel array AA that displays an input image on a screen. The pixel array AA includes a plurality of data lines DL, a plurality of gate lines GL crossing the data lines DL, a power supply line for applying a constant voltage (or a direct current (DC) voltage), and pixels arranged in a matrix defined by the data lines DL and the gate lines GL.

[0038] Each pixel can be divided into red, green and blue sub-pixels 101 to achieve color. Each pixel can also include a white sub-pixel. Each sub-pixel 101 includes a pixel circuit for driving the light-emitting element EL. In addition, each sub-pixel 101 may include a color filter, but the color filter may be omitted. Hereinafter, pixel can be understood to have the same meaning as sub-pixel.

[0039] The display panel 100 has a width along the X-axis direction, a length along the Y-axis direction, and a thickness along the Z-axis direction. The pixel array AA includes a plurality of pixel lines L1 to Ln. A pixel line includes pixels arranged in a line in the row direction (X-axis direction). The pixel array AA includes m pixel lines L1 to Lm (m is a natural number). The pixels arranged in the pixel line share a gate line and are connected to different data lines DL. The sub-pixels 101 arranged vertically along the column direction (Y-axis direction) share the same data line. In a horizontal period, the pixels arranged in the pixel line are charged by the data voltage of the pixel data.

[0040] A touch sensor may be provided on the screen of the display panel 100. The touch sensor includes an on-cell type or add-on type touch sensor provided on the screen of the display panel 100 or an in-cell type touch sensor included in the pixel array AA.

[0041] When observing the cross-sectional structure of the display panel 100 , the display panel may include a circuit layer 12 , a light emitting element layer 14 , and an encapsulation layer 16 stacked on a substrate 10 .

[0042] The circuit layer 12 may include: pixel circuits connected to interconnects such as data lines, gate lines, and power lines; gate drivers (GIPs) connected to the gate lines; a demultiplexer array 112; circuits for automatic probe inspection (not shown), etc. The interconnects and circuit elements of the circuit layer 12 may include multiple insulating layers, two or more metal layers separated from each other by an insulating layer therebetween, and an active layer including a semiconductor material.

[0043] The light-emitting element layer 14 may include a light-emitting element EL to be driven by the pixel circuit. The light-emitting element EL may include a red (R) light-emitting element, a green (G) light-emitting element, and a blue (B) light-emitting element. The light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting element EL of the light-emitting element layer 14 may be covered by a protective layer.

[0044] The encapsulation layer 16 covers the light-emitting element layer 14 to seal the circuit layer 12 and the light-emitting element layer 14. The encapsulation layer 16 may be a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic films block the penetration of moisture or oxygen. The organic films flatten the surface of the inorganic films. When the organic and inorganic films are stacked in multiple layers, the penetration path of moisture or oxygen is longer than that of a single layer, and thus the penetration of moisture and oxygen that may affect the light-emitting element layer 14 can be effectively blocked.

[0045] The touch sensor layer may be disposed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses touch input based on a change in capacitance before and after a touch input is input. The touch sensor layer may include a metal interconnect pattern and an insulating film that form the capacitance of the touch sensor. The capacitance of the touch sensor may be formed between the metal interconnect patterns. A polarizing plate may be disposed on the touch sensor layer. The polarizing plate may convert the polarization of external light reflected from the metal of the touch sensor layer and circuit layer 12 to improve visibility and contrast. The polarizing plate may be embodied as a circular polarizing plate or a polarizing plate in which a linear polarizing plate and a phase delay film are bonded to each other. A cover glass may be bonded to the polarizing plate.

[0046] The display panel 100 may also include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include red, green, and blue color filters and a black matrix pattern. The color filter layer may absorb the portion of the wavelength of light reflected from the circuit layer and touch sensor layer rather than the polarizing plate, thereby improving color purity. In this embodiment, a color filter layer 20 having a transmittance higher than that of the polarizing plate is applied to the display panel 100 to improve light transmission, thereby increasing the thickness and flexibility of the display panel 100. A cover glass may be bonded to the color filter layer.

[0047] The display panel 100 may be embodied as a flexible display panel, in which pixels are arranged on a flexible substrate such as a plastic substrate or a metal substrate. The size and shape of the screen of the flexible display may be changed by rolling, folding, or bending the flexible display panel. Flexible displays may include slidable displays, rollable displays, bendable displays, foldable displays, and the like.

[0048] Due to device characteristic variations and process variations in the manufacturing process of the display panel 100, the electrical characteristics of the driving elements of the pixels may vary, and the differences may increase as the pixel driving time increases. To compensate for the variations in the electrical characteristics of the driving elements of the pixels, internal or external compensation techniques may be applied to the organic light-emitting display device.

[0049] In the internal compensation technology, the threshold voltage of the driving element of each sub-pixel is sensed using an internal compensation circuit included in each pixel, and the gate-source voltage Vgs of the driving element is compensated by the threshold voltage. In the external compensation technology, the current or voltage of the driving element that changes according to the electrical characteristics of the driving element is sensed in real time using an external compensation circuit. In the external compensation technology, the pixel data (digital data) of the input image is modified by the electrical characteristic deviation (or change) of the driving element sensed in units of pixels to compensate for the electrical characteristic deviation (or change) of the driving element of each pixel in real time.

[0050] The display panel driver may drive pixels using internal compensation techniques and / or external compensation techniques.

[0051] The display panel driver writes pixel data of an input image to the sub-pixels 101 to reproduce the input image on the screen of the display panel 100. The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer 112 between the data driver 110 and the data lines DL.

[0052] The display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. In the low-speed drive mode, the input image can be analyzed, and when there is no change in the input image within a predetermined time, the power consumption of the display device can be reduced. In the low-speed drive mode, when a still image is input for a certain period of time or longer, the refresh rate of the pixel can be reduced to increase the data writing period of the pixel, thereby reducing power consumption. The low-speed drive mode is not limited to the case where a still image is input. For example, when the display device is operating in standby mode or when a user command or input image is not input to the display panel drive circuit within a certain period of time, the display panel drive circuit can operate in the low-speed drive mode.

[0053] The data driver 110 receives pixel data of an input image in the form of a digital signal from the timing controller 130. The data driver 110 generates data voltages by converting the pixel data of the input image into a gamma compensation voltage using a digital-to-analog converter (hereinafter referred to as a "DAC"). The data driver 110 may include a voltage divider circuit that outputs the gamma compensation voltage. The voltage divider circuit divides the gamma reference voltage GMA from the power supply 150 into gamma compensation voltages in units of grayscale and provides the gamma compensation voltages to the DAC. The data voltages output from the channels of the data driver 110 may be applied to the data lines DL of the display panel 100 through the demultiplexer 112.

[0054] The demultiplexer 112 distributes the data voltages outputted through the channels of the data driver 110 to the data lines DL by time division. Due to the demultiplexer 112, the number of channels of the data driver 110 can be reduced. The demultiplexer 112 can be omitted. In this case, the channels of the data driver 110 are directly connected to the data lines DL.

[0055] The gate driver 120 may be embodied together with the TFT array of the pixel array AA as a gate-in-panel (GIP) circuit formed on the circuit layer 12 on the display panel 100. The GIP circuit may be provided in the bezel region BZ of the display panel 100, or at least a portion of the GIP circuit may be dispersed in the pixel array AA.

[0056] The gate driver 120 sequentially outputs gate signals to the gate lines GL under the control of the timing controller 130. The gate driver 120 may shift the gate signals using a shift register and sequentially provide the resulting signals to the gate lines GL. The voltage of the gate signal swings between a gate-off voltage VGH and a gate-on voltage VGL. The gate signal may include an emission control pulse (hereinafter referred to as an "EM pulse") for controlling the emission time of a pixel and a scan pulse. The gate lines include gate lines to which the scan pulse is applied and gate lines to which the EM pulse is applied. The gate-on voltages of the scan pulse and the EM pulse may be set to the same voltage or different voltages. In addition, the gate-off voltages of the scan pulse and the EM pulse may be set to the same voltage or different voltages. The gate lines may be divided into scan lines to which the scan pulse is sequentially input and EM lines to which the EM pulse is sequentially input.

[0057] The gate driver 120 may be disposed on the left and right frames of the display panel 100 to provide gate signals to the gate lines GL using a dual-feed method. In the dual-feed method, the gate drivers 120 on opposite sides may be synchronized with each other to simultaneously provide gate signals to opposite ends of a gate line. In another embodiment, the gate driver 120 may be disposed on the left or right frame of the display panel 100 to provide gate signals to the gate lines GL using a single-feed method.

[0058] The gate driver 120 may include a first gate driver 121 and a second gate driver 122. The first gate driver 121 outputs a scan pulse using a first shift register and shifts the scan pulse in response to a shift clock. The second gate driver 122 outputs an EM pulse using a second shift register and shifts the EM pulse in response to a shift clock.

[0059] The timing controller 130 receives pixel data of an input image and timing signals to be synchronized with the pixel data from the host system. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, and the like. One period of the vertical synchronization signal Vsync is a frame period. One period of each of the horizontal synchronization signal Hsync and the data enable signal DE is a horizontal period 1H. The pulse of the data enable signal DE is synchronized with a row of data to be written to the pixels in the pixel line. The frame period and horizontal period can be identified by counting the data enable signal DE, and therefore the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted.

[0060] Examples of host systems may include main circuit boards of television (TV) systems, navigation systems, personal computers (PCs), tablet computers / notebook computers, vehicle systems, mobile systems, and wearable systems. In mobile systems or wearable systems, the timing controller 130, the data driver 110, and the power supply 150 may be integrated into one driver integrated circuit (IC).

[0061] The timing controller 130 may control the operation timing of the display panel drivers 110, 112, and 120 using a frame frequency corresponding to an input frame frequency Hz multiplied by i (i is a positive integer greater than 0). The input frame frequency is 60 Hz according to the National Television Standards Committee (NTSC) standard or 50 Hz in the Phase-Alternating Line (PAL) standard. The timing controller 130 may reduce the frame frequency to a frequency between 1 Hz and 30 Hz to reduce the refresh rate of the pixels in the low-speed drive mode.

[0062] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a switch control signal for controlling the operation timing of the demultiplexer 112, and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system.

[0063] Examples of the gate timing control signal may include a start pulse, a shift clock, etc. The voltage of the gate timing control signal output from the timing controller 130 may be applied to the gate driver 120 by being converted into a gate-off voltage VGH / VEH and a gate-on voltage VGL / VEL through a level shifter (not shown). The level shifter converts a low-level voltage of the gate timing control signal into a gate-on voltage VGL, and converts a high-level voltage of the gate timing control signal into a gate-off voltage VGH.

[0064] Examples of the power supply 150 include a charge pump, a regulator, a buck converter, a boost converter, a programmable gamma rectifier (P-GMA IC), and the like. The power supply 150 generates the constant voltage (or DC voltage) required to drive the display panel driver and the display panel 100 by adjusting the DC input voltage from the host system. The power supply 150 can output constant voltages such as a gamma reference voltage, a gate-off voltage VGH / VEH, a gate-on voltage VGL / VEL, a pixel drive voltage ELVDD, a low-potential power supply voltage ELVSS, or an initialization voltage Vini. The P-GMA IC can change the gamma reference voltage according to register settings. The gamma reference voltage GMA is applied to the data driver 110. The gate-off voltage VGH / VEH and the gate-on voltage VGL / VEL are applied to the level shifter and gate driver 120. The gate-off voltage VGH of the scan pulse can be divided into first and second gate-off voltages of different voltages. The pixel drive voltage ELVDD, the low-potential power supply voltage ELVSS, and the initialization voltage Vini are applied to the pixel circuit via power lines. The pixel driving voltage ELVDD may be set to be higher than the initialization voltage Vini, and the low potential power supply voltage VSS may be set to be equal to or lower than the initialization voltage Vini.

[0065] Figure 3 is a circuit diagram of a pixel circuit according to a first embodiment of the present disclosure.

[0066] refer to Figure 3 The pixel circuit includes an OLED EL, a driving element DT for supplying current to the OLED EL, a first driver 32 connected to the driving element DT, and a second driver 34 connected to the first driver 32 .

[0067] The OLED EL may include an anode electrode, a cathode electrode, and an organic compound layer connected between the anode electrode and the cathode electrode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When the voltage at the opposite end of the OLED EL is greater than or equal to the threshold voltage of the OLED EL, the OLED EL is turned on, so that current flows through the OLED EL. In this case, when the holes flowing through the HTL and the electrons flowing through the ETL move to the EML, visible light can be emitted, thereby generating excitons at the EML. The light-emitting element EL used as the light-emitting element EL can be a series structure in which a plurality of light-emitting layers are stacked. The OLED of the series structure can improve the brightness and life of the pixel.

[0068] The driving element DT supplies current to the OLED EL according to the gate-source voltage Vgs to drive the OLED EL.

[0069] The first driver 32 includes one or more switching elements and a capacitor connected to the gate electrode of the driving element DT. The data voltage Vdata of the pixel data and the pixel driving voltage ELVDD are applied to the first driver 32. The first driver 32 samples the threshold voltage Vth of the driving element DT, stores the threshold voltage Vth in a capacitor, and charges the capacitor with the data voltage Vdata. The capacitor can be charged with a data voltage that is compensated by the threshold voltage Vth of the driving element DT.

[0070] The second driver 34 includes one or more switching elements. An initialization voltage Vini is applied to the second driver 34. The second driver 34 applies the initialization voltage Vini to the first driver 32 and the anode electrode of the OLED EL to initialize the capacitor of the first driver 32 and the anode voltage of the OLED EL.

[0071] Each of the first and second drivers 32 and 34 and the switching element of the driving element DT may be embodied as a transistor. The first and second drivers 32 and 34 may be implemented in various ways. For example, the first and second drivers 32 and 34 may be embodied as, but not limited to, Figure 4 The circuit shown.

[0072] Figure 4 is a circuit diagram of an example of a pixel circuit to which an internal compensation circuit is applied. Figure 5 It shows Figure 4 Waveform diagram of the driving method of the pixel circuit.

[0073] Figure 4The pixel circuits may be provided on sub-pixels in an N-th pixel line (N is a positive integer). The pixel circuits in the N-th pixel line are charged with a data voltage Vdata synchronized with an N-th scan pulse SCAN(N). The pixel circuits in the (N-1)-th pixel line are charged with a data voltage Vdata synchronized with an (N-1)-th scan pulse SCAN(N-1) generated before the N-th scan pulse SCAN(N).

[0074] refer to Figure 4 and Figure 5 The pixel circuit includes an OLED EL, a driving element DT for supplying current to the OLED EL, a first driver 32 and a second driver 34.

[0075] The first driver 32 may include a capacitor Cst, a first switching element M1, and a second switching element M2. A threshold voltage Vth of the driving element DT is sampled and stored in the capacitor Cst, and the capacitor Cst is charged with a data voltage Vdata.

[0076] The second driver 34 may include a fifth switching element M5 and a sixth switching element M6. The second driver 34 applies an initialization voltage Vini to the first driver 32 and the anode electrode of the OLED EL to initialize the capacitor Cst and the anode voltage of the OLED EL.

[0077] The pixel circuit may further include a third driver 36. The third driver 36 may include one or more switching elements M3 and M4. The switching elements M3 and M4 of the third driver 36 switch the current path between the pixel driving voltage ELVDD and the OLED EL in response to the EM pulse.

[0078] Each of the driving element DT and the switching elements M1 to M6 of the pixel circuit may be embodied as a p-channel transistor, but is not limited thereto. The switching elements M1 to M6 are turned on by a gate-on voltage VGL / VEL applied to their gate electrodes and turned off by a gate-off voltage VGH / VEH.

[0079] The pixel circuit is connected to a data line DL to which a data voltage Vdata of pixel data is applied, gate lines GL1, GL2, and GL3 to which gate signals SCAN(N-1), SCAN(N), and EM(N) are applied, and power supply lines PL1, PL2, and PL3 to which static voltages ELVDD, ELVSS, and Vini are applied. The first and second gate lines GL1 and GL2 are scan lines to which scan pulses are applied, and the third gate line GL3 is an EM line to which an EM pulse is applied.

[0080] like Figure 5As shown in FIG, the pixel circuit can be driven by dividing the driving period into an initialization period Tini, a sampling period Tsam, and a light emitting period Tem. Figure 5 In FIG, DTG represents the gate voltage of the driving element DT, that is, the voltage of the second node n2.

[0081] The Nth scan pulse SCAN(N) is generated to have a gate-on voltage VGL during the sampling period Tsam and is applied to the first gate line GL1. The Nth scan pulse SCAN(N) is synchronized with the data voltage Vdata applied to the pixels of the Nth pixel line. The (N-1)th scan pulse SCAN(N-1) is generated to have a gate-on voltage VGL during the initialization period Tini before the sampling period Tsam and is applied to the second gate line GL2. The (N-1)th scan pulse SCAN(N-1) is synchronized with the data voltage Vdata applied to the pixels of the (N-1)th pixel line. The EM pulse EM(N) is generated to have a gate-off voltage VEH during the initialization period Tini and the sampling period Tsam and is applied to the third gate line GL3. The voltage of the EM pulse EM(N) is inverted to the gate-on voltage VEL during the light emission period Tem. The EM pulse EM(N) may be applied to the pixels of the (N-1)th and Nth pixel lines simultaneously.

[0082] During the initialization period Tini, the (N-1)th scan pulse SCAN(N-1) of the gate-on voltage VGL is supplied to the second gate line GL2, and the EM pulse EM(N) of the gate-off voltage VGH is supplied to the third gate line GL3. In this case, the voltage of the first gate line GL1 is the gate-off voltage VGH. During the initialization period Tini, the fifth switching element M5 is turned on by the gate-on voltage VGL of the (N-1)th scan pulse SCAN(N-1). During the initialization period Tini, the initialization voltage Vini is applied to the second node n2, thereby initializing the capacitor Cst.

[0083] During the sampling period Tsam, the Nth scan pulse SCAN(N) of the gate-on voltage VGL is applied to the first gate line GL1. In this case, the voltages of the second and third gate lines GL2 and GL3 are the gate-off voltages VGH and VEH. During the sampling period Tsam, the first and second switching elements M1 and M2 are turned on according to the gate-on voltage VGL of the Nth scan pulse SCAN(N), and thus the driving element DT is turned on to sample the threshold voltage Vth of the driving element DT. The data voltage Vdata compensated by the sampled threshold voltage Vth of the driving element DT is stored in the capacitor Cst. During the sampling period Tsam, the sixth switching element M6 is turned on, and thus the voltage of the fourth node n4 is initialized to the initialization voltage Vini, thereby suppressing the light emission of the OLED EL.

[0084] When the light-emission period Tem begins, the voltage of the EM pulse EM(N) supplied to the third gate line GL3 reverses to the gate-on voltage VEL. During the light-emission period Tem, both the first and second gate lines GL1 and GL2 maintain the gate-off voltage VGH. During the light-emission period Tem, the third and fourth switching elements M3 and M4 are turned on to form a current path between the pixel drive voltage ELVDD and the low-potential power supply voltage VSS, thereby causing the OLED EL to emit light. During the light-emission period Tem, to accurately represent low grayscale brightness, the voltage of the EM pulse EM(N) can reverse between the gate-on voltage VEL and the gate-off voltage VEH at a certain duty cycle. In this case, the third and fourth switching elements M3 and M4 can be repeatedly turned on and off during the light-emission period Tem according to the duty cycle of the EM pulse EM(N).

[0085] As described above, the OLED EL may include an anode electrode, a cathode electrode, and an organic compound layer connected between the anode electrode and the cathode electrode. The organic compound layer may include, but is not limited to, a HIL, a HTL, an EML, an ETL, and an EIL. The anode electrode of the OLED EL is connected to the fourth node n4. The cathode electrode of the OLED EL is connected to the second power line PL2 to which the low potential power supply voltage ELVSS is applied.

[0086] The driving element DT includes a gate electrode connected to the second node n2 , a first electrode connected to the first node n1 , and a second electrode connected to the third node n3 , and generates current according to a gate-source voltage Vgs to drive the OLED EL.

[0087] The capacitor Cst is connected between the second node n2 and the first power line PL1 to which the pixel driving voltage ELVDD is applied.

[0088] During the sampling period Tsam, the first switching element M1 connects the second node n2 to the third node n3 in response to the Nth scan pulse SCAN(N). The gate electrode of the first switching element M1 is connected to the first gate line GL1 to which the Nth scan pulse SCAN(N) is applied. The first electrode of the first switching element T1 is connected to the second node n2, and the second electrode of the first switching element T1 is connected to the third node n3.

[0089] The first switching element M1 is turned on during a very short horizontal period 1H of one frame period in which the N-th scan pulse SCAN(N) having the gate-on voltage VGL is generated, and thus leakage current may occur in the first switching element M1 in the off state. In order to suppress leakage current in the first switching element M1, the first switching element M1 may be embodied as a transistor having a dual-gate structure in which two transistors are connected in series.

[0090] During the sampling period Tsam, the second switching element M2 applies the data voltage Vdata of the pixel data to the first node n1 in response to the Nth scan pulse SCAN(N). The gate electrode of the second switching element M2 is connected to the first gate line GL1. The first electrode of the second switching element M2 is connected to the first node n1. The second electrode of the second switching element M2 is connected to the data line DL to which the data voltage Vdata is applied.

[0091] During the light emission period Tem, in response to the gate-on voltage VEL of the third gate line GL3 supplied with the EM pulse EM(N), the third switching element M3 is turned on to apply the pixel driving voltage ELVDD to the first node n1. The gate electrode of the third switching element M3 is connected to the third gate line GL3. A first electrode of the third switching element M3 is connected to the first power line PL1 to which the pixel driving voltage ELVDD is applied, and a second electrode thereof is connected to the first node n1.

[0092] In the light emission period Tem, in response to the gate-on voltage VEL of the third gate line GL3 supplied with the EM pulse EM(N), the third switching element M3 is turned on to connect the third node n3 to the fourth node n4. The gate electrode of the fourth switching element M4 is connected to the third gate line GL3. The first electrode of the fourth switching element T4 is connected to the third node n3, and the second electrode thereof is connected to the fourth node n4.

[0093] During the initialization period Tini, in response to the (N-1)th scan pulse SCAN(N-1), the fifth switching element M5 applies the initialization voltage Vini to the second node n2. The gate electrode of the fifth switching element M5 is connected to the second gate line GL2 to which the (N-1)th scan pulse SCAN(N-1) is applied. The first electrode of the fifth switching element M5 is connected to the second node n2, and the second electrode thereof is connected to the third power line PL3 to which the initialization voltage Vini is applied. In order to suppress leakage current in the fifth switching element M5, the fifth switching element M5 may be embodied as a transistor having a dual-gate structure in which two transistors are connected in series.

[0094] In the sampling period Tsam, in response to the Nth scan pulse SCAN(N), the sixth switching element M6 applies the initialization voltage Vini to the fourth node n4. The gate electrode of the sixth switching element M6 is connected to the first gate line GL1 to which the Nth scan pulse SCAN(N) is applied. The first electrode of the sixth switching element M6 is connected to the third power line PL3, and the second electrode thereof is connected to the fourth node n4.

[0095] The gate-off voltage of the N-th scan pulse SCAN(N) for controlling the first and second switching elements M1 and M2 of the first driver 32 and the gate-off voltages of the fifth and sixth switching elements M5 and M6 to be applied to the second driver 34 can be set to be different from each other. For example, as described in the following embodiments, the gate-off voltage VGH to be applied to the first driver 32 can be set to the first gate-off voltage VGH1, and the gate-off voltage VGH to be applied to the second driver 34 can be set to the second gate-off voltage VGH2, and vice versa. The gate-off voltage of the EM pulse EM(N) for controlling the third driver 36 can be the first gate-off voltage VGH1 or the second gate-off voltage VGH2.

[0096] The gate-off voltage VGH for controlling the off state of the switching elements M1 and M2 of the first driver 32 is set to a voltage that is turned on within the dynamic range of the data voltage Vdata corresponding to the grayscale value of the pixel data. The gate-off voltage VGH for controlling the off state of the switching elements M5 and M6 of the second driver 34 is set to prevent leakage current from occurring during the light emission period Tem. When the gate-off voltage VGH is set to be optimized for the first driver 32 or the second driver 34, the second switching element T2 may malfunction at data voltages of certain grayscale levels and thus may be turned off during the sampling period Tsam, or the leakage current in the second driver 34 may increase, and thus the voltage of the capacitor Cst may be discharged, resulting in a decrease in the brightness and retention characteristics of the pixel.

[0097] The optimal level of the gate-off voltage VGH to be applied to the first and second drivers 32 and 34 can vary depending on the aging method of the display device. For example, when the gate-off voltage VGH to be applied to the first driver 32 is set to be higher than the gate-off voltage VGH to be applied to the second gate driver 34, the driving characteristics of the first and second drivers 32 and 34 can be optimized. On the other hand, when the gate-off voltage VGH to be applied to the first driver 32 is set to be lower than the gate-off voltage VGH to be applied to the second gate driver 34, the driving characteristics of the first and second drivers 32 and 34 can be optimized. To this end, the gate drive circuit according to an embodiment of the present disclosure outputs different gate-off voltages VGH to be applied to the first driver 32 and the second driver 34. Since the luminance of each subpixel varies depending on the leakage current in the transistor, the optimal levels of the gate-off voltage VGH to be applied to the first driver 32 and the gate-off voltage VGH to be applied to the second driver 34 can be determined based on the results of measuring the luminance of each subpixel after the aging process.

[0098] Figure 6 A gate driving circuit according to an embodiment of the present disclosure is shown.

[0099] refer to Figure 6 , the gate driving circuit includes a shift register of a first gate driver 121 for sequentially outputting scan pulses.

[0100] The shift register includes signal transmitters ST(N-1) to ST(N) connected in a dependent manner through a carry signal line 60. The shift register receives a start pulse GVST and shift clocks GCLK1 and GCLK2, and sequentially outputs and shifts scan pulses SRO1(N-1) to SRO2(N) according to the shift clocks GCLK1 and GCLK2. The shift clocks GCLK1 and GCLK2 are input to the signal transmitters ST(i-1) to ST(i+2) through the carry signal line 60. Figure 6 In the example of , the shift clocks GCLK1 and GCLK2 may be two-phase clocks that are sequentially shifted, but are not limited thereto. For example, the shift clocks GCLK1 and GCLK2 may be n-phase clocks (n is a natural number greater than or equal to 2).

[0101] Each of the signal transmitters ST(N− 1) to ST(N) includes controllers 62 and 64 , first outputters 72 and 76 , and second outputters 74 and 78 .

[0102] Controllers 62 and 64 include a start signal input node to which a start pulse GVST or a carry signal CAR from a previous signal transmitter is input, and a clock input node connected to clock lines 84 and 85 to which shift clocks GCLK1 and GCLK2 are input. As shown in FIG7 , controllers 62 and 64 may also include a VGL node to which a gate-on voltage VGL is applied and a first VGH node to which a first gate-off voltage VGH1 is applied. Controllers 62 and 64 charge or discharge first and second control nodes to control the rise and fall timing of each of the first and second scan pulses SRO1(N-1), SRO1(N), SRO2(N-1), and SRO2(N) output from first output units 72 and 76 and second output units 74 and 78.

[0103] like Figure 7A and Figure 7B As shown, the first and second scan pulses SRO1(N-1) and SRO2(N-1) output from the (N-1)th signal transmitter ST(N-1) can have the same gate-on voltage VGL and different gate-off voltages VGH1 and VGH2. The first scan pulse SRO1(N-1) and the second scan pulse SRO2(N-1) can be generated as in-phase pulses, and therefore their rising and falling timings can be the same. The (N-1)th signal transmitter ST(N-1) outputs a carry signal CAR and simultaneously outputs the first and second scan pulses SRO1(N-1) and SRO2(N-1). The carry signal CAR can be input to the start signal input node of the next signal transmitter ST(N) through a carry signal line 60, which is connected to the first output node or the second output node. The first scan pulse SRO1(N-1) is output through the first output node, and the second scan pulse SRO2(N-1) is output through the second output node.

[0104] In response to the carry signal from the (N-1)th signal transmitter ST(N-1), after the scan pulses SRO1(N-1) and SRO2(N-1) are output from the (N-1)th signal transmitter ST(N-1), the Nth signal transmitter ST(N) outputs the first and second scan pulses SRO1(N) and SRO2(N). Figure 7A and Figure 7BAs shown, the first and second scan pulses SRO1(N) and SRO2(N) output from the Nth signal transmitter ST(N) can have the same gate-on voltage VGL and different gate-off voltages VGH1 and VGH2. The first scan pulse SRO1(N) and the second scan pulse SRO2(N) can be generated as in-phase pulses, and therefore their rising and falling timings can be the same. The Nth signal transmitter ST(N) outputs a carry signal CAR and simultaneously outputs the first and second scan pulses SRO1(N) and SRO2(N). The carry signal CAR can be input to the start signal input node of the next signal transmitter (not shown) through the carry signal line 60, and the carry signal line 60 is connected to the first output node or the second output node. The first scan pulse SRO1(N) is output through the first output node, and the second scan pulse SRO2(N) is output through the second output node.

[0105] The first scan pulses SRO1(N-1) and SRO1(N) may be applied to the first driver 32 or the second driver 34. When the first scan pulses SRO1(N-1) and SRO1(N) are applied to the first driver 32 of the pixel circuit, the second scan pulses SRO2(N-1) and SRO2(N) may be applied to the second driver 34 of the pixel circuit. On the other hand, when the first scan pulses SRO1(N-1) and SRO1(N) are applied to the second driver 34 of the pixel circuit, the second scan pulses SRO2(N-1) and SRO2(N) may be applied to the first driver 32 of the pixel circuit.

[0106] The first output parts 72 and 76 output the first scan pulses SRO1(N-1) and SRO1(N) under the control of the controllers 62 and 64. Figure 7A and Figure 7B As shown, the first output parts 72 and 76 are connected to the VGH1 line 81 to which the first gate-off voltage VGH1 is applied and the VGL line 83 to which the gate-on voltage VGL is applied, and output the first scan pulses SRO1(N-1) and SRO1(N) swinging between the gate-on voltage VGL and the first gate-off voltage VGH1.

[0107] The second output parts 74 and 78 output the second scan pulses SRO2(N-1) and SRO2(N) under the control of the controllers 62 and 64. The second output parts 74 and 78 are connected to the VGH2 line 82 to which the second gate-off voltage VGH2 is applied and the VGL line 83 to which the gate-on voltage VGL is applied, and output the second scan pulses SRO2(N-1) and SRO2(N) that swing between the gate-on voltage VGL and the second gate-off voltage VGH2.

[0108] exist Figure 4In the case of a pixel circuit, the gate-off voltage VGH of the Nth scan pulse applied to the first driver 32 may be the first gate-off voltage VGH1, and the gate-off voltage VGH of the (N-1)th scan pulse applied to the second driver 34 may be the second gate-off voltage VGH2, and vice versa.

[0109] The first scan pulse SRO1(N-1) output from the (N-1)th signal transmitter ST(N-1) and the first scan pulse SRO1(N) output from the Nth signal transmitter ST(N) may be applied to the gate electrodes of the switching elements M5 and M6 of the second driver 34. In this case, the second scan pulse SRO2(N) output from the Nth signal transmitter ST(N) may be applied to the gate electrodes of the switching elements M1 and M2 of the first driver 32. In this case, the Nth scan pulse applied to the first driver 32 may be the first scan pulse SRO1(N) output from the Nth signal transmitter ST(N), the (N-1)th scan pulse applied to the second driver 34 may be the second scan pulse SRO2(N-1) output from the (N-1)th signal transmitter ST(N-1), and the Nth scan pulse applied to the second driver 34 may be the second scan pulse SRO2(N) output from the Nth signal transmitter ST(N).

[0110] On the other hand, the second scan pulse SRO2(N-1) output from the (N-1)th signal transmitter ST(N-1) and the second scan pulse SRO2(N) output from the Nth signal transmitter ST(N) may be applied to the gate electrodes of the switching elements M5 and M6 of the second driver 34. In this case, the first scan pulse SRO1(N) output from the Nth signal transmitter ST(N) may be applied to the gate electrodes of the switching elements M1 and M2 of the first driver 32. In this case, the Nth scan pulse applied to the first driver 32 may be the second scan pulse SRO2(N) output from the Nth signal transmitter ST(N), the (N-1)th scan pulse applied to the second driver 34 may be the first scan pulse SRO1(N-1) output from the (N-1)th signal transmitter ST(N-1), and the Nth scan pulse applied to the second driver 34 may be the first scan pulse SRO1(N) output from the Nth signal transmitter ST(N).

[0111] like Figure 7A and Figure 7B As shown, the first gate-off voltage VGH1 can be set higher or lower than the second gate-off voltage VGH2. Figure 7A and Figure 7B In the example, "SRO1" means Figure 6The first scan pulses SRO1(N-1) and SRO1(N) are shown, and "SRO2" represents Figure 6 The second scan pulses SRO2(N-1) and SRO2(N) are shown.

[0112] Figure 8 yes Figure 6 A circuit diagram of an example of an (N-1)th signal transmitter. Figure 8 Other signal transmitters not shown in the figure may be embodied as Figure 8 The circuit shown is essentially the same circuit. Figure 9 yes Figure 6 The input and output signals of the signal transmitter and the waveform diagram of the control node voltage. It should be understood that the circuit of the signal transmitter is not limited to Figure 8 For example, in Figure 8 In the embodiment of the present invention, some transistors may be omitted or transistors may be added to the circuit of the controller 62.

[0113] refer to Figure 8 and Figure 9 Controller 62 includes a plurality of transistors T1A to T6. Controller 62 also includes: a clock input node to which the first shift clock GCLK1 and the second shift clock GCLK2 are input; a start signal input node to which the start pulse GVST or a carry signal from the previous signal transmitter is input; a VGL node to which the gate-on voltage VGL is applied; and a VGH1 node to which the first gate-off voltage VGH1 is applied. The first clock input node is connected to a first clock line 84. The second clock input node is connected to a second clock line 85. The start signal input node is connected to the carry signal line 60 or line to which the start pulse GVST is applied. The VGL node is connected to a VGL line 83.

[0114] The first transistor T1 can be embodied as one or more transistors T1A and T1B having a dual-gate structure in which two transistors are connected in series. The first transistor T1 is turned on according to the gate-on voltage VGL of the second shift clock GCLK2. When the first transistor T1 is turned on, the voltage of the start pulse GVST or the carry signal CAR is transmitted to the 1-1 control node Q', and the voltage of the 1-1 control node Q' changes to the gate-on voltage VGL. The first transistor T1 includes: a gate electrode connected to the second clock input node to which the second shift clock GCLK2 is applied; a first electrode to which the start pulse GVST or the carry signal CAR is applied; and a second electrode connected to the 1-1 control node Q'.

[0115] The second transistor T2 is turned on in response to the gate-on voltage VGL of the first shift clock GCLK1 to connect the I-1 control node Q' to the first electrode of the third transistor T3. The second transistor T2 includes: a gate electrode connected to the first clock input node to which the first shift clock GCLK1 is applied; a first electrode connected to the I-1 control node Q'; and a second electrode connected to the first electrode of the third transistor T3. The third transistor T3 is turned on in response to the gate-on voltage VGL of the second control node QB to connect the second electrode of the second transistor T2 to the VGH1 node. The third transistor T3 includes: a gate electrode connected to the second control node QB; a first electrode connected to the second electrode of the second transistor T2; and a second electrode connected to the VGH1 node. When both the second and third transistors T2 and T3 are turned on, the voltage of the I-1 control node Q' is the first gate-off voltage VGH1. The second control node QB can be connected to the gate electrode of the eleventh transistor T11 of the next signal transmitter ST(N).

[0116] The fourth transistor T4 is turned on in response to the gate-on voltage VGL of the second shift clock GCLK2 to connect the VGL node to the second control node QB. When the fourth transistor T4 is turned on, the voltage of the second control node QB changes to the gate-on voltage VGL. The fourth transistor T4 includes a gate electrode connected to the second clock input node to which the second shift clock GCLK2 is applied; a first electrode connected to the VGL node; and a second electrode connected to the second control node QB.

[0117] When the voltage of the I-1 control node Q' is the gate-on voltage VGL, the fifth transistor T5 is turned on to connect the second clock node to the second control node QB. The fifth transistor T5 includes: a gate electrode connected to the I-1 control node Q'; a first electrode connected to the second clock input node; and a second electrode connected to the second control node QB.

[0118] The sixth transistor T6 is turned on according to the gate-on voltage VGL to connect the 1-1 control node Q' to the 1-2 control node Q. When the sixth transistor T6 is turned on, the 1-2 control node Q can be charged by the gate-on voltage VGL. The sixth transistor T6 includes a gate electrode connected to the VGL node; a first electrode connected to the 1-1 control node Q'; and a second electrode connected to the 1-2 control node Q.

[0119] The signal transmitter may further include a first capacitor C_Q connected between the 1-2 control node Q and the first output node OUT1 and a second capacitor C_QB connected between the second control node QB and the VGH1 node. When the first output node OUT1 is charged with the gate-on voltage VGL, bootstrapping may occur through the first capacitor C_Q, and thus, for example, in the case Figure 9 The fourth time point 4 shown may increase the voltage of the 1-2 control node Q. The second capacitor C_QB suppresses fluctuations in the voltage of the second control node QB.

[0120] The first output part 72 outputs a first scan pulse SRO1 swinging between a gate-on voltage VGL and a first gate-off voltage VGH1 in response to voltages of the 1-2 control node Q and the second control node QB. The first output part 72 includes seventh and eighth transistors T7 and T8.

[0121] The seventh transistor T7 is a pull-up transistor for raising the first scan pulse SRO1 and includes a gate electrode connected to the 1-2 control node Q, a first electrode connected to the first clock input node, and a second electrode connected to the first output node OUT1.

[0122] The eighth transistor T8 is a pull-down transistor for dropping the first scan pulse SRO1 , and includes a gate electrode connected to the second control node QB, a first electrode connected to the first output node OUT1 , and a second electrode connected to the VGH1 node.

[0123] The second output part 74 outputs a second scan pulse SRO2 that swings between a gate-on voltage VGL and a second gate-off voltage VGH2 in response to voltages of the 1-2 control node Q and the second control node QB. The second output part 74 includes ninth to eleventh transistors T9, T10, and T11.

[0124] The ninth transistor T9 is a pull-up transistor for raising the second scan pulse SRO2 and includes a gate electrode connected to the 1-2 control node Q, a first electrode connected to the second output node OUT2, and a second electrode connected to the first output node OUT1.

[0125] The tenth transistor T10 is a pull-down transistor that causes the second scan pulse SRO2 to drop. The tenth transistor T10 includes a gate electrode connected to the second control node QB; a first electrode connected to the second electrode to which the second gate-off voltage VGH2 is applied via the eleventh transistor T11; and a second electrode connected to the second output node OUT2.

[0126] exist Figure 9In the embodiment of the present invention, when the 1-1 control node Q' and the 1-2 control node Q are simultaneously charged with the gate-on voltage VGL, for example at the third time point 3, the eighth to tenth transistors T8 to T10 can be turned on simultaneously, thereby short-circuiting the VGH1 node and the VGH2 node. When the 1-1 control node Q' and the 1-2 control node Q are simultaneously charged with the gate-on voltage VGL, the eleventh transistor T11 is turned off according to the voltage of the second control node QB(n-1) from the previous signal transmitter, thereby blocking the second gate-off voltage VGH2. The eleventh transistor T11 includes: a gate electrode connected to the second control node QB(n-1) of the previous signal transmitter; a first electrode connected to the VGH2 node; and a second electrode connected to the first electrode of the tenth transistor 10. The eleventh transistor T11 can be omitted. In this case, the second gate-off voltage VGH2 is applied to the first electrode of the tenth transistor 10.

[0127] exist Figure 9 In other words, the first output portion 72 may output the second scan pulse SRO2, and the second output portion 74 may output the first scan pulse SRO1.

[0128] According to the present disclosure, the gate-off voltage of the scan pulse for controlling the switching element of the pixel circuit can be divided into a voltage optimized for the driving characteristics of the switching element, thereby achieving a voltage optimized for leakage current occurring in the pixel circuit and improving retention characteristics.

[0129] The effects of the present disclosure are not limited thereto, and other effects not described herein will be clearly understood by those of ordinary skill in the art from the following claims.

[0130] The objects to be achieved by the present disclosure, means for achieving the objects, and the effects of the present disclosure described above are not essential features that define the claims, and therefore, the scope of the claims is not limited to the disclosed contents of the present disclosure.

[0131] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the following claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present disclosure.

Claims

1. A gate drive circuit comprising: The (N-1)th signal transmitter is applied with: a start pulse or a carry signal; shift clock; Gate on voltage; first gate off voltage; and a second gate cutoff voltage, wherein N is a natural number; as well as The Nth signal transmitter is applied with: the carry signal from the (N-1)th signal transmitter; the shift clock; the gate-on voltage; and the first gate-off voltage; and the second gate cut-off voltage, Wherein, each of the (N-1)th signal transmitter and the Nth signal transmitter includes: a first output unit configured to output a first scanning pulse swinging between the gate-on voltage and the first gate-off voltage; a second output portion configured to output a second scanning pulse that swings between the same gate-on voltage having the same polarity as the gate-on voltage of the first scanning pulse and a second gate-off voltage different from the first gate-off voltage; and A controller is configured to control the first output section and the second output section, the controller including a VGH1 node, wherein the first gate-off voltage is directly applied to the VGH1 node, and wherein the first gate-off voltage is set to be higher or lower than the second gate-off voltage.

2. The gate drive circuit according to claim 1, wherein: The first scan pulse and the second scan pulse output from the (N-1)th signal transmitter are generated to have the same phase.

3. The gate drive circuit according to claim 1, wherein: In response to the carry signal from the (N-1)th signal transmitter, the Nth signal transmitter outputs the first scan pulse and the second scan pulse after the first scan pulse and the second scan pulse are output from the (N-1)th signal transmitter, and The first scan pulse and the second scan pulse output from the Nth signal transmitter are generated to have the same phase.

4. The gate driving circuit according to claim 1, wherein: The controller includes: The first transistor includes: a gate electrode connected to a second clock input node to which a second shift clock is applied; a first electrode to which the start pulse or the carry signal is applied; and a second electrode connected to a 1-1 control node; a second transistor comprising: a gate electrode connected to a first clock input node to which a first shift clock is applied; a first electrode connected to the 1-1 control node; and a second electrode; a third transistor comprising: a gate electrode connected to a second control node; a first electrode connected to the second electrode of the second transistor; and a second electrode connected to the VGH1 node; a fourth transistor comprising: a gate electrode connected to the second clock input node; a first electrode connected to a VGL node to which a gate-on voltage is applied; and a second electrode connected to the second control node; a fifth transistor comprising: a gate electrode connected to the 1-1 control node; a first electrode connected to the second clock input node; and a second electrode connected to the second control node; and A sixth transistor includes: a gate electrode connected to the VGL node; a first electrode connected to the 1-1 control node; and a second electrode connected to the 1-2 control node.

5. The gate driving circuit according to claim 4, wherein: The first output unit includes: a seventh transistor comprising: a gate electrode connected to the 1-2 control node; a first electrode connected to the first clock input node; and a second electrode connected to a first output node, through which the first scan pulse is output; and An eighth transistor includes: a gate electrode connected to the second control node; a first electrode connected to the first output node; and a second electrode connected to the VGH1 node.

6. The gate driving circuit according to claim 4, wherein: The second output unit includes: a ninth transistor comprising: a gate electrode connected to the 1-2 control node; a first electrode connected to a second output node through which the second scan pulse is output; and a second electrode connected to the first output node; and A tenth transistor includes: a gate electrode connected to the second control node; a first electrode to which the second gate-off voltage is applied; and a second electrode connected to the second output node.

7. The gate driving circuit according to claim 4, wherein: The second output unit includes: a ninth transistor comprising: a gate electrode connected to the 1-2 control node; a first electrode connected to a second output node, through which the second scan pulse is output; and a second electrode connected to the first output node; a tenth transistor comprising: a gate electrode connected to the second control node; a first electrode to which the second gate-off voltage is applied; and a second electrode connected to the second output node; and The eleventh transistor includes: a gate electrode connected to the second control node of the previous signal transmitter; a first electrode connected to a VGH2 node to which the second gate-off voltage is applied; and a second electrode connected to the first electrode of the tenth transistor.

8. The gate driving circuit according to claim 1, wherein: The gate-on voltages of the first scanning pulse and the second scanning pulse are lower than both the first gate-off voltage and the second gate-off voltage; and The first scan pulse and the second scan pulse are both configured to be supplied to a p-type transistor.

9. The gate driving circuit according to claim 1, wherein: The controller further includes a transistor having an electrode directly connected to the VGH1 node.

10. A display device comprising: A pixel array comprising: a plurality of data lines; a plurality of gate lines; a plurality of power supply lines to which a constant voltage is applied; and a plurality of sub-pixels; a data driver configured to apply data voltages to the plurality of data lines; and a gate driver configured to sequentially provide scan pulses to scan lines among the plurality of gate lines using a first shift register, Wherein, the first shift register includes: The (N-1)th signal transmitter is applied with: a start pulse or a carry signal; a shift clock; a gate-on voltage; a first gate-off voltage; and a second gate-off voltage, wherein N is a natural number; and The Nth signal transmitter is applied with: the carry signal from the (N-1)th signal transmitter; the shift clock; the gate-on voltage; the first gate-off voltage; and the second gate-off voltage. Wherein, each of the (N-1)th signal transmitter and the Nth signal transmitter includes: a first output unit configured to output a first scanning pulse swinging between the gate-on voltage and the first gate-off voltage; a second output portion configured to output a second scanning pulse that swings between the same gate-on voltage having the same polarity as the gate-on voltage of the first scanning pulse and a second gate-off voltage different from the first gate-off voltage; and a controller configured to control the first output section and the second output section, the controller including a VGH1 node, wherein the first gate-off voltage is directly applied to the VGH1 node, and wherein, The first gate-off voltage is set to be higher or lower than the second gate-off voltage.

11. The display device according to claim 10, wherein: The first scan pulse and the second scan pulse output from the (N-1)th signal transmitter are generated to have the same phase.

12. The display device according to claim 10, wherein: In response to the carry signal from the (N-1)th signal transmitter, the Nth signal transmitter outputs the first scan pulse and the second scan pulse after the first scan pulse and the second scan pulse are output from the (N-1)th signal transmitter, and The first scan pulse and the second scan pulse output from the Nth signal transmitter are generated to have the same phase.

13. The display device according to claim 10, wherein: The pixel circuit of each sub-pixel includes: a driving element configured to drive the light-emitting element; A first driver including: a capacitor connected to a gate electrode of the driving element; and one or more switching elements; and a second driver configured to initialize the capacitor and the anode voltage of the light emitting element, the second driver comprising one or more switching elements, and Herein, the gate-off voltage of the scan pulse applied to the first driver and the gate-off voltage of the scan pulse applied to the second driver are different from each other.

14. The display device according to claim 13, wherein: the first scan pulse output from the (N-1)th signal transmitter and the first scan pulse output from the Nth signal transmitter are applied to the gate electrode of the switching element of the second driver, and the second scan pulse output from the Nth signal transmitter is applied to the gate electrode of the switching element of the first driver; or The second scan pulse output from the (N-1)th signal transmitter and the second scan pulse output from the Nth signal transmitter are applied to the gate electrode of the switching element of the second driver, and the first scan pulse output from the Nth signal transmitter is applied to the gate electrode of the switching element of the first driver.

15. The display device according to claim 10, wherein: The gate driver sequentially supplies light emitting control pulses to light emitting lines among the plurality of gate lines using a second shift register.

16. The display device according to claim 15, wherein The pixel circuit of each sub-pixel includes: a driving element configured to drive the light-emitting element; a first driver to which a pixel driving voltage and the data voltage are applied; a second driver to which an initialization voltage is applied; and A third driver is configured to switch a current path between the pixel driving voltage and the light emitting element.

17. The display device according to claim 16, wherein: The pixel circuit of each sub-pixel in the sub-pixels receives the pixel driving voltage, the data voltage, the initialization voltage, the (N-1)th scanning pulse, the Nth scanning pulse and the light-emitting control pulse, and is driven by dividing the driving period into an initialization period, a sampling period and a light-emitting period.

18. The display device according to claim 17, wherein: The first driver includes a capacitor, a first switching element, and a second switching element, and is configured to sample a threshold voltage of the driving element, store the sampled threshold voltage, and charge the capacitor using the data voltage; The third driver includes a third switching element and a fourth switching element, each of the third switching element and the fourth switching element being configured to switch a current path between the pixel driving voltage and the light emitting element in response to the light emitting control pulse; as well as The second driver is configured to apply the initialization voltage to the first driver and the anode electrode of the light emitting element to initialize the anode voltage of the capacitor and the light emitting element, and the second driver includes a fifth switching element and a sixth switching element.

19. The display device according to claim 18, wherein: The driving element includes: a gate electrode connected to the second node; a first electrode connected to the first node; and a second electrode connected to the third node. The light emitting element includes: an anode electrode connected to the fourth node; and a cathode electrode to which a low potential power supply voltage is applied. In the sampling period, in response to the Nth scan pulse, the first switching element connects the second node to the third node, In the sampling period, in response to the Nth scan pulse, the second switching element applies the data voltage to the first node, In the light emitting period, the third switching element is turned on according to the gate-on voltage of the light emitting control pulse to apply the pixel driving voltage to the first node, In the light emitting period, the fourth switching element is turned on according to the gate-on voltage of the light emitting control pulse to connect the third node to the fourth node, In the initialization period, in response to the (N-1)th scan pulse, the fifth switching element applies the initialization voltage to the second node, and In the sampling period, the sixth switching element applies the initialization voltage to the fourth node in response to the Nth scan pulse.

20. The display device according to claim 19, wherein The gate-off voltage of the Nth scan pulse applied to the first driver is the first gate-off voltage, and the gate-off voltages of the (N-1)th scan pulse and the Nth scan pulse applied to the second driver are the second gate-off voltage, or The gate-off voltage of the Nth scan pulse applied to the first driver is the second gate-off voltage, and the gate-off voltages of the (N-1)th scan pulse and the Nth scan pulse applied to the second driver are the first gate-off voltage.

21. The display device according to claim 19, wherein The Nth scan pulse applied to the first driver is a first scan pulse output from the Nth signal transmitter, the (N-1)th scan pulse applied to the second driver is a second scan pulse output from the (N-1)th signal transmitter, and the Nth scan pulse applied to the second driver is a second scan pulse output from the Nth signal transmitter, or The Nth scan pulse applied to the first driver is the second scan pulse output from the Nth signal transmitter, the (N-1)th scan pulse applied to the second driver is the first scan pulse output from the (N-1)th signal transmitter, and the Nth scan pulse applied to the second driver is the first scan pulse output from the Nth signal transmitter.

22. The display device according to claim 10, wherein: The gate-on voltages of the first scanning pulse and the second scanning pulse are lower than both the first gate-off voltage and the second gate-off voltage; and The first scan pulse and the second scan pulse are both configured to be supplied to a p-type transistor.

23. The display device according to claim 10, wherein: The controller further includes a transistor having an electrode directly connected to the VGH1 node.

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