Memory and method of operating the same, and memory system

Abstract

The embodiments of the present disclosure disclose a memory and an operating method thereof. The operating method comprises: based on a temperature difference existing between a programming temperature and a reference temperature, and a group to which a target programming state of selected memory cells in the memory belongs, temperature compensation is performed on a reference verification voltage corresponding to the selected memory cells to obtain a compensated verification voltage; wherein the amount of temperature compensation of the verification voltage corresponding to different groups is different; and the compensated verification voltage is applied to a word line coupled to the selected memory cells to perform a programming verification operation on the selected memory cells.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory, its operation method, and a memory system. Background Technology

[0002] Due to its high storage density and mature manufacturing process, 3D NAND flash memory has become one of the mainstream memory technologies for commercial applications. With the expansion of its application areas, the reliability of 3D NAND flash memory at different temperatures has become a crucial verification parameter for products.

[0003] After programming each memory cell, the threshold voltage of each cell changes, thus enabling information storage. During memory use, situations may arise such as low-temperature programming and high-temperature reading, or vice versa. However, the tunneling performance of electrons in the memory layer is highly sensitive to temperature, causing the threshold voltage of the memory cells to shift at different temperatures. The difference between the programming and reading temperatures leads to discrepancies between the threshold voltages determined at different stages of programming and the memory state determined at the reading stage. This, in turn, reduces the memory's read window, ultimately resulting in data read errors and reduced memory stability. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a memory is provided, comprising:

[0005] A storage array includes multiple storage cells and word lines coupling the storage cells;

[0006] An external circuit is coupled to the memory array; a temperature difference exists between the programming temperature and the reference temperature; the target programming states of the selected memory cells are grouped; wherein, the external circuit is configured to: perform temperature compensation on the reference verification voltage corresponding to the selected memory cell based on the grouping and the temperature difference to obtain a compensated verification voltage; wherein, the amount of temperature compensation for the verification voltage corresponding to different groups is different; the reference verification voltage is the verification voltage that makes the selected memory cell meet the target programming state at the reference temperature; the compensated verification voltage is applied to the word line coupled to the selected memory cell to perform a programming verification operation on the selected memory cell.

[0007] According to a second aspect of the present disclosure, a memory system is provided, comprising:

[0008] The memory and memory controller in the above embodiments are configured to be coupled to and control the memory.

[0009] According to a third aspect of the present disclosure, a method for operating a memory is provided, comprising:

[0010] Based on the temperature difference between the programming temperature and the reference temperature, and the group to which the target programming state of the selected memory cell belongs, the reference verification voltage corresponding to the selected memory cell is temperature compensated to obtain the compensated verification voltage; wherein, the amount of temperature compensation for the verification voltage corresponding to different groups is different.

[0011] The compensated verification voltage is applied to the word line coupled to the selected memory cell to perform a programming verification operation on the selected memory cell.

[0012] In this embodiment, the target programming state of the selected memory cell is grouped. Based on the grouping and the temperature difference between the programming temperature and the reference temperature, temperature compensation is performed on the reference verification voltage corresponding to different groups. The compensation amount is different for different groups, resulting in different verification voltages. The compensated verification voltage is applied to the word line coupled to the selected memory cell to perform programming verification operation on the selected memory cell. This improves the situation where the read failure bit rate count increases due to the different standards of programming and read operations caused by threshold voltage offset at different temperatures of the selected memory cell. Thus, on the one hand, the read success rate can be improved; on the other hand, the number of rereads can be reduced, the efficiency of read operation can be improved, and ultimately the stability of the memory can be improved. Attached Figure Description

[0013] Figure 1 This is a block diagram of an exemplary system with a memory according to embodiments of the present disclosure;

[0014] Figure 2a This is a schematic diagram illustrating an exemplary memory card with memory according to an embodiment of the present disclosure;

[0015] Figure 2b This is a schematic diagram illustrating an exemplary solid-state drive (SSD) with memory according to an embodiment of the present disclosure;

[0016] Figure 3 This is a schematic diagram of an exemplary memory including peripheral circuitry according to an embodiment of the present disclosure;

[0017] Figure 4 This is a schematic diagram illustrating an exemplary NAND flash memory string according to an embodiment of the present disclosure;

[0018] Figure 5 This is a schematic diagram of an exemplary memory including a storage array and peripheral circuitry according to an embodiment of the present disclosure;

[0019] Figure 6 This is a schematic diagram illustrating an exemplary programming method for a storage unit according to an embodiment of the present disclosure;

[0020] Figure 7 This is a schematic diagram illustrating the threshold voltage distribution of a memory cell after programming at different temperatures, according to an embodiment of the present disclosure.

[0021] Figure 8 This is a schematic diagram illustrating the distribution of threshold voltage and read voltage of a memory cell after programming at different temperatures, according to an embodiment of the present disclosure.

[0022] Figure 9 This is a schematic diagram illustrating the distribution of threshold voltages of two target programming states of a memory cell at different temperatures, according to an embodiment of the present disclosure.

[0023] Figure 10 This is a schematic diagram illustrating the programming voltage and verification voltage during the programming process of a memory cell according to an embodiment of the present disclosure;

[0024] Figure 11a This is a schematic diagram illustrating the distribution of threshold voltages in a memory cell during low-temperature and high-temperature programming, according to an embodiment of the present disclosure.

[0025] Figure 11b This is a schematic diagram illustrating the distribution of threshold voltage in a memory cell during high-temperature programming and low-temperature reading, according to an embodiment of the present disclosure.

[0026] Figure 12 This is a schematic flowchart illustrating a method for operating a memory according to an embodiment of the present disclosure. Specific Implementation

[0027] The technical solution of this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] In this embodiment of the disclosure, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order or sequence.

[0029] In this embodiment of the disclosure, the term "A in contact with B" includes the case where A and B are in direct contact, or the case where there are other components between A and B and A is indirectly in contact with B.

[0030] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. Layers may extend horizontally, vertically, and / or along inclined surfaces. Furthermore, a layer may comprise multiple sublayers.

[0031] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0032] It should be noted that although this specification describes the embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0033] Figure 1 Block diagrams of an exemplary system 100 with memory, representing some aspects of embodiments of this disclosure, are shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0034] Memory 104 can be any memory disclosed in this disclosure. As disclosed in detail below, memory 104 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0035] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108.

[0036] In some embodiments, the memory controller 106 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0037] In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0038] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In one example shown in Figure 2A, the memory controller 106 and a single memory 104 can be integrated into a memory card 202. The memory card 202 can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host (e.g., Figure 1The memory card connector 204 is coupled to the host (e.g., the host 108). In another example shown in FIG2B, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include a connector for coupling the SSD 206 to the host (e.g., the host 108). Figure 1 The SSD connector 208 is coupled to the host 108 in the host. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0039] Figure 3 A schematic circuit diagram of an exemplary memory 300, including peripheral circuitry, is shown, illustrating some aspects of embodiments of the present disclosure. The memory 300 may be... Figure 1 An example of memory 104 is shown. Memory 300 may include a memory array device 301 and peripheral circuitry 302 coupled to the memory array device 301. The memory array device 301 may be a NAND flash memory array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown).

[0040] In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell that includes a floating-gate transistor, or a charge-trapping type memory cell that includes a charge-trapping transistor.

[0041] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to write one of three possible nominal storage values ​​into the cell, while a fourth nominal storage value in addition to these three nominal storage values ​​may be used to indicate an erase state.

[0042] like Figure 3As shown, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. SSG 310 and DSG 312 may be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of NAND memory strings 308 within the same block 304 are coupled via the same source line (SL) 314 (e.g., a common SL).

[0043] According to some embodiments, all NAND memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0044] like Figure 3 As shown, the NAND storage string 308 can be organized into multiple blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block 304a, a source line 314 of the selected block 304a and an unselected block 304b on the same plane as the selected block 304a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)).

[0045] It should be understood that, in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any level with any suitable number of blocks or any suitable fraction of blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic unit of data used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates.

[0046] Figure 4 A side view of a cross-section of an exemplary memory array 301 including NAND memory strings 308 is shown, illustrating some aspects of embodiments of the present disclosure. (See also:) Figure 4 As shown,

[0047] The NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory array 401.

[0048] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0049] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0050] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0051] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0052] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0053] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect block 304 of the memory array 301 and to select / deselect word line 318 of block 304. The row decoder / word line driver 508 can also be configured to drive word line 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive SSG line 315 and DSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform an erase operation on memory cell 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0054] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0055] Figure 6 A flowchart illustrating an Increment Step Pulse Program (ISPP) method is shown. When programming NAND memory, Figure 3 Page 320 in the code can be the smallest data unit for a single programming operation. Taking a memory cell in page 320 as an example, before programming begins, an erase operation is performed on the memory block containing the memory cell. After programming begins, a starting programming voltage is applied to the word line coupled to the memory cell to program it. Then, a verification voltage is applied to the word line to verify whether the memory cell has been programmed to the target threshold. If the target threshold has not been reached, a higher programming voltage is used to continue programming the memory cell. The programmed memory cell is then verified, and the above programming and verification process is repeated until the threshold voltage of the memory cell is found to have reached the target threshold during verification. At this point, the programming of the memory cell is complete. During the programming of other memory cells in subsequent pages of page 320, a programming suppression voltage is applied to the bit line of the memory cell to prevent it from being programmed again. When the threshold voltages of all memory cells in this page have been programmed to the target threshold, the entire programming process of page 320 ends.

[0056] During memory operation, situations may arise where the programming and reading temperatures are inconsistent. Temperature affects the conductivity of the channel layer and the tunneling performance of electrons between the memory layers. Specifically, higher temperatures result in better channel conductivity and a higher electron tunneling migration rate between the memory layers. For programming operations, when the same programming voltage is applied to the memory cell, higher temperatures lead to more electrons being trapped in the memory layer, thus increasing the threshold voltage and potentially requiring a corresponding increase in the read voltage.

[0057] However, for read operations, after programming, the number of electrons trapped in the storage layer is constant, assuming negligible leakage current. Therefore, the higher the read temperature, the lower the threshold voltage. This demonstrates that temperature affects both programming and read operations of the storage cell, and the threshold voltage variation with temperature becomes more complex when the programming and read temperatures differ. In this embodiment, the number of electrons trapped in the storage layer can be used as the basis for determining the target programming state of the storage cell. That is, assuming the number of electrons corresponding to the same target programming state remains constant, the target programming state is verified based on the number of electrons, and the read voltage is set based on the number of electrons to determine the state of the storage cell. As temperature increases, the threshold voltage of the storage cell increases; as temperature decreases, the threshold voltage of the storage cell decreases.

[0058] It should be noted that in some high and low temperature stability measurement standards for memory, the test temperature range is -25℃ to 85℃. This temperature range can meet most of the operating conditions of memory. Depending on the memory specifications and the test standards implemented, the temperature range can be further expanded. The embodiments disclosed in this disclosure are merely examples, and no limitations are made on the temperature range or reference temperature.

[0059] For example, refer to Figure 7 As shown, 85°C can be used as a reference temperature. At a programming temperature of 85°C (the programming temperature can be the current temperature of the memory cell or the memory itself), the selected memory cell can be programmed to meet the target programming state. The read voltage V is set based on this threshold voltage distribution range. Read Taking two target programming states, P1 and P2, as an example, E2≤V Read <E3, apply V to the word line coupled to the selected memory cell. Read Threshold voltage less than V Read It is in state P1, and the threshold voltage is greater than V. Read It is in state P2. V Read -E2 represents the even margin of the read window; E3-V read The value represents the odd margin of the read window. Margin values ​​can be positive or negative, but are generally positive. A larger margin results in a larger read window, which is more conducive to distinguishing different target programming states and improving reliability.

[0060] When the temperature drops to 25°C, both the electron tunneling performance and the channel layer conductivity decrease. When the memory cell is programmed to the same target state, the threshold voltage will increase accordingly, thus shifting the threshold voltage towards higher voltage. When the temperature drops to -25°C, the threshold voltage will increase further, shifting it further towards higher voltage. Furthermore, the threshold voltage distribution peak shape of memory cells programmed at high temperatures is narrower, while that of memory cells programmed at low temperatures is wider.

[0061] Continue to refer to Figure 7 V during programming at 25℃ Read It can also distinguish between P1 and P2 states. When the temperature difference is too large and the programming temperature drops to -25℃, the even-numbered margin becomes negative. At this time, some P1 states will be read as P2 states, increasing the read failure rate. The probability of using rereading technology to reselect the read voltage for reading increases, and the read rate decreases.

[0062] To reduce the read failure rate of storage cells caused by the temperature difference between programming and reading temperatures, temperature compensation can be performed on the programming or reading process based on a reference temperature to reduce the shift in the threshold voltage of the storage cell at different temperatures, thereby improving the read success rate of the storage cell.

[0063] In an exemplary temperature compensation method according to an embodiment of this disclosure, a TLC product is used as an example of temperature compensation. The TLC product has 3 memory bits, 1 erase state, and 7 target programming states, including states P0 to P7.

[0064] Figure 8 Curve a in the figure shows the distribution curve of the threshold voltage of each target programmed state after the selected memory cell is programmed at a reference temperature of 85°C. Figure 8 Curve b in the figure shows the distribution curves of the threshold voltages for each target programmed state after programming at a temperature of -25°C. A The reading voltage at 85℃, V B The reading voltage is at -25°C, and the reading voltage from -25°C to 85°C is in V. A and V B Between. Among them, V A It can be V A1 To V A7 Any one of them, V B It can be V B1 To V B7 any one of them

[0065] Understandably, regarding Figure 8 The high-temperature programming and low-temperature reading of the a-curve can be used to... B Shift towards the direction of decreasing voltage, towards V AProximity satisfies the read requirements from P1 to P7 states, while for Figure 8 The scenario of low-temperature programming and high-temperature reading of the b-curve, with reduced V... B It may not be able to meet the reading requirements after low-temperature programming. Similarly, for... Figure 8 The low-temperature programming and high-temperature reading of the b-curve can be used to... A Shift towards the direction of increasing voltage, towards V B Proximity satisfies the read requirements from P1 to P7 states, while for Figure 8 The case of low-temperature programming and high-temperature reading of the a-curve, and the increased V A This may not necessarily satisfy the reading requirements after low-temperature programming. Therefore, when there is a significant temperature difference between the programming and reading temperatures, simply compensating for the reading voltage during the reading process does not fundamentally reduce the threshold voltage offset, and thus may result in an excessively high failure rate for reading from the target programmed state.

[0066] In some embodiments, V A and V B This can be a read voltage set based on the distribution of a threshold voltage for a specific target programming state of a selected memory cell at different temperatures. It is offset according to the temperature change of the memory cell, and the mapping relationship between temperature and read voltage is stored in a register. For example, in... Figure 8 In this context, after selected memory cells are programmed to the same target programming state, as the temperature decreases, their threshold voltage increases, and the read voltage shifts towards the direction of increased voltage. In other embodiments, V A and V B This could be due to the control logic unit controlling the row decoder and column decoder during the reading process. If a read fails, a reread operation is performed, and the V value is generated by re-determining the read voltage based on the threshold voltage offset at different temperatures. A and V B .

[0067] In some implementations, temperature compensation can be performed on the memory cells during programming operations to reduce threshold voltage shifts caused by temperature differences. During programming, after applying a programming voltage to the memory cell, a verification operation is performed on the programmed memory cell by applying a verification voltage. The verification voltage is generally lower than the read voltage, and is the minimum voltage on the target programmed state threshold voltage distribution curve. For example... Figure 7In the process, the verification voltage for state P1 can be E1, and the verification voltage for state P2 can be E3. The read voltage between states P1 and P2 is between E2 and E3. During verification, the threshold voltage of the memory cell is considered to meet the target programming state only when the threshold voltage after programming is greater than or equal to the verification voltage. Temperature compensation can be applied to the verification voltage; by increasing or decreasing the verification voltage, the offset of the threshold voltage can be adjusted, thereby reducing the read failure rate of the memory cell caused by temperature differences. (Continue the comparison.) Figure 8 By examining the threshold voltage distribution curves of memory cells programmed at two different programming temperatures, it can be observed that after programming at a high temperature of 85°C, V... B1 The value of V did not exceed E1. B6 Values ​​exceeding E11 are small, V B7 The relatively small value exceeding E13 indicates that even with programming at a temperature of 85°C and then reading based on a read voltage of -25°C, readings of the P1, P6, and P7 states will not result in many read failures. However, for the P2 through P5 states, high-temperature programming followed by low-temperature reading increases the probability of read failures compared to the P1, P6, and P7 states. Figure 8 In the b-curve, for the case of programming at -25℃ and then reading at 85℃, the results are similar to... Figure 8 The situation is similar to that in curve a.

[0068] In some embodiments, temperature compensation is performed on the programming process of the selected memory cell. For example, using 85°C as a reference temperature, the programming voltage or verification voltage corresponding to the reference temperature is increased or decreased based on the temperature difference between the programming temperature and the reference temperature. The increase or decrease is linearly related to the temperature difference, with the aim of reducing the threshold voltage offset after programming. Generally, the voltage is increased when the temperature is higher than the reference temperature and decreased when the temperature is lower than the reference temperature. In actual temperature compensation operations, the compensation amount is generally the same for all target programming states. However, for the TLC memory cell in this embodiment, the impact of temperature on the threshold voltage of states P2 to P5 is greater than that of states P1, P6, and P7. If the compensation amount for states P1 to P7 is the same, it may result in insufficient compensation for states P2 to P5, or overcompensation for states P1, P6, and P7.

[0069] For example Figure 9 As shown, with a reference temperature of 85℃, after temperature compensation for the programming process from P1 to P7 at a programming temperature of -25℃, the threshold voltages of P4 state after two programming iterations have a significant overlap on the VT axis, and the threshold voltages of P5 state after two programming iterations also have a significant overlap on the VT axis. This reduces the... Figure 8 The diagram shows the shift in threshold voltages for states P4 and P5 due to differences in programming temperature. However, from... Figure 9As can be seen, although temperature compensation brings the threshold voltage distribution curve at low temperatures closer to that at high temperatures, the adjustment of the width of individual distribution curves is still insufficient. The width of an individual distribution curve can include: the difference between E7 and E8, the difference between E7' and E8', the difference between E9 and E10, and the difference between E9' and E10'. Figure 9 The spacing between E8' and E9' is significantly smaller than the spacing between E8 and E9. Even after temperature compensation, the read window of the memory cell programmed at low temperature is still smaller than the read window of the memory cell programmed at the reference temperature.

[0070] Understandably, regardless of whether it's the P4 or P5 state, the increased width of the threshold voltage distribution curve due to low-temperature programming leads to a smaller read voltage window. To increase the read window, the compensation amount needs to be increased. For target programming states like P1, P6, and P7, which are less affected by temperature, a small amount of temperature compensation is sufficient to meet the read voltage requirements, or even without temperature compensation, there is a low read failure rate. Increasing the temperature compensation for these states can cause excessive threshold voltage shifts, increasing the read failure rate. Alternatively, it can cause the total width of the entire threshold voltage distribution to shift too much compared to the reference temperature, placing higher demands on the stability of devices such as voltage generators. Here, the total width could be... Figure 8 The spacing between E13 and E0. For example, when the reference temperature is 85°C and the programming temperature is -25°C, the threshold voltage after temperature compensation will shift in the direction of decreasing voltage, and the spacing between E12 and E0 will decrease. If the spacing is too small, it will reduce the read window.

[0071] Based on the analysis of the above embodiments, it is understood that regardless of whether high-temperature or low-temperature programming is performed, a large temperature difference between the programming temperature and the reading temperature will cause a shift in the threshold voltage, resulting in a higher read failure rate. Furthermore, for a memory cell with multiple target programming states, the shift in the threshold voltage of different target programming states under the same temperature difference will be different, further increasing the read failure rate. Therefore, this disclosure provides a memory, including:

[0072] A storage array includes multiple storage cells and word lines that couple the storage cells;

[0073] The peripheral circuit is coupled to the memory array; there is a temperature difference between the programming temperature and the reference temperature; the target programming state of the selected memory cell is grouped; based on the grouping and the temperature difference, the reference verification voltage corresponding to the selected memory cell is temperature compensated to obtain the compensated verification voltage; the amount of temperature compensation for the verification voltage corresponding to different groups is different; the compensated verification voltage is applied to the word line coupled to the selected memory cell to perform programming verification operation on the selected memory cell.

[0074] As previously mentioned, regardless of whether programming is performed at high or low temperatures, a significant temperature difference between the programming and reading temperatures can cause a shift in the threshold voltage, leading to a higher read failure rate. Therefore, this embodiment of the disclosure includes temperature compensation for the programming process, specifically compensating for the programming verification voltage. Furthermore, in this embodiment, to address the issue that the threshold voltage shift varies for different target programming states under the same temperature difference, grouping is added during compensation. Here, the grouping criterion is primarily the temperature sensitivity of the memory cell to different target programming states. Each group can include one or more target programming states, each with varying temperature sensitivity. Based on this, the amount of temperature compensation for the verification voltage differs for different groups.

[0075] In this embodiment, the memory may include Figure 5 The memory is equipped with peripheral circuitry. The registers in the peripheral circuitry can store information such as reference temperature, programming temperature, reference verification voltage, a first mapping table reflecting the mapping relationship between different target programming states and groups, and a second mapping table reflecting the mapping relationship between the temperature compensation amount and temperature difference of the verification voltage of different groups. This information can be data obtained by testing based on the characteristics of the memory unit and is stored in the registers before the memory leaves the factory.

[0076] The peripheral circuitry can query the first and second mapping tables in the registers to determine the amount of temperature compensation for the reference verification voltage corresponding to the selected memory cell based on the grouping and temperature difference. It then controls the voltage generator to produce the compensated verification voltage. The row decoder applies this compensated verification voltage to the word line coupled to the selected memory cell to perform a programming verification operation. After the memory cell completes its programming operation, the voltage generator produces a read voltage, which the row decoder uses to perform a read operation on the memory cell.

[0077] At the same programming temperature, the verification voltage of the target programmed state generally remains constant. The verification voltage is the minimum voltage in the threshold voltage distribution curve of the target programmed state, for example... Figure 8 The numbers are E1, E3, E5, E7, E9, E11, and E13.

[0078] In some embodiments, the reference verification voltage is the verification voltage at a reference temperature that enables the selected memory cell to meet the target programming state.

[0079] Specifically, the reference verification voltage at the reference temperature is the verification voltage that ensures the threshold voltage of the selected memory cell meets the target programming state. Figure 8 Taking the threshold voltage distribution curves of each target programming state after programming at 85℃ (85℃ can be a reference temperature) as an example, the threshold voltage distribution curve of the selected memory cell when it reaches state P1 is shown in the figure. The threshold voltage of this target programming state can be verified by voltage E1. When the threshold voltage is greater than or equal to E1, it means that the selected memory cell meets the target programming state. The reference verification voltages of other target programming states P2 to P7 at the reference temperature can also be determined by referring to the reference verification voltage of state P1, so that the selected memory cell meets the target programming state.

[0080] For example, the target programming state of the memory cell is selected as P2 state. During the programming process, the initial programming voltage V can be used. pgm1 The memory cell is programmed for the first time, and then a verification voltage V is applied. fy (E3) Read the memory cell. If the memory cell is turned on, it means that the current threshold voltage has not yet reached the target threshold voltage, and may only meet the threshold voltage of the P1 state. After verification failure, in V pgm1 Based on this, add a programming voltage to the V after the voltage is applied. pgm2 The voltage is applied to the selected memory cell and then verified. If it still fails, the voltage is increased again until the threshold voltage of the selected memory cell meets the target threshold voltage.

[0081] In this embodiment of the disclosure, the distribution of the programmed threshold voltage can be adjusted by adjusting the verification voltage. For example, Figure 7 In this process, lowering the verification voltage (i.e., decreasing E3) will decrease the threshold voltage of the P2 state, shifting it towards a lower voltage direction; conversely, increasing the verification voltage (i.e., increasing E3) will increase the threshold voltage of the P2 state, shifting it towards a higher voltage direction. Therefore, temperature compensation for the verification voltage can reduce the shift in the threshold voltage of the selected memory cell during programming at different temperatures, improve read success rate, and enhance the stability of the memory under varying temperatures.

[0082] For example Figure 7 As shown in curve c, after programming at -25℃, the threshold voltages of states P1 and P2 shift towards the voltage increase direction compared to 85℃, resulting in a higher read voltage V. Read Located between E1 and E2, some P1 states are read as P2 states, resulting in a high read error rate. In this case, the verification voltage V can be checked. fy(E1) is compensated to reduce the value of E1, causing the threshold voltage of P1 to shift in the direction of voltage reduction, thus making V Read Located between E2 and E3, it improves the read success rate.

[0083] The grouping of target programming states can be based on the degree to which the threshold voltage of each target programming state deviates due to temperature. For example, target programming states with smaller threshold voltage deviations caused by temperature changes can be grouped into the first group, and their reference programming verification voltage compensation can be reduced by a smaller amount; target programming states with larger threshold voltage deviations caused by temperature changes can be grouped into the second group, and their reference programming verification voltage compensation can be increased by a larger amount. This improves the read success rate of all target programming states and enhances the stability of memory programming and reading at various temperature stages.

[0084] In this embodiment, the threshold voltage verified by the temperature-compensated verification voltage has a reduced deviation from the threshold voltage at the reference temperature. This allows for reading using the read voltage at the reference temperature, improving the read success rate. It is important to emphasize that in this embodiment, the memory temperature during reading may not be the reference temperature. When the memory temperature is not the reference temperature during a read operation, the read voltage can be adjusted based on the temperature difference between the current temperature and the reference temperature. This aims to reduce the read voltage deviation caused by temperature changes and improve the read success rate.

[0085] In this embodiment, the target programming state of the selected memory cell is grouped. Based on the grouping and the temperature difference between the programming temperature and the reference temperature, temperature compensation is performed on the reference verification voltage corresponding to different groups. The compensation amount is different for different groups, resulting in different verification voltages. The compensated verification voltage is applied to the word line coupled to the selected memory cell to perform programming verification operation on the selected memory cell. This improves the situation where the read failure bit rate count increases due to the different standards of programming and read operations caused by threshold voltage offset at different temperatures of the selected memory cell. Thus, on the one hand, the read success rate can be improved; on the other hand, the number of rereads can be reduced, the efficiency of read operation can be improved, and ultimately the reliability and stability of the memory can be improved.

[0086] In some embodiments, the peripheral circuitry may also be configured to: acquire the programming temperature of the memory and determine the temperature difference between the programming temperature and the reference temperature.

[0087] The peripheral circuitry in this embodiment may further include a temperature sensing module for acquiring temperature information of the storage array or the entire memory. In other embodiments, the temperature sensing module may also be located within the memory system 102, and... Figure 5Interface 516 transmits the measured temperature information to the memory. For example, the temperature sensing module may include a temperature sensing circuit. In some embodiments, the temperature sensing module converts the temperature signal into an analog or digital signal and stores it in a register for access by the control logic unit.

[0088] For example, the control logic unit in the peripheral circuit can access registers to obtain the programming temperature and reference temperature of the memory during programming operations, and calculate the temperature difference between the programming temperature and the reference temperature.

[0089] In some embodiments, the peripheral circuitry is further configured to: determine the group to which the target programming state of a memory cell belongs.

[0090] For example, the peripheral circuit can query a first mapping table in the register, which reflects the mapping relationship between different target programming states and groups, to determine the group to which the target programming state of the selected memory cell belongs. Further, the peripheral circuit then queries a second mapping table in the register based on the temperature difference and the group of the target programming state of the selected memory cell to determine the amount of temperature compensation for the reference verification voltage corresponding to the selected memory cell, thus obtaining the temperature-compensated verification voltage. Finally, the peripheral circuit performs a programming verification operation on the selected memory cell to ensure that the selected memory cell meets the target programming state.

[0091] In some embodiments, the peripheral circuit is further configured to: perform temperature compensation on the reference programming voltage corresponding to the selected memory cell based on the grouping and temperature difference to obtain the compensated programming voltage; wherein, the amount of temperature compensation for the programming voltage corresponding to different groups is different; the reference programming voltage is the programming voltage that makes the selected memory cell meet the target programming state at a reference temperature;

[0092] A compensated programming voltage is applied to the word line coupled to the selected memory cell to program the selected memory cell.

[0093] Generally, the programming voltage is higher than the verification voltage. The reference programming voltage here is the final programming voltage applied to the memory cell at a reference temperature to ensure it passes the verification test. (Combined with...) Figure 10 As shown, for example, the programming voltage to reach the target programming state is V. pgm4 The starting voltage for this programming process is V. pgm1 From V pgm1 After programming, verification, and voltage application, the programming voltage is applied to V. pgm4 This ensures that the selected memory cell meets the target programming state, at which point the reference programming voltage is V. pgm4 .

[0094] In some embodiments, the programming verification voltage is one of a series of programming verification voltages, and the programming voltage is one of a series of programming voltages.

[0095] Understandably, to avoid overprogramming, the initial programming voltage is always increased gradually from a lower voltage. However, due to temperature variations causing threshold voltage shifts, the original reference programming voltage may be too far from the programming voltage required to reach the target threshold voltage. This increases the number of cycles between voltage-based programming and verification, reducing programming efficiency. Conversely, the original reference programming voltage may be too close to the programming voltage required to reach the target threshold voltage, making overprogramming more likely during the voltage-based programming process.

[0096] For example, in combination Figure 6 and Figure 10 As shown, the target programming state is the P1 state with a low threshold voltage. Excessive programming voltage causes the threshold voltage to shift towards or even reach the P2 state, resulting in overprogramming. This necessitates erasing the programmed memory cell and reprogramming, reducing programming efficiency. Therefore, this embodiment of the present disclosure can compensate for the reference programming voltage based on temperature difference, reducing overprogramming and improving programming efficiency.

[0097] When the programming voltage is obtained by temperature compensation of the reference programming voltage, the programming voltage can also be referenced. Figure 6 and Figure 10 The method involves starting with a small initial programming voltage and gradually increasing the voltage to verify the programming voltage, so that the selected memory cell meets the target programming state.

[0098] In some embodiments, during the gradual voltage increase process, the starting voltage at the reference temperature can be continued to be gradually increased to the temperature-compensated programming voltage. The number of programming and verification cycles at the programming temperature may increase or decrease compared to the number of cycles at the reference temperature. The reference programming voltage V at the reference temperature is used as the reference. pgm4 For example, only V pgm4 Compensation is performed to obtain a new V pgm4 The starting voltage is still V. pgm1 The number of loops for stress programming and verification may increase or decrease.

[0099] In some embodiments, during the gradual pressurization process, the initial programming voltage at the reference temperature can also be temperature-compensated. While maintaining a constant pressurization value for each pressurization, this is equivalent to temperature-compensating the programming voltage in each pressurization programming and verification cycle. The number of pressurization programming and verification cycles at the programming temperature may remain constant compared to the number of cycles at the reference temperature. The reference programming voltage V at the reference temperature is used as an example. pgm4 For example, for Vpgm1 and V pgm4 Temperature compensation is applied to all cases, resulting in a new programming voltage V after voltage increase. pgm2 And the new programming voltage V pgm3 This is equivalent to temperature compensation, so the number of cycles for pressurized programming and verification may remain unchanged.

[0100] It is understandable that the programming verification voltage varies for different target programming states. For example, the programming verification voltage for state P1 is E1, for state P2 it is E3, and for state P3 it is E5.

[0101] In some embodiments, refer to Figure 10 As shown, the same start-up voltage (V) can be used when programming a selected memory cell for any target programming state. pgm1 The target programming state is determined by verifying the voltage, but the programming voltage obtained after applying voltage is different for different target programming states.

[0102] In other embodiments, combined with Figure 7 , Figure 8 and Figure 10 As shown, when programming memory cells selected for target programming states with high threshold voltages, a voltage higher than V can be selected. pgm1 For higher voltages, you can start coding directly from V. pgm2 V pgm3 Or V pgm4 Start programming from any one of them until the target programming state is met.

[0103] In some embodiments, there is a linear relationship between the amount of temperature compensation and the temperature difference, and the linear parameters of the linear relationship are different for different groups.

[0104] For example, compensation for both verification voltage and programming voltage can be based on the following model:

[0105] Compensated verification voltage = Reference verification voltage + k1(Programmed temperature - Reference temperature)

[0106] Compensated programming voltage = Reference programming voltage + k2(Programming temperature - Reference temperature)

[0107] The k-value (including k1 or k2) is a linear parameter, which is a value designed by the memory supplier based on the offset between temperature and threshold voltage. For different target programming states, the corresponding k-value may be different, and multiplying the k-value by the same temperature difference will result in different compensation amounts. The k-value can be positive or negative, and can be selected according to the offset of the threshold voltage with temperature. For example, in this embodiment of the disclosure, the k-value can be positive. When the programming temperature is lower than the reference temperature, the threshold voltage shifts in the boost direction. A negative compensation amount can reduce the verification voltage or programming voltage to reduce the offset of the threshold voltage. Under the same temperature difference, a larger k-value results in a larger compensation amount, and a smaller k-value results in a smaller compensation amount. For example, the k-value may include, but is not limited to, -5.625mV / 2℃ or -5mV / 2℃.

[0108] In some embodiments, the selected memory cell has m bits of storage and a target programming state of 2. m -1, where m is a positive integer greater than or equal to 1; the target programming state is grouped into a first group and a second group; the threshold voltages corresponding to the target programming states contained in the first group and the target programming states contained in the second group have different sensitivities to temperature.

[0109] The selected memory cells can include multiple target memory cell states. The threshold voltage of different target programming states within the same selected memory cell may have different temperature sensitivities. Specifically, when there is a temperature difference between the programming temperature and the reference temperature, the offset of the threshold voltage of different target programming states may differ. If the same amount of temperature compensation is applied to the verification voltage or programming voltage of all target programming states, it may result in target programming states with large threshold voltage offsets not being adequately compensated, or target programming states with small threshold voltage offsets being overcompensated, leading to an excessive read failure rate. To address this, the target programming states can be grouped according to their varying temperature sensitivity to the threshold voltage of the selected memory cell's target programming states. Different amounts of temperature compensation can then be applied to the target programming states in different groups, reducing the read failure rate.

[0110] In some embodiments, the selected memory cell has 3 bits of storage and 7 target programming states; wherein, the target programming states of the first group include: state 1, state 6 and state 7; the target programming states of the second group include: state 2 to state 5; the second group is more sensitive to temperature than the first group; the amount of temperature compensation for the verification voltage corresponding to the second group is greater than the amount of temperature compensation for the verification voltage corresponding to the first group.

[0111] Different memory cells can have multiple target programming states depending on their number of memory bits. For example, an SLC type memory cell has 1 memory bit, including 1 erase state and 1 target programming state; an MLC type memory cell has 2 memory bits, including 1 erase state and 3 target programming states; a TLC type memory cell has 3 memory bits, including 1 erase state and 7 target programming states; and a QLC type memory cell has 4 memory bits, including 1 erase state and 15 target programming states.

[0112] like Figure 8 As shown, taking a TLC type (m=3) memory cell as an example, the erase state can be P0, the first state can be P1, the second state can be P2, the third state can be P3, and so on for the fourth to seventh states. Temperature has a greater impact on the threshold voltage of states P2 to P5 than on states P1, P6, and P7. Therefore, states P1, P6, and P7 can be divided into a first group for less compensation or no compensation, while states P2 to P5 can be divided into a second group for more compensation. This allows for separate compensation of the reference verification voltage corresponding to different groups. The amount of temperature compensation differs for the verification voltage or programming voltage corresponding to different groups, reducing overprogramming, improving programming efficiency, and increasing read success rate.

[0113] In some high and low temperature stability measurement standards for memory, the test temperature range is -25°C to 85°C. This temperature range can meet most of the operating conditions of memory. Depending on the memory specifications and the test standards implemented, the temperature range can be further expanded. The embodiments disclosed in this disclosure are merely examples, and no limitations are made on the temperature range or reference temperature.

[0114] In some embodiments, the lowest or highest temperature within the test temperature range is selected as the reference temperature. For example, 85°C can be selected as the reference temperature, and the programming temperatures within this temperature range will all be lower than 85°C. In other embodiments, the lowest temperature -25°C can also be selected as the reference temperature, and the programming temperatures within this temperature range will all be higher than this reference temperature.

[0115] In some embodiments, refer to Figure 11a The diagram illustrates the threshold voltage during low-temperature programming and high-temperature programming. During low-temperature programming, the low temperature increases sensing interference during the verification process, causing a decrease in the acquired induced current or voltage, resulting in overprogramming and further increasing the threshold voltage. Conversely, as the temperature gradually increases, the distribution width of the threshold voltage decreases; that is, the distance between E1 and E2 is smaller than the distance between E1' and E2'. With further temperature increases, the threshold voltage will also shift overall towards a decrease in voltage.

[0116] In other embodiments, reference is made to Figure 11bThe diagram illustrates a threshold voltage that is programmed at high temperature and read at low temperature. After high-temperature programming, the subsequent cooling for reading causes the threshold voltage width to increase, and the overall threshold voltage to shift towards a higher voltage direction. However, in... Figure 11b During the cooling process, the storage cells lose charge, which may cause the threshold voltage to shift towards the voltage drop direction. The greater the temperature difference, the more severe the shift will be. Applying a read voltage to read the data will result in a large number of read failures.

[0117] Therefore, it is evident that during the high-temperature programming and low-temperature reading process, the charge loss caused by the low temperature will cause the threshold voltage, which should originally shift towards voltage increase, to shift in the opposite direction towards voltage decrease. This increases the complexity of temperature compensation. Therefore, a high temperature (e.g., 85°C) can be used as the base temperature. The actual programming or reading temperature will be lower than this temperature. During the cooling process, temperature compensation is used to reduce the threshold voltage shift caused by charge loss, thereby improving the read / write success rate. In some embodiments, 85°C is used as the base temperature, and -25°C is used as the programming temperature. Temperature compensation tests are performed on the selected TLC memory cells using the maximum temperature difference. Figure 8 As shown, without temperature compensation, the P1, P6, and P7 states in the first group still have a high success rate when read at the reference temperature. However, the threshold voltages of the P2 to P5 states in the second group show a significant shift. For example, the read voltage VA3 between the P2 and P3 states is 40mV lower than E4, causing some read errors in the P2 state; the read voltage VA4 between the P3 and P4 states is 50mV lower than E6, causing some read errors in the P3 state; the read voltage VA5 between the P4 and P5 states is 20mV lower than E8, causing some read errors in the P4 state; and the read voltage VA6 between the P5 and P6 states is 20mV lower than E10, causing some read errors in the P5 state.

[0118] The programming verification voltage for states P1 through P7 was reduced by 40mV, which can make V A3 Exactly equal to E4, V A4 Equal to E6, it can read P2, P3, and P4 states; V A5 It's 20mV larger than the E8, V A6 It is 20mV larger than E10, which allows for better reading of the P5 state. However, the total threshold voltage distribution width (the distance between E13 and E0) is reduced by 85mV compared to before compensation, which is not conducive to expanding the reading window and also places higher demands on the reliability of devices such as voltage generators.

[0119] In some embodiments, no compensation is performed on the P1, P6 and P7 states of the first group. Only the programming verification voltage of the P2 to P5 states is reduced by 40mV. This achieves the threshold voltage distribution after all states are reduced by 40mV, which can meet all the reading requirements of the P1 to P7 states. Furthermore, the total threshold voltage distribution width (the distance between E13 and E0) is not reduced compared to before compensation, thus maintaining the original reading window range.

[0120] Understandably, the target programming states of the second group can be further subdivided, for example, the P5 and P6 states can be divided into a third group for compensation, so that V A5 It is exactly equal to E8, or V A6 It is exactly equal to E10, which is just enough to read the P5 and P6 states.

[0121] For QLC products with more target programming states, the target programming can be grouped, and the verification voltage and programming voltage can be compensated separately to improve the read accuracy of the target programming state and improve the stability of the memory at different temperatures.

[0122] In some embodiments, the memory may include a three-dimensional NAND flash memory, and the memory may include... Figure 4 The NAND string structure shown may include the following circuitry: Figure 3 The circuit shown is a NAND type memory circuit.

[0123] A second aspect of the embodiments of this disclosure, referring to... Figure 1 As shown, a memory system 102 is provided, including a memory 104 and a memory controller 106. The memory controller 106 is coupled to the memory 104 and configured to control the memory 104. The memory controller 106 can receive commands from the host 108 and control the memory 104 to perform operations such as programming, reading, or temperature compensation.

[0124] A third aspect of the embodiments of this disclosure, referring to... Figure 12 As shown, a method for operating a memory is provided, including:

[0125] S100: Based on the temperature difference between the programming temperature and the reference temperature, and the group to which the target programming state of the selected memory cell belongs, temperature compensation is performed on the reference verification voltage corresponding to the selected memory cell to obtain the compensated verification voltage; wherein, the amount of temperature compensation for the verification voltage corresponding to different groups is different.

[0126] S200: Apply a compensated verification voltage to the word line coupled to the selected memory cell to perform a programming verification operation on the selected memory cell.

[0127] In this embodiment, the reference verification voltage is the verification voltage that makes the selected memory cell meet the target programming state at a reference temperature.

[0128] In some embodiments, the operation method further includes, prior to performing S100:

[0129] Obtain the memory's programming temperature and determine the temperature difference between the programming temperature and the reference temperature.

[0130] In some embodiments, the operation method further includes performing S100 as follows:

[0131] Determine the group to which the target programming state of the selected memory cell belongs.

[0132] In some embodiments, based on grouping and temperature difference, the reference programming voltage corresponding to the selected memory cell is temperature compensated to obtain the compensated programming voltage; wherein, the amount of temperature compensation for the programming voltage corresponding to different groups is different; the reference programming voltage is the programming voltage that makes the selected memory cell meet the target programming state at a reference temperature;

[0133] A compensated programming voltage is applied to the word line coupled to the selected memory cell to program the selected memory cell.

[0134] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, comprising: The memory comprises: a memory array comprising a plurality of memory cells, and word lines coupled with the memory cells; a peripheral circuit coupled with the memory array; a temperature difference exists between a programming temperature and a reference temperature; a plurality of groups exist for target programming states of selected memory cells in the memory, at least one of the groups comprises a plurality of target programming states; wherein the peripheral circuit is configured to: based on the groups and the temperature difference, temperature-compensate a reference verify voltage corresponding to the selected memory cells to obtain a compensated verify voltage; wherein the amount of temperature compensation for verify voltages corresponding to different groups is different; and apply the compensated verify voltage to a word line coupled with the selected memory cells to perform a program verify operation on the selected memory cells.

2. The memory of claim 1, wherein, The peripheral circuit is further configured to: obtain the programming temperature of the memory, and determine the temperature difference according to the programming temperature and the reference temperature.

3. The memory of claim 1, wherein, The peripheral circuit is further configured to: determine the group to which a target programming state of selected memory cells in the memory belongs.

4. The memory of claim 1, wherein, The peripheral circuit is further configured to: based on the groups and the temperature difference, temperature-compensate a reference program voltage corresponding to the selected memory cells to obtain a compensated program voltage; wherein the amount of temperature compensation for program voltages corresponding to different groups is different; the reference program voltage is a program voltage at the reference temperature that causes the selected memory cells to satisfy the target programming state; apply the compensated program voltage to a word line coupled with the selected memory cells to perform a program operation on the selected memory cells.

5. The memory of claim 4, wherein, The verify voltage is one of a series of program verify voltages, and the program voltage is one of a series of program voltages.

6. The memory of claim 1, wherein, There is a linear relationship between the amount of temperature compensation and the temperature difference, and the linear parameters of the linear relationship corresponding to different groups are different.

7. The memory of claim 6, wherein, The number of storage bits of the selected memory cells comprises m bits, the target programming states of the selected memory cells are 2m-1, and m is a positive integer greater than or equal to 1; the groups of target programming states comprise a first group and a second group; the target programming states included in the first group and the target programming states included in the second group correspond to different sensitivities of threshold voltage to temperature.

8. The memory of claim 7, wherein, The number of storage bits of the selected memory cells is 3 bits, and the target programming states of the selected memory cells are 7; wherein the target programming states of the first group include: the 1st state, the 6th state, and the 7th state; the target programming states of the second group include: the 2nd state to the 5th state; the sensitivity of the second group to temperature is greater than the sensitivity of the first group to temperature; and the amount of temperature compensation for verify voltages corresponding to the second group is greater than the amount of temperature compensation for verify voltages corresponding to the first group.

9. The memory of claim 1, wherein, The reference temperature is higher than the programming temperature.

10. A memory system, characterized by comprising: The memory comprises: the memory of any one of claims 1 to 9; and a memory controller configured to be coupled with the memory and control the memory.

11. A method of operating a memory, comprising: The memory comprises: temperature compensation is performed on a reference verify voltage corresponding to the selected memory cell based on a temperature difference between a programming temperature and a reference temperature and a group to which a target programming state of the selected memory cell belongs, to obtain a compensated verify voltage; wherein the target programming state of the selected memory cell in the memory has multiple groups, and at least one of the groups contains multiple target programming states; and the temperature compensation of the verify voltage corresponding to different groups is different in amount; a word line coupled to the selected memory cell is applied with the compensated verify voltage to perform a program verify operation on the selected memory cell.

12. The method of claim 11, wherein, The method further includes: obtaining the programming temperature of the memory, and determining the temperature difference based on the programming temperature and the reference temperature.

13. The method of claim 11, wherein, The method further includes: determining the group to which the target programming state of the selected memory cell in the memory belongs.

14. The operating method according to claim 11, characterized in that, The method further includes: temperature compensation is performed on a reference programming voltage corresponding to the selected memory cell based on the group and the temperature difference, to obtain a compensated programming voltage; wherein the temperature compensation of the programming voltage corresponding to different groups is different in amount; and the reference programming voltage is a programming voltage that makes the selected memory cell satisfy the target programming state at the reference temperature; a word line coupled to the selected memory cell is applied with the compensated programming voltage to perform a program operation on the selected memory cell.

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