Memory and method of operating the same

Abstract

A memory and an operating method thereof are disclosed. The memory includes: first register circuit through Nth register circuit, each of which is adapted to receive and store a fault address transferred from a memory controller when a corresponding selection signal among first selection signal through Nth selection signal is activated, where N is an integer equal to or greater than 2; first resource latch circuit through Nth resource latch circuit, which are adapted to store first resource signal through Nth resource signal indicating availability of the first register circuit through the Nth register circuit, respectively; and a priority selection circuit adapted to activate one of the selection signals corresponding to the activated resource signals respectively among the first resource signal through the Nth resource signal when two or more among the first resource signal through the Nth resource signal are activated.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0130108, filed on September 30, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention relate to memory. Background Technology

[0004] Typically, memory like dynamic random access memory (DRAM) undergoes a testing process after design and manufacturing to determine if the memory has any defects.

[0005] If even one memory cell among many in a memory is found to be defective, the memory cannot perform its function properly and is discarded as a defective product. However, discarding the memory as a defective product even with a small number of defective cells is inefficient in terms of yield. To overcome this problem, a method is currently being used that provides a memory with redundant memory cells and replaces the defective memory cells with the redundant cells through a testing process.

[0006] Post-packaging repair refers to repairing memory after the packaging process. Post-packaging repair can be performed not only during memory manufacturing but also during user operation. For efficient post-packaging repair, a technique for effectively allocating and managing repair resources within the memory is crucial. Summary of the Invention

[0007] Embodiments of the present invention relate to a method for efficiently allocating and managing repair resources within a memory.

[0008] According to one embodiment of the present invention, a memory includes: a first register circuit to an Nth register circuit, each of the first register circuit to the Nth register circuit being adapted to: receive and store a fault address transmitted from a memory controller when a corresponding selection signal among the first selection signal to the Nth selection signal is activated, wherein N is an integer equal to or greater than 2; a first resource latch circuit to the Nth resource latch circuit, adapted to store a first resource signal to the Nth resource signal respectively indicating the availability of the first register circuit to the Nth register circuit; and a priority selection circuit adapted to: activate one of the selection signals among the first selection signal to the Nth selection signal respectively corresponding to the activated resource signal when two or more of the first resource signal to the Nth resource signal are activated.

[0009] According to another embodiment of the present invention, a method for operating a memory includes: entering a soft-repair mode; searching for available register circuits among a first register circuit to an Nth register circuit, where N is an integer equal to or greater than 2; selecting a high-priority register circuit among the available register circuits; and storing a fault address transmitted from the memory controller into the selected register circuit.

[0010] According to another embodiment of the present invention, a method of operating a memory in a soft-repair mode includes: storing a fault address initially provided by a controller in a selected register circuit with high priority among a plurality of available register circuits; and, in response to a lock command accompanying a fault address subsequently provided by the controller, prohibiting the selected register circuit from storing subsequent data for further soft repair. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a memory 100 according to an embodiment of the present invention.

[0012] Figure 2 This illustrates an embodiment of the invention. Figure 1 The block diagram of register circuit 120 shown is shown.

[0013] Figure 3 This illustrates an embodiment of the invention. Figure 1 The block diagram of the resource latch circuit 130 shown is shown.

[0014] Figure 4 An embodiment of the invention is shown. Figure 1 The operation of the priority selection circuit 140 shown.

[0015] Figure 5 This illustrates an embodiment of the invention. Figure 1 The block diagram of the control circuit 150 shown is shown.

[0016] Figure 6 This illustrates an embodiment of the invention. Figure 1 The block diagram of the access masking circuit 160 shown is illustrated.

[0017] Figure 7 This describes an embodiment of the present invention. Figure 1 The flowchart shows the soft repair operation of the memory 100 shown.

[0018] Figure 8 This describes an embodiment of the present invention. Figure 1 The flowchart shows the undo operation of the memory 100 shown.

[0019] Figure 9This describes an embodiment of the present invention. Figure 1 The flowchart shows the locking operation of the memory 100. Detailed Implementation

[0020] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various figures and embodiments of the invention.

[0021] Figure 1 This is a block diagram illustrating a memory 100 according to an embodiment of the present invention.

[0022] refer to Figure 1 The memory 100 may include a non-volatile storage circuit 110, a register circuit 120, a resource latch circuit 130, a priority selection circuit 140, a control circuit 150, an access masking circuit 160, an address latch circuit 170, an address comparison circuit 180, a row circuit 190, and a cell array 195.

[0023] The non-volatile memory circuit 110 can store repair data, i.e., fault addresses. The non-volatile memory circuit 110 may include multiple electronic fuses and can store fault addresses in the electronic fuses. Typically, fault addresses corresponding to defects detected during testing performed during the manufacturing process of memory 100 can be stored in the non-volatile memory circuit 110. The non-volatile memory circuit 110 may also be referred to as an electronic fuse array circuit. Those skilled in the art will recognize that the non-volatile memory circuit 110 can be configured to include other types of non-volatile memory cells besides electronic fuses.

[0024] Register circuit 120 can store fault addresses to be repaired. Register circuit 120 can store fault addresses ARE_ADDR<15:0> transferred from non-volatile memory circuit 110 during the startup operation performed at the initial stage of memory 100 operation. Furthermore, register circuit 120 can receive and store fault addresses ADDR<15:0> transferred from outside memory 100 (e.g., memory controller) during soft repair operations. That is, a portion of register circuit 120 can store fault addresses ARE_ADDR<15:0> transferred from non-volatile memory circuit 110 during startup operations, while the remaining register circuit 120 can receive and store fault addresses ADDR<15:0> transferred from outside memory 100 during soft repair operations. Among the memory cells of cell array 195, the memory cell corresponding to the fault address stored in register circuit 120 can be the repair target. The selection circuit 121 at the front end of the register circuit 120 can transfer the fault address ADDR<15:0> transferred from outside the memory 100 to the register circuit 120 during a soft repair operation (i.e., when the soft repair signal SOFT_EN is activated). Otherwise, the selection circuit 121 can transfer the fault address ARE_ADDR<15:0> transferred from the non-volatile memory circuit 110 to the register circuit 120.

[0025] Address latch circuit 170 can receive and store addresses ADDR<15:0> transferred from outside memory 100 during activation operation. The address stored in address latch circuit 170 can be the address used to specify the memory cell to be accessed in cell array 195. Here, the number of bits in address ADDR<15:0> is shown as 16 bits. The activation pulse ACTIVE_PULSE input to address latch circuit 170 can be a pulse signal that is activated during activation operation, and address latch circuit 170 can receive and store the address in response to activation of activation pulse ACTIVE_PULSE.

[0026] Address comparison circuit 180 compares the address ADDRESS_L<15:0> output from address latch circuit 170 with fault addresses FAIL_ADDRESS_0<15:0>, FAIL_ADDRESS_1<15:0>, FAIL_ADDRESS_2<15:0>, and FAIL_ADDRESS_3<15:0> to generate match signals MATCH_0 to MATCH_3. Match signal MATCH_0 is activated when fault address FAIL_ADDRESS_0<15:0> matches address ADDRESS_L<15:0>. Match signal MATCH_1 is activated when fault address FAIL_ADDRESS_1<15:0> matches address ADDRESS_L<15:0>. Similarly, match signal MATCH_2 is activated when fault address FAIL_ADDRESS_2<15:0> matches address ADDRESS_L<15:0>. The match signal MATCH_3 can be activated when the fault address FAIL_ADDRESS_3<15:0> matches the address ADDRESS_L<15:0>.

[0027] During the activation operation when the row activation signal RACT is activated, the row circuit 190 can activate one of the rows WL0 to WLN and RWL0 to RWL3 of the cell array 195. The row activation signal RACT can be a signal activated during the activation operation period. That is, the row activation signal RACT can be a signal that is activated in response to an activation command and deactivated in response to a precharge command. When all match signals MATCH_0 to MATCH_3 are deactivated, the row circuit 190 can decode the address ADDRESS_L<15:0> to activate one of the normal rows WL0 to WLN. In addition, when match signals MATCH_0 to MATCH_3 are activated, the row circuit 190 can activate the redundant row among the redundant rows RWL0 to RWL3 that corresponds to the activated match signal. For example, the row circuit 190 can activate the redundant row RWL0 when the match signal MATCH_0 is activated, and activate the redundant row RWL2 when the match signal MATCH_2 is activated. Row circuit 190 can activate one of the normal rows WL0 to WLN during activation by decoding address ADDRESS_L<15:0>. However, when one of the match signals MATCH_0 to MATCH_3 is activated, i.e., when address ADDRESS_L<15:0> matches one of the fault addresses FAIL_ADDRESS_0<15:0> to FAIL_ADDRESS_3<15:0>, one of the redundant rows can be activated instead of the defective normal row.

[0028] When the fault addresses FAIL_ADDRESS_0<15:0> to FAIL_ADDRESS_3<15:0> stored in register circuit 120 overlap, or when two or more of the match signals MATCH_0 to MATCH_3 are redundantly activated due to an error, row circuit 190 can activate the redundant row corresponding to the lower-numbered match signal among the activated match signals. This allows soft repair to be prioritized when several repair operations overlap.

[0029] Cell array 195 may include storage cells arranged in multiple rows and multiple columns. In this document, a row of cell array 195 may also be referred to as a word line.

[0030] Resource latch circuit 130 can generate resource signals RESOURCE<0:3>, which indicate the availability of register circuit 120. Resource signals RESOURCE<0:3> can indicate a set (i.e., a register group) of one or more register circuits within register circuit 120 that are available for soft repair. A register circuit may be unavailable when one of the register circuits 120 has already been used for repair using non-volatile memory circuit 110 (normal repair) or when the redundant row corresponding to a register circuit in register circuit 120 is defective.

[0031] Priority selection circuit 140 can receive resource signals RESOURCE<0:3> and generate selection signals SELECTION<0:3>. Selection signal SELECTION<0:3> can be a signal used to select the register group to be used for soft repair within register circuit 120. When two or more resource signals RESOURCE<0:3> are activated, priority selection circuit 140 can activate only one of the selection signals corresponding to the activated resource signals. That is, when two or more available register circuits exist, priority selection circuit 140 can be used to select one of the two or more available register circuits.

[0032] The control circuit 150 can be a circuit used to control undo and lock operations. The undo operation can be an operation to cancel a soft repair of a specific fault address. Furthermore, the lock operation can be an operation used to put a soft repair for a specific fault address into a state where undoing is impossible.

[0033] Access masking circuit 160 can be used to perform control in a way that makes it impossible to perform additional soft repairs on fault addresses that are locked after a soft repair.

[0034] Figure 2 This illustrates an embodiment of the invention. Figure 1 The block diagram of register circuit 120 shown is shown.

[0035] refer to Figure 2 Register circuit 120 may include four register circuits 210 to 240. The four register circuits 210 to 240 may respectively include latches 211, 221, 231 and 241, AND gates 213, 223, 233 and 243, and OR gates 215, 225, 235 and 245. This document uses four register circuits as an example, but this is merely an example, and those skilled in the art will recognize that the number of register circuits 120 may differ from this example.

[0036] The startup pulse signal BOOTUP_PULSE<0:3> can be a signal used during startup operations to select, among register circuits 210 to 240, the register circuit used to store the address ADDR_S<15:0> selected by selection circuit 121. For example, the startup pulse signal BOOTUP_PULSE <0> This can be a signal used to select register circuit 210, and a start pulse signal BOOTUP_PULSE. <1> It can be a signal used to select register circuit 220.

[0037] The selection signal SELECTION<0:3> can be used during a soft-repair operation to select from the register circuit the register circuit used to store the address ADDR_S<15:0> selected by the select circuit 121. For example, the selection signal SELECTION <1> It can be a signal used to select register circuit 220, and the selection signal SELECTION <3> It can be a signal used to select register circuit 240.

[0038] The soft masking signal SOFT_EN_MASKB can be a signal that is kept at level "1" but is activated to level "0" when a locking operation is needed to prevent a soft repair operation.

[0039] The soft clock SOFT_CLK can be a clock that is switched during a soft repair operation.

[0040] When the BOOTUP_PULSE<0:3> signal is activated to level "1" or signal B<0:3> is activated, OR gates 215, 225, 235, and 245 can activate signal A<0:3> to level "1". When the soft clock SOFT_CLK and the selection signal SELECTION<0:3> are activated to level "1", AND gates 213, 223, 233, and 243 can activate signal B<0:3>. Here, when the soft masking signal SOFT_EN_MASKB is activated to level "0", AND gates 213, 223, 233, and 243 can mask signal B<0:3> so that it is not activated.

[0041] Each of latches 211, 221, 231, and 241 can store 16 bits. Latches 211, 221, 231, and 241 may include an input terminal D, an output terminal Q, and a clock terminal CLK. When the signal A<0:3> at the clock terminal CLK is activated, latches 211, 221, 231, and 241 can receive and store the address ADDR_S<15:0> transmitted to input terminal D. Fault addresses FAIL_ADDRESS_0<15:0> to FAIL_ADDRESS_3<15:0> stored in latches 211, 221, 231, and 241 can be output through output terminal Q. When the undo signal UNDOB<0:3> is activated, the information stored in latches 211, 221, 231, and 241 can be initialized.

[0042] During startup, selection circuit 121 can select and output the fault address ARE_ADDR<15:0> (ADDR_S<15:0> = ARE_ADDR<15:0>) transmitted from non-volatile memory circuit 110. Therefore, the latch corresponding to the activated startup pulse signal in startup pulse signal BOOTUP_PULSE<0:3> can receive and store the fault address ARE_ADDR<15:0>.

[0043] During the soft repair operation, the selection circuit 121 can select and output the fault address ADDR<15:0> (ADDR_S<15:0> = ADDR<15:0>) transferred from outside the memory 100. Therefore, when the soft masking signal SOFT_EN_MASKB is held at level "1", the latch corresponding to the activated selection signal in the selection signal SELECTION<0:3> can receive and store the fault address ADDR<15:0>.

[0044] Figure 3 This illustrates an embodiment of the invention. Figure 1 The block diagram of the resource latch circuit 130 shown is shown.

[0045] refer to Figure 3 The resource latch circuit 130 may include four resource latch circuits 310 to 340. The number of resource latch circuits 130 may be the same as the number of register circuits 120.

[0046] Resource latching circuits 310 to 340 may each include first latches 311, 321, 331 and 341, second latches 313, 323, 333 and 343, NAND gates 315, 325, 335, 345, 316, 326, 336 and 346, AND gates 317, 327, 337 and 347, and inverters 319, 329, 339 and 349.

[0047] When the BOOTUP_PULSE<0:3> start pulse signal is activated, the first latches 311, 321, 331, and 341 can receive and store the use signal USED. The use signal USED can be a signal transmitted from the non-volatile memory circuit 110 during the start operation, and it indicates whether the corresponding register circuits 210 to 240 have been used for normal repair operations, i.e., repair operations other than soft repair operations. Activation of the use signal USED indicates that register circuits 210 to 240 have been used or cannot be used due to defects. Deactivation of the use signal USED indicates that register circuits 210 to 240 can be used. For example, when register circuit 210 is used during normal repair operations, the start pulse signal BOOTUP_PULSE... <0> When activated, the Used signal can be activated to level "1". Additionally, when register circuit 220 is not used during normal repair operations, the BOOTUP_PULSE startup pulse signal... <1> When activated, the USED signal can be deactivated to level "0".

[0048] Inverters 319, 329, 339 and 349 can invert the outputs of the first latches 311, 321, 331 and 341 to generate the unused signal UNUSED<0:3>.

[0049] NAND gates 315, 325, 335, and 345 can receive the unused signal UNUSED<0:3> and the delayed startup pulse signal BOOTUP_PULSE_D<0:3>. The delayed startup pulse signal BOOTUP_PULSE_D<0:3> can be obtained by slightly delaying the startup pulse signal BOOTUP_PULSE<0:3> by a timing margin. The output signals of NAND gates 315, 325, 335, and 345 can have an inverted level of the unused signal UNUSED<0:3> and can be slightly later in timing than the unused signal UNUSED<0:3>.

[0050] NAND gates 316, 326, 336, and 346 can receive the output signals of NAND gates 315, 325, 335, and 345, as well as the undo signal UNDOB<0:3>, and generate signal C<0:3>. The undo signal UNDOB<0:3> can be a signal activated to level "0" during an undo operation performed on the corresponding register circuits 210 to 240. Normally, the undo signal UNDOB<0:3> remains at level "1". Therefore, in most cases, the level of signal C<0:3> can be the same as the level of the unused signal UNUSED<0:3>.

[0051] AND gates 317, 327, 337, and 347 can receive a delayed soft clock SOFT_CLK_D, a select signal SELECTION<0:3>, and output a signal D<0:3>. Since the delayed soft clock SOFT_CLK_D is obtained by delaying the soft clock SOFT_CLK, the signal D<0:3> can be a signal activated after register circuits 210 to 240 are selected based on the select signal SELECTION<0:3>. For example, in the case of the select signal SELECTION... <1> After selecting register circuit 220, signal D <1> It can be activated.

[0052] Second latches 313, 323, 333, and 343 can activate the resource signal RESOURCE<0:3> to level "1" in response to signal C<0:3> being activated to level "1," and deactivate the resource signal RESOURCE<0:3> to level "0" in response to signal D<0:3> being activated to level "1." Second latches 313, 323, 333, and 343 can be SR latches that use signal C<0:3> as a set signal and signal D<0:3> as a reset signal.

[0053] The resource signal RESOURCE<0:3> can be a signal that is normally activated when the unused signal UNUSED<0:3> is activated and deactivated after the selection signal SELECTION<0:3> is activated. The resource signal RESOURCE<0:3> can be a signal with a level of "1" when the corresponding register circuits 210 to 240 are available and a level of "0" after register circuits 210 to 240 are used. However, the resource signal RESOURCE<0:3> can be reactivated from a deactivated state when the undo signal UNDOB<0:3> is activated to a level of "0". For example, when the resource signal RESOURCE... <2> The UNDOB signal is canceled when it is deactivated to a level of "0". <2> When activated to level "0", the resource signal RESOURCE <2> It can be activated to level "1".

[0054] Figure 4 An embodiment of the invention is shown. Figure 1 The operation of the priority selection circuit 140 shown.

[0055] refer to Figure 4 It can be seen that when several resource signals RESOURCE<0:3> are activated together, the priority selection circuit 140 activates the selection signal corresponding to the highest-numbered resource signal in descending order of the activated resource signals.

[0056] When a resource signal RESOURCE <2> When activated to level "1", the corresponding selection signal SELECTION can be observed. <2> It is activated to level "1".

[0057] When the resource signal RESOURCE <0> and RESOURCE <2> When activated at level "1", press the activated resource signal RESOURCE. <0> and RESOURCE <2> The descending order and the highest numbered resource signal RESOURCE <2> The corresponding selection signal SELECTION <2> It can be activated to level "1". Similarly, when the resource signal RESOURCE... <1> RESOURCE <2> and RESOURCE <3> When activated at level "1", press the activated resource signal RESOURCE. <1> RESOURCE <2> and RESOURCE <3> The descending order and the highest numbered resource signal RESOURCE <3> The corresponding selection signal SELECTION <3> It can be activated to level "1".

[0058] When several resource signals RESOURCE<0:3> are activated together, the priority selection circuit 140 can activate the selection signal corresponding to the highest-numbered resource signal in descending order of the activated resource signals. In other words, when register circuits 210 to 240 are redundantly used, they are preferably used in descending order for repair. As described above, when match signals MATCH_0 to MATCH_3 are redundantly activated, the row circuit 190 can activate the redundant row corresponding to the lowest-numbered match signal in ascending order of the activated match signals. Since soft repair operations are generally performed later than normal repair operations, and register circuits are also preferentially used in descending order during normal repair operations, soft repair operations can be performed preferentially when soft repair operations and normal repair operations overlap.

[0059] Figure 5 This illustrates an embodiment of the invention. Figure 1 The block diagram of the control circuit 150 shown is shown.

[0060] refer to Figure 5 The control circuit 150 may include a first circuit 510 to a fourth circuit 540. The first circuit 510 to the fourth circuit 540 may generate a lock signal LOCK<0:3> and a deactivation signal UNDOB<0:3>. The lock signal LOCK<0:3> may be a signal used to lock the corresponding register circuits 210 to 240, and the deactivation signal UNDOB<0:3> may be a signal used to deactivate the lock state of the corresponding register circuits 210 to 240.

[0061] The first circuit 510 to the fourth circuit 540 may each include inverters 511, 521, 531 and 541, NOR gates 513, 523, 533 and 543, SR latches 515, 525, 535 and 545, NOR gates 517, 527, 537 and 547, and NAND gates 519, 529, 539 and 549.

[0062] Inverters 511, 521, 531 and 541 can generate inverse matching signals MATCHB_0 to MATCHB_3 by inverting the matching signals MATCH_0 to MATCH_3.

[0063] NOR gates 513, 523, 533, and 543 can receive the soft lock signal SOFT_LOCKB and the inverse match signals MATCHB_0 to MATCHB_3. The soft lock signal SOFT_LOCKB can be a signal activated to level "0" when a lock command is present from the memory controller. The address corresponding to the lock operation can be input from the memory controller along with the lock command, and the inverse match signal can be activated to level "0" when the address matches the fault addresses FAIL_ADDRESS_0<15:0> to FAIL_ADDRESS_3<15:0> stored in register circuits 210 to 240.

[0064] When the soft lock signal SOFT_LOCKB and the inverse match signal MATCHB_0 are both activated to level "0", the lock signal LOCK can be locked through the SR latch 515. <0> Activate to level "1". Lock the signal LOCK. <0> An activation level of "1" can mean that register circuit 210 is in a locked state.

[0065] When the soft lock signal SOFT_LOCKB and the inverse match signal MATCHB_1 are both activated to level "0", the lock signal LOCK can be locked via the SR latch 525. <1> Activate to level "1". Lock the signal LOCK. <1> An activation level of "1" can mean that register circuit 220 is in a locked state.

[0066] When the soft lock signal SOFT_LOCKB and the inverse match signal MATCHB_2 are both activated to level "0", the lock signal LOCK can be locked through the SR latch 535. <2> Activate to level "1". Lock the signal LOCK. <2> An activation level of "1" can mean that register circuit 230 is in a locked state.

[0067] When the soft lock signal SOFT_LOCKB and the inverse match signal MATCHB_3 are both activated to level "0", the lock signal LOCK can be locked via the SR latch 545. <3> Activate to level "1". Lock the signal LOCK. <3> An activation level of "1" can mean that register circuit 240 is in a locked state.

[0068] The latch signal LOCK<0:3>, activated to level "1" by SR latches 515, 525, 535 and 545, can remain at level "1" until the reset signal RSTB is activated to level "0".

[0069] NOR gates 517, 527, 537, and 547 can receive the lock signal LOCK<0:3> and the soft undo signal SOFT_UNDOB and output the pre-undo signal PRE_UNDO<0:3>. The soft undo signal SOFT_UNDOB can be a signal that is activated to level "0" when an undo command is received from the memory controller. The pre-undo signal PRE_UNDO<0:3> can be a signal that is activated to level "1" when the soft undo signal SOFT_UNDOB is activated to level "0" while the lock signal LOCK<0:3> is deactivated to level "0".

[0070] NAND gates 519, 529, 539, and 549 can receive the pre-cancellation signal PRE_UNDO<0:3> and the matching signals MATCH_0 to MATCH_3 to generate the cancellation signal UNDOB<0:3>. When the pre-cancellation signal PRE_UNDO<0:3> and the matching signals MATCH_0 to MATCH_3 are simultaneously activated to level "1", the cancellation signal UNDOB<0:3> can be activated to level "0".

[0071] To summarize the operation of control circuit 150, when one of the match signals MATCH_0 to MATCH_3 is activated together with the soft lock signal SOFT_LOCKB, the lock signal in the lock signals LOCK<0:3> corresponding to the activated match signal can be activated. For example, when the soft lock signal SOFT_LOCKB and the match signal MATCH_3 are activated, the lock signal LOCK... <3> It can be activated. Furthermore, when one of the match signals MATCH_0 to MATCH_3 is activated together with the soft undo signal SOFT_UNDOB, the undo signal in the undo signals UNDOB<0:3> corresponding to the activated match signal can be activated. For example, when the soft undo signal SOFT_UNDOB and the match signal MATCH_1 are activated, the undo signal UNDOB... <1> It can be activated. However, when the lock signal LOCK<0:3> is activated, the undo signal UNDOB<0:3> may not be activated. For example, when the lock signal LOCK... <0> When activated, the UNDOB signal is deactivated. <0> It may not be activated.

[0072] Figure 6 This illustrates an embodiment of the invention. Figure 1 The block diagram of the access masking circuit 160 shown is illustrated.

[0073] refer to Figure 6 The access masking circuit 160 may include NAND gates 611 to 617 and inverter 618.

[0074] The NAND gate 611 can receive the match signal MATCH_0 and the lock signal LOCK. <0> When the lock signal LOCK <0> When activated to level "1" and the match signal MATCH_0 is activated to level "1", the output signal of NAND gate 611 can be "0". Otherwise, it can become "1". In other words, when the address ADDR<15:0>, which is the same as the fault address FAIL_ADDRESS_0<15:0> stored in register circuit 210, is transferred from the memory controller after register circuit 210 is locked, the output signal of NAND gate 611 can be "0".

[0075] The NAND gate 612 can receive the match signal MATCH_1 and the lock signal LOCK. <1> When the lock signal LOCK <1> When activated to level "1" and the match signal MATCH_1 is activated to level "1", the output signal of NAND gate 612 can be "0". Otherwise, it can become "1". In other words, when the address ADDR<15:0>, which is the same as the fault address FAIL_ADDRESS_1<15:0> stored in register circuit 220, is transferred from the memory controller after register circuit 220 is locked, the output signal of NAND gate 612 can be "0".

[0076] NAND gate 613 can receive the match signal MATCH_2 and the lock signal LOCK. <2> When the lock signal LOCK <2> When activated to level "1" and the match signal MATCH_2 is activated to level "1", the output signal of NAND gate 613 can be "0". Otherwise, it can become "1". In other words, when the address ADDR<15:0>, which is the same as the fault address FAIL_ADDRESS_2<15:0> stored in register circuit 230, is transferred from the memory controller after register circuit 230 is locked, the output signal of NAND gate 613 can be "0".

[0077] The NAND gate 614 can receive the match signal MATCH_3 and the lock signal LOCK. <3> When the lock signal LOCK <3> When activated to level "1" and the match signal MATCH_3 is activated to level "1", the output signal of NAND gate 614 can be "0". Otherwise, it can become "1". In other words, when the address ADDR<15:0>, which is the same as the fault address FAIL_ADDRESS_3<15:0> stored in register circuit 240, is transferred from the memory controller after register circuit 240 is locked, the output signal of NAND gate 614 can be "0".

[0078] NAND gate 615 can receive the outputs of NAND gates 611 to 614. When there is a "0" in the outputs of NAND gates 611 to 614, the output of NAND gate 615 can become "1", and when all the outputs of NAND gates 611 to 614 are "1", the output of NAND gate 615 can become "0".

[0079] NAND gate 616 can receive the output of NAND gate 615, the soft undo signal SOFT_UNDOB, and the soft lock signal SOFT_LOCKB to output the masking signal MASKB. Since the soft undo signal SOFT_UNDOB and the soft lock signal SOFT_LOCKB can remain at the value "1" (unless an undo or lock operation is being performed), in most cases NAND gate 616 can generate the masking signal MASKB by inverting the output of NAND gate 615.

[0080] NAND gate 617 can receive and output the soft repair signal SOFT_EN and the masking signal MASKB activated during the soft repair operation, and inverter 618 can invert the output of NAND gate 617 to output the soft masking signal SOFT_EN_MASKB. The soft masking signal SOFT_EN_MASKB can be a signal that is activated to level "0" during the soft repair operation when the masking signal MASKB is activated to level "0".

[0081] To summarize the operation of access masking circuit 160, when a new soft repair operation is to be performed on an address that is the same as the fault address in the locked registers stored in register circuits 210 to 240, access masking circuit 160 can activate the soft masking signal SOFT_EN_MASKB, which is used to prevent the new soft repair operation, to level "0". When the soft masking signal SOFT_EN_MASKB is activated to level "0", Figure 2 Signal B<0:3> can be deactivated. Therefore, no new address will be stored in register circuits 210 to 240.

[0082] Figure 7 This describes an embodiment of the present invention. Figure 1 The flowchart shows the soft repair operation of the memory 100 shown.

[0083] refer to Figure 7 In operation S701, commands for soft repair operations can be present. The soft repair operation can begin as the memory controller transmits the fault address ADDR<15:0> along with the soft repair command to memory 100. When the soft repair operation begins, the soft repair signal SOFT_EN can be activated.

[0084] In S703 operation, it can be determined whether the soft repair operation command is related to the locked fault address. When the fault address ADDR<15:0> of the current soft repair operation is... Figure 2 When the fault address stored in the locked registers of register circuits 210 to 240 shown is the same ("Yes" in operation S703), that is, when the soft masking signal SOFT_EN_MASKB is activated to level "0", the soft repair operation can be terminated immediately without performing the soft repair operation. Otherwise ("No" in operation S703), the soft repair operation can be performed.

[0085] In operating the S705, it is possible to check whether one or more register circuits are available for soft-repair operations. When Figure 3 When all resource signals RESOURCE<0:3> are deactivated, it may mean that there are no register circuits among register circuits 210 to 240 available for the soft repair operation, and therefore the soft repair operation cannot be performed. In this case, the soft repair operation can be terminated (No in operation S705).

[0086] When a single available register circuit exists ("No" in operation S707), in operation S709, that single available register circuit can be selected for the soft repair operation. For example, when only the resource signal RESOURCE in the resource signals RESOURCE<0:3>... <2> When activated, register circuit 230 can be selected as the register circuit to which a soft repair operation is to be performed.

[0087] When multiple available register circuits exist ("Yes" in operation S707), in operation S711, the priority selection circuit 140 can select the register circuit with the highest priority among the available register circuits as the register circuit for the soft repair operation. For example, when the resource signal RESOURCE... <1> and RESOURCE <3> When activated, register circuit 240 can be selected as the register circuit to which a soft repair operation is to be performed.

[0088] In operation S713, a soft repair operation can be performed, which stores the fault address ADDR<15:0> transferred from the memory controller in the register circuit selected in operation S709 or S711.

[0089] Then, in operation S715, the state of the register circuit that has already performed a soft repair operation can be changed to an unavailable state. That is, the resource signal corresponding to the register circuit that performed the soft repair operation can be deactivated from level "1" to level "0". For example, when register circuit 220 is used for a soft repair operation, the resource signal RESOURCE of register circuit 220 can be deactivated. <1> Change from level "1" to level "0".

[0090] After performing a soft repair operation, redundant lines can be used to repair the normal lines corresponding to the fault addresses stored in the register circuits where the soft repair operation was performed.

[0091] Figure 8 This describes an embodiment of the present invention. Figure 1 The flowchart shows the undo operation of the memory 100 shown.

[0092] refer to Figure 8 First, in operation S801, memory 100 can receive a cancellation command and a cancellation address transmitted from the memory controller.

[0093] In operation S803, a cancellation target can be selected from register circuits 210 to 240. The register circuit 210 to 240 that stores the fault address with the same cancellation address can be selected as the cancellation target. In the cancellation signal UNDOB<0:3>, corresponding to the... Figure 5 The register circuit of the control circuit 150 that activates the cancellation signal can be the cancellation target.

[0094] In S805 operation, the state of the deactivation target register circuit can be changed to an available state. (Reference) Figure 3 The undo signal UNDOB<0:3> can be used to control the second latches 313, 323, 333, and 343. Within the undo signal UNDOB<0:3>, the resource signal stored in the second latch corresponding to the activated undo signal can change from "0" to "1". For example, when register circuit 230 is the undo target, the resource signal RESOURCE of register circuit 230... <2> It can change from level "0" to level "1".

[0095] In S807 operation, the target register circuit can be initialized. In other words, it can be initialized via the cancel signal. Figure 2 The latch initialization of the cancellation target register circuit in latches 211, 221, 231, and 241 shown. For example, when register circuit 230 is the cancellation target, it can be initialized via the cancellation signal UNDOB. <2> Initialize latch 231 of register circuit 230.

[0096] The repair operation of the target register circuit can be canceled by the undo operation, and the target register circuit can be returned to an available state.

[0097] Figure 9 This describes an embodiment of the present invention. Figure 1 The flowchart shows the locking operation of the memory 100.

[0098] refer to Figure 9 First, in operation S901, the memory 100 can receive a lock command and a lock address transmitted from the memory controller.

[0099] In operation S903, a lock target can be selected from register circuits 210 to 240. The register circuit 210 to 240 that stores a fault address with the same lock address can be selected as the lock target. In the lock signal LOCK<0:3>, corresponding to... Figure 5 The register circuit of the control circuit 150 that activates the lock signal can be the lock target.

[0100] In operation of S905, the target register circuit can be locked. When the lock signal corresponding to the target register circuit is activated to level "1", the corresponding register circuit can be locked. After locking, it may be impossible to deactivate the corresponding register circuit, and it may also be impossible to perform a repair operation on the address that is the same as the fault address stored in the corresponding register circuit. For example, when the lock signal LOCK... <0> When activated to level "1", register circuit 210 may not be deactivated, and soft repair operations may not be performed on the same address as the fault address FAIL_ADDRESS_0<15:0> stored in register circuit 210.

[0101] According to embodiments of the present invention, the register circuit to be used for the soft repair operation can be effectively selected from a plurality of available register circuits. Furthermore, the target register circuit for cancellation and the target register circuit for locking can be effectively selected during cancellation and locking operations.

[0102] According to embodiments of the present invention, repair resources within the memory can be effectively allocated and managed.

[0103] The effects desired in the various embodiments of the present invention are not limited to those described above, and those skilled in the art to which this invention pertains can clearly understand from the above description other effects not described above.

[0104] While the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A memory, comprising: The first register circuit to the Nth register circuit, each of the first register circuit to the Nth register circuit is adapted to: receive and store a fault address transmitted from the memory controller when the corresponding selection signal among the first selection signal to the Nth selection signal is activated, where N is an integer equal to or greater than 2; The first resource latch circuit to the Nth resource latch circuit are adapted to store the first resource signal to the Nth resource signal, respectively, indicating the availability of the first register circuit to the Nth register circuit; as well as A priority selection circuit is adapted to: when two or more of the first to Nth resource signals are activated, activate the higher priority selection signal among the selection signals of the first to Nth selection signals that correspond to the activated resource signals. The high-priority selection signal activates the high-priority register circuits in the first register circuit to the Nth register circuit.

2. The memory according to claim 1, further comprising: A control circuit adapted to activate a resource signal corresponding to a register circuit in the first to the Nth register circuits that stores a fault address that is transmitted from the memory controller along with a cancellation command.

3. The memory according to claim 2, wherein, The register circuit storing the same fault address is also adapted to initialize the fault address stored in the register circuit.

4. The memory according to claim 2, wherein, The control circuit is further adapted to: set the register circuits in the first register circuit to the Nth register circuit that store the same fault address as the address transmitted from the memory controller together with the lock command to a locked state, in which the cancellation operation cannot be performed.

5. The memory according to claim 4, further comprising: Access masking circuitry, the access masking circuitry being adapted to control register circuitry storing the same fault address as the address transmitted along with the lock command in such a manner that additional soft-repair operations cannot be performed on the address transmitted along with the lock command.

6. The memory according to claim 1, further comprising: An address comparison circuit is adapted to generate a first matching signal to an Nth matching signal by comparing a fault address stored in the first register circuit to the Nth register circuit with an address transmitted from the memory controller. as well as Linear circuits are suitable for: When all of the first to Nth matching signals are deactivated, one of the multiple normal rows is activated by decoding the address transmitted from the memory controller. When one of the first matching signal to the Nth matching signal is activated, the redundant row corresponding to the activated matching signal among the first redundant row to the Nth redundant row is activated.

7. The memory according to claim 6, in, The priority selection circuit activates the selection signal corresponding to the resource signal selected in descending order among the activated resource signals, and When two or more of the first to the Nth matching signals are activated, the row circuit activates a redundant row corresponding to the matching signal selected in ascending order among the activated matching signals.

8. The memory according to claim 1 further includes a non-volatile storage circuit. in, Each of the first register circuit to the Nth register circuit is further adapted to receive and store the fault address transmitted from the non-volatile memory circuit when the corresponding start pulse in the first start pulse to the Nth start pulse is activated.

9. The memory according to claim 1, wherein, Each of the first resource signal to the Nth resource signal is deactivated when the corresponding register circuit in the first register circuit to the Nth register circuit is defective or used for repair operations; otherwise, it is activated.

10. A method for operating a memory, comprising: Enter soft repair mode; Search for available register circuits among the first to Nth register circuits included in the memory, where N is an integer equal to or greater than 2; A high-priority register circuit is selected from the available register circuits by a high-priority selection signal, wherein the high-priority selection signal activates the first register circuit to the Nth register circuit with the highest priority. as well as The fault address transmitted from the memory controller is stored in the selected register circuit.

11. The method of claim 10, further comprising: Set the selected register circuit to an unavailable state.

12. The method of claim 10, further comprising: Receive the undo command and undo address transmitted from the memory controller; The register circuit storing the fault address that is the same as the cancellation address among the first register circuit to the Nth register circuit is selected as the cancellation target register circuit; and Set the cancel target register circuit to an available state.

13. The method of claim 12, further comprising: The fault address stored in the cancellation target register circuit is initialized.

14. The method of claim 10, further comprising: Receive the lock command and lock address transmitted from the memory controller; The register circuits storing fault addresses that are the same as the locked address among the first register circuit to the Nth register circuit are selected as the target register circuits for locking; and Set the target register locking circuit to a locked state.

15. The method according to claim 14, wherein, The locked state is a state in which the undo operation cannot be performed.

16. The method of claim 14, wherein, The locked target register circuit, which is in the locked state, is in a writable state for soft repair.

17. The method of claim 10, further comprising: After the fault address transmitted from the memory controller is stored in the selected register circuit, In response to a lock command accompanying the fault address subsequently provided from the memory controller, the selected register circuitry is prohibited from storing subsequent data for further soft repair.

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