Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application relates to a semiconductor structure preparation method and a semiconductor structure. The semiconductor structure preparation method comprises the following steps: providing a substrate, a plurality of shallow trench isolation structures are formed in the substrate and at least partially exposed to the substrate, and an initial liner oxide layer is formed on the upper surface of the substrate between two adjacent shallow trench isolation structures; performing thinning treatment on the initial liner oxide layer to obtain a liner oxide layer; performing thermal oxidation treatment on the substrate to form an initial sacrifice layer in the substrate, and the initial sacrifice layer is formed on the lower surface of the liner oxide layer; removing the liner oxide layer and performing thinning treatment on the initial sacrifice layer to obtain a sacrifice layer; performing thermal oxidation treatment on the substrate to form a gate oxide layer in the substrate, and the gate oxide layer is formed on the lower surface of the sacrifice layer; and removing the sacrifice layer. The semiconductor structure preparation method provided by the application can prevent the formation of pits in the semiconductor structure, can avoid the pits from causing the device to open in advance under pressure, and can help improve the electrical performance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a preparation method of a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] With the continuous improvement of semiconductor process technology, the size of the device is also continuously reduced. In order to adapt to the reduction of the size of the device, STI (Shallow Trench Isolation) technology has been widely concerned.

[0003] In the production process of a semiconductor device, after forming a shallow trench isolation structure, the surface pad oxide layer of the substrate needs to be removed. During the process of removing the pad oxide layer, a pit will be generated at the upper surface edge region of the junction between the shallow trench isolation structure and the substrate, and the pit will be deepened and widened when the sacrificial layer is removed subsequently. SUMMARY

[0004] Therefore, it is necessary to provide a preparation method of a semiconductor structure and the semiconductor structure to solve the problem of the pit generated in the shallow trench isolation structure.

[0005] To achieve the above-mentioned purpose, on one hand, the present application provides a preparation method of a semiconductor structure, comprising:

[0006] providing a substrate, a plurality of shallow trench isolation structures at least partially exposed to the substrate are formed in the substrate, and an initial pad oxide layer is formed on the upper surface of the substrate between two adjacent shallow trench isolation structures;

[0007] thinning the initial pad oxide layer to obtain a pad oxide layer;

[0008] performing a thermal oxidation process on the substrate to form an initial sacrificial layer in the substrate, the initial sacrificial layer being formed on the lower surface of the pad oxide layer;

[0009] removing the pad oxide layer and thinning the initial sacrificial layer to obtain a sacrificial layer;

[0010] performing a thermal oxidation process on the substrate to form a gate oxide layer in the substrate, the gate oxide layer being formed on the lower surface of the sacrificial layer;

[0011] removing the sacrificial layer.

[0012] The method for manufacturing the semiconductor structure of the present application forms an initial liner oxide layer on the upper surface of the substrate between adjacent shallow trench isolation structures. When the initial liner oxide layer is removed, the initial liner oxide layer is not removed all at once, but is thinned, and part of the thickness of the liner oxide layer is retained, so that initial pits are not formed in the edge region of the upper surface at the junction of the shallow trench isolation structure and the substrate. The substrate is subjected to thermal oxidation to form an initial sacrificial layer in the substrate. The initial sacrificial layer is formed on the lower surface of the liner oxide layer. When the initial sacrificial layer is removed, the initial sacrificial layer is not removed all at once, but is thinned, and part of the thickness of the liner oxide layer is retained. After the substrate is subjected to thermal oxidation to form a gate oxide layer in the substrate, the remaining sacrificial layer above the gate oxide layer is removed, so that the initial pits are not deepened and widened when the sacrificial layer is removed. A semiconductor structure without pits is obtained. This can avoid the phenomenon of double peaks in the curve of the gate voltage-drain current of the device caused by the pits causing the device to open prematurely when pressure is applied, and can improve the electrical performance of the device.

[0013] In one of the embodiments, the thinning of the initial liner oxide layer comprises:

[0014] The partial initial liner oxide layer is removed by a wet etching process, wherein the concentration of the etching solution of the wet etching process is 0.4% to 0.6%.

[0015] In one of the embodiments, the thickness of the liner oxide layer is

[0016] In one of the embodiments, during the thermal oxidation of the substrate to form an initial sacrificial layer in the substrate, the temperature of the thermal oxidation is 915°C to 925°C, and the time of the thermal oxidation is 10 minutes to 12 minutes.

[0017] In one of the embodiments, the removal of the liner oxide layer and the thinning of the initial sacrificial layer to obtain a sacrificial layer comprises:

[0018] The liner oxide layer is removed.

[0019] The substrate is subjected to ion implantation to form a lightly doped region in the substrate.

[0020] The initial sacrificial layer is thinned to obtain the sacrificial layer.

[0021] In one of the embodiments, the removal of the liner oxide layer comprises:

[0022] The liner oxide layer is removed by a wet etching process, wherein the concentration of the etching solution of the wet etching process is 0.4% to 0.6%.

[0023] In one of the embodiments, the thinning process of the initial sacrificial layer comprises:

[0024] The partial initial sacrificial layer is removed by using a wet etching process, wherein the solubility of the etching solution of the wet etching process is 0.4% to 0.6%.

[0025] In one of the embodiments, the thickness of the sacrificial layer is

[0026] In one of the embodiments, during the process of the thermal oxidation of the substrate to form the gate oxide layer, the temperature of the thermal oxidation is 895℃ to 905℃, and the time of the thermal oxidation is 18 minutes to 22 minutes.

[0027] The application also provides a semiconductor structure prepared by using the preparation method of the semiconductor structure according to any one of the above-mentioned embodiments.

[0028] The semiconductor structure of the application is prepared by using the preparation method of the semiconductor structure of the application; wherein the upper surface of the substrate between the adjacent shallow trench isolation structures is formed with an initial liner oxide layer, when the initial liner oxide layer is removed, the initial liner oxide layer is not removed all at once, but is subjected to a thinning process, and the partial thickness of the liner oxide layer is reserved, so that the initial pits at the upper surface edge region of the junction of the shallow trench isolation structure and the substrate are avoided, the initial sacrificial layer is formed in the substrate by the thermal oxidation of the substrate, the initial sacrificial layer is formed on the lower surface of the liner oxide layer, when the initial sacrificial layer is removed, the initial sacrificial layer is not removed all at once, but is subjected to a thinning process, and the partial thickness of the liner oxide layer is reserved, after the thermal oxidation of the substrate to form the gate oxide layer in the substrate, the remaining sacrificial layer above the gate oxide layer is removed, so that the initial pits are not deepened and widened when the sacrificial layer is removed, and the semiconductor structure without the pits is obtained; in this way, the pits can be avoided to cause the device to open early when pressurized, and the double-peak effect phenomenon of the gate voltage-drain current curve of the device can be avoided, and the electrical performance of the device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0030] Figure 1A cross-sectional structure schematic diagram of a conventional semiconductor device;

[0031] Figure 2 A flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0032] Figure 3 A cross-sectional structure schematic diagram of a structure obtained in step S101 of a method for preparing a semiconductor structure provided in an embodiment;

[0033] Figure 4 A cross-sectional structure schematic diagram of a structure obtained in step S102 of a method for preparing a semiconductor structure provided in an embodiment;

[0034] Figure 5 A cross-sectional structure schematic diagram of a structure obtained in step S103 of a method for preparing a semiconductor structure provided in an embodiment;

[0035] Figure 6 A step flow chart of step S104 of a method for preparing a semiconductor structure provided in an embodiment;

[0036] Figure 7 A cross-sectional structure schematic diagram of a structure obtained in step S1041 of a method for preparing a semiconductor structure provided in an embodiment;

[0037] Figure 8 A cross-sectional structure schematic diagram of a structure obtained in step S1042 of a method for preparing a semiconductor structure provided in an embodiment;

[0038] Figure 9 A cross-sectional structure schematic diagram of a structure obtained in step S1043 of a method for preparing a semiconductor structure provided in an embodiment;

[0039] Figure 10 A cross-sectional structure schematic diagram of a structure obtained in step S105 of a method for preparing a semiconductor structure provided in an embodiment;

[0040] Figure 11 A cross-sectional structure schematic diagram of a structure obtained in step S106 of a method for preparing a semiconductor structure provided in an embodiment.

[0041] BRIEF DESCRIPTION OF THE DRAWINGS

[0042] 1 - substrate; 2 - liner oxide layer; 21 - initial liner oxide layer; 3 - shallow trench isolation structure; 4 - sacrificial layer; 41 - initial sacrificial layer; 5 - gate oxide layer. DETAILED DESCRIPTION

[0043] For the purposes of this application, a more complete description of the application will be presented with reference to the associated drawings. The drawings provided herein are intended to explain the best implementation of the application. However, the application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the application is more thorough and complete.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0045] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

[0046] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the included spatial description terminology is interpreted accordingly.

[0047] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0048] With the continuous improvement of semiconductor process technology, the size of devices is also shrinking. To adapt to the shrinking device size, STI (Shallow Trench Isolation) technology has attracted widespread attention.

[0049] like Figure 1 As shown, in the conventional semiconductor device manufacturing process, after forming the shallow trench isolation structure, the pad oxide layer on the substrate surface needs to be removed. During the removal of the pad oxide layer, the etching solution inevitably comes into contact with both the substrate and the pad oxide layer. Due to the different etching selectivity of the etching solution for the substrate and the pad oxide layer, pits 31 are generated in the upper surface edge region at the junction of the shallow trench isolation structure and the substrate during the removal of the pad oxide layer. When the sacrificial layer is removed subsequently, the etching solution inevitably comes into contact with both the substrate and the sacrificial layer. Due to the different etching selectivity of the etching solution for the substrate and the sacrificial layer, the pits 31 are deepened and widened. The pits 31 cause the device to turn on prematurely at the edge of the active region, forming a double-hump effect, which affects the yield and reliability of the device and limits the application range of the device.

[0050] Therefore, it is necessary to provide a method for fabricating a semiconductor structure and a semiconductor structure to address the problem of pits generated in the aforementioned shallow trench isolation structure.

[0051] To solve the above problems, such as Figure 2 As shown, this application provides a method for fabricating a semiconductor structure, comprising:

[0052] S101: Provide a substrate, wherein a plurality of shallow trench isolation structures at least partially exposed in the substrate are formed therein, and an initial pad oxide layer is formed on the upper surface of the substrate between two adjacent shallow trench isolation structures.

[0053] S102: Thin the initial gasket oxide layer to obtain the gasket oxide layer;

[0054] S103: The substrate is subjected to thermal oxidation treatment to form an initial sacrificial layer in the substrate, the initial sacrificial layer being formed on the lower surface of the pad oxide layer;

[0055] S104: removing the liner oxide layer and thinning the initial sacrificial layer to obtain a sacrificial layer;

[0056] S105: performing thermal oxidation treatment on the substrate to form a gate oxide layer in the substrate, the gate oxide layer being formed on the lower surface of the sacrificial layer;

[0057] S106: removing the sacrificial layer.

[0058] The semiconductor structure obtained after steps S101-S106 can refer to Figure 11 . Of course, in order to facilitate the understanding of the present application, Figure 11 a kind of example of the semiconductor structure prepared by the preparation method of the semiconductor structure of the present application is given, the semiconductor structure prepared by the preparation method of the semiconductor structure of the present application can also have other suitable examples, and the present application does not limit this.

[0059] The preparation method of the semiconductor structure in the above embodiment forms an initial liner oxide layer on the upper surface of the substrate between adjacent shallow trench isolation structures, and when the initial liner oxide layer is removed, not all of the initial liner oxide layer is removed at one time, but the initial liner oxide layer is thinned to retain a part of the thickness of the liner oxide layer, thereby avoiding the formation of initial pits in the upper surface edge region of the shallow trench isolation structure and the substrate. By performing thermal oxidation treatment on the substrate to form an initial sacrificial layer in the substrate, the initial sacrificial layer is formed on the lower surface of the liner oxide layer. When the initial sacrificial layer is removed, not all of the initial sacrificial layer is removed at one time, but the initial sacrificial layer is thinned to retain a part of the thickness of the liner oxide layer. After performing thermal oxidation treatment on the substrate to form a gate oxide layer in the substrate, the remaining sacrificial layer above the gate oxide layer is removed, thereby avoiding deepening and widening of the initial pits when the sacrificial layer is removed, to obtain a semiconductor structure without pit formation. In this way, the pits can be avoided to cause the device to open prematurely under pressure, thereby causing the gate voltage-drain current curve of the device to produce a double-peak effect phenomenon, and the electrical performance of the device can be improved.

[0060] In step S101, the substrate 1 can be provided by referring to Figure 3 , the substrate 1 is formed with a plurality of shallow trench isolation structures 3 at least partially exposed on the substrate 1, and the upper surface of the substrate 1 between two adjacent shallow trench isolation structures 3 is formed with an initial liner oxide layer 21.

[0061] The substrate 1 can include but is not limited to a silicon substrate or a silicon carbide substrate, and can also be other materials, not limited by the above examples; the initial liner oxide layer 21 can be but is not limited to an oxide layer; further, the oxide layer can be but is not limited to a silicon oxide layer.

[0062] For example, a thermal oxidation process can be used to oxidize the upper surface of the substrate 1 to form an initial pad oxide layer 21 on the upper surface of the substrate 1.

[0063] For example, the thickness of the initial liner oxide layer 21 can be Specifically, the thickness of the initial liner oxide layer 21 can be or It could also be located in other places. The thickness between them is not limited by the examples above.

[0064] In other embodiments, the thickness of the initial pad oxide layer 21 can be adaptively adjusted according to the device type and requirements, and is not limited to the thickness range of the initial pad oxide layer 21 exemplified above.

[0065] In step S102, please refer to Figure 4 The initial liner oxide layer 21 is thinned to obtain the liner oxide layer 2.

[0066] The pad oxide layer 2 can be, but is not limited to, an oxide layer; further, the oxide layer can be, but is not limited to, a silicon oxide layer.

[0067] In one embodiment, thinning the initial pad oxide layer 21 may include removing a portion of the initial pad oxide layer 21 using a wet etching process, wherein the concentration of the etching solution in the wet etching process may be 0.4% to 0.6%.

[0068] For example, a wet etching process is used to remove part of the initial pad oxide layer 21. The concentration of the etching solution used can be 0.4%, 0.45%, 0.49%, 0.5%, 0.55%, 0.58%, or 0.6%, or other concentrations between 0.4% and 0.6%, not limited to the above examples.

[0069] Furthermore, an etching solution with a concentration of 40% to 60% can be prepared by mixing it with clean water at a volume ratio of 1:100 to obtain an etching solution with a concentration of 0.4% to 0.6%.

[0070] In other embodiments, a wet etching process is used to remove part of the initial pad oxide layer 21. The concentration of the etching solution used can be adaptively adjusted according to the thickness of the initial pad oxide layer 21 and the required corrosion rate, and is not limited to the etching solution concentration range exemplified above.

[0071] In one embodiment, a wet etching process is used to remove part of the initial pad oxide layer 21, and the etching rate used can be [missing information].

[0072] For example, the wet etching process is used to remove part of the initial liner oxide layer 21, and the etching rate can be or and other etching rates located between 0.1 and 1.0 are also possible, which are not limited by the above examples.

[0073] In other embodiments, the wet etching process is used to remove part of the initial liner oxide layer 21, and the etching rate can be adjusted according to the thickness of the initial liner oxide layer 21 and the type of etching solution, which is not limited by the above-mentioned etching rate range.

[0074] In one embodiment, the wet etching process is used to remove part of the initial liner oxide layer 21, and the etching solution can be but not limited to hydrofluoric acid solution; wherein, the appropriate etching solution can be selected according to the thickness of the initial liner oxide layer 21 and the required etching rate, and this embodiment is not limited.

[0075] In one embodiment, the thickness of the liner oxide layer 2 can be

[0076] For example, the thickness of the liner oxide layer 2 can be or and other thicknesses located between 0.1 and 1.0 are also possible, which are not limited by the above examples.

[0077] In other embodiments, the thickness of the liner oxide layer 2 can be adjusted according to the type and demand of the device, which is not limited by the above-mentioned thickness range of the liner oxide layer 2.

[0078] In step S103, the substrate 1 can be subjected to Figure 5 thermal oxidation treatment to form an initial sacrificial layer 41 in the substrate 1, and the initial sacrificial layer 41 is formed on the lower surface of the liner oxide layer 2.

[0079] The initial sacrificial layer 41 can be but not limited to an oxide layer; further, the oxide layer can be but not limited to a silicon oxide layer.

[0080] For example, the thickness of the initial sacrificial layer 41 can be Specifically, the thickness of the initial sacrificial layer 41 can be or and other thicknesses located between 0.1 and 1.0 are also possible, which are not limited by the above examples.

[0081] ​​​In one embodiment, the thermal oxidation temperature for forming the initial sacrificial layer 41 in the substrate 1 can be 915-925 °C, and the thermal oxidation time can be 10-12 minutes.

[0082] For example, the thermal oxidation temperature for forming the initial sacrificial layer 41 in the substrate 1 can be 915 °C, 918 °C, 920 °C, 922 °C or 925 °C, or other temperature within the range of 915-925 °C, which is not limited to the above examples; for example, the thermal oxidation time can be 10 minutes, 11 minutes or 12 minutes, or other time, which needs to be noted that the thermal oxidation time is set according to the required thickness of the initial sacrificial layer 41 and the thermal oxidation temperature, and in this embodiment, it is only for better understanding of the scheme, and is not used to limit the thermal oxidation time.

[0083] In other embodiments, the thermal oxidation temperature and the thermal oxidation time can be adjusted according to the thickness requirement of the initial sacrificial layer 41, which is not limited to the above-mentioned thermal oxidation temperature range.

[0084] In one embodiment, the substrate 1 can be subjected to an in-situ steam generation (ISSG) process to form the initial sacrificial layer 41 in the substrate 1.

[0085] In step S104, the liner oxide layer 2 can be removed, and the initial sacrificial layer 41 can be thinned to obtain the sacrificial layer 4. Figure 6 to Figure 9

[0086] The sacrificial layer 4 can be, but is not limited to, an oxide layer; further, the oxide layer can be, but is not limited to, a silicon oxide layer.

[0087] In one embodiment, as shown in Figure 6 , the liner oxide layer 2 can be removed, and the initial sacrificial layer 41 can be thinned to obtain the sacrificial layer 4, including:

[0088] S1041: removing the liner oxide layer 2; the resulting structure is shown in Figure 7

[0089] S1042: ion implantation is performed on the substrate 1 to form a lightly doped region (not shown in the figure); the resulting structure is shown in Figure 8

[0090] S1043: the initial sacrificial layer 41 is thinned to obtain the sacrificial layer 4; the resulting structure is shown in Figure 9 ​​​​

[0091] In one embodiment, the removing the pad oxide layer 2 can include: removing the pad oxide layer 2 by using a wet etching process, wherein a concentration of an etching solution of the wet etching process is 0.4% to 0.6%.

[0092] For example, the pad oxide layer 2 is removed by using the wet etching process, and a concentration of the etching solution used can be 0.4%, 0.45%, 0.49%, 0.5%, 0.55%, 0.58% or 0.6%, or other concentrations between 0.4% and 0.6%, which are not limited by the above examples.

[0093] Further, the etching solution with a concentration of 0.4% to 0.6% can be prepared by mixing an etching stock solution with a concentration of 40% to 60% and clean water at a volume ratio of 1:100.

[0094] In other embodiments, the pad oxide layer 2 is removed by using the wet etching process, and a concentration of the etching solution used can be adjusted according to a thickness of the pad oxide layer 2 and a required etching rate, which is not limited by the above examples of the concentration range of the etching solution.

[0095] In the above embodiments, the pad oxide layer 2 is removed after the initial sacrificial layer 41 is formed. Since the pad oxide layer 2 is located on the upper surface of the initial sacrificial layer 41, the etching solution is not in contact with the substrate 1 during the etching process for removing the pad oxide layer 2, so that no pits are generated in the edge region of the upper surface of the substrate 1 at the junction of the shallow trench isolation structure 3 and the substrate 1.

[0096] In one embodiment, the pad oxide layer 2 is removed by using the wet etching process, and a concentration of the etching solution used can be but not limited to a hydrofluoric acid solution; wherein a suitable etching solution can be selected at will according to the thickness of the pad oxide layer 2 and the required etching rate, which is not limited in the present embodiment.

[0097] In one embodiment, the shallow trench isolation structure 3 isolates a plurality of active regions arranged at intervals in the substrate 1, and the active regions are located between adjacent shallow trench isolation structures 3.

[0098] In one embodiment, the ion implantation is performed on the substrate 1 to form a lightly doped region in the substrate 1, which can include: performing boron ion or nitrogen ion implantation on the substrate 1 to form a lightly doped region in the active region of the substrate 1.

[0099] It should be noted that the type of ion implantation can be set correspondingly according to the type of device (such as N-type or P-type device), which is not limited in the present embodiment.

[0100] In one embodiment, thinning the initial sacrificial layer 41 may include removing a portion of the initial sacrificial layer 41 using a wet etching process, wherein the concentration of the etching solution in the wet etching process is 0.4% to 0.6%.

[0101] For example, a wet etching process is used to remove part of the initial sacrificial layer 41. The concentration of the etching solution used can be 0.4%, 0.45%, 0.49%, 0.5%, 0.55%, 0.58%, or 0.6%, or other concentrations between 0.4% and 0.6%, without being limited to the above examples.

[0102] Furthermore, an etching solution with a concentration of 40% to 60% can be prepared by mixing it with clean water at a volume ratio of 1:100 to obtain an etching solution with a concentration of 0.4% to 0.6%.

[0103] In other embodiments, a wet etching process is used to remove part of the initial sacrificial layer 41. The concentration of the etching solution used can be adaptively adjusted according to the thickness of the initial sacrificial layer 41 and the required corrosion rate, and is not limited to the etching solution concentration range exemplified above.

[0104] In one embodiment, a wet etching process is used to remove part of the initial sacrificial layer 41. The concentration of the etching solution used can be, but is not limited to, hydrofluoric acid solution. The etching solution can be selected arbitrarily according to the thickness of the initial sacrificial layer 41 and the required etching rate. This embodiment does not impose any restrictions.

[0105] In one embodiment, the thickness of the sacrificial layer 4 is

[0106] For example, the thickness of the sacrificial layer 4 can be or It could also be located in other places. The thickness between them is not limited by the examples above.

[0107] In other embodiments, the thickness of the sacrificial layer 4 can be adaptively adjusted according to the type of device and requirements, and is not limited to the thickness range of the sacrificial layer 4 exemplified above.

[0108] In step S105, please refer to Figure 10 The substrate 1 is subjected to thermal oxidation to form a gate oxide layer 5 in the substrate 1. The gate oxide layer 5 is formed on the lower surface of the sacrificial layer 4.

[0109] The gate oxide layer 5 can be, but is not limited to, an oxide layer; further, the oxide layer can be, but is not limited to, a silicon oxide layer.

[0110] For example, the thickness of the gate oxide layer 5 can be Specifically, the thickness of the gate oxide layer 5 can be or and other thicknesses between 5 nm and 10 nm, not limited by the above examples.

[0111] In one embodiment, the substrate 1 is subjected to a thermal oxidation process to form the gate oxide layer 5 in the substrate 1, the thermal oxidation temperature is 895℃-905℃, and the thermal oxidation time is 18-22 minutes.

[0112] For example, the substrate 1 is subjected to a thermal oxidation process to form the gate oxide layer 5 in the substrate 1, the thermal oxidation temperature can be 895℃, 898℃, 900℃, 902℃ or 905℃, and other thermal oxidation temperatures between 895℃ and 905℃, not limited by the above examples; for example, the thermal oxidation time can be 18 minutes, 19 minutes, 20 minutes, 21 minutes or 22 minutes, and other oxidation times, it should be noted that the thermal oxidation time is set according to the required thickness of the gate oxide layer 5 and the thermal oxidation temperature, and in this embodiment, it is only for better understanding of the scheme, and is not used to limit the thermal oxidation time.

[0113] In other embodiments, the thermal oxidation temperature and the thermal oxidation time can be adjusted according to the thickness requirement of the gate oxide layer 5, not limited by the above examples of the thermal oxidation temperature range.

[0114] In one embodiment, the substrate 1 can be subjected to a thermal oxidation process by using an in-situ steam generation (ISSG) process to form the gate oxide layer 5 in the substrate 1.

[0115] In step S106, the sacrificial layer 4 can be removed by referring to Figure 11

[0116] In the above embodiment, the sacrificial layer 4 is removed after the formation of the gate oxide layer 5, because the sacrificial layer 4 is located on the upper surface of the gate oxide layer 5, so during the etching process of removing the sacrificial layer 4, the etching liquid is always not in contact with the substrate 1, which will not cause the upper surface edge area of the shallow trench isolation structure 3 and the substrate 1 to be concave.

[0117] ​​It should be understood that although the steps in the flowcharts of the embodiments are shown in a sequential order following the arrows, the steps are not necessarily executed in the order shown by the arrows. Unless otherwise specified herein, the execution of the steps is not necessarily limited to the order shown, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution of the steps or stages is not necessarily sequential, but can be round-robin or alternately executed with other steps or steps or stages in other steps.

[0118] The application also provides a semiconductor structure prepared by the method.

[0119] As shown in Figure 11 , the semiconductor structure includes a substrate 1, a shallow trench isolation structure 3, and a gate oxide layer 5, wherein the upper surface edge region of the shallow trench isolation structure 3 at the junction with the substrate 1 has no pits.

[0120] The substrate 1 can include but is not limited to a silicon substrate or a silicon carbide substrate, and can also be other materials, not limited by the above examples.

[0121] For example, the thickness of the gate oxide layer 5 can be For example, the thickness of the gate oxide layer 5 can be or or other thicknesses between , not limited by the above examples.

[0122] The semiconductor structure of the present application is prepared by the preparation method of the semiconductor structure of the present application; wherein the initial liner oxide layer 21 is formed on the upper surface of the substrate 1 between the adjacent shallow trench isolation structures 3, when the initial liner oxide layer 21 is removed, all the initial liner oxide layer 21 is not removed at one time, but the initial liner oxide layer 21 is thinned, and the liner oxide layer 2 with a partial thickness is reserved, so that the initial pit is avoided to be generated at the upper surface edge region of the junction of the shallow trench isolation structure 3 and the substrate 1, the substrate 1 is subjected to thermal oxidation treatment to form the initial sacrifice layer 41 in the substrate 1, the initial sacrifice layer 41 is formed on the lower surface of the liner oxide layer 2, when the initial sacrifice layer 41 is removed, all the initial sacrifice layer 41 is not removed at one time, but the initial sacrifice layer 41 is thinned, and the liner oxide layer 2 with a partial thickness is reserved, after the substrate 1 is subjected to thermal oxidation treatment to form the gate oxide layer 5 in the substrate 1, the remaining sacrifice layer 4 above the gate oxide layer 5 is removed, so that the initial pit is avoided to be deepened and widened when the sacrifice layer 4 is removed, and the semiconductor structure without pit formation is obtained; in this way, the pit can be avoided to make the device open in advance when pressurized, so that the double-peak effect phenomenon of the curve of the gate voltage-drain current of the device is avoided, and the electrical performance of the device can be improved.

[0123] The technical features of the above-described embodiments can be combined in any manner, and to make the description concise, all possible combinations of the technical features of the above-described embodiments are not described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0124] The above-described embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as the limitation of the patent application scope. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The application relates to a semiconductor structure and a preparation method thereof. The application provides a substrate, a plurality of shallow trench isolation structures are formed in the substrate, the upper surface of the substrate between two adjacent shallow trench isolation structures is provided with an initial liner oxide layer; The thickness of the initial liner oxide layer is 100-120 angstroms; The initial liner oxide layer is thinned to obtain a liner oxide layer; the thickness of the liner oxide layer is 4-20 angstroms; The substrate is subjected to a thermal oxidation treatment to form an initial sacrifice layer in the substrate, the initial sacrifice layer is formed on the lower surface of the liner oxide layer; the thickness of the initial sacrifice layer is 100-120 angstroms; The liner oxide layer is removed, and the initial sacrifice layer is thinned to obtain a sacrifice layer; the thickness of the sacrifice layer is 4-20 angstroms; The substrate is subjected to a thermal oxidation treatment to form a gate oxide layer in the substrate, the gate oxide layer is formed on the lower surface of the sacrifice layer; The sacrifice layer is removed.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The thinning of the initial liner oxide layer comprises the following steps: Part of the initial liner oxide layer is removed by using a wet etching process, wherein the concentration of the etching solution of the wet etching process is 0.4%-0.6%.

3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: During the thermal oxidation treatment of the substrate to form the initial sacrifice layer in the substrate, the temperature of the thermal oxidation is 915-925 DEG C, and the time of the thermal oxidation is 10-12 minutes.

4. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The removal of the liner oxide layer and the thinning of the initial sacrifice layer to obtain the sacrifice layer comprise the following steps: The liner oxide layer is removed; The substrate is subjected to ion implantation to form a lightly doped region in the substrate; The initial sacrifice layer is thinned to obtain the sacrifice layer.

5. The method of claim 4, wherein the semiconductor structure is prepared by a method comprising: The removal of the liner oxide layer comprises the following steps: The liner oxide layer is removed by using a wet etching process, wherein the concentration of the etching solution of the wet etching process is 0.4%-0.6%.

6. The method of claim 4, wherein the step of forming the semiconductor structure is performed by a method comprising: The thinning of the initial sacrifice layer comprises the following steps: Part of the initial sacrifice layer is removed by using a wet etching process, wherein the concentration of the etching solution of the wet etching process is 0.4%-0.6%.

7. The method of claim 1, wherein the semiconductor structure is formed by a method comprising: During the thermal oxidation treatment of the substrate to form the gate oxide layer in the substrate, the temperature of the thermal oxidation is 895-905 DEG C, and the time of the thermal oxidation is 18-22 minutes.

8. A semiconductor structure, characterized by The application further provides a semiconductor structure prepared by using the preparation method of the semiconductor structure. The application relates to a semiconductor structure and a preparation method thereof. The application provides a substrate, a plurality of shallow trench isolation structures are formed in the substrate, the upper surface of the substrate between two adjacent shallow trench isolation structures is provided with an initial liner oxide layer; The thickness of the initial liner oxide layer is 100-120 angstroms; The initial liner oxide layer is thinned to obtain a liner oxide layer; the thickness of the liner oxide layer is 4-20 angstroms; The substrate is subjected to a thermal oxidation treatment to form an initial sacrifice layer in the substrate, the initial sacrifice layer is formed on the lower surface of the liner oxide layer; the thickness of the initial sacrifice layer is 100-120 angstroms; The liner oxide layer is removed, and the initial sacrifice layer is thinned to obtain a sacrifice layer; the thickness of the sacrifice layer is 4-20 angstroms; The substrate is subjected to a thermal oxidation treatment to form a gate oxide layer in the substrate, the gate oxide layer is formed on the lower surface of the sacrifice layer; The sacrifice layer is removed. The thinning of the initial liner oxide layer comprises the following steps: Part of the initial liner oxide layer is removed by using a wet etching process, wherein the concentration of the etching solution of the wet etching process is 0.4%-0.6%. During the thermal oxidation treatment of the substrate to form the initial sacrifice layer in the substrate, the temperature of the thermal oxidation is 915-925 DEG C, and the time of the thermal oxidation is 10-12 minutes. The removal of the liner oxide layer and the thinning of the initial sacrifice layer to obtain the sacrifice layer comprise the following steps: The liner oxide layer is removed; The substrate is subjected to ion implantation to form a lightly doped region in the substrate; The initial sacrifice layer is thinned to obtain the sacrifice layer. The removal of the liner oxide layer comprises the following steps: The liner oxide layer is removed by using a wet etching process, wherein the concentration of the etching solution of the wet etching process is 0.4%-0.6%. The thinning of the initial sacrifice layer comprises the following steps: Part of the initial sacrifice layer is removed by using a wet etching process, wherein the concentration of the etching solution of the wet etching process is 0.4%-0.6%. During the thermal oxidation treatment of the substrate to form the gate oxide layer in the substrate, the temperature of the thermal oxidation is 895-905 DEG C, and the time of the thermal oxidation is 18-22 minutes. The application further provides a semiconductor structure prepared by using the preparation method of the semiconductor structure.

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