Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate including a device region and an isolation region, the isolation region having a modified layer; patterning the substrate to form a base, a plurality of device fins and a plurality of modified fins located on the base; forming a first isolation material layer on the base, the first isolation material layer covering the device fins and exposing the modified fins; and removing the modified fins. By forming the modified layer, a large etching selectivity ratio is achieved between the modified fins formed by the modified layer and the isolation region, thereby ensuring that the modified fins on each isolation region are completely removed with minimal damage to the substrate, reducing the problem of short circuits between transistors. Furthermore, when the first isolation material layer is formed, the modified fins are not yet removed, and the distribution of the device fins and modified fins is relatively uniform. Therefore, the stress distribution of the formed first isolation material layer is also relatively uniform, effectively reducing the problem of fin bending deformation caused by stress differences.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous advancement of semiconductor technology, the process nodes of semiconductor devices are constantly shrinking. However, due to the limitations of the precision of existing photolithography processes, the mask patterns formed by current photolithography processes are insufficient to meet the demands of continuously shrinking feature sizes in semiconductor devices, thus hindering the development of semiconductor technology.

[0003] To further reduce the size of semiconductor devices based on existing photolithography processes, a multi-patterning process has been proposed. Among them, the self-aligned quadruple patterning (SAQP) process shows promise due to its ability to form smaller masks.

[0004] However, existing semiconductor structures formed using self-aligned quadruple patterning processes still have many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the final semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a plurality of device regions and a plurality of isolation regions; modifying the isolation regions to form a modified layer within the isolation regions; after forming the modified layer, patterning the substrate to form a base, a plurality of device fins located on the base, and a plurality of modified fins located on the base, wherein the device fins are formed by patterning the device regions and the modified fins are formed by patterning the modified layer; forming a first isolation material layer on the base, the first isolation material layer covering the device fins and exposing the modified fins; and removing the modified fins after forming the first isolation material layer.

[0007] Optionally, the method for modifying the isolation region includes: implanting modified ions into the isolation region to form the modified layer.

[0008] Optionally, the modified ions include boron ions or arsenic ions.

[0009] Optionally, the process parameters for the implantation treatment of the modified ions include: implantation energy of 1 keV to 600 keV; implantation dose of 1 E12 atoms / cm 2 ~2E18atoms / cm2 ...

[0010] Optionally, the thickness of the modified layer is greater than the height of the modified fin; the thickness of the modified layer is 800 angstroms to 1350 angstroms.

[0011] Optionally, after patterning the substrate, a retention layer is formed within the substrate. The retention layer is formed by patterning the modified layer, and the bottom surface of the retention layer is lower than the top surface of the substrate.

[0012] Optionally, after removing the modified fin, the method further includes: removing the retaining layer to form an isolation opening within the substrate.

[0013] Optionally, the method for removing the modified fin and the retention layer includes: using a first etching process to remove a portion of the modified fin to form a transition modified fin, wherein the top surface of the transition modified fin is lower than the top surface of the device fin; and using a second etching process to remove the transition modified fin and the retention layer.

[0014] Optionally, the first etching process includes: a dry etching process.

[0015] Optionally, the second etching process includes a wet etching process.

[0016] Optionally, after removing the modified fin and the retained layer, the method further includes: forming a second isolation material layer on the isolation region, the second isolation material layer filling the isolation opening, and the top surface of the second isolation material layer being flush with the top surface of the first isolation material layer; and etching back the first isolation material layer and the second isolation material layer to form an isolation layer, the top surface of the isolation layer being lower than the top surface of the device fin.

[0017] Optionally, the process for forming the second isolation material layer includes: fluid chemical vapor deposition process.

[0018] Optionally, the material of the second insulating material layer includes silicon oxide.

[0019] Optionally, the method for forming the first isolation material layer includes: forming an initial first isolation material layer on the substrate, the initial first isolation material layer covering the device fin and the modified fin; forming a first patterned layer on the initial first isolation material layer, the first patterned layer exposing the surface of the initial first isolation material layer located on the isolation region; and etching the initial first isolation material layer using the first patterned layer as a mask to form the first isolation material layer.

[0020] Optionally, the process for forming the initial first isolation material layer includes: fluid chemical vapor deposition.

[0021] Optionally, the material of the first insulating material layer includes silicon oxide.

[0022] Optionally, the height of the device fin is 800 angstroms to 1200 angstroms; the width of the device fin is 10 nanometers to 16 nanometers; and the spacing between adjacent device fins is 20 nanometers to 30 nanometers.

[0023] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate including a plurality of device regions and a plurality of isolation regions; a plurality of device fins located on the device regions; and a plurality of modified fins located on the isolation regions, the modified fins having modified ions.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the semiconductor structure formation method of the present invention, by forming a modified layer in the isolation region, the modified fins formed by the modified layer have a large etching selectivity with respect to the isolation region. This ensures that the modified fins on each isolation region are completely removed with minimal damage to the substrate during the removal of the modified fins, thereby reducing the problem of short circuits between subsequently formed transistors.

[0026] Furthermore, the modified fins are removed after the first isolation material layer is formed. Since the modified fins were not removed during the formation of the first isolation material layer, the distribution of the device fins and the modified fins is relatively uniform. Therefore, the stress distribution of the formed first isolation material layer is also relatively uniform, which can effectively reduce the problem of fin bending deformation caused by stress difference, thereby improving the performance of the final semiconductor structure.

[0027] Furthermore, after patterning the substrate, a retention layer is formed within the substrate. This retention layer is formed by patterning the modified layer, and its bottom surface is lower than the top surface of the substrate. After removing the modified fins, the process further includes removing the retention layer and forming an isolation opening within the substrate. By forming this isolation opening, the subsequently formed isolation layer is also located within it. Because the bottom surface of the isolation opening is lower than the top surface of the substrate, the isolation effect of the isolation layer between adjacent device regions is increased. Attached Figure Description

[0028] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure.

[0029] Figures 3 to 10 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0030] As described in the background section, existing semiconductor structures formed using a self-aligned quadruple patterning process still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0031] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including a plurality of device regions I and a plurality of isolation regions II, the substrate 100 having a plurality of mutually discrete fins 101; the fins 101 located on each of the isolation regions II are removed.

[0032] Please refer to Figure 2 After removing the fins 101 located on each of the isolation regions II, an isolation material layer (not shown) is formed on the substrate, the isolation material layer covering a plurality of the device fins 101; the isolation material layer is etched back to form an isolation layer 102, the top surface of the isolation layer 102 being lower than the top surface of the device fins 101.

[0033] In this embodiment, since the feature size of the device fin 100 and the spacing between adjacent device fins 100 are small, a number of device fins are formed by a self-aligned quadruple patterning process (SAQP).

[0034] However, due to the design requirements of the semiconductor structure, the dimensions of each isolation region II differ in the direction perpendicular to the sidewall of the device fin 101. Therefore, when removing the fin 101 located on each isolation region II, the etching environment for etching the fin 101 on each isolation region II will differ. When etching the fin 101 on the smaller isolation region II, more of the device fin 101 may be etched, resulting in the formation of grooves within the isolation region II (e.g., ...). Figure 1 (As shown in region A); When etching the fin 101 on the larger isolation region II, there is a problem that the device fin 101 is etched less, resulting in a portion of the device fin 101 remaining on the isolation region II (e.g., Figure 1 As shown in region B, when the height of the remaining device fin 101 is high, it can easily cause short circuits between the transistors formed subsequently.

[0035] Because the morphology of each substrate 100 differs after the fins 101 located on each of the isolation regions II are removed, the stress distribution generated by the isolation material layer on the substrate 100 becomes uneven. Due to this stress difference, some of the device fins 101 are prone to bending deformation (e.g., ...). Figure 2 (As shown in region C), which in turn affects the performance of the final semiconductor structure.

[0036] Based on this, the present invention provides a semiconductor structure and its formation method. By forming a modified layer with a large etching selectivity between the isolation regions, the modified fins on each isolation region can be completely removed with minimal substrate damage during the removal of the modified fins, reducing the risk of short circuits between subsequently formed transistors. Furthermore, when the first isolation material layer is formed, the modified fins have not yet been removed, and the distribution of the device fins and modified fins is relatively uniform. Therefore, the stress distribution of the formed first isolation material layer is also relatively uniform, effectively reducing the problem of fin bending deformation caused by stress differences, thereby improving the performance of the final semiconductor structure.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 3 to 10 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 3 and Figure 4 , Figure 3 It is a 3D diagram of a semiconductor structure. Figure 4 yes Figure 3 A schematic cross-sectional view along line AA shows a substrate 200, which includes several device regions I and several isolation regions II.

[0040] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0041] In this embodiment, a device structure is formed on the device region I, but no device structure is formed on the isolation region II. This increases the spacing between device structures on adjacent device regions I and reduces the problem of short circuits occurring between device structures on adjacent device regions I.

[0042] Please refer to Figure 5 , Figure 5 and Figure 4With the view direction consistent, the isolation zone II is modified to form a modified layer 201 within the isolation zone II.

[0043] In this embodiment, the method for modifying the isolation region II includes: implanting modified ions into the isolation region II to form the modified layer 201.

[0044] By forming the modified layer 201 within the isolation region II, the material of the modified layer 201 differs from the material of the isolation region II. This facilitates the removal of the modified layer II in subsequent processes.

[0045] In this embodiment, boron ions are used as the modified ion; in other embodiments, arsenic ions may also be used as the modified ion.

[0046] In this embodiment, the process parameters for the implantation treatment of the modified ions include: implantation energy of 1 keV to 600 keV; implantation dose of 1 E12 atoms / cm 2 ~2E18atoms / cm 2 .

[0047] Please refer to Figure 6 After the modified layer 201 is formed, the substrate 200 is patterned to form a base 202, a plurality of device fins 203 located on the base 202, and a plurality of modified fins 204 located on the base 202. The device fins 203 are formed by patterning the device region I, and the modified fins 204 are formed by patterning the modified layer 201.

[0048] In this embodiment, the patterning process employs a self-aligned quadruple patterning (SAQP) process. This SAQP process enables the formation of device fins with smaller feature sizes, thereby increasing the integration density of device structures within the semiconductor architecture to meet the needs of modern semiconductor technology development.

[0049] In this embodiment, the height of the device fin is 800 angstroms to 1200 angstroms; the width of the device fin is 10 nanometers to 16 nanometers; and the spacing between adjacent device fins is 20 nanometers to 30 nanometers.

[0050] In this embodiment, the thickness of the modified layer 201 is greater than the height of the modified fin 204; the thickness of the modified layer 204 is 800 angstroms to 1350 angstroms, and the thickness direction is along the normal direction of the surface of the substrate 200.

[0051] In this embodiment, after the substrate 200 is patterned, a retention layer 205 is formed within the substrate 202. The retention layer 205 is formed by patterning the modified layer 201, and the bottom surface of the retention layer 205 is lower than the top surface of the substrate 202.

[0052] Please refer to Figure 7 A first isolation material layer 206 is formed on the substrate 202, the first isolation material layer 206 covering the device fin 203 and exposing the modified fin 204.

[0053] In this embodiment, when the first isolation material layer 206 is formed, the modified fins 204 have not yet been removed. The distribution of the plurality of device fins 203 and the plurality of modified fins 204 is relatively uniform. Therefore, the stress distribution of the first isolation material layer 206 is also relatively uniform, which can effectively reduce the problem of fin bending deformation caused by stress difference, thereby improving the performance of the final semiconductor structure.

[0054] In this embodiment, the method for forming the first isolation material layer 206 includes: forming an initial first isolation material layer (not shown) on the substrate 202, the initial first isolation material layer covering the device fin 203 and the modified fin 204; forming a first patterned layer (not shown) on the initial first isolation material layer, the first patterned layer exposing the surface of the initial first isolation material layer located on the isolation region II; and etching the initial first isolation material layer using the first patterned layer as a mask to form the first isolation material layer 206.

[0055] In this embodiment, the initial first isolation material layer is formed using a fluid chemical vapor deposition process.

[0056] In this embodiment, the first insulating material layer 206 is made of silicon oxide.

[0057] Please refer to Figure 8 After the first insulating material layer 206 is formed, the modified fin 204 is removed.

[0058] In this embodiment, by forming a modified layer 201 in the isolation region II, the modified fins 204 formed by the modified layer 201 have a large etching selectivity with the isolation region II. This ensures that the modified fins 204 on each isolation region II are completely removed with minimal damage to the substrate 200 during the removal of the modified fins 204, thereby reducing the problem of short circuits between subsequently formed transistors.

[0059] Please continue to refer to this. Figure 8After removing the modified fin 204, the method further includes: removing the retaining layer 205 and forming an isolation opening 207 in the substrate 202.

[0060] In this embodiment, by forming the isolation opening 207, the subsequently formed isolation layer is also located within the isolation opening 207. Since the bottom surface of the isolation opening 207 is lower than the top surface of the substrate 202, the isolation effect of the isolation layer between adjacent device regions I can be increased.

[0061] In this embodiment, the method for removing the modified fin 204 and the retention layer 205 includes: using a first etching process to remove a portion of the modified fin 204 to form a transition modified fin (not shown), wherein the top surface of the transition modified fin is lower than the top surface of the device fin 203; and using a second etching process to remove the transition modified fin and the retention layer 205.

[0062] In this embodiment, the first etching process is a dry etching process.

[0063] In this embodiment, the second etching process is a wet etching process.

[0064] Please refer to Figure 9 After removing the modified fin 204 and the retained layer 205, a second isolation material layer 208 is formed on the isolation area II. The second isolation material layer 208 fills the isolation opening 207, and the top surface of the second isolation material layer 208 is flush with the top surface of the first isolation material layer 206.

[0065] In this embodiment, the method for forming the second isolation material layer 208 includes: forming an initial second isolation material layer (not shown) on the substrate 202 and the first isolation material layer 206; and planarizing the initial second isolation material layer until the top surface of the first isolation material layer 206 is exposed, thereby forming the second isolation material layer 208.

[0066] In this embodiment, the initial second isolation material layer is formed using a fluid chemical vapor deposition process.

[0067] In this embodiment, the material of the second insulating material layer is silicon oxide.

[0068] In this embodiment, the planarization process employs a chemical mechanical polishing process.

[0069] Please refer to Figure 10After the second isolation material layer 208 is formed, the first isolation material layer 206 and the second isolation material layer 208 are etched back to form an isolation layer 209, the top surface of which is lower than the top surface of the device fin 203.

[0070] In this embodiment, the process of etching back the first isolation material layer 206 and the second isolation material layer 208 is a dry etching process; in other embodiments, the process of etching back the first isolation material layer and the second isolation material layer can also be a wet etching process.

[0071] Accordingly, a semiconductor structure is also provided in the embodiments of the present invention. Please refer to [link / reference needed]. Figure 6 It includes: a substrate 202, the substrate 202 including a plurality of device regions I and a plurality of isolation regions II; a plurality of device fins 203 located on the device regions I; and a plurality of modified fins 204 located on the isolation regions II, the modified fins 204 containing modified ions.

[0072] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a plurality of device regions and a plurality of isolation regions; The isolation zone is modified to form a modified layer within the isolation zone; After the modified layer is formed, the substrate is patterned to form a base, a plurality of device fins on the base, and a plurality of modified fins on the base. The device fins are formed by patterning the device region, and the modified fins are formed by patterning the modified layer. A first isolation material layer is formed on the substrate, the first isolation material layer covering the device fins and exposing the modified fins; After forming the first insulating material layer, the modified fins are removed; wherein, After the substrate is patterned, a retention layer is formed within the substrate. The retention layer is formed by patterning the modified layer, and the bottom surface of the retention layer is lower than the top surface of the substrate. After removing the modified fins, the retaining layer is removed, and an isolation opening is formed within the substrate.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for modifying the isolation region includes: implanting modified ions into the isolation region to form the modified layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, Modified ions include boron ions or arsenic ions.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process parameters for the implantation treatment of the modified ions include: implantation energy of 1 keV to 600 keV; implantation dose of 1 E12 atoms / cm. 2 ~2E18atoms / cm 2 .

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the modified layer is greater than the height of the modified fin; the thickness of the modified layer is 800 angstroms to 1350 angstroms.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for removing the modified fin and the retention layer includes: using a first etching process to remove a portion of the modified fin to form a transition modified fin, wherein the top surface of the transition modified fin is lower than the top surface of the device fin; and using a second etching process to remove the transition modified fin and the retention layer.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The first etching process includes: dry etching process.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The second etching process includes: wet etching process.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, After removing the modified fin and the retained layer, the method further includes: forming a second isolation material layer on the isolation region, the second isolation material layer filling the isolation opening, and the top surface of the second isolation material layer being flush with the top surface of the first isolation material layer; and etching back the first isolation material layer and the second isolation material layer to form an isolation layer, the top surface of the isolation layer being lower than the top surface of the device fin.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process for forming the second isolation material layer includes: fluid chemical vapor deposition process.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the second insulating layer includes silicon oxide.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the first isolation material layer includes: forming an initial first isolation material layer on the substrate, the initial first isolation material layer covering the device fin and the modified fin; forming a first patterned layer on the initial first isolation material layer, the first patterned layer exposing the surface of the initial first isolation material layer located on the isolation region; and etching the initial first isolation material layer using the first patterned layer as a mask to form the first isolation material layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for forming the initial first isolation material layer includes: fluid chemical vapor deposition process.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first insulating layer includes silicon oxide.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The height of the device fin is 800 angstroms to 1200 angstroms; the width of the device fin is 10 nanometers to 16 nanometers; and the spacing between adjacent device fins is 20 nanometers to 30 nanometers.

16. A semiconductor structure formed by any one of claims 1 to 15, characterized in that, include: The substrate includes several device regions and several isolation regions; Several device fins located on the device region; Several modified fins are located on the isolation zone, and the modified fins contain modified ions.

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