Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The semiconductor structure includes: a plurality of fins disposed on a substrate; an isolation layer located on the substrate and surrounding the fins, the top surface of the isolation layer being lower than the top surface of the fins; a device gate structure located on the isolation layer of a device cell region and spanning the fins; source / drain doped regions located in the fins of the device cell regions on both sides of the device gate structure; and a blocking structure located between the source / drain doped regions of adjacent device cell regions along the extension direction of the fins, and at least penetrating the fins exposed by the isolation layer between adjacent device cell regions. The blocking structure is arranged in parallel with and spaced apart from the device gate structures of adjacent device cell regions. The blocking structure includes a conductive layer and dielectric structures located on the sidewalls and bottom of the conductive layer. The blocking structure further includes a conductive layer, enabling it to be used as a connecting wire to achieve electrical connections between different device structures, increasing the functional versatility of the blocking structure and the interconnection freedom of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] To better adapt to the shrinking feature size, semiconductor processes are gradually transitioning from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate has stronger control over the channel and can effectively suppress short-channel effects. Furthermore, FinFETs have better compatibility with existing integrated circuit manufacturing processes compared to other devices.

[0003] However, as the size of semiconductor devices continues to shrink, the distance between adjacent fin field-effect transistors also decreases. To prevent adjacent fin field-effect transistors from merging, existing technologies have introduced the fabrication technology of single diffusion break (SDB) isolation structures.

[0004] However, the performance of current semiconductor structures still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which increases the functional diversity of the partition structure and the degree of freedom in the interconnection of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including discrete device cell regions; a plurality of fins discretely disposed on the substrate; an isolation layer located on the substrate and surrounding the fins, the top surface of the isolation layer being lower than the top surface of the fins; a device gate structure located on the isolation layer of the device cell regions and spanning the fins, the device gate structure covering a portion of the top and a portion of the sidewalls of the fins; source / drain doped regions located in the fins of the device cell regions on both sides of the device gate structure; and a blocking structure located between the source / drain doped regions of adjacent device cell regions along the extension direction of the fins, and at least penetrating the fins exposed by the isolation layer between adjacent device cell regions, the blocking structure being arranged parallel to and spaced apart from the device gate structures of adjacent device cell regions; the blocking structure including a conductive layer and a dielectric structure located on the sidewalls and bottom of the conductive layer.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including discrete device cell regions, wherein discrete fins and an isolation layer surrounding the fins are formed on the substrate, the top surface of the isolation layer being lower than the top surface of the fins; a plurality of gate structures spanning the fins are formed on the isolation layer, the extension direction of the gate structures being perpendicular to the extension direction of the fins; active and drain doped regions are formed in the fins on both sides of the gate structures; removing at least the fins exposed by the isolation layer below the gate structures located between adjacent device cell regions along the extension direction of the fins and below the gate structures between adjacent device cell regions, forming a separation opening between adjacent device cell regions; filling the separation opening with a partition structure, the partition structure including a dielectric structure located on the sidewalls and bottom of the separation opening, and a conductive layer located on the dielectric structure and filling the separation opening.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] The semiconductor structure provided in this embodiment of the invention includes a dielectric structure located on the sidewalls and bottom of the isolation opening, and a conductive layer located on the dielectric structure and filling the isolation opening. Thus, the isolation structure can not only be used to achieve isolation between adjacent device unit regions, but the conductive layer of the isolation structure also enables the isolation structure to be used as a connecting wire to achieve electrical connection between different device structures, thereby increasing the functional diversity of the isolation structure and the degree of freedom of interconnection of the semiconductor structure.

[0010] In the semiconductor structure formation method provided by the embodiments of the present invention, a partition structure is filled in the partition opening. The partition structure includes a dielectric structure located on the sidewalls and bottom of the partition opening and a conductive layer located on the dielectric structure and filling the partition opening. Thus, the partition structure can not only be used to achieve isolation between adjacent device unit regions, but the conductive layer of the partition structure also enables the partition structure to be used as a connecting wire to achieve electrical connection between different device structures, thereby increasing the functional diversity of the partition structure and the degree of freedom of interconnection of the semiconductor structure. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a semiconductor structure.

[0012] Figures 2 to 7 This is a schematic diagram of the structure corresponding to each step in another method for forming a semiconductor structure.

[0013] Figures 8 to 10 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0014] Figures 11 to 21 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0015] As the background technology shows, the performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement by combining two different semiconductor structures.

[0016] Figure 1 This is a schematic diagram of a semiconductor structure. Specifically, Figure 1 A schematic diagram of the cross-sectional structure along the extension direction of the fin is shown.

[0017] like Figure 1 As shown, the semiconductor structure includes: a substrate 10, including a plurality of discrete device cell regions 10a; a plurality of fins 11 discretely disposed on the substrate 10 of the device cell regions 10a, wherein adjacent fins 11 of the device cell regions 10a and the substrate 10 form a groove (not shown) along the extending direction of the fins 11; an isolation layer 12 located on the substrate 10 and surrounding the fins 11, the isolation layer 12 being located within the groove; a device gate structure 13 located on the isolation layer 12 of the device cell regions 10a and spanning the fins 11, the device gate structure 13 covering a portion of the top and a portion of the sidewalls of the fins 11; a dummy gate structure 14 located on the isolation layer 12 between the device cell regions 10a, the dummy gate structure 14 and the device gate structure 13 being arranged in parallel and spaced apart, and the extending directions of the dummy gate structure 14 and the device gate structure 13 being perpendicular to the extending direction of the fins 11; and source / drain doped regions 15 located within the fins 11 on both sides of the device gate structure 13.

[0018] In the semiconductor structure, the pseudo-gate structure 14 is used as a single diffused barrier (SDB) isolation structure to achieve isolation between adjacent device cell regions 10a.

[0019] However, during the formation of the semiconductor structure, the process of forming the pseudo gate structure 14 includes an etching process. During the formation of the pseudo gate structure 14, the etching process is prone to alignment deviation (overlay shift), which increases the probability of bridging between the pseudo gate structure 14 and the source / drain doped regions 15 of the adjacent device cell region 10a, and the process window for forming the pseudo gate structure 14 is relatively small.

[0020] Figures 2 to 7 This is a schematic diagram of the structure corresponding to each step in another method for forming a semiconductor structure.

[0021] like Figures 2 to 4 As shown, Figure 2 This is a top view. Figure 3 for Figure 2Cross-sectional view along the x-x1 direction (i.e., the direction of fin extension). Figure 4 for Figure 2 A cross-sectional view along the y-y1 direction shows a substrate 20 including discrete device cell regions 20a. Discrete fins 21 are formed on the substrate 20, and an insulating layer 22 surrounds the fins 21. The top surface of the insulating layer 22 is lower than the top surface of the fins 21. A plurality of gate structures 23 are formed on the insulating layer 22, spanning the fins 21. The extending direction of the gate structures 23 is perpendicular to the extending direction of the fins 21. Active and drain doped regions 24 are formed in the fins 21 on both sides of the gate structures 23.

[0022] like Figures 5 to 7 As shown, Figure 5 This is a top view. Figure 6 for Figure 4 Cross-sectional view along the x-x1 direction. Figure 7 for Figure 4 A cross-sectional view along the y-y1 direction shows the removal of the gate structure 23 located between adjacent device cell regions 20a along the extension direction of the fin 21, and the fin 21 below the gate structure 23 between the adjacent device cell regions 20a, forming an isolation opening (not shown) between the adjacent device cell regions 20a; the isolation opening is filled with dielectric material to form an isolation structure 26.

[0023] In the method for forming the semiconductor structure, during the process of forming the isolation opening, self-alignment with the position of the gate structure 23 can be achieved, which is beneficial to accurately locate the position of the isolation structure 25 and reduces the impact on the source and drain doped regions 24 of the adjacent device cell region 20a, thereby increasing the process window for forming the isolation structure 25.

[0024] However, the material of the isolation structure 25 is a dielectric material, and the isolation structure 25 cannot conduct electricity, which means that the isolation structure 25 cannot be used as a wire and loses its function as a connection. For example, the gate structure 23 of the adjacent device unit region 20a cannot be electrically connected by making electrical contact with the isolation structure 25 respectively.

[0025] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure comprising: a substrate including discrete device cell regions; a plurality of fins discretely disposed on the substrate; an isolation layer located on the substrate and surrounding the fins, the top surface of the isolation layer being lower than the top surface of the fins; a device gate structure located on the isolation layer of the device cell regions and spanning the fins, the device gate structure covering a portion of the top and a portion of the sidewalls of the fins; source / drain doped regions located in the fins of the device cell regions on both sides of the device gate structure; and a blocking structure located between the source / drain doped regions of adjacent device cell regions along the extension direction of the fins, and at least penetrating the fins exposed by the isolation layer between adjacent device cell regions, the blocking structure being arranged parallel to and spaced apart from the device gate structures of adjacent device cell regions; the blocking structure including a conductive layer and dielectric structures located on the sidewalls and bottom of the conductive layer.

[0026] The semiconductor structure provided in this embodiment of the invention includes a dielectric structure located on the sidewalls and bottom of the isolation opening, and a conductive layer located on the dielectric structure and filling the isolation opening. Thus, the isolation structure can not only be used to achieve isolation between adjacent device unit regions, but the conductive layer of the isolation structure also enables the isolation structure to be used as a connecting wire to achieve electrical connection between different device structures, thereby increasing the functional diversity of the isolation structure and the degree of freedom of interconnection of the semiconductor structure.

[0027] To address the aforementioned technical problem, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including discrete device cell regions; forming discrete fins and an isolation layer surrounding the fins on the substrate, the top surface of the isolation layer being lower than the top surface of the fins; forming a plurality of gate structures spanning the fins on the isolation layer, the extension direction of the gate structures being perpendicular to the extension direction of the fins; forming active and drain doped regions in the fins on both sides of the gate structures; removing at least the fins exposed by the isolation layer below the gate structures located between adjacent device cell regions along the extension direction of the fins and below the gate structures between adjacent device cell regions; forming a separation opening between adjacent device cell regions; filling the separation opening with a partition structure, the partition structure including a dielectric structure located on the sidewalls and bottom of the separation opening, and a conductive layer located on the dielectric structure and filling the separation opening.

[0028] In the semiconductor structure formation method provided by the embodiments of the present invention, a partition structure is filled in the partition opening. The partition structure includes a dielectric structure located on the sidewalls and bottom of the partition opening and a conductive layer located on the dielectric structure and filling the partition opening. Thus, the partition structure can not only be used to achieve isolation between adjacent device unit regions, but the conductive layer of the partition structure also enables the partition structure to be used as a connecting wire to achieve electrical connection between different device structures, thereby increasing the functional diversity of the partition structure and the degree of freedom of interconnection of the semiconductor structure.

[0029] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 8 to 10 , Figure 8 This is a top view. Figure 9 for Figure 8 Cross-sectional view along the x-x1 direction. Figure 10 for Figure 8 A cross-sectional view along the y-y1 direction shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0030] like Figures 8 to 10 As shown, in this embodiment, the semiconductor structure includes: a substrate 100, including discrete device cell regions 100a; a plurality of fins 110, discretely disposed on the substrate 100; an isolation layer 120, located on the substrate 100 and surrounding the fins 110, the top surface of the isolation layer 120 being lower than the top surface of the fins 110; a device gate structure 200, located on the isolation layer 120 of the device cell regions 100a and spanning the fins 110, the device gate structure 200 covering a portion of the top and a portion of the sidewalls of the fins 110; and source / drain doped regions 140, located on... The device gate structure 200 is located in the fins 110 of the device cell regions 100a on both sides of the device gate structure 200; the isolation structure 190 is located between the source and drain doped regions 140 of the adjacent device cell regions 100a along the extension direction of the fins 110, and at least penetrates the fins 110 exposed by the isolation layer 120 between the adjacent device cell regions 100a, the isolation structure 190 is arranged in parallel with the device gate structure 200 of the adjacent device cell regions 100a; the isolation structure 190 includes a conductive layer 180 and a dielectric structure 170 located on the sidewalls and bottom of the conductive layer 180.

[0031] The substrate 100 is used to provide a process platform for the formation of fin field-effect transistors.

[0032] In this embodiment, the substrate 100 is a silicon substrate, meaning the material of the substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0033] The device cell region 100a is used to form a device cell. As one embodiment, the device cell region 100a is used to form a standard cell.

[0034] As an example, the device cell region 100a includes an NMOS region (not shown) for forming an NMOS transistor and a PMOS region (not shown) for forming a PMOS transistor, wherein the NMOS region and the PMOS region are arranged in an extension direction perpendicular to the fin 110.

[0035] The fin 110 is used to provide a conductive channel for a fin field-effect transistor (FinFET). The material of the fin 110 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the material of the fin 110 is single-crystal silicon.

[0036] In this embodiment, the fin 110 and the substrate 100 are an integral structure.

[0037] The top of the isolation layer 120 is lower than the top of the fin 110, so that the fin 110 exposed by the isolation layer 120 serves as an active fin, which provides a conductive channel for the field-effect transistor.

[0038] In this embodiment, the isolation layer 120 is a shallow trench isolation (STI) structure, used to isolate adjacent fins 110, and also used to isolate the substrate 100 from the gate structure 130.

[0039] In this embodiment, the material of the insulating layer 120 is silicon oxide. In other embodiments, the material of the insulating layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

[0040] The device gate structure 200 is used to control the opening and closing of the conductive channel of the fin field-effect transistor.

[0041] In this embodiment, the device gate structure 200 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0042] The gate dielectric layer is used to electrically isolate the gate layer from the conductive channel.

[0043] The material of the gate dielectric layer includes one or more of the following: silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0044] In a specific implementation, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer or a high-k gate dielectric layer.

[0045] The gate layer is used as an external electrode to realize the electrical connection between the device gate structure 200 and the external circuit.

[0046] In this embodiment, the device gate structure 200 is a metal gate structure, and the gate layer is made of a metal material. The gate layer material includes one or more of the following: TiN, TaN, Ti, Ta, TiAl, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0047] In a specific implementation, the gate layer may include a work function layer and a metal electrode layer located on the work function layer, or the gate layer may only include a work function layer.

[0048] The device gate structure 200 is a plurality of such structures, and the plurality of such structures are arranged at intervals along the extension direction of the fin 110, wherein the extension direction of the device gate structure 200 is perpendicular to the extension direction of the fin 110.

[0049] In this embodiment, the semiconductor structure further includes a gate sidewall 135, located on the sidewall of the device gate structure 200.

[0050] The gate sidewall 135 is used to protect the sidewall of the device gate structure 200, and the gate sidewall 135 is also used to define the formation location of the source and drain doped regions 140.

[0051] The gate sidewall 135 can be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. The gate sidewall 135 can be a single-layer structure or a multilayer structure. In this embodiment, the gate sidewall 135 is a single-layer structure, and the material of the gate sidewall 135 is silicon nitride.

[0052] When the device is in operation, the source / drain doped regions 140 are used to provide a carrier source. In this embodiment, the source / drain doped regions 140 include a stress layer doped with ions, which is used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0053] Specifically, when forming an NMOS transistor, the material of the source / drain doped region 140 is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0054] When forming a PMOS transistor, the source and drain doped regions 140 are made of a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, which helps to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0055] The isolation structure 190 serves as a Single Diffusion Break (SDB) to isolate adjacent device cell regions 100a. Specifically, the isolation structure 190 prevents bridging between the source / drain doped regions 140 of adjacent device cell regions 100a.

[0056] The partition structure 190 can also increase the density of devices and save chip area.

[0057] In this embodiment, the partition structure 190 also extends through the fin 110 covered by the isolation layer 120, which helps to reduce the probability of leakage current in the remaining fin 110 or substrate 100 located below the partition structure 190.

[0058] In this embodiment, the isolation structure 190 includes a conductive layer 180 and a dielectric structure 170 located on the sidewalls and bottom of the conductive layer 180. Thus, the isolation structure 190 can not only be used to achieve isolation between adjacent device unit regions 100a, but the conductive layer 180 of the isolation structure 190 also enables the isolation structure 190 to be used as a connecting wire to achieve electrical connection between different device structures, thereby increasing the functional diversity of the isolation structure 190 and the degree of freedom of interconnection of the semiconductor structure.

[0059] The conductive layer 180 is used as a connecting wire to realize electrical connection between different device structures, thereby increasing the functional diversity of the isolation structure 190 and the degree of freedom of interconnection of the semiconductor structure.

[0060] The conductive layer 180 is made of a conductive material, such as one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0061] Specifically, the dielectric structure 170 is used to achieve electrical isolation between adjacent device unit regions 100a, and also to achieve electrical isolation between the conductive layer 180 and the substrate 100, and between the conductive layer 180 and the fin 110.

[0062] The dielectric structure 170 is made of a dielectric material, which includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and boron silicon carbide.

[0063] In this embodiment, the thickness of the dielectric structure 170 located at the bottom of the conductive layer 180 along the direction perpendicular to the substrate 100 is the first thickness; the thickness of the dielectric structure 170 located at the sidewall of the conductive layer 180 along the direction perpendicular to the sidewall of the conductive layer 180 is the second thickness; the first thickness is greater than the second thickness.

[0064] By making the first thickness greater than the second thickness, the thickness of the dielectric structure 170 located in the direction perpendicular to the substrate 100 is greater than the thickness of the dielectric structure 170 located in the direction perpendicular to the sidewall of the conductive layer 180. This is beneficial to improve the isolation effect of the isolation structure 190 on the fins 110 of the adjacent device unit region 100a and reduce the probability of leakage current at the bottom of the fins 110 of the adjacent device unit region 100a.

[0065] Specifically, in this embodiment, the dielectric structure 170 includes a dielectric layer (not shown) located at the bottom of the conductive layer 180 and an insulating layer (not shown) located at the sidewalls of the conductive layer 180, the sidewalls of the dielectric layer, and the bottom, so that the first thickness is greater than the second thickness.

[0066] The insulating layer conformally covers the sidewalls and bottom of the dielectric layer, as well as the sidewalls and bottom of the conductive layer.

[0067] In other embodiments, the dielectric layer may be omitted from the partition structure based on actual process requirements.

[0068] In this embodiment, the bottom surface of the conductive layer 180 is higher than the top surface of the insulating layer 120 as an example. In other embodiments, the height of the bottom surface of the conductive layer can be adjusted based on actual process requirements; for example, the bottom surface of the conductive layer can be lower than or flush with the top surface of the insulating layer.

[0069] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 150, located on the isolation layer 120 and covering the source / drain doped regions 140, and the interlayer dielectric layer 150 fills the space between the device gate structures 200 and between the device gate structures 200 and the isolation structure 190.

[0070] The interlayer dielectric layer 150 is used to isolate adjacent devices.

[0071] Therefore, the material of the interlayer dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 150 is silicon oxide.

[0072] In this embodiment, for ease of illustration and explanation, only the interlayer dielectric layer 150, the isolation layer 120, and the gate sidewall 135 are shown in the cross-sectional view.

[0073] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 11 to 21 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0074] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0075] refer to Figures 11 to 13 , Figure 11 This is a top view. Figure 12 for Figure 11 Cross-sectional view along the x-x1 direction. Figure 13 for Figure 11 A cross-sectional view along the y-y1 direction shows a substrate 100 including discrete device cell regions 100a. Discrete fins 110 are formed on the substrate 100, and an isolation layer 120 surrounds the fins 110. The top surface of the isolation layer 120 is lower than the top surface of the fins 110. A plurality of gate structures 130 are formed on the isolation layer 120, spanning the fins 110. The extending direction of the gate structures 130 is perpendicular to the extending direction of the fins 110. Active and drain doped regions 140 are formed in the fins 110 on both sides of the gate structures 130.

[0076] The substrate 100 is used to provide a process platform for subsequent processes.

[0077] In this embodiment, the substrate 100 is a silicon substrate, meaning the material of the substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0078] The device cell region 100a is used to form a device cell. As one embodiment, the device cell region 100a is used to form a standard cell.

[0079] As an example, the device cell region 100a includes an NMOS region (not shown) for forming an NMOS transistor and a PMOS region (not shown) for forming a PMOS transistor, wherein the NMOS region and the PMOS region are arranged in an extension direction perpendicular to the fin 110.

[0080] The fin 110 is used to provide a conductive channel for a fin field-effect transistor (FinFET). The material of the fin 110 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the material of the fin 110 is single-crystal silicon.

[0081] In this embodiment, the fin 110 and the substrate 100 are an integral structure.

[0082] In this embodiment, an isolation layer 120 is also formed on the substrate exposed by the fin 110. The isolation layer 120 covers part of the sidewall of the fin 110, and the top surface of the isolation layer 120 is lower than the top surface of the fin 110.

[0083] The top of the isolation layer 120 is lower than the top of the fin 110, so that the fin 110 exposed by the isolation layer 120 serves as an active fin, which provides a conductive channel for the field-effect transistor.

[0084] In this embodiment, the isolation layer 120 is a shallow trench isolation (STI) structure, used to isolate adjacent fins 110, and also used to isolate the substrate 100 from the gate structure 130.

[0085] In this embodiment, the material of the insulating layer 120 is silicon oxide. In other embodiments, the material of the insulating layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

[0086] The gate structure 130 can be a device gate structure or a dummy gate structure. The gate structure 130 is located on the isolation layer 120 and covers part of the top and part of the sidewalls of the fin 110.

[0087] In this embodiment, the gate structure 130 is described as a dummy gate structure. The gate structure 130 of the device cell region 100a is used to occupy space for forming the device gate structure.

[0088] Specifically, the gate structure 130 includes a dummy gate oxide layer (not shown) and a gate layer (not shown) located on the dummy gate oxide layer.

[0089] In this embodiment, the gate structure 130 is a polycrystalline silicon gate structure or an amorphous silicon gate structure. The material of the dummy gate oxide layer can be silicon oxide or nitrogen-doped silicon oxide; the material of the gate layer is polycrystalline silicon or amorphous silicon.

[0090] The number of gate structures 130 is multiple, and the multiple gate structures 130 are arranged at intervals along the extension direction of the fin 110, and the extension direction of the gate structures 130 is perpendicular to the extension direction of the fin 110.

[0091] In this embodiment, a gate sidewall 135 is also formed on the sidewall of the gate structure 130.

[0092] The gate sidewall 135 is used to protect the sidewall of the gate structure 130, and the gate sidewall 135 is also used to define the formation location of the source and drain doped regions 140.

[0093] The gate sidewall 135 can be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. The gate sidewall 135 can be a single-layer structure or a multilayer structure. In this embodiment, the gate sidewall 135 is a single-layer structure, and the material of the gate sidewall 135 is silicon nitride.

[0094] When the device is in operation, the source / drain doped regions 140 are used to provide a carrier source. In this embodiment, the source / drain doped regions 140 include a stress layer doped with ions, which is used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0095] Specifically, when forming an NMOS transistor, the material of the source / drain doped region 140 is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0096] When forming a PMOS transistor, the source and drain doped regions 140 are made of a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, which helps to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0097] It should be noted that, in this embodiment, the method for forming the semiconductor structure further includes: after providing the substrate 100, forming an interlayer dielectric layer 150 on the isolation layer 120 exposed by the gate structure 130, wherein the interlayer dielectric layer 150 covers the source and drain doped regions 140.

[0098] The interlayer dielectric layer 150 is used to isolate adjacent devices.

[0099] Therefore, the material of the interlayer dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 150 is silicon oxide.

[0100] In this embodiment, for ease of illustration and explanation, only the interlayer dielectric layer 150, the isolation layer 120, and the gate sidewall 135 are shown in the cross-sectional view.

[0101] refer to Figures 14 to 16 , Figure 14 This is a top view. Figure 15 for Figure 14 Cross-sectional view along the x-x1 direction. Figure 16 for Figure 14 A cross-sectional view along the y-y1 direction shows that the fins 110 located between adjacent device cell regions 100a along the extension direction of the fins 110, and the fins 110 exposed below the gate structures 130 between adjacent device cell regions 100a, are removed, forming an isolation opening 160 between adjacent device cell regions 100a.

[0102] The partition opening 160 is used to provide space for forming the partition structure.

[0103] The isolation opening 160 is formed by removing the gate structure 130 between adjacent device cell regions 100a and the fin 110 below the gate structure 130, thereby isolating the fin 110 and the source / drain doped region 140 of the adjacent device cell regions 100a, and thus achieving the isolation effect on the adjacent device cell regions 100a.

[0104] In this embodiment, the isolation opening 160 is formed by removing the gate structure 130 between adjacent device cell regions 100a and the fin 110 below the gate structure 130. During the formation of the isolation opening 160, self-alignment with the position of the gate structure 130 can be achieved, which is beneficial to accurately locate the position of the isolation opening 160 and reduces the impact on the source and drain doped regions 140 of the adjacent device cell regions 100a, thereby increasing the process window for forming the isolation opening 160.

[0105] In this embodiment, the extension direction of the isolation opening 160 is the same as the extension direction of the gate structure 130, and the isolation opening 160 and the adjacent gate structure 130 are arranged at intervals along the extension direction of the fin 110.

[0106] In this embodiment, the isolation opening 160 penetrates the gate structure 130 located between adjacent device cell regions 100a along the extension direction of the fin 110, and the fin 110 covered by the isolation layer 120 below the gate structure 130.

[0107] By having the isolation opening 160 also extend through the fin 110 covered by the isolation layer 120, it is beneficial to reduce the probability of leakage current in the remaining fin 110 or substrate 100 located below the isolation opening 160.

[0108] In this embodiment, an interlayer dielectric layer 150 is also formed on the exposed isolation layer 120 of the gate structure 130. Therefore, the isolation opening 160 is located in the interlayer dielectric layer 150 and the fin 110 between adjacent device units 100a along the extension direction of the fin 110.

[0109] As an example, the step of forming the isolation opening 160 includes: forming a mask layer (not shown) on the interlayer dielectric layer 150 and the gate structure 130, wherein a mask opening (not shown) is formed in the mask layer above the top of the gate structure 130 between the adjacent device cell regions 100a; using the mask layer as a mask, etching the gate structure 130 and the fin 110 located below the gate structure 130 along the mask opening; and removing the mask layer to expose the top of the interlayer dielectric layer 150 and the remaining gate structure 130 for subsequent process steps.

[0110] refer to Figures 17 to 19 , Figure 17 This is a top view. Figure 18 for Figure 17 Cross-sectional view along the x-x1 direction. Figure 19 for Figure 17 A cross-sectional view along the y-y1 direction shows that the partition opening 160 is filled with a partition structure 190, the partition structure 190 including a dielectric structure 170 located on the sidewalls and bottom of the partition opening 160, and a conductive layer 180 located on the dielectric structure 170 and filling the partition opening 160.

[0111] The isolation structure 190 serves as a Single Diffusion Break (SDB) to isolate adjacent device cell regions 100a. Specifically, the isolation structure 190 prevents bridging between the source / drain doped regions 140 of adjacent device cell regions 100a.

[0112] The partition structure 190 can also increase the density of devices and save chip area.

[0113] In this embodiment, the isolation structure 190 includes a dielectric structure 170 located on the sidewalls and bottom of the isolation opening 160, and a conductive layer 180 located on the dielectric structure 170 and filling the isolation opening 160. Thus, the isolation structure 190 can not only be used to achieve isolation between adjacent device unit regions 100a, but the conductive layer 180 of the isolation structure 190 also enables the isolation structure 190 to be used as a connecting wire to achieve electrical connection between different device structures, thereby increasing the functional diversity of the isolation structure 190 and the degree of freedom of interconnection of the semiconductor structure.

[0114] Specifically, the dielectric structure 170 is used to achieve electrical isolation between adjacent device unit regions 100a, and also to achieve electrical isolation between the conductive layer 180 and the substrate 100, and between the conductive layer 180 and the fin 110.

[0115] The dielectric structure 170 is made of a dielectric material, which includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and boron silicon carbide.

[0116] The conductive layer 180 is used as a connecting wire to realize electrical connection between different device structures, thereby increasing the functional diversity of the isolation structure 190 and the degree of freedom of interconnection of the semiconductor structure.

[0117] The conductive layer 180 is made of a conductive material, such as one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0118] As an example, the steps of forming the isolation structure 190 include: forming an insulating layer (not shown) conformally covering the bottom and sidewalls of the isolation opening 160; forming a dielectric layer (not shown) on the insulating layer that fills a portion of the isolation opening 160, the top surface of the dielectric layer being lower than the top surface of the gate structure 130; the dielectric layer and the insulating layer constituting the dielectric structure 170; and forming a conductive layer 180 on the dielectric layer that fills the remaining isolation opening 160.

[0119] After forming an insulating layer that conformally covers the bottom and sidewalls of the partition opening 160, a dielectric layer that fills part of the partition opening 160 is also formed on the insulating layer. This results in a greater thickness of the dielectric structure 170 located in the direction perpendicular to the substrate 100 compared to the thickness of the dielectric structure 170 located in the direction perpendicular to the sidewalls of the conductive layer 180. This is beneficial to improve the isolation effect of the partition structure 190 on the fins 110 of the adjacent device unit region 100a and reduce the probability of leakage current at the bottom of the fins 110 of the adjacent device unit region 100a.

[0120] In other embodiments, the dielectric layer may not be formed, depending on actual process requirements.

[0121] Specifically, the insulating layer can be formed using an atomic layer deposition process. The stepped coverage properties of the atomic layer deposition process improve the conformal coverage of the insulating layer on the bottom and sidewalls of the partition opening 160.

[0122] After forming the insulating layer, the step of forming the dielectric layer includes: forming a dielectric material layer on the insulating layer that fills the partition opening 160; removing a portion of the height dielectric material layer located within the partition opening 160, and using the remaining portion of the thickness dielectric material layer located within the partition opening 160 as the dielectric layer.

[0123] In this embodiment, a deposition process (e.g., chemical vapor deposition, flow-through chemical vapor deposition, etc.) is used to form the dielectric material layer.

[0124] As an example, an etching process (e.g., dry etching) is used to remove a portion of the dielectric material layer located within the partition opening 160.

[0125] After forming the dielectric layer, the step of forming the conductive layer 180 may include: filling the partition opening 160 with a conductive material layer (not shown), the conductive material layer also being located above the interlayer dielectric layer 150; removing the conductive material layer located on the interlayer dielectric layer 150, the remaining conductive material layer filling the partition opening 160 being used as the conductive layer 180.

[0126] As an example, the conductive material layer is made of tungsten and is formed by chemical vapor deposition; a chemical mechanical planarization process is used to remove the conductive material layer located on the interlayer dielectric layer 150.

[0127] In this embodiment, the bottom surface of the conductive layer 180 is higher than the top surface of the insulating layer 120 as an example. In other embodiments, the height of the bottom surface of the conductive layer can be adjusted based on actual process requirements; for example, the bottom surface of the conductive layer can be lower than or flush with the top surface of the insulating layer.

[0128] refer to Figures 20 to 21 , Figure 20 This is a top view. Figure 21 for Figure 20 In the cross-sectional view along the x-x1 direction, in this embodiment, the gate structure 130 is a pseudo-gate structure. Therefore, after forming the isolation structure 190, the method for forming the semiconductor structure further includes: removing the pseudo-gate structure to form a gate opening (not shown); and forming a device gate structure 200 in the gate opening.

[0129] The gate opening provides space for forming the device gate structure. The gate opening spans the fin 110.

[0130] The process for removing the gate structure 130 may include any one or both of dry etching and wet etching. As an embodiment, the gate structure 130 is removed by sequentially performing dry etching and wet etching processes.

[0131] The device gate structure 200 is used to control the opening and closing of the conductive channel of the fin field-effect transistor.

[0132] In this embodiment, the device gate structure 200 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0133] The gate dielectric layer is used to electrically isolate the gate layer from the conductive channel.

[0134] The material of the gate dielectric layer includes one or more of the following: silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0135] In a specific implementation, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer or a high-k gate dielectric layer.

[0136] The gate layer is used as an external electrode to realize the electrical connection between the device gate structure 200 and the external circuit.

[0137] In this embodiment, the device gate structure 200 is a metal gate structure, and the gate layer is made of a metal material. The gate layer material includes one or more of the following: TiN, TaN, Ti, Ta, TiAl, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0138] In a specific implementation, the gate layer may include a work function layer and a metal electrode layer located on the work function layer, or the gate layer may only include a work function layer.

[0139] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes discrete device cell regions; Multiple fins are disposed on the substrate; An isolation layer is located on the substrate and surrounds the fin, with the top surface of the isolation layer being lower than the top surface of the fin; A device gate structure is located on the isolation layer of the device cell region and spans the fin, the device gate structure covering part of the top and part of the sidewall of the fin; The source and drain doped regions are located in the fins of the device cell regions on both sides of the gate structure of the device; A barrier structure is located between the source and drain doped regions of adjacent device cell regions along the extension direction of the fin, and at least penetrates the fin exposed by the isolation layer between adjacent device cell regions. The barrier structure is arranged parallel to and spaced apart from the device gate structure of the adjacent device cell region. The barrier structure includes a conductive layer and a dielectric structure located on the sidewalls and bottom of the conductive layer. The conductive layer is used as a connecting wire, and the dielectric structure has a first thickness in a direction perpendicular to the substrate that is greater than a second thickness in a direction perpendicular to the sidewalls of the conductive layer.

2. The semiconductor structure as described in claim 1, characterized in that, The partition structure also extends through the fin covered by the isolation layer.

3. The semiconductor structure as described in claim 1, characterized in that, A dielectric structure having a first thickness along a direction perpendicular to the substrate is located at the bottom of the conductive layer; a dielectric structure having a second thickness along a direction perpendicular to the sidewall of the conductive layer is located at the sidewall of the conductive layer.

4. The semiconductor structure as described in claim 1, characterized in that, The substrate material includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The fin material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The materials of the dielectric structure include one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and boron oxynitride.

5. The semiconductor structure as described in claim 1, characterized in that, The device gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

6. The semiconductor structure as described in claim 5, characterized in that, The material of the gate dielectric layer includes one or more of the following: silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3; The material of the gate layer includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the conductive layer includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

8. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: an interlayer dielectric layer located on the isolation layer and covering the source / drain doped regions, wherein the interlayer dielectric layer fills the space between the device gate structures and between the device gate structures and the isolation structure.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including discrete device cell regions, on which discrete fins are formed and an isolation layer surrounding the fins, the top surface of the isolation layer being lower than the top surface of the fins; Multiple gate structures are formed across the fin on the isolation layer, and the extending direction of the gate structures is perpendicular to the extending direction of the fin; active and drain doped regions are formed in the fin on both sides of the gate structures. Remove the fins that are exposed by the isolation layer below the gate structure between adjacent device cell regions and the gate structure between adjacent device cell regions along the extension direction of the fins, and form an isolation opening between adjacent device cell regions; A partition structure is filled within the partition opening. The partition structure includes a dielectric structure located on the sidewalls and bottom of the partition opening, and a conductive layer located on the dielectric structure and filling the partition opening. The conductive layer serves as a connecting wire, and the first thickness of the dielectric structure in a direction perpendicular to the substrate is greater than the second thickness in a direction perpendicular to the sidewalls of the conductive layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the isolation opening, the isolation opening penetrates the gate structure located between adjacent device cell regions along the extension direction of the fin, and the fin covered by the isolation layer below the gate structure.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming the partition structure includes: forming an insulating layer that conformally covers the bottom and sidewalls of the partition opening; A dielectric layer is formed on the insulating layer to fill a portion of the isolation opening, the top surface of the dielectric layer being lower than the top surface of the gate structure; the dielectric layer and the insulating layer are used to constitute the dielectric structure; A conductive layer is formed on the dielectric layer to fill the remaining isolation openings.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, The gate structure is a pseudo-gate structure; After forming the barrier structure, the method for forming the semiconductor structure further includes: removing the dummy gate structure to form a gate opening; A device gate structure is formed in the gate opening.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the semiconductor structure further includes: after providing a substrate and before forming the isolation opening, forming an interlayer dielectric layer on the isolation layer exposed by the gate structure, wherein the interlayer dielectric layer covers the source and drain doped regions; In the step of forming the partition opening, the partition opening is located in the interlayer dielectric layer and within the fin between adjacent device units along the extension direction of the fin.

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