Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate including a substrate and a fin material layer; etching a partial thickness of the fin material layer to form an initial fin, and the etching has a first etch rate ratio; etching a remaining fin material layer exposed by the initial fin to form a fin standing on the substrate, the fin including a bottom fin, a first portion fin and a second portion fin from bottom to top, the second portion fin and the first portion fin constituting an effective fin, and the etching the partial thickness of the fin material layer exposed by the initial fin has a second etch rate ratio, the second etch rate ratio is less than the first etch rate ratio, for making a bottom line width of the first portion fin less than a top line width of the first portion fin; forming an isolation layer covering a sidewall of the bottom fin and exposing the effective fin. The present application reduces leakage current and reduces the impact on the on-current, thereby improving the on-off current ratio of the transistor.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the gradual development of semiconductor process technology, the semiconductor process node is constantly reduced following the development trend of Moore's Law. In order to adapt to the reduction of the process node, the channel length of the MOSFET field effect transistor is also shortened accordingly. However, as the device channel length is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel is poor, and the difficulty of the gate voltage to pinch off the channel is also increasing, making the subthreshold leakage phenomenon, namely the so-called short channel effect (SCE) more likely to occur.

[0003] Therefore, in order to better adapt to the requirement of device size scaling down, the semiconductor process gradually begins to transition from the planar MOSFET to the three-dimensional transistor with higher efficiency, such as the fin field effect transistor (FinFET). In the FinFET, the gate can at least control the ultra-thin body (fin) from two sides, compared with the planar MOSFET, the control ability of the gate to the channel is stronger, and the short channel effect can be well suppressed; and the FinFET has better compatibility with the existing integrated circuit manufacturing compared with other devices. SUMMARY

[0004] The problem solved by the embodiments of the present application is to provide a semiconductor structure and a forming method thereof, and to improve the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; fins protruding from the substrate; an isolation layer located on the substrate at the side of the fins, the isolation layer covering a portion of the sidewalls of the fins, the fins exposed by the isolation layer serving as effective fins, a portion of the effective fins being designated as a first partial fin, and the remaining portion of the effective fins being designated as a second partial fin, the first partial fin being closer to the isolation layer, wherein the bottom linewidth of the first partial fin is smaller than the top linewidth of the first partial fin, and the top linewidth of the second partial fin is smaller than the top linewidth of the first partial fin; a gate structure located on the isolation layer, the gate structure spanning the effective fins and covering a portion of the top and a portion of the sidewalls of the effective fins; sidewalls located on both sides of the gate structure and covering the sidewalls of the gate structure; and source / drain doped layers located in the effective fins on both sides of the gate structure, and located on the side of the sidewalls away from the gate structure.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a fin material layer located on the substrate, the fin material layer being used to form a bottom fin and an effective fin located on the top surface of the bottom fin; etching a portion of the thickness of the fin material layer to form an initial fin protruding from the remaining fin material layer, wherein the ratio of the longitudinal etching rate to the transverse etching rate during etching is a first etching rate ratio; etching the remaining fin material layer exposed by the initial fin to form a fin protruding from the substrate, wherein the fin includes a bottom fin and a first portion of the fin from bottom to top. The first and second fin portions constitute an effective fin. A first etching process is performed on a portion of the fin material layer exposed from the initial fin portion to form the effective fin. The ratio of the longitudinal etching rate to the transverse etching rate of the first etching is a second etching rate ratio, which is less than the first etching rate ratio, to ensure that the bottom linewidth of the first fin portion is less than the top linewidth. An isolation layer is formed on the substrate on the side of the fin portion, covering the sidewall of the bottom fin portion and exposing the effective fin portion.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure provided by this embodiment of the invention, a portion of the effective fin height is designated as a first fin portion, and the remaining effective fin height is designated as a second fin portion. The bottom linewidth of the first fin portion is smaller than the top linewidth of the first fin portion, and the top linewidth of the second fin portion is smaller than the top linewidth of the first fin portion. By reducing the bottom linewidth of the first fin portion, the control capability of the gate structure over the bottom of the effective fin portion is improved, thereby reducing the leakage current of the transistor. Furthermore, in this semiconductor structure, the influence on the top linewidth of the effective fin portion is relatively small, which helps to reduce the impact on the channel length of the transistor, and correspondingly reduces the on-current (I) of the transistor. ON In summary, by making the bottom linewidth of the first fin portion smaller than the top linewidth of the first fin portion, the morphology of the effective fin portion is altered, which is beneficial for improving the transistor's switching current ratio (I0). ON / I OFF This reduces the static power consumption of the transistor, thereby improving the performance of the semiconductor structure.

[0009] In the semiconductor structure formation method provided in this embodiment of the invention, a portion of the fin material layer is first etched to form an initial fin protruding from the remaining fin material layer. Then, the remaining fin material layer exposed by the initial fin is etched to form a fin protruding from the substrate. The fin includes, from bottom to top, a bottom fin, a first partial fin, and a second partial fin, with the second partial fin and the first partial fin constituting an effective fin. During the etching process of the portion of the fin material layer exposed by the initial fin, the second etching rate ratio is less than the first etching rate ratio. That is, compared to the etching process for forming the initial fin, the etching rate ratio is higher when etching the bottom fin. When the exposed portion of the fin material layer is thinner than the fin material layer, the etching process has a weaker anisotropic etching capability, i.e., a greater lateral etching capability. This results in the bottom linewidth of the first portion of the fin being smaller than the top linewidth of the first portion of the fin. Consequently, the sidewalls of the first portion of the fin gradually recede inward, thereby reducing the bottom linewidth of the first portion of the fin. This improves the gate structure's control over the effective fin bottom, thus reducing the transistor's leakage current. Moreover, the impact on the top linewidth of the effective fin is relatively small, which helps to reduce the impact on the transistor's channel length and correspondingly reduce the transistor's on-current (I). ON In summary, by making the bottom linewidth of the first fin portion smaller than the top linewidth of the first fin portion, the morphology of the effective fin portion is altered, which is beneficial for improving the transistor's switching current ratio (I0). ON / I OFF This reduces the static power consumption of the transistor, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a semiconductor structure.

[0011] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 3 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] The performance of current semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of one particular semiconductor structure needs further improvement.

[0014] Figure 1 This is a schematic diagram of a semiconductor structure.

[0015] The semiconductor structure includes: a substrate 10; a fin 20 protruding from the substrate 10, the fin 20 including a bottom fin 21 and an effective fin 22 located on the top surface of the bottom fin 21 from bottom to top; an isolation layer 30 located on the substrate 10 on the side of the fin 20, the isolation layer 30 covering the sidewall of the bottom fin 21 and exposing the effective fin 22; and a gate structure 40 located on the isolation layer 30, the gate structure 40 spanning the effective fin 22 and covering part of the top and part of the sidewall of the effective fin 22.

[0016] Generally, the gate structure 40 pairs with the bottom of the effective fin 22 (such as...). Figure 1 The control capability of the area (shown by the dashed circle) is the worst. Furthermore, the fin 20 is obtained by etching the fin material layer. Due to the etching process, the longitudinal cross-sectional shape of the fin 20 is typically trapezoidal. This means that the bottom linewidth (CD) of the fin 20 is usually larger than its top linewidth. This further reduces the control capability of the gate structure 40 over the bottom of the effective fin 22, resulting in a larger leakage current in the transistor, which in turn leads to a smaller switching current and consequently higher static power consumption. Therefore, the performance of the semiconductor structure deteriorates accordingly. Here, the switching current ratio refers to the transistor's on-state current (Ion). ON ) and turn-off current (I OFF The ratio of ).

[0017] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a fin material layer located on the substrate, the fin material layer being used to form a bottom fin and an effective fin located on the top surface of the bottom fin; etching a portion of the thickness of the fin material layer to form an initial fin protruding from the remaining fin material layer, wherein the ratio of the longitudinal etching rate to the lateral etching rate during etching is a first etching rate ratio; etching the remaining fin material layer exposed by the initial fin to form a fin protruding from the substrate, the fin comprising, from bottom to top, a bottom fin, a first fin, and an effective fin located on the top surface of the bottom fin; etching the remaining fin material layer to form a fin protruding from the substrate, the fin comprising, from bottom to top, a bottom fin, a first fin, and an effective fin located on the top surface of the bottom fin; etching the remaining fin material layer to form a fin protruding from the bottom fin ... bottom fin, the first fin, and an effective fin located on the top surface of the bottom fin; etching the remaining fin material layer to form a The fin is divided into a first fin portion and a second fin portion, which together with the first fin portion constitute an effective fin. A first etching process is performed on a portion of the fin material layer exposed from the initial fin portion to form the effective fin. The ratio of the longitudinal etching rate to the transverse etching rate of the first etching is a second etching rate ratio, which is less than the first etching rate ratio, to ensure that the bottom linewidth of the first fin portion is less than the top linewidth. An isolation layer is formed on the substrate on the side of the fin portion, covering the sidewall of the bottom fin portion and exposing the effective fin portion.

[0018] This invention improves the gate structure's control over the bottom of the effective fin by reducing the bottom linewidth of the first portion of the fin, thereby reducing the transistor's leakage current. Furthermore, the top linewidth of the effective fin has a relatively small impact on the semiconductor structure, which helps to reduce the influence on the transistor's channel length and, consequently, the influence on the transistor's on-state current. In summary, by making the bottom linewidth of the first portion of the fin smaller than the top linewidth, the morphology of the effective fin is altered, which helps to improve the transistor's switching current ratio and, consequently, reduces the transistor's static power consumption. Therefore, the performance of the semiconductor structure is improved.

[0019] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Specifically, Figure 2 It is a cross-sectional view along the direction perpendicular to the extension of the fin.

[0021] The semiconductor structure includes: a substrate 400; a fin 500 protruding from the substrate 400; and an isolation layer 440 located on the substrate 400 at the side of the fin 500, the isolation layer 440 covering a portion of the sidewall of the fin 500, the portion of the fin 500 exposed by the isolation layer 440 serving as an effective fin 500e, a portion of the effective fin 500e serving as a first partial fin 510, and the remaining portion of the effective fin 500e serving as a second partial fin 520, the first partial fin 510 being closer to the isolation layer 440, wherein the bottom linewidth cd3 of the first partial fin 510 is smaller than that of the first partial fin 520. The top linewidth cd2 of the second fin portion 520 is smaller than the top linewidth cd2 of the first fin portion 510; the gate structure 600 is located on the isolation layer 440, the gate structure 600 spans the effective fin portion 500e and covers part of the top and part of the sidewall of the effective fin portion 500e; the sidewall (not shown) is located on both sides of the gate structure 600 and covers the sidewall of the gate structure 600; the source / drain doped layer (not shown) is located in the effective fin portion 500e on both sides of the gate structure 600 and is located on the side of the sidewall away from the gate structure 600.

[0022] The substrate 400 is used to provide a process platform for the formation of semiconductor structures.

[0023] In this embodiment, the substrate 400 is made of silicon. In other embodiments, the substrate may be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0024] In this embodiment, the semiconductor structure is a fin field-effect transistor (FinFET), therefore, a fin 500 is formed on the substrate 400.

[0025] In this embodiment, the isolation layer 440 covers part of the sidewall of the fin 500, the fin 500 exposed by the isolation layer 440 is the effective fin 500e, and the fin 500 covered by the isolation layer 440 is the bottom fin 500b.

[0026] Therefore, the fin 500 includes a bottom fin 500b and an effective fin 500e located on the top surface of the bottom fin 500b, the bottom fin 500b being used to support the effective fin 500e, and the effective fin 500e being used to provide a channel for the transistor.

[0027] Specifically, the material of the fin 500 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials. The material of the fin 500 is determined according to the channel conductivity type and performance requirements of the transistor.

[0028] In this embodiment, the first fin portion 510 and the second fin portion 520 are an integral structure. Specifically, the bottom fin portion 500b, the first fin portion 510, the second fin portion 520, and the substrate 400 are an integral structure. Therefore, the fin portion 500 and the substrate 400 are made of the same material, and the material of the fin portion 500 is silicon. That is to say, the materials of the bottom fin portion 500b, the first fin portion 510, and the second fin portion 520 are all silicon.

[0029] It should be noted that the substrate 400 typically includes multiple regions for forming different types of transistors. Figure 2 Only one region is shown. In actual semiconductor structures, the material of the fin 500 is not limited to silicon, and the material of the fin 500 in different regions can also be different.

[0030] In this embodiment, the fin 500 includes, from bottom to top, a bottom fin 500b, a first partial fin 510, and a second partial fin 520, wherein the second partial fin 520 and the first partial fin 510 constitute an effective fin 500e. Here, "from bottom to top" refers to the direction from the bottom of the fin 500 towards the top.

[0031] like Figure 2 As shown, the interface between the first fin portion 510 and the second fin portion 520 is represented by a dashed line.

[0032] The bottom linewidth cd3 of the first fin portion 510 is smaller than the top linewidth cd2 of the first fin portion 510. That is, the angle between the sidewall of the first fin portion 510 and the surface of the substrate 400 is an acute angle. This reduces the bottom linewidth cd3 of the first fin portion 510, thereby improving the control capability of the gate structure 600 over the bottom of the effective fin portion 500e and reducing the leakage current of the transistor. Moreover, in the semiconductor structure, the influence on the top linewidth cd1 of the effective fin portion 500e is relatively small, which helps to reduce the influence on the channel length of the transistor and correspondingly reduce the influence on the conduction current of the transistor. In summary, by making the bottom linewidth cd3 of the first fin portion 510 smaller than the top linewidth cd2 of the first fin portion 510, the morphology of the effective fin portion 500e is changed, which helps to improve the switching current ratio of the transistor and correspondingly reduces the static power consumption of the transistor. Therefore, the performance of the semiconductor structure is improved.

[0033] Wherein, the bottom line width cd3 of the first fin portion 510 is smaller than the top line width cd2 of the first fin portion 510, and the top line width cd1 of the second fin portion 520 is smaller than the top line width cd2 of the first fin portion 510. This is beneficial to ensure that the top line width cd1 of the effective fin portion 500e is not too large, thereby reducing the bottom line width cd3 of the first fin portion 510 while reducing the impact on the top line width cd1 of the effective fin portion 500e.

[0034] For example, by reasonably setting the bottom linewidth cd2 of the second fin portion 520 and the height H of the second fin portion 520, it can be ensured that the top linewidth cd1 of the effective fin portion 500e can meet the requirements of transistor performance.

[0035] It is understood that the second fin portion 520 is located on the top surface of the first fin portion 510, and the sidewall of the second fin portion 520 is connected to the sidewall of the first fin portion 510. Therefore, the bottom line width cd2 of the second fin portion 520 is the top line width cd2 of the first fin portion 510.

[0036] Furthermore, by reducing the bottom linewidth cd3 of the first portion of the fin 510, the impact on the overall linewidth of the effective fin 500e is reduced, which helps to ensure the mechanical strength of the effective fin 500e and further improves the performance of the semiconductor structure.

[0037] As an example, since the bottom linewidth cd3 of the first fin portion 510 is smaller than the top linewidth cd2 of the first fin portion 510, and the top linewidth cd1 of the second fin portion 520 is smaller than the top linewidth cd2 of the first fin portion 510, the sidewall of the second fin portion 520 and the sidewall of the first fin portion 510 form an outwardly convex apex angle at their intersection. Specifically, the apex angle is arc-shaped.

[0038] During the formation of the semiconductor structure, after the fin 500 is formed, subsequent processes typically include multiple annealing processes (e.g., annealing during the formation of the isolation layer 440, and annealing during the formation of the gate structure 600). These annealing processes typically consume material from the fin 500, resulting in a rounded corner shape. Furthermore, by making the corners rounded, the probability of electric field concentration at the corner location is reduced, thereby reducing the probability of gate dielectric layer breakdown at the corner location.

[0039] In this embodiment, the top line width cd1 of the second fin portion 520 is smaller than the top line width cd2 of the first fin portion 510. Correspondingly, the top line width cd1 of the second fin portion 520 is smaller than the bottom line width cd2 of the second fin portion 520.

[0040] By making the top linewidth cd1 of the second fin portion 520 smaller than the bottom linewidth cd2 of the second fin portion 520, it is not only beneficial to improve the mechanical strength of the effective fin portion 500e, thereby reducing the probability of the effective fin portion 500e breaking, collapsing, or twisting during the formation of the semiconductor structure (e.g., in a wet cleaning process), but also beneficial to improve the line edge roughness (LER) of the sidewall of the second fin portion 520, thereby further improving the performance of the semiconductor structure.

[0041] Furthermore, by making the top linewidth cd1 of the second fin portion 520 smaller than the bottom linewidth cd2 of the second fin portion 520, a larger switching current ratio can be obtained.

[0042] The bottom linewidth cd3 of the first fin portion 510 should not be too small or too large. If the bottom linewidth cd3 of the first fin portion 510 is too small, the mechanical strength of the effective fin portion 500e is easily insufficient, increasing the probability of breakage, collapse, or twisting, thus degrading the performance of the semiconductor structure. If the bottom linewidth cd3 of the first fin portion 510 is too large, it is difficult to significantly improve the control capability of the gate structure 600 over the bottom of the effective fin portion 500e, thus easily leading to poor improvement in the switching current ratio of the transistor. Therefore, in this embodiment, the difference between the bottom linewidth cd3 of the first fin portion 510 and the top linewidth cd1 of the second fin portion 520 (i.e., the top linewidth cd1 of the effective fin portion 500e) is -1 nanometer to 0.5 nanometers. For example, the difference between the bottom linewidth cd3 of the first fin portion 510 and the top linewidth cd1 of the second fin portion 520 is -0.5 nanometers, 0 nanometers, or 0.2 nanometers.

[0043] In this embodiment, the bottom line width cd3 of the first fin portion 510 is close to the top line width cd1 of the second fin portion 520, which helps to ensure the mechanical strength of the effective fin portion 500e.

[0044] In this embodiment, the difference between the top line width cd2 and the bottom line width cd3 of the first fin portion 510 should not be too small or too large.

[0045] When the difference between the top linewidth cd2 and the bottom linewidth cd3 of the first fin portion 510 is too small, and the top linewidth cd2 of the first fin portion 510 meets the process requirements, the bottom linewidth cd3 of the first fin portion 510 becomes too large. This makes it difficult to significantly improve the control capability of the gate structure 600 over the bottom of the effective fin portion 500e, which in turn easily leads to an increase in the transistor's switching current ratio (I). ON / I OFF The effect is not good, or, when the bottom linewidth cd3 of the first fin portion 510 meets the process requirements, it is easy to cause the top linewidth cd2 of the first fin portion 510 to be too small. Since the top linewidth cd2 of the first fin portion 510 is the bottom linewidth of the second fin portion 520, this is likely to cause the top linewidth cd1 of the second fin portion 520 to be too small, thereby reducing the channel length of the transistor and consequently reducing the switching current ratio (I) of the transistor. ON / I OFF (It becomes smaller.)

[0046] When the difference between the top linewidth cd2 and the bottom linewidth cd3 of the first fin portion 510 is too large, if the top linewidth cd2 of the first fin portion 510 meets the process requirements, the bottom linewidth cd3 of the first fin portion 510 will be too small. This will easily lead to insufficient mechanical strength of the effective fin portion 500e, and the probability of the effective fin portion 500e breaking, collapsing, or twisting will increase accordingly. Alternatively, if the bottom linewidth cd3 of the first fin portion 510 meets the process requirements, the top linewidth cd2 of the first fin portion 510 will be too large, which will correspondingly lead to an excessively large overall linewidth of the second fin portion 520, thereby causing a shift in the electrical performance of the transistor.

[0047] Based on the above analysis, in this embodiment, the difference between the top linewidth cd2 and the bottom linewidth cd3 of the first fin portion 510 is greater than 0.5 nanometers and less than 2 nanometers. For example, the difference between the top linewidth cd2 and the bottom linewidth cd3 of the first fin portion 510 is 1 nanometer or 1.5 nanometers.

[0048] In this embodiment, the linewidth of the first portion of the fin 510 gradually decreases from top to bottom. Therefore, to ensure that the effective fin 500e has sufficient mechanical strength, the height H of the second portion of the fin 520 is greater than half of the total height (not shown) of the effective fin 500e. Here, "from top to bottom" refers to the direction from the top of the fin 500 to the bottom.

[0049] Furthermore, based on the analysis of the control capability of the gate structure 600 at each position of the effective fin 500e, the control capability of the gate structure 600 at the bottom of the effective fin 500e is the worst. Therefore, only the effective fin 500e at a certain height near the top surface of the isolation layer 440 is used as the first part of the fin 510, and the height of the first part of the fin 510 is relatively small. In this way, while improving the control capability of the gate structure 600 at the bottom of the effective fin 500e, the occurrence of side effects can be minimized.

[0050] It should be noted that the difference between the total height of the effective fin 500e and the height H of the second part of the fin 520 should not be too small or too large. If the difference between the total height of the effective fin 500e and the height H of the second fin portion 520 is too small, the height of the first fin portion 510 will be correspondingly too small. If the overall linewidth of the second fin portion 520 meets the process requirements, it may easily lead to an excessively large bottom linewidth cd3 of the first fin portion 510, or increase the difficulty of forming a first fin portion 510 with a bottom linewidth cd3 that meets the process requirements. Conversely, if the difference between the total height of the effective fin 500e and the height H of the second fin portion 520 is too large, the height H of the second fin portion 520 will be too small, and the height of the first fin portion 510 will be correspondingly too large. Since the linewidth of the first fin portion 510 gradually decreases from top to bottom, this may easily lead to a smaller overall linewidth of the effective fin 500e, resulting in a deviation in the electrical performance of the transistor and a reduction in the mechanical strength of the effective fin 500e. Therefore, in this embodiment, the difference between the total height of the effective fin 500e and the height H of the second fin portion 520 is... to For example, the difference between the total height of the effective fin 500e and the height H of the second partial fin 520 is

[0051] The isolation layer 440 is used to achieve electrical isolation between different transistors. Specifically, the isolation layer 440 is a shallow trench isolation (STI) structure.

[0052] The insulating layer 440 is made of an insulating material. As an example, the insulating layer 440 is made of silicon oxide. Silicon oxide has good insulation properties and generates relatively low stress, which is beneficial for improving process reliability.

[0053] In other embodiments, the material of the insulating layer may also be a suitable insulating material such as silicon oxynitride.

[0054] The gate structure 600 is used to control the opening or closing of the transistor's channel.

[0055] Specifically, the gate structure 600 includes a gate dielectric layer 610 and a gate electrode layer 620 covering the gate dielectric layer 610.

[0056] The gate dielectric layer 610 is used to isolate the gate electrode layer 620 and the channel.

[0057] The material of the gate dielectric layer 610 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0058] In this embodiment, the gate structure 600 is a metal gate structure. Therefore, the gate dielectric layer 610 includes a high-k gate dielectric layer.

[0059] The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the gate dielectric layer 610 is HfO2.

[0060] It should be noted that the gate dielectric layer may further include an interfacial layer (IL) located between the high-k gate dielectric layer and the effective fin 500e. The interfacial layer serves as the gate oxide layer. As an example, the material of the gate oxide layer may be silicon oxide.

[0061] The gate electrode layer 620 is used to bring out the electrical properties of the gate structure 600.

[0062] The material of the gate electrode layer 620 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0063] The gate electrode layer 620 may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 620 may only include the work function layer. The work function layer is used to adjust the threshold voltage of the formed transistor.

[0064] It should be noted that by reasonably setting the difference between the bottom linewidth cd3 of the first fin portion 510 and the top linewidth cd1 of the second fin portion 520, the difference between the top linewidth cd2 of the first fin portion 510 and the bottom linewidth cd3 of the first fin portion 510, and the height H of the second fin portion 520, it is ensured that the first fin portion 510 has sufficient height and that the angle between the sidewall of the first fin portion 510 and the surface of the substrate 400 is not too small (i.e., the inclination of the first fin portion 510 is not too large), thereby providing sufficient space for the gate structure 600 to cover the sidewall of the first fin portion 510, which is beneficial to ensuring the control capability of the gate structure 600 over the first fin portion 510.

[0065] It should also be noted that the semiconductor structure further includes: sidewalls (not shown), located on both sides of the gate structure 600 and covering the sidewalls of the gate structure 600; and source / drain doped layers (not shown), located in the effective fins 500e on both sides of the gate structure 600, and located on the side of the sidewalls away from the gate structure 600.

[0066] The sidewall is used to protect the sidewall of the gate structure 600 and also to define the formation location of the source and drain doped layers.

[0067] The sidewall can be a single-layer structure or a multi-layer structure, and the material of the sidewall includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the sidewall is a single-layer structure, and the material of the sidewall is silicon nitride.

[0068] The source and drain doped layers are used as the source or drain regions of the transistor.

[0069] Specifically, the doping type of the source / drain doped layer is the same as the channel conductivity type of the corresponding transistor. When the transistor is a PMOS transistor, the material of the source / drain doped layer includes silicon germanide doped with P-type ions, where the P-type ions include B, Ga, or In. When the transistor is an NMOS transistor, the material of the source / drain doped layer includes silicon or silicon carbide doped with N-type ions, where the N-type ions include P, As, or Sb.

[0070] Figures 3 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0071] refer to Figure 3 A substrate (not shown) is provided, including a substrate 100 and a fin material layer 110 on the substrate 100, the fin material layer 110 being used to form a bottom fin and an effective fin located on the top surface of the bottom fin.

[0072] The substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0073] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0074] In this embodiment, the forming method is used to form a fin field-effect transistor (FinFET). Therefore, the fin material layer 110 is used to form a fin, which includes a bottom fin and an effective fin located on the top surface of the bottom fin.

[0075] Specifically, the material of the fin material layer 110 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials. The material of the fin material layer 110 is determined according to the channel conductivity type and performance requirements of the transistor.

[0076] In this embodiment, the fin material layer 110 and the substrate 100 are an integral structure. Therefore, the fin material layer 110 and the substrate 100 are made of the same material, and the material of the fin material layer 110 is silicon.

[0077] It should be noted that the substrate 100 typically includes multiple regions for forming different types of transistors. Figure 3 Only one region is shown. In actual manufacturing, the material of the fin material layer 110 is not limited to silicon, and the material of the fin material layer 110 in different regions can also be different.

[0078] Continue to refer to Figure 3 The forming method further includes forming a fin mask layer 120 on the fin material layer 110.

[0079] The fin mask layer 120 is used as a mask for subsequent etching of the fin material layer 110.

[0080] The fin mask layer 120 is made of a hard mask (HM) material. The material of the fin mask layer 120 can be silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (aC), silicon oxycarbonide (SiOCN), or a stack thereof. In this embodiment, the material of the fin mask layer 120 is silicon nitride.

[0081] Specifically, the fin mask layer 120 can be formed by using self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), or double photolithography and etching (LELE) processes, depending on the process requirements.

[0082] refer to Figure 4 Etching a portion of the fin material layer 110 to form an initial fin 130 protruding from the remaining fin material layer 110 (e.g., ...). Figure 4 As shown in the figure, the ratio of the longitudinal etching rate to the transverse etching rate during etching is the first etching rate ratio.

[0083] The initial fin 130 is used to prepare for the subsequent formation of fins protruding from the substrate 100.

[0084] In this embodiment, the remaining fin material layer 110 exposed by the initial fin 130 is subsequently etched to form a fin protruding on the substrate 100. The fin includes a bottom fin, a first part fin, and a second part fin from bottom to top. The second part fin and the first part fin constitute an effective fin. The initial fin 130 is used to form an effective fin.

[0085] In the subsequent etching process of the fin material layer of the initial fin 130 exposed by a certain thickness, the lateral etching capability of the etching process is increased by reducing the ratio of the longitudinal etching rate to the lateral etching rate, thereby making the bottom line width of the first part of the fin smaller than the top line width of the first part of the fin, thus achieving the effect of reducing the bottom line width of the first part of the fin.

[0086] In this embodiment, the angle α between the sidewall of the initial fin 130 and the surface of the remaining fin material layer 110 is an obtuse angle, that is, the shape of the initial fin 130 is trapezoidal.

[0087] By making the angle α between the sidewall of the initial fin 130 and the surface of the remaining fin material layer 110 obtuse, the top linewidth of the second part of the fin can be smaller than the bottom linewidth of the second part of the fin after the effective fin is formed. This not only helps to improve the mechanical strength of the effective fin, thereby reducing the probability of the effective fin breaking, collapsing or twisting during the formation of the semiconductor structure (e.g., in a wet cleaning process), but also helps to improve the line edge roughness of the sidewall of the second part of the fin, thereby further improving the performance of the semiconductor structure.

[0088] Correspondingly, the angle α between the sidewall of the initial fin 130 and the surface of the remaining fin material layer 110 should not be too small or too large. If the angle α between the sidewall of the initial fin 130 and the surface of the remaining fin material layer 110 is too small, it is easy to form an inverted trapezoidal effective fin, thereby reducing the mechanical strength of the effective fin, increasing the probability of the effective fin breaking, collapsing or twisting, and also easily reducing the line edge roughness of the sidewall of the effective fin, which is not conducive to improving the performance of the semiconductor structure. If the angle α between the sidewall of the initial fin 130 and the surface of the remaining fin material layer 110 is too large, during the subsequent etching of the remaining fin material layer 110 exposed by the initial fin 130, if the etching time is not long enough under the condition of a large lateral etching rate, it is easy to cause the overall linewidth of the part of the fin corresponding to the initial fin 130 to be too large, thereby reducing the gate structure's control capability over the channel, and thus causing the leakage current to increase. Therefore, in this embodiment, the angle α between the sidewall of the initial fin 130 and the surface of the remaining fin material layer 110 is 95 degrees to 100 degrees.

[0089] The angle α between the sidewall of the initial fin 130 and the surface of the remaining fin material layer 110 mentioned here refers to the angle between the sidewall of the initial fin 130 and the surface of the remaining fin material layer 110 located on the side of the initial fin 130. Therefore, the larger the angle α, the greater the inclination of the sidewall of the initial fin 130.

[0090] In this embodiment, the fin mask layer 120 is used as a mask to etch a portion of the thickness of the fin material layer 110.

[0091] Specifically, the etching process for the fin material layer 110 of the etched portion thickness is a plasma etching process, which includes a bias power pulse etching process or a synchronous pulse etching process.

[0092] Among them, the bias power pulse etching process refers to a process where the source power is constant and the bias power is in pulse mode; the synchronous pulse etching process refers to a process where both the source power and the bias power are in pulse mode, and the pulse modes of the source power and the bias power are at the same frequency and in phase. That is to say, when the source power is in the high level segment, the bias power is also in the high level segment, and when the source power is in the low level segment, the bias power is also in the low level segment. The pulse modes of the source power and the bias power are rectangular waves.

[0093] Compared with etching processes where both source power and bias power are constant, by selecting bias power pulse etching or synchronous pulse etching and reasonably adjusting etching parameters, it is easier to obtain a narrower ion angle distribution, thereby obtaining better etching anisotropic etching characteristics, i.e., obtaining a larger first etching rate ratio. This makes it easier to obtain an initial fin 130 with inclined and smooth sidewalls, and ensures that the sidewall morphology and linewidth of the initial fin 130 can meet the process requirements. This provides a good process foundation for subsequent etching processes.

[0094] As an example, in the step of etching a portion of the fin material layer 110, the etching process is a synchronous pulse etching process. By selecting a synchronous pulse etching process, a narrower ion angle distribution can be obtained, thereby achieving stronger anisotropic etching capability.

[0095] It should be noted that the ratio of the longitudinal etching rate to the transverse etching rate during etching is the first etching rate ratio. Accordingly, to obtain strong anisotropic etching capability, the first etching rate ratio should not be too small. When the first etching rate ratio is too small, it can easily lead to excessively strong transverse etching capability, making it difficult to obtain a trapezoidal initial fin 130. It can also easily cause the angle α between the sidewall of the initial fin 130 and the surface of the remaining fin material layer 110, as well as the overall linewidth of the initial fin 130, to fail to meet process requirements. Therefore, in this embodiment, the first etching rate ratio is greater than 5:1.

[0096] The linewidth refers to the width dimension of the initial fin 130 along the direction perpendicular to the extension direction of the initial fin 130.

[0097] Accordingly, based on the top linewidth and height requirements of the initial fin 130, and the angle α between the sidewall of the initial fin 130 and the surface of the remaining fin material layer 110, the etching parameters of the synchronous pulse etching process are reasonably set.

[0098] The subsequently formed effective fins have a preset effective height, which is determined according to the transistor's performance. Specifically, in the step of etching a portion of the fin material layer 110, the height D1 of the initial fin 130 should not be too small or too large. If the height D1 of the initial fin 130 is too small, the height of the subsequently formed second fin portion will be too small, and the height of the first fin portion will be correspondingly too large. Since the linewidth of the first fin portion gradually decreases from top to bottom, this can easily lead to a smaller overall linewidth of the effective fin, resulting in a shift in the transistor's electrical performance and potentially reducing the mechanical strength of the effective fin. If the height D1 of the initial fin 130 is too large, the height of the first fin portion will easily be too small. Even if the overall linewidth of the second fin portion meets the process requirements, this can easily lead to an excessively large bottom linewidth of the first fin portion, or increase the difficulty of forming a first fin portion with a bottom linewidth that meets the process requirements. Therefore, in this embodiment, the difference between the height D1 of the initial fin 130 and the preset effective height is... to

[0099] It should be noted that, as described above, during the subsequent etching of the exposed portion of the fin material layer 110 of the initial fin 130, the lateral etching capability of the etching process is increased by reducing the ratio of the longitudinal etching rate to the lateral etching rate. This results in the bottom linewidth of the first fin portion being smaller than the top linewidth of the first fin portion. Consequently, the sidewall of the second fin portion and the sidewall of the first fin portion form an outwardly convex apex angle at their intersection. However, during the subsequent etching of the exposed portion of the fin material layer 110 of the initial fin 130, a certain amount of etching is easily produced on the initial fin 130. Therefore, the bottom surface of the initial fin 130 to the substrate... The distance from the bottom 100 may not be equal to the distance from the bottom surface of the second fin to the substrate 100. In other words, the initial fin 130 may not be the same as the second fin. Moreover, after the fin is formed, it needs to undergo multiple annealing processes (e.g., annealing during the process of forming the isolation layer and annealing during the process of forming the gate structure). Due to the influence of the annealing process, the position of the apex may move up and down. Therefore, even if the height D1 of the initial fin 130 is greater than or equal to the preset effective height, the height of the final effective fin can still reach the preset effective height according to the actual process conditions, and a first fin with a smaller bottom linewidth can be obtained.

[0100] refer to Figure 5 Etching the initial fin 130 (e.g.) Figure 4The remaining fin material layer 110 exposed (as shown) forms a fin 200 protruding from the substrate 100. The fin 200 includes a bottom fin 200b, a first part fin 210 and a second part fin 220 from bottom to top. The second part fin 220 and the first part fin 210 constitute an effective fin 200e. During the etching of the fin material layer 110 with a thickness of the exposed portion of the initial fin 130, the ratio of the longitudinal etching rate to the transverse etching rate is a second etching rate ratio. The second etching rate ratio is less than the first etching rate ratio, which is used to make the bottom linewidth cd3 of the first part fin 210 less than the top linewidth cd2 of the first part fin 210.

[0101] The bottom fin 200b is used to support the effective fin 200e, which is used to provide a channel for the transistor.

[0102] Specifically, the step of etching the remaining fin material layer 110 exposed by the initial fin 130 includes: performing a first etching process on the portion of the fin material layer 110 exposed by the initial fin 130 to form an effective fin 200e protruding from the remaining fin material layer 110, wherein the ratio of the longitudinal etching rate to the transverse etching rate of the first etching is a second etching rate ratio, and the second etching rate ratio is less than the first etching rate ratio, so that the bottom linewidth cd3 of the first portion of the fin 210 is less than the top linewidth cd2 of the first portion of the fin 210; and performing a second etching process on the remaining fin material layer 110 exposed by the effective fin 200e to form a bottom fin 200b.

[0103] During the first etching process, the second etching rate ratio is less than the first etching rate ratio. That is, compared with the etching process for forming the initial fin 130, when etching the exposed portion of the fin material layer 110 of the initial fin 130, the etching process has a weaker anisotropic etching capability, i.e., a greater lateral etching capability. This causes the sidewalls of the first fin portion 210 to gradually recede inward, thereby reducing the bottom linewidth cd3 of the first fin portion 210. This correspondingly improves the control capability of the subsequent gate structure over the bottom of the first fin portion 210, thereby reducing the leakage current of the transistor. Moreover, the formation method has a smaller impact on the top linewidth of the effective fin portion 200, which helps to reduce the impact on the channel length of the transistor and correspondingly reduce the impact on the conduction current of the transistor.

[0104] In summary, by making the bottom linewidth cd3 of the first fin portion 210 smaller than the top linewidth cd2 of the first fin portion 210, the morphology of the effective fin portion 200e is changed, which is beneficial to improving the switching current ratio of the transistor and correspondingly reducing the static power consumption of the transistor. Therefore, the performance of the semiconductor structure is improved.

[0105] As an example, since the bottom linewidth cd3 of the first fin portion 210 is smaller than the top linewidth cd2 of the first fin portion 210, the sidewall of the second fin portion 220 and the sidewall of the first fin portion 210 form an outwardly convex apex angle at their intersection (e.g., Figure 5 (As shown by the dashed coil in the middle).

[0106] In this embodiment, the remaining fin material layer 110 exposed by the initial fin 130 is etched using the fin mask layer 120 as a mask.

[0107] It should be noted that after the fin 200 is formed, the effective fin 200e includes the first part fin 210 and the second part fin 220 located on top of the first part fin 210. Therefore, the height H of the second part fin 220 is correspondingly smaller than the preset effective height of the effective fin 200e.

[0108] The difference between the preset effective height and the height H of the second fin portion 220 should not be too small or too large. If the difference is too small, the height of the first fin portion 210 will be too small. If the overall linewidth of the second fin portion 220 meets the process requirements, the bottom linewidth cd3 of the first fin portion 210 may become too large, or the process difficulty of forming a first fin portion 210 with a bottom linewidth cd3 that meets the process requirements may increase. If the difference is too large, the height H of the second fin portion 220 will be too small, and the height of the first fin portion 210 will become too large. Since the linewidth of the first fin portion 210 gradually decreases from top to bottom, this may lead to a smaller overall linewidth of the effective fin portion 200e, resulting in a shift in the electrical performance of the transistor and a reduction in the mechanical strength of the effective fin portion 200e. Therefore, in this embodiment, the difference between the preset effective height and the height H of the second fin portion 220 is... to

[0109] The bottom linewidth cd3 of the first fin portion 210 should not be too small or too large. When the bottom linewidth cd3 of the first fin portion 210 is too small, the mechanical strength of the effective fin portion 200e is easily too small, which increases the probability of the effective fin portion 200e breaking, collapsing, or twisting, thereby leading to a decrease in the performance of the semiconductor structure. When the bottom linewidth cd3 of the first fin portion 210 is too large, it is difficult to significantly improve the control capability of the gate structure over the bottom of the effective fin portion 200e, which easily leads to poor effect in improving the switching current ratio of the transistor. Therefore, in this embodiment, the difference between the bottom linewidth cd3 of the first fin portion 210 and the top linewidth cd1 of the second fin portion 220 (i.e., the top linewidth cd1 of the effective fin portion 200e) is -1 nanometer to 1 nanometer.

[0110] The bottom line width cd3 of the first fin portion 210 is close to the top line width cd1 of the second fin portion 220, which helps to ensure the mechanical strength of the effective fin portion 200e.

[0111] In this embodiment, the difference between the top line width cd2 and the bottom line width cd3 of the first fin portion 210 should not be too small or too large.

[0112] When the difference between the top linewidth cd2 and the bottom linewidth cd3 of the first fin portion 210 is too small, if the top linewidth cd2 of the first fin portion 210 meets the process requirements, the bottom linewidth cd3 of the first fin portion 210 will be too large. This will make it difficult to significantly improve the control capability of the gate structure over the bottom of the effective fin portion 200e, which will easily lead to poor performance in improving the switching current ratio of the transistor. Alternatively, if the bottom linewidth cd3 of the first fin portion 210 meets the process requirements, the top linewidth cd2 of the first fin portion 210 will be too small. Since the top linewidth cd2 of the first fin portion 210 is the bottom linewidth of the second fin portion 220, this will correspondingly lead to a smaller top linewidth cd1 of the second fin portion 220, which will result in a smaller channel length of the transistor and a smaller switching current ratio of the transistor.

[0113] When the difference between the top linewidth cd2 and the bottom linewidth cd3 of the first fin portion 210 is too large, if the top linewidth cd2 of the first fin portion 210 meets the process requirements, the bottom linewidth cd3 of the first fin portion 210 will be too small. This will easily lead to insufficient mechanical strength of the effective fin portion 200e, and the probability of the effective fin portion 200e breaking, collapsing, or twisting will increase accordingly. Alternatively, if the bottom linewidth cd3 of the first fin portion 210 meets the process requirements, the top linewidth cd2 of the first fin portion 210 will be too large, which will correspondingly lead to an excessively large overall linewidth of the second fin portion 220, thereby causing a shift in the electrical performance of the transistor.

[0114] Based on the above analysis, in this embodiment, the difference between the top linewidth cd2 and the bottom linewidth cd3 of the first fin portion 210 is 1 nanometer to 3 nanometers.

[0115] It should be noted that during the formation of the effective fin 200e, in order to reduce the anisotropic etching capability (i.e., reduce the ratio of longitudinal etching rate to lateral etching rate), the second etching rate ratio should not be too small or too large. When the second etching rate ratio is too small, it is easy to cause the lateral etching capability to be too strong, resulting in severe lateral etching of the initial fin 130, which in turn leads to an excessively small linewidth of the second fin 220, thereby causing a shift in the electrical performance of the transistor, and also easily leading to insufficient mechanical strength of the effective fin 200e; when the second etching rate ratio is too large, the effect of reducing the anisotropic etching capability is not good, resulting in an ineffective reduction of the bottom linewidth cd3 of the first fin 210. Therefore, in this embodiment, the second etching rate ratio is 3:1 to 5:1.

[0116] In the step of performing the first etching process on the exposed portion of the fin material layer 110 of the initial fin 130, the etching depth should not be too small or too large. If the etching depth is too small, the bottom linewidth cd3 of the first portion of the fin 210 may be too large, which is not conducive to reducing the leakage current of the transistor. If the etching depth is too large, due to the weak anisotropic etching capability of the first etching process, the minimum linewidth of the fin 200 may be too small, thereby reducing the mechanical strength of the fin 200. Therefore, in this embodiment, the etching depth is... to For example, the etching depth is

[0117] In this embodiment, the initial fin 130 is etched (e.g., Figure 4The process of the exposed remaining fin material layer 110 (as shown) includes bias power pulse etching process or synchronous pulse etching process.

[0118] Compared with etching processes where both source power and bias power are constant, by selecting bias power pulse etching or synchronous pulse etching, different ion angle distributions can be obtained by adjusting the etching parameters. This allows for adjustment of the ratio of longitudinal etching rate to lateral etching rate to meet the etching effect required by the process, which helps to reduce the complexity of the etching process.

[0119] In this embodiment, the process of etching the remaining fin material layer 110 exposed by the initial fin 130 is a bias power pulse etching process.

[0120] Based on the aforementioned characteristics of bias power pulse etching process and synchronous pulse etching process, in this embodiment, in the same etching process, after etching a portion of the thickness of the fin material layer 110, the etching parameters are adjusted to etch the remaining fin material layer 110 exposed by the initial fin 130.

[0121] Etching processes with constant source power and bias power are difficult to achieve significant differences in ion angular distribution by adjusting etching parameters. Therefore, by selecting bias power pulse etching or synchronous pulse etching, fin material layers 110 of different thicknesses can be etched in the same etching process by adjusting etching parameters in real time, thereby forming fins 200. This simplifies the etching process for forming fins 200 and improves manufacturing efficiency accordingly.

[0122] Moreover, forming the fin 200 in the same etching process allows etching to be performed without air break, which is beneficial for improving process stability and reliability.

[0123] In this embodiment, based on the angle α between the sidewall of the initial fin 130 and the surface of the remaining fin material layer 110, after the first etching process, the remaining fin material layer 110 exposed by the effective fin 200e is subjected to multiple second etching processes. The second etching process includes sequentially performing a first sub-etch and a second sub-etch. The ratio of the longitudinal etching rate to the transverse etching rate of the first sub-etch is the third etching rate ratio, and the ratio of the longitudinal etching rate to the transverse etching rate of the second sub-etch is the fourth etching rate ratio. The third etching rate ratio is greater than the second etching rate ratio, and the fourth etching rate ratio is less than the third etching rate ratio.

[0124] If only an etching process with strong anisotropic etching capability is used for etching, the apex angle formed by the intersection of the sidewall of the second part fin 220 and the sidewall of the first part fin 210 can be easily eliminated, thus easily forming an inverted trapezoidal effective fin 200e. This reduces the mechanical strength of the effective fin 200e and increases the probability of the effective fin 200e breaking, collapsing, or twisting. It also easily reduces the line edge roughness of the sidewall of the effective fin 200e, which is not conducive to improving the performance of the semiconductor structure. If only an etching process with weak anisotropic etching capability is used for etching, the strong lateral etching capability of this etching process can easily cause lateral etching of the effective fin 200e, thus affecting the morphology and linewidth of the effective fin 200e. Furthermore, severe lateral etching can easily lead to excessively low mechanical strength of the effective fin 200e.

[0125] Therefore, in this embodiment, when etching the remaining fin material layer 110 exposed by the effective fin 200e, if the third etching rate ratio is greater than the second etching rate ratio, the first sub-etching has a stronger anisotropic etching capability. If the fourth etching rate ratio is less than the third etching rate ratio, the second sub-etching has a weaker anisotropic etching capability. After etching a portion of the fin material layer 110 through the first sub-etching, the second sub-etching, which has a stronger lateral etching capability, continues to etch a portion of the fin material layer 110 while maintaining the apex angle formed by the intersection of the sidewall of the second part of the fin 220 and the sidewall of the first part of the fin 210 (that is, maintaining the morphology of the effective fin 200e). Therefore, by alternating between the first and second sub-etching, the bottom fin 200b with a morphology and linewidth that meet the process requirements is formed, while reducing the impact on the morphology and linewidth of the effective fin 200e.

[0126] It should be noted that when the third etching rate ratio is too small, it can easily lead to excessively strong lateral etching capability, which can easily cause lateral etching of the effective fin 200e, thereby affecting the morphology, linewidth, and mechanical strength of the effective fin 200e. Moreover, it can also easily lead to an excessively small linewidth of the bottom fin 200b, resulting in poor mechanical strength of the fin 200. Therefore, in this embodiment, the third etching rate ratio is greater than 5:1.

[0127] It should also be noted that the fourth etching rate ratio should not be too small or too large. When the fourth etching rate ratio is too small, it is easy to cause excessive lateral etching capability, resulting in severe lateral etching of the effective fin 200e, which in turn affects the morphology, linewidth, and mechanical strength of the effective fin 200e. Moreover, it is also easy to cause the linewidth of the bottom fin 200b to be too small, resulting in poor mechanical strength of the fin 200. When the fourth etching rate ratio is too large, it is easy to eliminate the apex angle formed by the intersection of the sidewall of the second part of the fin 220 and the sidewall of the first part of the fin 210. Therefore, in this embodiment, the fourth etching rate ratio is 3:1 to 5:1.

[0128] Furthermore, in other embodiments, when the angle between the initial fin sidewall and the surface of the remaining fin material layer is larger, the second etching process can also use the same etching parameters as the first etching process. That is, under the same etching parameters, the remaining fin material layer exposed by the initial fin is etched, and the first and second etching processes are the same etching step. In the above embodiments, even if only an etching process with strong lateral etching capability is used to etch the remaining fin material layer exposed by the initial fin, because the initial fin has a large sidewall inclination and a large bottom linewidth, the etching process has a large process window, and effective fins and bottom fins with morphology and size that meet the process requirements can still be obtained.

[0129] Reference Figure 6 and Figure 7 An isolation layer 140 is formed on the substrate 100 on the side of the fin 200. The isolation layer 140 covers the sidewall of the bottom fin 200b and exposes the effective fin 200e.

[0130] The isolation layer 140 is used to achieve electrical isolation between different transistors. Specifically, the isolation layer 140 is a shallow trench isolation structure.

[0131] The insulating layer 140 is made of an insulating material. As an example, the insulating layer 140 is made of silicon oxide. Silicon oxide has good insulation properties and generates relatively low stress, which is beneficial for improving process reliability. In other embodiments, the insulating layer can also be made of suitable insulating materials such as silicon oxynitride.

[0132] Specifically, the steps for forming the isolation layer 140 include: Figure 6 As shown, an isolation material layer is formed on the substrate 100 on the side of the fin 200, and the isolation material layer covers the fin mask layer 120; the isolation material layer is planarized with the top of the fin mask layer 120 as the stop position to form an initial isolation layer 130; the initial isolation layer 130 is subjected to a first annealing treatment; as shownFigure 7 As shown, after the first annealing process, the initial isolation layer 130 of a certain thickness is etched back to expose the effective fin 200e, and the remaining initial isolation layer 130 covering the sidewall of the bottom fin 200b serves as the isolation layer 140.

[0133] The initial isolation layer 130 is subjected to a first annealing process to improve its density.

[0134] It should be noted that the process temperature of the first annealing treatment should not be too low or too high. If the process temperature of the first annealing treatment is too low, the effect of improving the density of the initial isolation layer 130 will be correspondingly worse, which is not conducive to improving the quality and performance of the isolation layer 140. Since the fins 200 will be consumed during the first annealing treatment, if the process temperature of the first annealing treatment is too high, it is easy to cause excessive consumption of the fins 200, thereby adversely affecting the morphology and linewidth of the fins 200, which may in turn cause the electrical performance of the transistor to deviate.

[0135] Based on the above analysis, when setting the process temperature for the first annealing treatment, it is necessary not only to consider the quality and performance of the isolation layer 140, but also to minimize the impact on the morphology and linewidth of the fin 200. In this embodiment, the process temperature for the first annealing treatment is 650 degrees Celsius to 900 degrees Celsius.

[0136] As an example, after the first annealing process and before etching back a portion of the initial isolation layer 130, the process further includes removing the fin mask layer 120. Removing the fin mask layer 120 before etching back a portion of the initial isolation layer 130 improves the etching efficiency of the initial isolation layer 130. In other embodiments, depending on process requirements, the fin mask layer may also be removed after etching back a portion of the initial isolation layer.

[0137] In other embodiments, the process sequence of the first annealing treatment and other steps can be adjusted according to process requirements. For example, after forming an isolation material layer on the substrate on the side of the fin, the isolation material layer is subjected to the first annealing treatment.

[0138] It should be noted that the formation method further includes: forming a dummy gate structure (not shown) on the isolation layer 140, the dummy gate structure spanning the effective fin 200e and covering part of the top and part of the sidewalls of the effective fin 200e; forming a sidewall on the sidewall of the dummy gate structure; after forming the sidewall, forming source / drain doped layers (not shown) in the effective fins 200e on both sides of the dummy gate structure, and the source / drain doped layers are located on the side of the sidewall away from the dummy gate structure; forming an interlayer dielectric layer (not shown) covering the source / drain doped layers on the isolation layer 140, the interlayer dielectric layer covering the sidewalls of the dummy gate structure and exposing the top of the dummy gate structure; removing the dummy gate structure and forming a gate opening (not shown) in the interlayer dielectric layer.

[0139] The specific descriptions of the above steps will not be repeated here.

[0140] Reference Figure 8 and Figure 10 The forming method further includes: forming a gate structure 300 on the isolation layer 140 (e.g., Figure 10 As shown, the gate structure 300 spans the effective fin 200e and covers part of the top and part of the sidewalls of the effective fin 200e. The gate structure 300 includes a gate dielectric layer 310 and a gate electrode layer 320 covering the gate dielectric layer 310.

[0141] The gate structure 300 is used to control the opening or closing of the transistor's channel.

[0142] In this embodiment, the gate structure 300 is a metal gate structure.

[0143] In other embodiments, the gate structure may be other types of gate structures, depending on the transistor performance requirements. For example, the gate structure may be a polysilicon gate structure.

[0144] refer to Figure 9 A gate dielectric layer 310 is formed covering the top and sidewalls of the effective fin 200e and the top of the isolation layer 140.

[0145] Specifically, the gate dielectric layer 310 covers the top and sidewalls of the effective fin 200e exposed by the gate opening, as well as the top of the isolation layer 140.

[0146] The gate dielectric layer 310 is used to isolate the gate electrode layer 320 and the channel.

[0147] The material of the gate dielectric layer 310 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0148] Therefore, the gate dielectric layer 310 includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, where a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the gate dielectric layer 310 is HfO2.

[0149] It should be noted that the gate dielectric layer 310 may further include an interface layer located between the high-k gate dielectric layer and the effective fin. The interface layer serves as the gate oxide layer. As an example, the material of the gate oxide layer may be silicon oxide.

[0150] refer to Figure 9 A gate electrode layer 320 is formed covering the gate dielectric layer 310.

[0151] Specifically, the gate electrode layer 320 is formed in the remaining space of the gate opening.

[0152] The gate electrode layer 320 is used to draw out the electrical properties of the gate structure 30.

[0153] The material of the gate electrode layer 320 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0154] The gate electrode layer 320 may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 320 may only include the work function layer. The work function layer is used to adjust the threshold voltage of the formed transistor.

[0155] In this embodiment, the process of forming the gate structure 300 further includes a second annealing process, which includes one or both of post nitridation annealing (PNA) and post HKdeposition annealing (PDA).

[0156] Specifically, before forming the gate electrode layer 320 (e.g., before forming the high-k gate dielectric layer), the gate oxide layer is typically subjected to decoupled plasma nitridation (DPN) treatment. Therefore, the second annealing process includes a post-nitridation annealing process. This post-nitridation annealing process is used to solidify the nitrogen ions incorporated into the gate oxide layer, thereby improving nitrogen fixation efficiency.

[0157] Furthermore, after forming the high-k gate dielectric layer, a post-deposition annealing process is performed on the high-k gate dielectric layer to repair it, thereby improving the quality and performance of the high-k gate dielectric layer.

[0158] Specifically, depending on the process requirements, the post-deposition annealing process can be performed before the formation of the gate electrode layer 320, or after the formation of the power function layer and before the formation of the electrode layer.

[0159] It should be noted that the process temperature of the second annealing process should not be too low or too high. If the process temperature of the second annealing process is too low, it is easy to lead to poor performance of the gate structure 300, resulting in poor transistor performance. Since the fin 200 is consumed during the second annealing process, if the process temperature of the second annealing process is too high, it is easy to lead to excessive consumption of the fin 200, which will adversely affect the morphology and linewidth of the fin 200, and may even cause the electrical performance of the transistor to deviate.

[0160] Based on the above analysis, when setting the process temperature for the second annealing process during the formation of the gate structure 300, it is necessary to consider not only the transistor performance but also to minimize the impact on the morphology and linewidth of the fin 200. In this embodiment, the process temperature for the second annealing process is 700 degrees Celsius to 950 degrees Celsius.

[0161] In this embodiment, after deposition and annealing, the difference between the bottom linewidth cd3 of the first fin portion 210 and the top linewidth cd1 of the second fin portion 220 (i.e., the top linewidth cd1 of the effective fin portion 200e) is -1 nm to 0.5 nm; the difference between the top linewidth cd2 of the first fin portion 210 and the bottom linewidth cd3 of the first fin portion 210 is greater than 0.5 nm and less than 2 nm; the difference between the preset effective height (i.e., the total height of the effective fin portion 200e) and the height H of the second fin portion 220 is... to

[0162] In this embodiment, the height H of the second fin portion 220 is greater than half of the preset effective height. The linewidth of the first fin portion 210 gradually decreases from top to bottom. By ensuring that the height H of the second fin portion 220 exceeds half of the preset effective height, it is beneficial to ensure that the effective fin portion 200 has sufficient mechanical strength. Here, "from top to bottom" refers to the direction from the top to the bottom of the effective fin portion 200e.

[0163] Furthermore, based on the analysis of the control capability of the gate structure 300 at each position of the effective fin 200e, the control capability of the gate structure 300 at the bottom of the effective fin 200e is the worst. Therefore, only the effective fin 200e at a certain height near the top surface of the isolation layer 140 is designated as the first part of the fin 210, and the height of the first part of the fin 210 is relatively small. In this way, while improving the control capability of the gate structure 300 at the bottom of the effective fin 200e, the occurrence of side effects can be minimized.

[0164] Accordingly, by reasonably setting the size of the fin 200 after its formation, as well as the process conditions of subsequent processes, the final size and shape of the fin 200 can meet the process requirements.

[0165] In this embodiment, by reasonably setting the difference between the bottom linewidth cd3 of the first fin portion 210 and the top linewidth cd1 of the second fin portion 220, the difference between the top linewidth cd2 of the first fin portion 210 and the bottom linewidth cd3 of the first fin portion 210, and the height H of the second fin portion 220, it is ensured that the first fin portion 210 has sufficient height and that the angle between the sidewall of the first fin portion 210 and the surface of the substrate 100 is not too small (i.e., the tilt angle of the first fin portion 210 is not too large), thereby providing sufficient space for the gate structure 300 to cover the sidewall of the first fin portion 210, which is beneficial to ensuring the control capability of the gate structure 300 over the first fin portion 210.

[0166] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The fins protrude from the substrate; An isolation layer is located on the substrate on the side of the fin. The isolation layer covers a portion of the sidewall of the fin. The fin exposed by the isolation layer is the effective fin. A portion of the effective fin is designated as the first part of the fin, and the remaining portion of the effective fin is designated as the second part of the fin. The first part of the fin is closer to the isolation layer. The bottom linewidth of the first part of the fin is smaller than the top linewidth of the first part of the fin, and the top linewidth of the second part of the fin is smaller than the top linewidth of the first part of the fin. The sidewall of the second part of the fin and the sidewall of the first part of the fin form an outwardly convex apex angle at their intersection. The angle between the sidewall of the first part of the fin and the substrate surface is an acute angle. A gate structure is located on the isolation layer, the gate structure spans the effective fin and covers part of the top and part of the sidewalls of the effective fin; Sidewalls are located on both sides of the gate structure and cover the sidewalls of the gate structure; The source and drain doped layers are located in the effective fins on both sides of the gate structure, and are located on the side of the sidewall away from the gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, The difference between the bottom linewidth of the first fin portion and the top linewidth of the second fin portion is -1 nanometer to 0.5 nanometers.

3. The semiconductor structure as described in claim 1, characterized in that, The difference between the top linewidth and the bottom linewidth of the first fin portion is greater than 0.5 nanometers and less than 2 nanometers.

4. The semiconductor structure as described in claim 1, characterized in that, The height of the second part of the fin is greater than half of the total height of the effective fin.

5. The semiconductor structure as described in claim 4, characterized in that, The difference between the total height of the effective fin and the height of the second part of the fin is 100 Å to 200 Å.

6. The semiconductor structure as described in claim 1, characterized in that, The fins are made of silicon, silicon germanide, germanium, or group III-V semiconductor materials.

7. The semiconductor structure as described in claim 1, characterized in that, The gate structure includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer; the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3, and the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a fin material layer on the substrate, the fin material layer being used to form a bottom fin and an effective fin located on the top surface of the bottom fin; The fin material layer of a certain thickness is etched to form an initial fin that protrudes from the remaining fin material layer, and the ratio of the longitudinal etching rate to the transverse etching rate during etching is a first etching rate ratio. The remaining fin material layer exposed by the initial fin is etched to form a fin protruding from the substrate. The fin includes a bottom fin, a first part fin, and a second part fin from bottom to top. The second part fin and the first part fin constitute an effective fin. The fin material layer of a certain thickness exposed by the initial fin is subjected to a first etching process to form the effective fin. The ratio of the longitudinal etching rate to the transverse etching rate of the first etching is a second etching rate ratio. The second etching rate ratio is less than the first etching rate ratio, so that the bottom linewidth of the first part fin is less than the top linewidth of the first part fin. An isolation layer is formed on the substrate on the side of the fin, the isolation layer covering the sidewall of the bottom fin and exposing the effective fin.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of etching a portion of the thickness of the fin material layer, the angle between the initial fin sidewall and the surface of the remaining fin material layer is an obtuse angle.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The first etching rate ratio is greater than 5:1, and the second etching rate ratio is 3:1 to 5:

1.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of etching the remaining fin material layer exposed by the initial fin further includes: After the first etching process, the remaining fin material layer exposed by the effective fin is subjected to multiple second etching processes to form the bottom fin. The second etching process includes performing a first sub-etch and a second sub-etch in sequence. The ratio of the longitudinal etching rate to the transverse etching rate of the first sub-etch is a third etching rate ratio, and the ratio of the longitudinal etching rate to the transverse etching rate of the second sub-etch is a fourth etching rate ratio. The third etching rate ratio is greater than the second etching rate ratio, and the fourth etching rate ratio is less than the third etching rate ratio. or, After the first etching process, a second etching process is performed on the remaining fin material layer exposed by the effective fin to form the bottom fin. The etching parameters of the second etching process are the same as those of the first etching process.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The third etching rate ratio is greater than 5:1, and the fourth etching rate ratio is 3:1 to 5:

1.

13. The method for forming a semiconductor structure as described in claim 8, characterized in that, The etching process for the fin material layer of a certain thickness includes a bias power pulse etching process or a synchronous pulse etching process.

14. The method for forming a semiconductor structure as described in claim 8 or 11, characterized in that, The process of etching the remaining fin material layer exposed by the initial fin includes a bias power pulse etching process or a synchronous pulse etching process.

15. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the same etching process, after etching a portion of the fin material layer, the etching parameters are adjusted to etch the remaining fin material layer exposed by the initial fin.

16. The method for forming a semiconductor structure as described in claim 8 or 11, characterized in that, In the step of performing a first etching process on the portion of the fin material layer exposed at the initial fin, the etching depth is 150 Å to 250 Å.

17. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing the substrate, a fin mask layer is formed on the substrate; Using the fin mask layer as a mask, a portion of the fin material layer is etched; Using the fin mask layer as a mask, the remaining fin material layer exposed by the initial fin is etched. The steps of forming the isolation layer include: forming an isolation material layer on the substrate on the side of the fin, the isolation material layer covering the fin mask layer; planarizing the isolation material layer with the top of the fin mask layer as the stop position to form an initial isolation layer; etching back a portion of the initial isolation layer to expose the effective fin, and covering the remaining initial isolation layer on the bottom fin sidewall as an isolation layer; The step of forming the isolation layer further includes: performing a first annealing treatment on the isolation material layer, or performing a first annealing treatment on the initial isolation layer before etching back a portion of the initial isolation layer; the process temperature of the first annealing treatment is 650 degrees Celsius to 900 degrees Celsius.

18. The method for forming a semiconductor structure as described in claim 8, characterized in that, The forming method further includes: forming a gate structure on the isolation layer, the gate structure spanning the effective fin and covering a portion of the top and a portion of the sidewalls of the effective fin, the gate structure including a gate dielectric layer and a gate electrode layer covering the gate dielectric layer; The process of forming the gate structure includes a second annealing process, which includes one or both of post-nitriding annealing and post-deposition annealing, and the process temperature of the second annealing process is 700 degrees Celsius to 950 degrees Celsius.

19. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing the base, the effective fin has a preset effective height; In the step of etching a portion of the fin material layer, the difference between the initial fin height and the preset effective height is -100 Å to 100 Å.

20. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of etching a portion of the thickness of the fin material layer, the angle between the initial fin sidewall and the surface of the remaining fin material layer is 95 degrees to 100 degrees.

21. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of etching the remaining fin material layer exposed by the initial fin, the difference between the bottom linewidth of the first part of the fin and the top linewidth of the second part of the fin is -1 nanometer to 1 nanometer.

22. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of etching the remaining fin material layer exposed by the initial fin, the difference between the top linewidth and the bottom linewidth of the first portion of the fin is 1 nanometer to 3 nanometers.

23. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing the base, the effective fin has a preset effective height; In the step of etching the remaining fin material layer exposed by the initial fin, the difference between the preset effective height and the height of the second part of the fin is 20 Å to 150 Å.

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