Single-stage synchronous solid-state transformer system

Abstract

An input line-connected current-controlled bridge is dynamically coupled to an output line-connected voltage-controlled bridge of a single-stage bi-directional isolated resonant power supply using a synchronous average harmonic current controller. A bridge current sensor measures low frequencies and switching currents across nodes of the current controlled bridge. Synchronized average harmonic bridge current is controlled using superimposed non-modulated and modulated feedback, respectively, to track line current commands and linearize the coupling to the voltage controlled bridge. The power factor correction signal drives the line current command to regulate the DC voltage bus. The feed-forward and feedback trim circuits generate commands to the voltage-controlled bridge to track the input line voltage with attenuated harmonics. A single stage power supply has a defined interface for synchronizing and regulating power sharing of one or more modules.

Description

Technical Field

[0001] This disclosure generally relates to solid-state transformer power conversion systems, and more specifically to a single-stage synchronous solid-state transformer resonant power converter system and its control method. Background Technology

[0002] Solid-state transformers are used to convert isolated AC / AC voltages, similar to conventional transformers, with the potential additional benefits of smaller size, improved voltage regulation and filtering, and power factor correction. In some applications, solid-state transformers can be part of systems with both AC and DC connections to support bidirectional power storage and generation loads. (Prior art...) Figure 1 The architecture uses three consecutive stages: AC / DC rectification and boost power factor correction (100A), isolated DC / DC conversion and regulation (101), and DC / AC inverter (100B). The architecture with symmetrical AC / DC (100A) and DC / AC (100B) stages can be configured for bidirectional loads to support energy storage and generation. The illustrated DC / DC converter (101) supports bidirectional power transfer through inductor phase-shift control. In the prior art, DC / DC converters can be configured using a conventional resonant architecture, resulting in a near-resonant overall (or nearly constant) gain, supplemented by the power factor correction and inverter stage gains. In some variations, large energy storage elements (CS1 and CS2) are omitted, and inductor elements can be added between stages for current-feed arrangements. Figure 1 The prior art arrangement shown includes DC terminals V1 and V2, which, in addition to AC terminals (VAC1 and VAC2), also support isolated DC bus connections.

[0003] Existing implementations of solid-state transformers may have lower efficiency than conventional transformers due to series losses across multiple power stages. There is a need to develop a single-stage solid-state transformer with current-controlled connections for power line interfaces, isolated regulated voltage control line connections, and an isolated DC port. Summary of the Invention

[0004] In one aspect, the object of the present invention is to realize a single-stage solid-state transformer with isolated current and voltage control line connections and an isolated DC bus connection. This object is achieved in the present invention by using a current-controlled bridge and a voltage-controlled bridge coupled by a transformer and a resonant impedance to generate... Figure 3 The single-stage transformer module shown. The synchronous average harmonic current (SAHC) compensator is used to control both the line current flowing through the switching nodes of the current-controlled bridge and the synchronous average transformer current. Figure 2Schematic details of the SAHC compensator and pulse width modulator control process (208) are shown, which uses superimposed unmodulated and modulated feedback to linearize the sensed current (206) flowing through nodes VC and VD of the current-controlled bridge relative to the command current. The unmodulated feedback signal modifies the duty cycle command to track the command current (via the line-connected input, VAC2). The modulated feedback signal modifies the phase command to reduce the current synchronized with the square wave (SQ) input associated with the triangular wave (TRI) used for pulse width modulation. The modulated feedback signal linearizes the coupling between the first bus voltage (V1) and the second bus voltage (V2) by actively superimposing the admittance that linearizes the resonant network (205) to align with the switching frequency. The voltage-controlled bridge (201) applies a pulse width modulated (207) voltage (VA relative to VB) to the load (VAC1), where the pulse width modulated voltage is proportional to the bus voltage (V1) and the duty cycle command (VCMD). Figure 4 A dynamic model is presented that uses dynamic admittance to couple the harmonic currents between the first and second harmonic voltages, thereby describing the coupling relationship between voltage buses. Figure 5 The embodiment given uses a linearized dynamic relationship generated by an SAHC controller and corresponding voltage and current commands. This embodiment includes power factor correction, isolated DC-DC conversion, and a regulated inverter output that is adjusted using a feedforward regulator with superimposed fine-tuning feedback to reduce distortion relative to a reference. Figure 6 An embodiment of the invention is shown, which employs one or more synchronous follower modules to share voltage and current respectively. Figure 6 The embodiments described use a feedforward regulation relationship defined by the SAHC controller to allow control voltage and current to be shared between each module. The described embodiments of a single-stage synchronous solid-state transformer system combine the functionality of a multi-stage system with fewer series components.

[0005] These and additional objects and advantages provided by the embodiments described herein will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0006] Figure 1 A prior art multi-stage solid-state transformer is shown.

[0007] Figure 2 This is a schematic diagram illustrating an embodiment of a single-stage synchronous solid-state transformer module with command line current and voltage according to one or more embodiments shown and described herein, wherein the corresponding bus voltage is dynamically coupled by a synchronous harmonic current controller.

[0008] Figure 3It is based on one or more embodiments shown and described herein. Figure 2 The nominal description of the module described in [the document].

[0009] Figure 4 One or more embodiments shown and described herein are illustrated. Figure 2 Detailed dynamic description of the module described in the document.

[0010] Figure 5 A single-stage synchronous solid-state transformer system with output voltage regulation according to one or more embodiments shown and described herein is illustrated.

[0011] Figure 6 A multi-module single-stage synchronous solid-state transformer system with voltage and current sharing is illustrated according to one or more embodiments shown and described herein. Detailed Implementation

[0012] The embodiments described herein generally relate to solid-state power transformers and methods for forming a single-stage synchronous solid-state transformer system with synchronous average harmonic current control. As shown and described herein, new embodiments of solid-state transformers with synchronous average harmonic current control are provided. The system of the present invention controls the synchronous harmonic current between two isolation bridges to achieve power factor correction input line connections and regulation output line connections in a single stage.

[0013] An embodiment of a single-stage synchronous solid-state transformer module is shown in Figure 2 As shown in the figure, the numbered parts are described and expanded, and the mathematical principles of the synchronous average harmonic current controller are derived. Figure 3 and Figure 4 The simplified equivalent block diagram shown is illustrated. Figure 2 , Figure 3 and Figure 4 The module developed in [the context] supports current and voltage commands, which facilitates [the application of] [the following]. Figure 5 and Figure 6 The power factor correction and voltage regulation are shown in the single-stage synchronous solid-state transformer example given in the text. Figure 2The illustrated embodiment includes a current-controlled bridge (202) coupled to a current-controlled line (VAC2) and an isolation transformer (209) with DC blocking capacitors (C0) via its switching nodes VC and VD. A bridge current sensor (206) signal proportional to the current across nodes VC and VD is added to a current command (ICMD) and fed back to a synchronous average harmonic current (SAHC) compensator, which feeds back the current error synchronized with each half-cycle of a square wave (SQ). An SAHC-compensated pulse-width modulation controller (208) compares the superposition of the unmodulated and modulated feedback commands d2p2 with a synchronous triangular (TRI) waveform. The unmodulated duty cycle feedback generates a current through the line connection VAC2, tracking the command current ICMD. The modulated phase feedback results in dynamic linearization of the harmonic voltage coupling between voltage buses V1 and V2, minimizing the reactive current synchronized with the square wave. The voltage-controlled pulse-width modulation (207) process uses the command duty cycle (VCMD) relative to the synchronous triangular waveform to control the voltage-controlled bridge (201). The voltage-controlled and current-controlled bridges have isolated voltage references (203 and 204) and are coupled via a transformer and a resonant network (205). Dynamic coupling between the voltage buses is controlled by a synchronous average harmonic current control process that uses active admittance to linearize the system with respect to the switching frequency. This linearized dynamic coupling produces a harmonic buck-boost relationship between the bus voltages based on the duty cycle. The components of each block, along with their interfaces and mathematical relationships, are further described, such as... Figure 3 and Figure 4 As shown.

[0014] Voltage-controlled bridge (201) in Figure 2As shown, nodes VA and VB are connected to the voltage control line connection (VAC1) via an inductor filter and to the isolation transformer (209) via a resonant network (205), spanning the V1 DC bus (relative to reference potential 203). The voltage-controlled bridge also includes complementary switching element groups SA and SAN, as well as SB and SBN. Switching operation approximates continuous conduction with appropriate dead times to reduce cross-conduction, as driven by complementary gate signals gA and gB, respectively. The corresponding switches and their gate drive circuits are implemented according to existing techniques based on switching and conduction characteristics, depending on the application; examples include SiCFET, GaNFET, MOSFET, and IGBT. The bridge switching elements may include diodes to prevent reverse bias across the switching elements. An energy storage capacitor (CS1) is placed near the bridge between the voltage bus (V1) and the reference potential (203). Bridge nodes VA and VB are connected to the voltage control line (VAC1) via inductors (L3 and L4) and to the magnetically coupled transformer inductor (LT1) via a resonant network (205) that further includes inductors and capacitors (LR and CR). The voltage-controlled pulse width modulation (207) process compares the voltage command (VCMD) and the synchronous triangular waveform (TRI) to generate gate signals gA and gB. The transformer (209) also includes magnetically coupled inductors (LT1 and LT2) that couple the voltage-controlled bridge and the current-controlled bridge to the first and second harmonic voltages, respectively. The transformer can have a unity turns ratio, or an arbitrary turns ratio can be used to vary the gain while preserving power.

[0015] Current-controlled bridge (202) in Figure 2The diagram shows a bridge with connections to the current control line (VAC2) via an inductor filter, to the isolation transformer (209) via a DC blocking capacitor (C0), and across the DC bus (V2, 204 relative to the reference potential). The current-controlled bridge also includes complementary switching element groups SC and SCN, and SD and SDN. The complementary groups are controlled using complementary gate signals gC and gD, employing a continuous conduction approximation with appropriate dead time to prevent cross-conduction. The individual switches are implemented according to existing technology, where a balance is chosen to address application-specific costs, switching losses, and conduction losses. Each switch may include diode elements to prevent reverse bias. Switch bridge nodes VC and VD are connected to the current control line (VAC2) via inductor filters (L5 and L6) and to the magnetically coupled transformer inductor element (LT2) via a DC blocking capacitor (C0). This embodiment utilizes blocking capacitors to couple the AC transformer voltage to the bridge voltage, and alternative embodiments including capacitors and inductors (such as magnetized inductors) participating in the resonant network (205) are possible. In the illustrated embodiment, resistive shunts RSC and RSD, respectively connected to the sources of SCN and SDN, are used to sense the bridge current. The current amplifier (206) also includes resistive shunts RSC and RSD and a differential amplifier (DAMPCD). The current amplifier drives the bridge current signal VICD to a synchronous average harmonic current (SAHC) compensator implemented using a switched-capacitor filter. The SAHC compensator forms an error current signal by summing the bridge current signal (VICD) proportionally to the command current signal (ICMD) and compensates for the error current synchronously with each half-cycle of the square wave (SQ). The SAHC compensator is implemented using a switched-capacitor filter that injects the error current (using R11 and R12) into the inverting node of the operational amplifier (OP1) and integrates it using switched capacitors C1 and C2. Switches SC1 and SC2 are used to alternately switch the corresponding capacitors between the inverting node and the output of OP1 in the operational amplifier circuitry synchronously during each half-cycle of the square wave. The switch encodes the superimposed unmodulated and modulated feedback signals, where the common (unmodulated) signal at each half-cycle encodes the duty cycle feedback, and the difference (modulated) signal at each half-cycle encodes the phase feedback. The SAHC-compensated pulse width modulation stage (208) compares the superimposed unmodulated and modulated feedback signals d2p2 with a synchronous triangular waveform to modulate the gate signals gC and gD. The error feedback implemented by the SAHC compensator results in a current tracking current command (ICMD) via the line connection (VAC2) and harmonic linearization is achieved by minimizing the current of the square-wave synchronous reactive transformer. Using the block diagram from an additional embodiment incorporated into a single-stage synchronous solid-state transformer system… Figure 3 and frame Figure 4 The mathematical description further illustrates linearization.

[0016] exist Figure 2 In the illustrated embodiments, the corresponding voltage-controlled (201) bridge and current-controlled (201) bridge are shown using a full-bridge arrangement, and different bridge arrangements may alternatively be configured. Examples include a capacitive half-bridge, whereby bridge nodes (e.g., VD, VB) are connected to elements capacitively coupled to their respective DC buses. A virtual node connection is another example similar to a capacitive half-bridge connection, whereby multiple nodes are added to a single point, resulting in a low effective impedance at that point due to current cancellation.

[0017] An example of a single-stage synchronous solid-state transformer (S5X) is shown in... Figure 3 As shown, it focuses on the external connection interface. The right edge of the S5X block shows the connection to a voltage-controlled bridge (such as...). Figure 2 The connection of the S5X block (201) is shown. The voltage-controlled bridge connection includes: a voltage control line connection between the DC voltage bus V1, VA, and VB relative to the voltage return (RTN1) reference, and a command voltage (VCMD). An energy storage capacitor (CS1) is placed across the DC voltage bus, and the voltage control line (VAC1) is connected to VA and VB via an inductor filter. A pulse width modulation (PWM) controller generates a differential gate control signal (gAB), which controls the internal voltage source (VAB) based on the bus voltage (V1 relative to RTN1) and the command duty cycle (VCMD). The left edge of the S5X block shows the connection to a current-controlled bridge (such as...). Figure 2 The connection is shown in section 202. The current-controlled bridge connection includes: a current control line connection between the DC voltage buses V2, VC, and VD relative to the voltage return (RTN2A and RTN2B) references, and a command current (ICMD). An energy storage capacitor (CS2) is placed across the V2 DC voltage bus, and the current control line (VAC2) is connected to VC and VD via an inductor filter. The Synchronous Average Harmonic Current (SAHC) controller generates a gate control signal (gCD) that controls the internal current source (ICD) according to the command current (ICMD). The bottom edge of the S5X block shows the superimposed duty cycle and phase signal outputs d2p2, which can be used for feedforward regulation, as well as the synchronization signal inputs including the synchronous square wave (SQ) and triangle wave (TRI) used by the SAHC and PWM controllers.

[0018] An embodiment of the internal dynamic model of a single-stage synchronous solid-state transformer (S5X (details)) is presented in... Figure 4 As shown in the diagram. The right edge of the S5X (details) block shows the DC bus (V1 relative to RTN1) and voltage control line connection (VA relative to VB) interfaces, similar to... Figure 3The S5X block is shown in the diagram. The left edge of the S5X (details) block shows the DC bus (V2 relative to RN2A and RTN2B) and current control line connection (VC relative to VD) interfaces, similar to... Figure 3 The S5X block is shown below. The bottom edge of the S5X (details) block shows the line-level interfaces of the Synchronous Average Harmonic Current (SAHC) controller and the Pulse Width Modulation (PWM) controller, including: Command Line Current (ICMD), generated duty cycle and phase (d2p2), Synchronous Triangle Wave (TRI) and Square Wave (SQ), and Command Line Voltage (VCMD). The Synchronous Average Harmonic Current controller simultaneously controls the duty cycle and phase of the gate signal gCD to control the low-frequency bridge current ICD to track the command current ICMD and linearizes the synchronous harmonic current with respect to the switching frequency. The linearized harmonic current flowing across the equivalent inductor (LEQ) between the isolation bridges (ILEQ) is caused by the linearization dynamics applied by the SAHC controller due to the harmonic voltages (given by VMULT2 and VMULT1). The output of VMULT1 represents the first harmonic voltage, which is the harmonic linearization of the bus voltage (V1) and the voltage-controlled bridge gate signal. The output of VMULT2 represents the second harmonic voltage, which is a harmonic linearization of the bus voltage (V2) and the current-controlled bridge gate signal. The corresponding currents I1X and I2X, given by IMULT1 and IMULT2, are generated by the system power retained due to the harmonic power transfer isolated between the bridges. The power generated by the internal current source (ICD) is coupled to the DC bus (V2) via IMULT4, which controls the current collected in I20. The current sinks I20 and I2X represent superposition terms using the same current-controlled bridge. The pulse width modulation (PWM) controller synchronously controls the gate signal (gAB) of the voltage-controlled bridge to generate a voltage VAB, which is a function of the DC bus voltage (from V1 to RTN1) and the command duty cycle (VCMD mapped to d1). The PWM controller is synchronized with the SAHC controller such that the duty cycle d1 also linearizes the harmonic power flow. The duty cycle d1 can be used as a degree of freedom to adjust the coupled bus voltage (V1) and the line voltage (VAB). The corresponding current absorption terminals I1X and I10 represent the superposition of the power due to harmonic power transmission and the power coupled to the voltage control line.

[0019] Similar to Figure 4 The internal model shown provides a mathematical description of one or more embodiments for linearized harmonic current flow related to frequency (f):

[0020]

[0021] in This indicates that due to harmonic weighting ( Figure 4 VMULT1 and VMULT2 bus voltages and (or Figure 4 The current flows across the equivalent harmonic inductance element (V1 and V2 in the equation). The impedance of the equivalent harmonic inductance element... for:

[0022]

[0023] Wherein, the equivalent harmonic resistance is And the equivalent harmonic inductance is R0 represents the internal resistance of the switch and the resonant network, and L R This represents the inductance of the resonant network. Impedance is the frequency-dependent relationship between the input current and the predicted output voltage, while admittance is the reciprocal of the impedance (or the current due to the voltage). In EQ1, admittance (or the reciprocal of the impedance) is used to predict the current flow due to the weighted input voltage.

[0024] The bus current transfer as a result of the linearized harmonic current flow is given below:

[0025]

[0026] Among them, the current entering each bus and The first switching harmonic of the corresponding bridge gate signal is modulated to generate a weight that is sinusoidally related to each corresponding duty cycle.

[0027] exist Figure 4 Linear calculations using I10 and I20 illustrate the power transfer between each corresponding DC bus and its line connection voltage. The feedback signal from the unmodulated SAHC compensator of the linearized current ICD is also shown. The frequency-dependent loop gain is:

[0028]

[0029] The full-bridge duty cycle is determined by the DC bus voltage. Amplification, and through a series inductor The associated admittance is calculated to convert the voltage to current and through the compensator gain. Calculations are performed to command the duty cycle. Series inductors (such as...) Figure 4 L2 in the middle has admittance This admittance is determined by its impedance. The reciprocal is given. Figure 4The current source ICD modeled in the model is a reasonable approximation of the unmodulated SAHC control over the loop gain frequency bandwidth of EQ4 (wherein... The amplitude is greater than 1). Voltage VAB (e.g.) Figure 4 (As shown) is directly commanded by pulse width modulation V1 using d1.

[0030] The modulation feedback signal path of the synchronous average harmonic current compensator is used to linearize the harmonic coupling admittance, such as Figure 4 (LEQ) is shown. Linearized system coupling is described in EQ5A, EQ5B, EQ5C, and EQ5D, and simplified to EQ1 through EQ3 in terms of control bandwidth. Frequency-dependent bus current transfer due to bus voltage disturbances is given as follows:

[0031]

[0032] in, The current flow in the first bus is caused by the voltage disturbance of the first bus, and The current flow in the first bus is caused by the voltage disturbance of the second bus, and its sum is in Figure 4 The diagram shows I1X. This represents the flow of the second bus current due to a disturbance in the first bus voltage. and the second bus current flow caused by second bus voltage disturbance exist Figure 4 The summation is I²X. Each current described in EQ5A, EQ5B, EQ5C, and EQ5D is the superposition of the open-loop modulation admittance term and the active admittance subtracted due to control. For example, It is related to the admittance of the resonant network ( Figure 2 The open-loop admittance associated with 205 in the resonant network is modulated by the gate signal gAB, and its input is modulated by the gate signal gCD. The square wave gate signal gS is a synchronous square wave used by the SAHC controller, and is out of phase with gAB by 90 degrees and approximately out of phase with gCD. The controller cross-admittance term (which includes an S subscript and one of the AB or CD subscripts, such as...) ) Detect the admittance of the resonant network with respect to the switching frequency (f c The conjugate symmetry error of the resonant network. As an example, the admittance of the resonant network (Y) R ) can be achieved by dividing each element (i.e. Figure 2 The effective series impedances of 205 (CR and LR) are added together and the total network impedance is inverted to calculate the impedance. The controller cross admittance term is used as an error metric, which applies conjugate imaginary weights to the resonant network admittance to obtain the error from the control cross admittance. Subtract proportionally ,in yes The complex conjugate of . For loop gain ( For cases where the value is greater than 1, each active admittance term is subtracted from the admittance portion parallel to the error metric. Physically, the error metric is minimized when the controller superimposes modified resonant network admittances to have active admittances with a new resonance aligned with the switching frequency.

[0033] Loop gain in the modulation feedback path Within a bandwidth greater than 1, the active admittance subtracted due to control is simplified. The control admittance equations (EQ5A, EQ5B, EQ5C, EQ5D) are reproduced over the control bandwidth. Figure 4 The linearized model equations (EQ1, EQ2, and EQ3) used are approximated, and the modeled harmonic inductance outside the control bandwidth is approximated. The modulated feedback path loop gain is:

[0034]

[0035] Where g is the duty cycle operating point The relevant linearized gain constant, and This is the DC bus voltage (V2). The frequency-dependent gain of the SAHC compensator is... The compensator gain can be achieved using a combination of R11 and dual C1 (such as...). Figure 2 The model is created using an integrator with the given time constant (as shown), where each switched capacitor (with equivalent capacitances C1 and C2) integrates the error current signal over half of the switching cycle. The system response due to the control input is then considered. It is a square wave modulated current caused by the modulation phase command input. The control bandwidth is defined as... The frequency range with an amplitude greater than 1.

[0036] The open-loop modulation admittance term (used in EQ5A, EQ5B, EQ5C, and EQ5D) is:

[0037]

[0038] Each term is a superposition of the admittances of the conjugate resonant networks at two frequencies, weighted by the gate signal. Gate signal and Indicates used for Figure 2 The fundamental frequency of the switching process shown is the pulse width modulation process. For resonant networks (such as...) Figure 2 In the context of 205, LR, and CR), when the open-loop natural frequency of the resonant network admittance is tuned to align with the switching frequency, the open-loop modulation impedance terms simplify to EQ1 through EQ3. This simplification is due to the capacitive admittance being conjugate to the inductive admittance on either side of the natural frequency, such that when (e.g., ...) The first admittance term is conjugated (the two conjugates cancel each other out) and reflected with respect to the switching frequency, then constructively added to the second term. The SAHC controller effectively superimposes the active admittance onto the open-loop modulation admittance to align the closed-loop intrinsic frequency with the switching frequency by reducing the conjugate symmetry error with respect to the switching frequency. As a result of the active admittance term, the closed-loop equations (EQ5A, EQ5B, EQ5C, EQ5D) converge to the design model (after extending the gate signal using the fundamental frequency of the gate signal according to the pulse width modulation process).

[0039] The controller cross-admittance term (used in EQ5A, EQ5B, EQ5C, and EQ5D) is:

[0040]

[0041] in, It is the fundamental wave of the square wave (SQ), and its integral is the triangular wave (TRI) used for pulse width modulation. Due to the mathematical properties of the integral, the triangular wave is 90 degrees out of phase with the square wave. Assuming a small phase command, the gate signal... and This can be modeled as being in phase with a triangular waveform due to the pulse width modulation process. Therefore, the gate signal... and It is 90 degrees out of phase with the synchronous square wave. Therefore, and gate signal and Each fundamental combination is an imaginary number. The imaginary numbers weighted over the cross-admittance terms are conjugate symmetric, leading to sign reversal, which causes the weighting equation to change from... Subtract To form a measure of conjugate symmetric error.

[0042] The open-loop automatic admittance term (used to calculate the loop gain of the EQ6B) is:

[0043]

[0044] in, This is the modulation current response caused by the modulation phase command. The natural frequency f associated with the resonant network. n Due to the switching frequency f c Modulation to cause the open-loop device to automatically admittance at The apparent resonance at that point. For levels below... At frequencies above a certain threshold, the automatic admittance of the open-loop device is capacitive, while for frequencies above a certain threshold... At that frequency, the automatic admittance is inductive. When When the control bandwidth is relatively small, the inductive automatic admittance term dominates the frequency response. Given that inductive impedance increases proportionally with frequency and inductive admittance varies one-over-frequency, the open-loop automatic admittance term exhibits integral characteristics. The open-loop admittance is combined with the compensator to calculate the loop gain (EQ6B). The integral compensator response (e.g.) Figure 2 The SAHC compensator in the diagram can be modified to include stable phase lead, for example, by adding a... Figure 2 Each switched capacitor (C1 and C2) is connected in parallel with a series resistor and capacitor. Alternatives such as phase control using a phase-locked loop (PLL) with a voltage-controlled oscillator (VCO) are disadvantageous for this system because the VCO introduces another integrator into the total loop gain. As estimated using the loop gains (EQ4 and EQ6B), good stability can be achieved over a wide range of operating points. Figure 2 The SAHC compensator shown in the figure is for... Figure 2 and Figure 3 The linearization behavior shown is robustly modeled.

[0045] Such as Figure 3 The illustrated embodiment of the resonant power converter achieves current balance when the harmonic voltages are balanced. EQ10 demonstrates voltage-controlled bus harmonic balance in steady state for a given regulated bus voltage V2:

[0046]

[0047] Among them, V1 is related to V2 by the sine ratio of the corresponding bridge duty cycle.

[0048] The voltage-controlled bridge regulates both VAB and V1 relative to V2, where VAB is a function of the bus voltage V1 and the duty cycle d1:

[0049]

[0050] Equation EQ11 assumes the duty cycle sensitivity of the full-bridge circuit. Combining EQ10 and EQ11 yields the average line-attached voltage response:

[0051]

[0052] Among them, the line voltage V AB For d1 in the numerator and d1 in the denominator It has sensitivity. For systems utilizing a linear combination of feedforward and feedback signals, V AB The sensitivity to d1 is extended to:

[0053]

[0054] Here, d1 is extended to d2 + dx to represent feedforward and feedback regulation. Assuming the small perturbation in the feedback is dx, the derivative of EQ13 is:

[0055]

[0056] The derivative given in EQ14 is The linear constant, where and Both are zero, and for It becomes relatively more nonlinear. The relationships in EQ14 are sufficient to design feedback regulators, where clipping is used to ensure that the feedback gain is bounded. Clipping circuits (such as...) Figure 5 The VHTRIM in the middle prevents saturation and instability outside the appropriate adjustment range.

[0057] exist Figure 5 An embodiment of a single-stage synchronous solid-state transformer system is shown, which includes power factor correction and isolation voltage regulation. Figure 5 The S5X block shown and its associated power terminal connections are similar to Figure 2 , Figure 3 and Figure 4 One or more embodiments are shown. In this embodiment, the line connection (VAC2) is sensed as an input to a multiplication process to shape the line current (ICD) used for power factor correction (PFC). The PFC block (501) includes a multiplier (MULT1), an error amplifier (EA2), and a voltage reference (REF2). The error amplifier (EA2) feeds back the difference between the scaled voltage reference (REF2) and the bus voltage (V2). The command output of the error amplifier (EA2) is shaped by the multiplier (MULT1) to command the shaped current (ICMD) to the S5X block. The SAHC controller causes the line current (ICD via VAC2) to track the command current while applying dynamic characteristics of the coupled bus voltages (V2 and V1) according to EQ10.

[0058] exist Figure 5In the illustrated embodiment, voltage regulation is performed using a voltage error amplifier (503) and a harmonic voltage trimmer (502) amplifier (VHTRIM). Feedforward adjustment of the duty cycle d1 relative to d2 produces a balance between the DC bus voltages (V2-RTN2 and V1-RTN1) and the filter bridge voltages (inductor-filtered VCD and VAB). The harmonic voltage trimmer amplifier uses a low-pass filter d2p2 to adjust d1 using d2 feedforward (where superimposed modulation phase commands are filtered out). The trimmer input is generated by the voltage error amplifier (503), which also includes an error amplifier EA1, a tracking voltage reference (REF1), and a voltage difference amplifier (DAMP1). The voltage error amplifier (503) applies negative feedback to reduce the error between the line output voltage and the tracking voltage reference (REF1). The tracking voltage reference is implemented using a filtered reference according to existing techniques, such as using a low-pass filter, a band-pass / complementary notch filter, or a phase-locked loop to filter VAC2. The trimmer amplifier (VHTRIM) is configured to have an overall low-pass gain up to d2, along with a wideband input from the voltage error amplifier. The trimmer amplifier also includes resistors with matching ratios (R2 and R3, and R1 and R4 respectively), capacitors filtering the duty cycle input (CF), and operational amplifier OP2. The trimmer amplifier is configured to limit its trimming input from the voltage error amplifier to an effective range. The voltage error amplifier and trimmer amplifier work together such that the voltage control line (VAC1) tracks the line voltage (VAC2) connected to the current-controlled bridge, where noise is suppressed. Appropriate energy storage capacitors (CS1 and CS2) connected across each bus voltage are used to buffer unstable currents. The single-stage synchronous solid-state transformer (S5X) module, the PFC module, and the voltage trimmer controller work together to form a single-stage regulated power factor correction system.

[0059] exist Figure 6 An embodiment of a multi-module single-stage synchronous solid-state transformer system is shown. The multi-module arrangement consists of two or more S5X modules arranged to share voltage and current (according to...). Figure 2 , Figure 3 and Figure 4The system comprises one or more embodiments shown. A first module (denoted as S5X1) establishes DC bus voltages V1 and V2, as well as line connection voltages VCD and VAB. DC bus voltages V1 and V2 are tracked together using a feedforward filter (602). The feedforward filter (including R1d and C1d filters d2p2) is used to transmit unmodulated duty cycle information (d2) as a feedforward adjustment signal (to d1). The SAHC controller linearizes the coupling between the V1 and V2 DC buses, making the bus voltages similar (using d2 to command d1). The inductor-filtered bridge voltages VCD and VAB have similar responses because they are commanded with similar duty cycles. Bus voltage V2 is controlled by a power factor correction (PFC) block (601), which is similar to the power factor correction (PFC) block (601) in the case of a DC bus. Figure 5 The PFC block (501) described herein is used for operation. A multiplier (MULT1) is used to generate a current command (ICMD) by shaping the output of the line voltage (VAC2) from an error amplifier (EA2), which reduces the tracking error between the bus voltage (V2) and the reference (REF2). A current source ICDF from one or more follower modules (denoted as S5XF) is connected in parallel with an inductor to the line voltage VAC1 (and voltage VAB). The follower module S5XF also uses a voltage source VABF connected in series with an inductor to the line voltage VAC2 (and the first module current ICD). The terminal label of the follower module is fixed with a capital "F" to indicate its follower position, but otherwise resembles... Figure 2 , Figure 3 and Figure 4 The S5X embodiment described herein. A follower voltage source (VABF) is used to share the input line voltage, and a follower current source (ICDF) is used to share the power to and from the attached load on the output line. DC buses V1 (relative to RTN1) and V2F (relative to RTN2AF and RTN2BF) are connected in parallel. An error amplifier (EA3) drives the follower current command ICMDF to the SACCF controller to share the current to line VAC1. A feedforward filter (602) is used to set the duty cycles d1 and d2 of the first module to be equal, and feedforward regulation of the follower module is achieved by driving the VCMDF with d1. The connection of the follower current source ICDF to the VAB makes its duty cycle also track d1, so that each module has a similar feedforward regulated duty cycle based on the d2 signal of the first module. Any number of follower modules can be inductively connected to follower interfaces (VAF, VBF, VCF, VDF, V2F, RTN2F, ICMDF) to share voltage and current, and synchronization (such as the SQ complementary signal SQN) is used to eliminate switching harmonics.

[0060] Figure 6The illustrated embodiment uses feedforward regulation to achieve voltage and current sharing, and can be enhanced in additional embodiments to use similar... Figure 5 Voltage regulation. Fine-tuning can be achieved by changing the voltage command (VCMD) sent to the first module (S5X1). Figure 6 The illustrated embodiment. Further embodiments are possible that involve changing the voltage command to the module (VCMDF) to achieve regulation. Commands can be applied differently to multiple follower modules to independently change the resulting voltage (VCD) of the first module relative to the series-connected line voltage (VAC2). According to embodiments, single-stage synchronous solid-state transformer modules can be combined in various ways to form a general-purpose system.

[0061] While specific embodiments have been shown and described herein, it should be understood that various other changes and modifications may be made without departing from the spirit and scope of the claimed subject matter. Furthermore, although various aspects of the claimed subject matter have been described herein, these aspects need not be used in combination. Therefore, the appended claims are intended to cover all such changes and modifications within the scope of the claimed subject matter.

Claims

1. A power converter comprising: a voltage controlled bridge circuit comprising a first plurality of switching devices across a first voltage bus and a first energy storage capacitor, wherein the first plurality of switching devices are coupled to a first transformer winding of a transformer device and a first line voltage; at least one voltage controller circuit configured to generate a voltage command that controls coupling of a first bus voltage to both the first line voltage and a fundamental harmonic voltage using the first plurality of switching devices; a current controlled bridge circuit comprising a second plurality of switching devices across a second voltage bus and a second energy storage capacitor, wherein the second plurality of switching devices are coupled to a second transformer winding of the transformer device and a second line voltage; at least one current controller circuit configured to generate a current command that controls both bidirectional current to the second line voltage and a second harmonic voltage using the second plurality of switching devices; a resonant network comprising at least one capacitor and inductor coupled to the first transformer winding or the second transformer winding, or both the first transformer winding and the second transformer winding; and a synchronous average harmonic current controller comprising a feedback circuit that reduces a current error signal that is synchronous-averaged over each half of a switching period by changing a modulation waveform of at least one of a first controller circuit or a second controller circuit that linearizes a coupling admittance between the fundamental harmonic voltage and the second harmonic voltage, the current error signal comprising an error between a commanded current and a measured current across a bridge switching node.

2. The power converter of claim 1, wherein, the voltage controller circuit further comprises: a filter that generates a voltage regulation duty cycle; and a pulse width modulation stage that compares a synchronous triangular waveform and the voltage regulation duty cycle.

3. The power converter of claim 2, wherein, the filter that generates the voltage regulation duty cycle further comprises one or more resistors and one or more capacitors configured to low pass a duty cycle signal generated by the synchronous average harmonic current controller.

4. The power converter of claim 2, wherein, the filter for generating the voltage regulation duty cycle further comprises an amplifier that sums a linear combination of a duty cycle signal generated by the synchronous average harmonic current controller and a signal generated by an error amplifier that subtracts the first line voltage from a reference voltage.

5. The power converter of claim 4, wherein, the signal generated by the error amplifier is clipped with respect to a limit.

6. The power converter of claim 1, wherein, the current controller generates the current command with a power factor correction circuit comprising: a voltage error amplifier that subtracts a signal proportional to the second bus voltage from a voltage reference to generate an average command signal; and a multiplier that shapes the average command signal by a signal proportional to the second line voltage to generate a shaped current command.

7. The power converter of claim 1, wherein, the synchronous average harmonic current controller further comprises: A switched-capacitor filter is configured to process the error current signal by synchronously integrating and compensating on each half of the switching cycle and by alternately sampling on each half of the switching cycle synchronized with a square wave. The superimposed unmodulated duty cycle feedback loop circuit is configured to reduce the integral error current signal over the switching cycle by changing the bridge duty cycle through negative feedback. A superimposed modulated phase feedback loop circuit is configured to reduce the difference in the integral error current signal at each half-switching cycle by using a negative feedback phase adjustment command; and The pulse width modulation stage compares the synchronous triangular waveform with the superposition of the unmodulated and modulated integral error current signals.

8. The power converter of claim 1, further comprising a current sensor that provides a measure of current across a bridge switch node to drive the synchronous average harmonic current controller, wherein, The current sensor has at least one resistive shunt and a preamplifier.

9. The power converter of claim 1, wherein, The transformer equipment includes the first transformer winding and the second transformer winding, and also includes a determined turns ratio.

10. The power converter of claim 1, wherein, The first plurality of switching devices includes a full-bridge circuit, the full-bridge circuit including at least two pairs of switching devices.

11. The power converter of claim 1, wherein, The second plurality of switching devices includes a full-bridge circuit, which includes at least two pairs of switching devices.

12. The power converter of claim 1, wherein, The first plurality of switching devices includes at least two switching devices coupled to a virtual node, the virtual node being formed by a capacitive half-bridge or a connection to a power supply having canceling current phases.

13. The power converter of claim 1, wherein, The second plurality of switching devices includes at least two switching devices coupled to a virtual node, the virtual node being formed by a capacitive half-bridge or a connection to a power supply having canceling current phases.

14. The power converter of claim 1, wherein, The three-phase lines are connected across multiple synchronous power converter modules.

15. The power converter of claim 1, wherein, The first module controls the line current and the line voltage respectively, and one or more follower modules are arranged to use feedforward regulation to share the voltage in series with the line current and to share the current in parallel with the line voltage.

16. The power converter of claim 15, wherein, The follower module is synchronized with a square wave clock signal, which is the logical complement of the square wave clock signal that synchronizes the first module.

17. A method comprising: A current command is generated, which controls the current flowing through the second line voltage coupled to the current-controlled bridge to regulate the current-controlled bridge bus voltage and the second harmonic coupling voltage. The harmonics of the current-controlled bridge are coupled to the voltage-controlled bridge by sensing, compensating and sampling the synchronous average current during each half-switching cycle and superimposing the feedback signal onto the modulated waveform. as well as A voltage command is generated, which controls the first line voltage coupled to the voltage-controlled bridge and adjusts the voltage-controlled bridge bus voltage and the first harmonic coupling voltage.

18. The method of claim 17, further comprising connecting one or more harmonic-coupled power converters to share voltage across a control current source and current across a control voltage source.

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