Semiconductor devices, fabrication methods, power conversion circuits and vehicles

Abstract

This application provides a semiconductor device, a fabrication method, a power conversion circuit, and a vehicle, comprising: an N-type semiconductor substrate, a drift layer disposed on the semiconductor substrate, a trench structure disposed within the drift layer, a gate, an interlayer dielectric layer, a source, and a drain. The drift layer includes a first N-type semiconductor region, a second P-type semiconductor region, and a source region sequentially stacked on the semiconductor substrate, as well as first P-type semiconductor regions disposed on both sides of the drift layer. The trench structure has multiple first trenches and second trenches, and a gate is disposed in the first trenches and second trenches. The fabrication of a closely spaced trench array in the drift layer facilitates reducing the trench spacing between the first trenches, thereby miniaturizing the cell and improving the cell density and current carrying capacity of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to semiconductor devices, fabrication methods, power conversion circuits, and vehicles. Background Technology

[0002] Silicon carbide (SiC) materials offer advantages over silicon (Si) materials, including a wider bandgap, higher critical breakdown electric field, higher thermal conductivity, and higher electron saturation drift velocity. Metal-oxide-semiconductor field-effect transistors (MOSFETs) made from SiC exhibit higher breakdown voltage and lower on-state voltage drop compared to insulated-gate bipolar transistors (IGBTs) made from Si. Furthermore, the unipolar conductivity of SiC MOSFETs results in faster switching speeds, lower conduction losses, and lower switching losses compared to Si IGBTs. Therefore, SiC MOSFETs have already replaced Si IGBTs in some applications, such as automotive microcontroller units (MCUs) and on-board battery chargers (OBCs).

[0003] Compared to conventional planar gate devices, SiC MOSFET devices employing trench gate structures embed the gate within the SiC body, shifting the conductive channel from a planar orientation to a vertical one. This significantly reduces the device's cell size and greatly increases the conductive channel density, thereby substantially reducing the chip's on-resistance and improving current-carrying capacity. Trench gate structures have become the mainstream technology for future devices. However, in trench-gate SiC MOSFET devices, there is a significant contradiction between the channel resistance and the junction field-effect transistor (JFET) resistance. (Refer to...) Figure 1 The horizontal axis represents the cell size, and the vertical axis represents the resistance. Figure 1 It is known that by reducing the spacing of the trench gate structure in SiC MOSFET devices, the cell size of SiC MOSFET devices can be reduced, the conductive channel density can be increased, and the channel resistance can be reduced. However, at the same time, the current-carrying width of the JFET region will also decrease, resulting in an increase in the resistance of the JFET region. Consequently, the overall on-resistance of the SiC MOSFET device will increase, reducing device performance and increasing chip losses. Summary of the Invention

[0004] This application provides a semiconductor device, a fabrication method, a power conversion circuit, and a vehicle, which are used to reduce the total on-resistance of the device, improve device performance, and reduce device losses.

[0005] In a first aspect, embodiments of this application provide a semiconductor device, comprising: an N-type semiconductor substrate, a drift layer disposed on the semiconductor substrate, a trench structure disposed within the drift layer, a gate, an interlayer dielectric layer, a source, and a drain. The drift layer includes: a first N-type semiconductor region, a second P-type semiconductor region, and a source region sequentially stacked on the semiconductor substrate, and first P-type semiconductor regions disposed on two sides of the drift layer. Specifically, the second P-type semiconductor region is disposed between the first N-type semiconductor region and the source region, and the plurality of first P-type semiconductor regions extend from the top of the drift layer into the second P-type semiconductor region along a third direction perpendicular to the plane of the semiconductor substrate. The trench structure includes a plurality of first trenches and a plurality of second trenches. The plurality of first trenches are arranged along a second direction parallel to the plane of the semiconductor substrate, and the plurality of second trenches extend along the second direction. The plurality of second trenches and the plurality of first trenches extend from the top of the drift layer into the first N-type semiconductor region along a third direction. A second trench is disposed between two adjacent first trenches, and the plurality of second trenches are interconnected with the plurality of first trenches. This allows for the fabrication of a closely packed trench array in the drift layer.

[0006] Furthermore, the gate is filled and disposed within the plurality of first trenches and the plurality of second trenches through a gate dielectric layer. When the drift layer material in this application is SiC, the gate can be embedded inside the SiC drift layer, and the semiconductor device provided in this embodiment is formed as a SiC MOSFET with a trench gate structure.

[0007] Furthermore, the interlayer dielectric layer covers the side of the gate away from the semiconductor substrate, and covers the entire gate and a first portion of the source region, exposing a second portion of the first P-type semiconductor region and the source region. This is equivalent to the interlayer dielectric layer having a contact hole. The contact hole extends along a second direction parallel to the plane of the semiconductor substrate. The orthographic projection of the contact hole onto the semiconductor substrate does not overlap with the orthographic projection of the gate onto the semiconductor substrate, and the contact hole exposes a second portion of the first P-type semiconductor region and the source region. The source electrode covers the side of the interlayer dielectric layer away from the semiconductor substrate, and covers the interlayer dielectric layer, the first P-type semiconductor region, and the second portion of the source region. This is equivalent to the source electrode contacting the first P-type semiconductor region and the second portion of the source region exposed by the contact hole through the contact hole. The drain electrode is disposed on the side of the semiconductor substrate away from the drift layer, i.e., the drain electrode covers the semiconductor substrate. Because the source electrode can contact the first P-type semiconductor region and the source region through the contact hole, the effect of connecting the source electrode to the first P-type semiconductor region and the source region is achieved. Thus, when the gate control channel is turned on, a signal can be transmitted between the source and the drain.

[0008] For example, the first direction, the second direction, and the third direction are arranged to intersect each other. For instance, the first direction, the second direction, and the third direction are arranged to be perpendicular to each other.

[0009] The semiconductor device provided in this application embodiment has a closely spaced trench array fabricated in a drift layer, with gates disposed in the first and second trenches, and the region at the boundary between the second P-type semiconductor region and the gate dielectric layer forming a channel. Furthermore, the extension direction of the contact holes disposed in the interlayer dielectric layer is a second direction, and the extension direction of the first gate is a first direction. Therefore, the extension direction of the contact holes is perpendicular to the extension direction of the first gate, meaning the contact holes are placed in a direction perpendicular to the first gate. Compared to the prior art where the gate trenches and contact holes are parallel, the semiconductor device provided in this application embodiment reduces the restriction on the trench spacing of adjacent first trenches in the second direction imposed by the contact holes, allowing for a more compact fabrication of the first trenches, resulting in a more compact gate. This facilitates reducing the trench spacing between the first trenches, thereby miniaturizing the cells and improving cell density and device current carrying capacity. Therefore, the gate trench array density of the semiconductor device provided in this application embodiment can be much higher than the gate trench array density of the device structure in the prior art, thereby increasing the channel density of the SiC MOSFET with trench gate structure, significantly reducing the total on-resistance per unit area of ​​the device, improving the current carrying capacity and device performance, and reducing device losses.

[0010] For example, the semiconductor substrate can be a silicon carbide substrate doped with pentavalent elements. The drift layer can be formed by epitaxial growth of SiC material doped with the corresponding impurities. For example, the first N-type semiconductor region is a portion of the drift layer formed by epitaxial growth. The source region is an N-type semiconductor region, and the source region can be formed by ion implantation process to dope the drift layer with N-type impurities.

[0011] For example, in this application, the N-type semiconductor region is mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).

[0012] For example, the doping concentration of the semiconductor substrate is greater than the doping concentration of the first N-type semiconductor region, and the doping concentration of the source region is also greater than the doping concentration of the first N-type semiconductor region. Optionally, the doping concentration of the semiconductor substrate is similar to or the same as the doping concentration of the source region. Of course, the doping concentration of the semiconductor substrate and the doping concentration of the source region can also be different; for example, the doping concentration of the semiconductor substrate may be greater than or less than the doping concentration of the source region, which is not limited here.

[0013] For example, the second P-type semiconductor region can also be formed by epitaxially growing SiC material doped with P-type impurities; that is, the second P-type semiconductor region can also be a portion of the drift layer formed by epitaxial growth. Alternatively, the second P-type semiconductor region can also be formed by ion implantation, through P-type impurity doping of the drift layer. This application does not limit the formation process of the second P-type semiconductor region.

[0014] For example, in this application, the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga).

[0015] In some possible implementations, within the same trench structure, a second trench is provided between two adjacent first trenches, and the second trench is located on the sidewall of the first trench. This allows two adjacent first trenches to communicate with each other through the second trench.

[0016] In some possible implementations, each of the plurality of first trenches has a first sidewall and a second sidewall disposed opposite to each other in the first direction. In the same trench structure, the plurality of second trenches are located at the first sidewall of the first trench, thus creating a comb-like trench structure. Alternatively, in the same trench structure, the plurality of second trenches are located at the second sidewall of the first trench. This also creates a comb-like trench structure. Alternatively, in the same trench structure, the plurality of second trenches are located at the first sidewall and the second sidewall of the first trench. Alternatively, in the same trench structure, a first portion of the second trench is disposed at the first sidewall of the first trench, and a second portion of the second trench is disposed at the second sidewall of the first trench, with the first portion of the second trench and the second portion of the second trench alternating along the second direction.

[0017] In some possible implementations, each of the plurality of first trenches extends along the first direction, i.e., each first trench extends along the same direction. Furthermore, the orthographic projection of the sidewall of the second trench along the first direction onto the semiconductor substrate is straight, zigzag, or arc-shaped. For example, the edge of the orthographic projection of the sidewall of the second trench along the first direction onto the semiconductor substrate is straight. For example, the second trench has opposing third and fourth sidewalls in the first direction; the orthographic projection of the third sidewall of the second trench onto the semiconductor substrate can be straight, and the orthographic projection of the fourth sidewall of the second trench onto the semiconductor substrate can also be straight. Optionally, the third sidewall of the second trench can be the sidewall closer to the contact hole, and the fourth sidewall of the second trench can be the sidewall farther from the contact hole.

[0018] Alternatively, the edge of the sidewall of the second trench in the first direction, projected onto the semiconductor substrate, is either a polygonal line or an arc. The second trench has opposing third and fourth sidewalls in the first direction. The projection of the third sidewall of the second trench onto the semiconductor substrate can be a straight line, and the projection of the fourth sidewall of the second trench onto the semiconductor substrate can also be a polygonal line or an arc. Optionally, the third sidewall of the second trench can be the sidewall closer to the contact hole, and the fourth sidewall of the second trench can be the sidewall farther from the contact hole.

[0019] Of course, in practical applications, the orthogonal projection of the sidewalls of the second trench in the first direction onto the semiconductor substrate can also be set to other shapes, and this application does not limit this.

[0020] For example, the first trench has a trench width in the second direction. This application does not limit the trench width; for example, the trench width is not greater than 1 μm. Optionally, the trench width is approximately one of 0.9 μm, 0.8 μm, 0.5 μm, or 0.3 μm.

[0021] Exemplarily, the first trench has a trench length in a first direction. This application does not limit the trench length; for example, the trench length is no greater than 10 μm. Optionally, the trench length is no greater than 5 μm. For example, the trench length is approximately one of 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0022] Assuming the electron mobility is uniform across different sides, a simple estimate shows that the current density ratio of the SiC MOSFET structure in this application is approximately 1.25*(2D1+1) / (D1+2) compared to the existing SiC MOSFET structure where the trench and contact holes are parallel. Here, D1 represents the trench length of the first trench in the first direction, and D1 ≤ 5µm. Simulation results show that when D1 is approximately 3µm, the gate layout structure of the SiC MOSFET in this application is almost 1.75 times more effective than the existing SiC MOSFET structure. When D1 is approximately 4µm, the gate layout structure of the SiC MOSFET in this application is almost 1.88 times more effective than the existing SiC MOSFET structure.

[0023] Exemplarily, the second trench has a trench width in the second direction. This application does not limit the trench width. Exemplarily, the trench width can be approximately set to the trench spacing. For example, the trench width is not greater than 1 μm. Optionally, the trench width ranges from 50 nm to 0.5 μm. For example, the trench width E2 can be approximately one of 50 nm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, or 0.5 μm.

[0024] For example, the second trench has a trench length in the first direction. This application does not limit the trench length; for example, the trench length is not greater than 1 μm. Optionally, the trench length is approximately one of 0.9 μm, 0.8 μm, 0.5 μm, or 0.3 μm.

[0025] In some possible implementations, the length of the second groove in the first direction is the same as the width of the first groove in the second direction. Of course, the length of the second groove in the first direction can also be greater than or less than the width of the first groove in the second direction; this is not limited here.

[0026] In some possible implementations, the first portion of the first trench extends along a fourth direction parallel to the plane of the semiconductor substrate, and the second portion of the first trench extends along a fifth direction parallel to the plane of the semiconductor substrate, wherein the fourth direction, the fifth direction, the second direction, and the first direction intersect each other. This allows for the provision of multiple first trenches extending in different directions. Furthermore, the orthographic projection of the sidewall of the second trench in the first direction onto the semiconductor substrate is linear, zigzag, or arc-shaped.

[0027] In some possible implementations, a third P-type semiconductor region is also provided in the drift layer. This third P-type semiconductor region is disposed below the trench structure and is in direct contact with the bottom of the first and second trenches in the trench structure. Furthermore, in this application, the third P-type semiconductor region can be connected to the source. When the SiC MOSFET device is operating, a voltage is applied to the source. Since the third P-type semiconductor region is connected to the source, the voltage applied to the source is input to the third P-type semiconductor region, giving it a corresponding voltage. This effectively shields the gate dielectric layer electric field at the bottom of the first and second trenches in the trench structure, thereby improving the robustness of the device operation.

[0028] For example, each trench structure is provided with a third P-type semiconductor region, and the third P-type semiconductor regions corresponding to different trench structures are spaced apart, that is, the third P-type semiconductor regions corresponding to different trench structures do not contact each other.

[0029] In some possible implementations, the orthographic projection of the third P-type semiconductor region onto the semiconductor substrate covers the orthographic projection of the bottom of the trench structure onto the semiconductor substrate. This can further and effectively shield the gate dielectric layer electric field at the bottom of the first and second trenches, thereby improving the robustness of device operation.

[0030] For example, the edge of the orthographic projection of the third P-type semiconductor region onto the semiconductor substrate can overlap with the edge of the orthographic projection of the bottom of the corresponding first trench and second trench onto the semiconductor substrate. Alternatively, the edge of the orthographic projection of the third P-type semiconductor region onto the semiconductor substrate can be disposed outside the edge of the orthographic projection of the bottom of the corresponding first trench and second trench onto the semiconductor substrate, further effectively shielding the gate dielectric layer electric field at the bottom of the first trench and second trench, thereby improving the robustness of device operation.

[0031] In actual manufacturing processes, due to limitations in process conditions or other factors, the aforementioned overlapping relationships may not be completely identical and may have some deviations. Therefore, as long as the aforementioned overlapping relationships roughly meet the above conditions, they are all within the scope of protection of this application. For example, the aforementioned overlapping relationships can be those that are permissible within the allowable error range.

[0032] In some examples of this application, the third P-type semiconductor region is formed at the bottom of the trench structure using a self-aligned process and a vertical ion implantation process after the trench structure is formed. Therefore, in the third direction, the third P-type semiconductor region can cover the trench structure. Furthermore, due to the diffusivity of ions during the ion implantation process, the third P-type semiconductor region diffuses towards the outer periphery of the bottom of the trench structure, meaning that the orthogonal projection edge of the third P-type semiconductor region on the semiconductor substrate is located outside the orthogonal projection edge of the trench structure on the semiconductor substrate.

[0033] This application does not limit the thickness of the third P-type semiconductor region in the third direction. For example, the thickness of the third P-type semiconductor region in the third direction may be less than 1 μm, or the thickness of the third P-type semiconductor region in the third direction may be 0.3 μm to 0.8 μm.

[0034] For example, when the SiC MOSFET provided in this application is applied to a power conversion circuit, its source can be grounded and its drain can be connected to other components. In this case, the voltage at the source of the SiC MOSFET is the ground voltage (0V). Since the third P-type semiconductor region is connected to the source, the voltage of the third P-type semiconductor region is also the ground voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0035] For example, when the SiC MOSFET provided in this application is applied to a power conversion circuit, its source can also be connected to other components, and its drain can also be connected to other components. In this case, the voltage at the source of the SiC MOSFET is the voltage of the signal input to the other components. Since the third P-type semiconductor region is connected to the source, the voltage of the third P-type semiconductor region is also the voltage of the input signal, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0036] In some possible implementations, the first trench has a first sidewall and a second sidewall disposed opposite to each other in the first direction, and the drift layer further includes a fourth P-type semiconductor region disposed on at least one first sidewall and / or second sidewall of the first trench, the fourth P-type semiconductor region being in contact with the third P-type semiconductor region and the first P-type semiconductor region, respectively. For example, the fourth P-type semiconductor region is disposed on the second sidewall of one or more first trenches. Alternatively, the fourth P-type semiconductor region is disposed on the first sidewall of one or more first trenches. Alternatively, the fourth P-type semiconductor region is disposed on the first sidewall and the second sidewall of one or more first trenches.

[0037] For example, the fourth P-type semiconductor region can be formed by doping the drift layer using an ion implantation process. Furthermore, the dopant in the P-type semiconductor region is primarily P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga).

[0038] For example, the doping concentrations of the first, third, and fourth P-type semiconductor regions are greater than the doping concentration of the second P-type semiconductor region. Optionally, the doping concentrations of the first, third, and fourth P-type semiconductor regions can be the same or similar. Of course, at least two of the doping concentrations of the first, third, and fourth P-type semiconductor regions can be different. It should be noted that the doping concentrations of the first, third, and fourth P-type semiconductor regions can be determined according to the requirements of the actual application environment, and are not limited here.

[0039] In this application, the fourth P-type semiconductor region is in contact with the third P-type semiconductor region and the first P-type semiconductor region, respectively. That is, the fourth P-type semiconductor region, the third P-type semiconductor region and the first P-type semiconductor region are respectively connected to the source, so that the voltage loaded at the source can be input to the third P-type semiconductor region through the first P-type semiconductor region and the fourth P-type semiconductor region, thereby effectively shielding the gate dielectric layer electric field at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0040] In some possible implementations, within the same trench structure, multiple first trenches are divided into at least one first unit and at least one second unit, with each first unit and second unit having at least one first trench. The first unit and second unit are alternately arranged along a second direction. Furthermore, the first trenches in the first unit have the same trench width in the second direction, and the first trenches in the second unit have the same trench width in the second direction, but the trench width of the first trench in the second unit is greater than the trench width of the first trench in the first unit in the second direction. That is, each trench structure contains two different trench widths for the first trenches. Additionally, the fourth P-type semiconductor region is disposed on the first sidewall and / or the second sidewall of each first trench in the second unit. Thus, by disposing of the fourth P-type semiconductor region on the second sidewall of the first trench, the third P-type semiconductor region can be effectively connected to the source electrode via the fourth P-type semiconductor region and the first P-type semiconductor region.

[0041] In some possible implementations, the number of first grooves is the same in different second units. Alternatively, some first units may have the same number of first grooves, while the remaining first units may have different numbers of first grooves. Or, different first units may have different numbers of first grooves.

[0042] And / or, the number of first grooves in different first units is the same. Of course, it is also possible for the number of first grooves in some second units to be the same, while the number of first grooves in the remaining second units is different. Alternatively, the number of first grooves in different second units may be different; this application does not limit this.

[0043] In some possible implementations, each first unit has one or more first trenches. For example, each first unit has multiple first trenches.

[0044] In some possible implementations, each second unit has one or more first trenches. For example, each second unit has one first trench.

[0045] In some possible implementations, the width of the first groove in the second unit in the second direction is not less than 1.5 times the width of the first groove in the first unit in the second direction. For example, the width of the first groove in the second unit in the second direction is approximately equal to 1.5 times the width of the first groove in the first unit in the second direction. Alternatively, the width of the first groove in the second unit in the second direction is approximately equal to 2 times the width of the first groove in the first unit in the second direction. Alternatively, the width of the first groove in the second unit in the second direction is approximately equal to 3 times the width of the first groove in the first unit in the second direction. Alternatively, the width of the first groove in the second unit in the second direction is approximately equal to 4 times the width of the first groove in the first unit in the second direction.

[0046] In some possible implementations, the drift layer further includes a fifth P-type semiconductor region, which is disposed below each of the first P-type semiconductor regions and is in contact with the first P-type semiconductor regions to form a P-type semiconductor structure. The fifth P-type semiconductor region extends into the first N-type semiconductor region along the third direction. Furthermore, the distance between the bottom of the fifth P-type semiconductor region and the top of the drift layer is greater than the distance between the bottom of the trench structure and the top of the drift layer. Therefore, the depth of the P-type semiconductor structure in the third direction is greater than the depth of the trench structure in the third direction. Additionally, the source can also contact the first P-type semiconductor region through a contact hole. Since the first P-type semiconductor region is in contact with the fifth P-type semiconductor region, the source and the fifth P-type semiconductor region are also electrically connected. That is, in this application, the source and the fifth P-type semiconductor region can be electrically connected, i.e., the source and the P-type semiconductor structure are electrically connected. In practical applications, when a SiC MOSFET device is working, a voltage is applied to the source. Since the fifth P-type semiconductor region is connected to the source, the voltage applied to the source is input to the fifth P-type semiconductor region, so that the fifth P-type semiconductor region also has a corresponding voltage. The fifth P-type semiconductor region acts as a shielding structure, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0047] For example, the orthographic projection of the first P-type semiconductor region onto the semiconductor substrate is located within the orthographic projection of the fifth P-type semiconductor region disposed directly below the first P-type semiconductor region onto the semiconductor substrate.

[0048] For example, when the SiC MOSFET provided in this application embodiment is applied to a power conversion circuit, its source can be grounded and its drain can be connected to other components. In this case, the voltage of the source of the SiC MOSFET is the ground voltage (0V). Since the fifth P-type semiconductor region is connected to the source, the voltage of the fifth P-type semiconductor region is also the ground voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0049] For example, when the SiC MOSFET provided in this application is applied to a power conversion circuit, its source can also be connected to other components, and its drain can also be connected to other components. In this case, the voltage at the source of the SiC MOSFET is the voltage of the signal input to the other components. Since the fifth P-type semiconductor region is connected to the source, the voltage of the fifth P-type semiconductor region is also the voltage of the input signal, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0050] In some possible implementations, each of the plurality of second trenches has a third sidewall and a fourth sidewall disposed opposite to each other in the first direction, and the orthographic projection of the P-type semiconductor structure on a first plane formed by the second direction and the third direction covers the orthographic projection of the corresponding second trench on the first plane.

[0051] In some possible implementations, the P-type semiconductor structures disposed on both sides of the drift layer can be each a single, integral region. That is, the P-type semiconductor structures disposed on the first and second sides of the trench structure can each be a single, integral region; conversely, the P-type semiconductor structures disposed on the first side of the same trench structure can be configured as a single, integral region, and the P-type semiconductor structures disposed on the second side of the same trench structure can also be configured as a single, integral region. Furthermore, if the orthographic projection of each P-type semiconductor structure onto the semiconductor substrate is a strip-shaped region extending along a second direction, then each P-type semiconductor structure extends from a first edge to a second edge along the second direction. Additionally, the orthographic projection of the P-type semiconductor structure onto the first plane overlaps the orthographic projection of the trench structure onto the first plane.

[0052] In some possible implementations, the P-type semiconductor structures disposed on the two sides of the drift layer are multiple regions, that is, the P-type semiconductor structures disposed on the first and second sides of the trench structure are multiple regions, and the multiple P-type semiconductor structures are spaced apart from each other. Furthermore, the multiple P-type semiconductor structures and the third part of the source region are spaced apart from each other, that is, the third part of the source region is projected onto the semiconductor substrate between two adjacent P-type semiconductor structures.

[0053] In some possible implementations, when the P-type semiconductor structures disposed on the first and second sides of the trench structure are multiple regions, the edge of the orthogonal projection of the P-type semiconductor structure on the first plane is disposed outside the edge of the orthogonal projection of the third and fourth sidewalls of the corresponding second trench on the first plane.

[0054] In some possible implementations, the orthographic projection of the P-type semiconductor structure onto the semiconductor substrate and the orthographic projection of the trench structure onto the semiconductor substrate do not overlap. That is, in the third direction, there is no overlapping region between each P-type semiconductor structure and each trench structure.

[0055] In some possible implementations, a fourth portion of the source region is present between the P-type semiconductor structure and the corresponding trench structure. That is, a portion of the source region is projected onto the semiconductor substrate between the orthographic projection of the P-type semiconductor structure onto the semiconductor substrate and the orthographic projection of the trench structure onto the semiconductor substrate. Alternatively, the gate dielectric layer disposed on the surfaces of the first and second sidewalls of the first trench in the trench structure may be disposed without contact with the corresponding P-type semiconductor structure.

[0056] In some possible implementations, when the P-type semiconductor structure disposed on the first and second sides of the trench structure comprises multiple regions, the trench structure contacts the corresponding P-type semiconductor structure through the corresponding gate dielectric layer; that is, the orthographic projection of the P-type semiconductor structure onto the semiconductor substrate contacts the orthographic projection of the gate dielectric layer corresponding to the trench structure onto the semiconductor substrate. Alternatively, it can be said that the gate dielectric layer disposed on the surfaces of the first and second sidewalls of the first trench in the trench structure is in contact with the corresponding P-type semiconductor structure.

[0057] In some possible implementations, the drift layer further includes first shielding trenches disposed on two sides of the drift layer, with the P-type semiconductor structure disposed on the sidewalls and bottom of the first shielding trenches. Furthermore, the plurality of first shielding trenches extend from the top of the drift layer into the first N-type semiconductor region along the third direction, with the first shielding trenches disposed on the first and second sides of the trench structure, respectively. Additionally, each of the plurality of first shielding trenches has a P-type semiconductor region disposed on its sidewall in the first direction, and the P-type semiconductor region disposed on the sidewall of each first shielding trench in the first direction serves as the P-type semiconductor structure.

[0058] For example, when a first shielding trench is provided between two adjacent trench structures, the orthographic projection of the first shielding trench onto the semiconductor substrate can be a strip-shaped region extending along the second direction. Alternatively, when multiple first shielding trenches are provided between two adjacent trench structures, the orthographic projection of a third region of the active region onto the semiconductor substrate can be provided between the orthographic projections of two adjacent first shielding trenches onto the semiconductor substrate.

[0059] For example, each sidewall of the first shielding trench is provided with a P-type semiconductor region. That is, each sidewall of each first shielding trench is provided with a P-type semiconductor region. Optionally, the P-type semiconductor region provided on the sidewall of each first shielding trench in the first direction can serve as a P-type semiconductor structure. For example, in the first direction, the first shielding trench has a fifth sidewall and a sixth sidewall disposed opposite to each other, and the P-type semiconductor region provided on the fifth sidewall and the P-type semiconductor region provided on the sixth sidewall of the first shielding trench can serve as a P-type semiconductor structure.

[0060] For example, a P-type semiconductor region is also provided at the bottom of each first shielding trench. By providing a P-type semiconductor region at the bottom of the first shielding trench, this application can further effectively shield the gate dielectric layer electric field at the bottom of the trench structure, thereby improving the robustness of device operation.

[0061] For example, the doping concentration of the P-type semiconductor region at the bottom of the first shielding trench is similar to or the same as the doping concentration of the P-type semiconductor region at its sidewalls. Alternatively, an ion implantation process can be used to form P-type semiconductor regions at the bottom and sidewalls of the first shielding trench to form a fifth P-type semiconductor region.

[0062] For example, the distance between the first shielding trench and the top of the drift layer is greater than the distance between the trench structure and the top of the drift layer. That is, the depth of the first shielding trench in the third direction is greater than the depth of the trench structure in the third direction. Thus, when using an ion implantation process to dope the sidewalls and bottom of the first shielding trench with P-type impurities, the doped ions will diffuse, thereby allowing the depth of the formed fifth P-type semiconductor region in the third direction to be greater than the depth of the trench structure in the third direction.

[0063] For example, the distance between the first shielding trench and the top of the drift layer can also be approximately equal to the distance between the trench structure and the top of the drift layer. That is, the depth of the first shielding trench in the third direction is similar to or the same as the depth of the trench structure in the third direction. In this way, when the sidewalls and bottom of the first shielding trench are doped using an ion implantation process, the doped ions will diffuse, thereby allowing the depth of the formed fifth P-type semiconductor region in the third direction to be greater than the depth of the trench structure in the third direction F3.

[0064] In some possible implementations, the trench structure is configured as a plurality of trench structures, which are arranged along the first direction, and adjacent trench structures share a first shielding trench disposed between the adjacent two trench structures.

[0065] Exemplarily, each first shielding trench is filled with a filler material, and this application does not limit the filler material. Exemplarily, the filler material can be the gate material, that is, each first shielding trench can be filled with the gate material. For example, in the actual process fabrication, when forming the gate, the gate material can be filled into the first shielding trench. Of course, each first shielding trench can also be filled with the material of the interlayer dielectric layer. Alternatively, each first shielding trench can also be filled with the material of the source or drain.

[0066] In some possible implementations, the drift layer further includes a second N-type semiconductor region disposed between the first N-type semiconductor region and the second P-type semiconductor region. Furthermore, the doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region, and the doping concentration of the second N-type semiconductor region is less than the doping concentration of the source region.

[0067] In this application, by providing a second N-type semiconductor region in the drift layer, the diffusion resistance of the current in the device at the upper end of the drift layer can be reduced.

[0068] This application does not limit the doping concentration of the second N-type semiconductor region; the doping concentration can meet the above requirements.

[0069] Secondly, embodiments of this application also provide a method for fabricating a semiconductor device, comprising:

[0070] A drift layer is epitaxially grown on an N-type semiconductor substrate, and a first N-type semiconductor region, a second P-type semiconductor region, and a source region are sequentially stacked on the semiconductor substrate in the drift layer. A first P-type semiconductor region is disposed on two sides of the drift layer, that is, the second P-type semiconductor region is disposed between the first N-type semiconductor region and the source region. The first P-type semiconductor region extends from the top of the drift layer to the second P-type semiconductor region along a third direction perpendicular to the plane of the semiconductor substrate.

[0071] The drift layer is etched to form a trench structure in the drift layer. The trench structure includes a plurality of first trenches and a plurality of second trenches. The plurality of first trenches are arranged along a second direction parallel to the plane of the semiconductor substrate. The plurality of second trenches extend along the second direction. The plurality of second trenches and the plurality of first trenches extend from the top of the drift layer to the first N-type semiconductor region along the third direction. A second trench is disposed between two adjacent first trenches, and the plurality of second trenches are interconnected with the plurality of first trenches.

[0072] A gate dielectric layer is formed in the trench structure;

[0073] A gate is formed in a trench structure in which a gate dielectric layer is formed;

[0074] An interlayer dielectric layer covering the entire drift layer is formed on the gate;

[0075] The interlayer dielectric layer is etched to expose the first P-type semiconductor region and a second portion of the source region, and the interlayer dielectric layer covers a first portion of the source region and completely covers the gate.

[0076] A source electrode is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, such that the source electrode is in contact with the first P-type semiconductor region and the second portion of the source region, and a drain electrode is formed on the side of the semiconductor substrate away from the drift layer.

[0077] In some possible implementations, to form the drift layer and the various semiconductor regions within the drift layer, in some examples, the steps of epitaxially growing the drift layer on an N-type semiconductor substrate, and forming a first N-type semiconductor region, a second P-type semiconductor region, and a source region sequentially stacked on the semiconductor substrate in the drift layer, as well as a first P-type semiconductor region disposed on both sides of the drift layer, may include:

[0078] First, an epitaxial layer is grown on an N-type semiconductor substrate using an epitaxial process. For example, an epitaxial layer of SiC material doped with N-type impurities is grown on an N-type SiC semiconductor substrate to form a drift layer of a predetermined thickness. This application does not limit the specific value of the predetermined thickness. In practical applications, the specific value of the predetermined thickness can be determined according to the requirements of the actual application environment.

[0079] Subsequently, ion implantation is performed in a portion of the drift layer to form a first P-type semiconductor region, a second P-type semiconductor region, and a source region. Regions in the drift layer not implanted with ions form a first N-type semiconductor region, and the formed second P-type semiconductor region is positioned between the first N-type semiconductor region and the source region. For example, firstly, ion implantation is used to dope the surface of the drift layer with P-type impurities to form a second P-type semiconductor region. Then, a first mask layer (which can be a mask made of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. A suitable etching process, either dry or wet, is used to etch the first mask layer, forming a first mask opening. This opening exposes the corresponding region in the drift layer where the source region needs to be formed, while the remaining areas of the drift layer are covered by the retained first mask layer. Next, ion implantation is used to dope the surface of the drift layer with N-type impurities to form the source region. Finally, the first mask layer is removed. Next, a second mask layer is formed on the drift layer (this second mask layer can be a mask formed of silicon dioxide, polysilicon, or silicon nitride). The second mask layer is etched using a suitable etching process, either dry or wet, to form a second mask opening. This opening exposes the corresponding region in the drift layer where the first P-type semiconductor region needs to be formed, while the remaining areas of the drift layer are covered by the retained second mask layer. Then, an ion implantation process is used to dope the surface of the drift layer with P-type impurities, forming the first P-type semiconductor region. Finally, the second mask layer is removed.

[0080] In some possible implementations, to form the drift layer and the various semiconductor regions within the drift layer, in other examples, the steps of epitaxially growing the drift layer on an N-type semiconductor substrate, and forming a first N-type semiconductor region, a second P-type semiconductor region, and a source region sequentially stacked on the semiconductor substrate in the drift layer, as well as a first P-type semiconductor region disposed on both sides of the drift layer, may include:

[0081] First, an epitaxial layer of a first predetermined thickness is grown on an N-type semiconductor substrate using an epitaxial process. For example, an epitaxial process is used to grow SiC material doped with N-type impurities on an N-type SiC semiconductor substrate to form a drift layer reaching the first predetermined thickness. This application does not limit the specific value of the first predetermined thickness. In practical applications, the specific value of the first predetermined thickness can be determined according to the requirements of the actual application environment.

[0082] Subsequently, an epitaxial growth process is used to epitaxially grow a second P-type semiconductor region of a second predetermined thickness on a drift layer of a first predetermined thickness. For example, an epitaxial growth process is used to epitaxially grow SiC material doped with P-type impurities on the drift layer to form a second P-type semiconductor region reaching the second predetermined thickness. This application does not limit the specific value of the second predetermined thickness. In practical applications, the specific value of the second predetermined thickness can be determined according to the requirements of the actual application environment.

[0083] Subsequently, epitaxial growth is continued on the second P-type semiconductor region using an epitaxial process until a drift layer reaching a third predetermined thickness is formed. For example, using an epitaxial process, SiC material doped with N-type impurities is further epitaxially grown on the second P-type semiconductor region to form a drift layer reaching the third predetermined thickness. This application does not limit the specific value of the third predetermined thickness. In practical applications, the specific value of the third predetermined thickness can be determined according to the requirements of the actual application environment.

[0084] Subsequently, an ion implantation process is used to implant ions into a portion of the drift layer to form a first P-type semiconductor region and a source region. Regions in the drift layer not implanted with ions form a first N-type semiconductor region, and a second P-type semiconductor region is positioned between the first N-type semiconductor region and the source region. For example, firstly, a first mask layer (which can be a mask made of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. A suitable etching process, either dry or wet, is used to etch the first mask layer, forming a first mask opening. This opening exposes the corresponding region in the drift layer where the source region needs to be formed, while the remaining areas of the drift layer are covered by the retained first mask layer. Next, an ion implantation process is used to dope the surface of the drift layer with N-type impurities to form the source region. Finally, the first mask layer is removed. Next, a second mask layer is formed on the drift layer (this second mask layer can be a mask formed of silicon dioxide, polysilicon, or silicon nitride). The second mask layer is etched using a suitable etching process, either dry or wet, to form a second mask opening. This opening exposes the corresponding region in the drift layer where the first P-type semiconductor region needs to be formed, while the remaining areas of the drift layer are covered by the retained second mask layer. Then, an ion implantation process is used to dope the surface of the drift layer with P-type impurities, forming the first P-type semiconductor region. Finally, the second mask layer is removed.

[0085] In some possible implementations, to form a trench structure, the step of etching the drift layer to form the trench structure in the drift layer may include: forming a third mask layer on the drift layer (the third mask layer may be a mask formed of silicon dioxide, polysilicon, or silicon nitride); etching the third mask layer using a suitable etching process, either dry or wet, to form a third mask opening; exposing the corresponding region in the drift layer where the trench structure needs to be formed through the third mask opening, while covering the remaining region of the drift layer 100 with the remaining third mask layer; then etching the drift layer exposed through the second mask opening using a dry or wet etching process until etching reaches the first N-type semiconductor region to form the first trench and the second trench in the trench structure in the drift layer; and finally removing the third mask layer.

[0086] In some possible implementations, to form the gate dielectric layer, in some examples, forming the gate dielectric layer in the trench structure may include using an oxidation process to oxidize the entire drift layer, so that the surface of the drift layer forms the gate dielectric layer. Specifically, the surface of each first trench and each second trench forms the gate dielectric layer, and the surface of the drift layer facing away from the semiconductor substrate also forms the gate dielectric layer.

[0087] In some possible implementations, to form the gate, in some examples, the gate is formed in a trench structure having a gate dielectric layer. This may include: first, using a deposition process, depositing polysilicon material onto the entirety of the drift layer forming the gate trenches, filling each first trench and each second trench with the polysilicon material, and after filling each first trench and each second trench with the polysilicon material, covering the entire drift layer with a polysilicon film. Then, using a planarization process, planarizing the polysilicon film, stopping when the top of the drift layer (e.g., the source region of the drift layer) is exposed, retaining the polysilicon material in the first and second trenches, and removing the remaining polysilicon material to form the gate. For example, the polysilicon film is planarized using a planarization process such as Chemical Mechanical Polishing (CMP).

[0088] In some possible implementations, to form an interlayer dielectric layer, in some examples, forming an interlayer dielectric layer on the gate that covers the entire drift layer may include: using a deposition process to deposit the interlayer dielectric layer on the entire drift layer and make the interlayer dielectric layer cover the entire drift layer.

[0089] In some possible implementations, in order to etch the interlayer dielectric layer, in some examples, the interlayer dielectric layer is etched to expose a second portion of the first P-type semiconductor region and the source region, and the interlayer dielectric layer covers the first portion of the source region and completely covers the gate. This can include: first, forming a fourth mask layer on the drift layer (the fourth mask layer may be a mask formed of silicon dioxide, polysilicon, or silicon nitride), etching the fourth mask layer using a suitable etching process, either dry etching or wet etching, to form a fourth mask opening, covering the first portion of the source region and the area that completely covers the gate (i.e., the area where contact hole 02 does not need to be formed) in the interlayer dielectric layer with the retained fourth mask layer, and exposing the area in the interlayer dielectric layer that corresponds to the second portion of the first P-type semiconductor region and the source region (i.e., the area where contact hole 02 is formed) with the fourth mask opening. Subsequently, a dry etching process or a wet etching process is used to etch the area exposed through the fourth mask opening in the interlayer dielectric layer to form contact holes, thereby exposing the second part of the source region and the first P-type semiconductor region.

[0090] In some possible implementations, to form the source and drain, in some examples, the source is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, so that the source contacts the first P-type semiconductor region and the second portion of the source region, and the drain is formed on the side of the semiconductor substrate away from the drift layer. This can include: using a deposition process to deposit a metal material on the side of the interlayer dielectric layer away from the semiconductor substrate to form the source, so that the source contacts not only the interlayer dielectric layer but also the second portion of the first P-type semiconductor region and the source region. That is, the source contacts the first P-type semiconductor region and the source region through the metal material filled in the contact holes. Furthermore, when forming the source, a deposition process is also used to deposit a metal material on the side of the semiconductor substrate away from the drift layer to form the drain.

[0091] In some possible implementations, to form the source and drain, in other examples, the source is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, so that the source contacts the second portion of the first P-type semiconductor region and the source region, and the drain is formed on the side of the semiconductor substrate away from the drift layer. This may also include: using a deposition process to deposit a metal material on the side of the interlayer dielectric layer away from the semiconductor substrate to form the source, so that the source contacts not only the interlayer dielectric layer but also the second portion of the first P-type semiconductor region and the source region. That is, the metal material is used to fill contact holes, so that the source contacts the first P-type semiconductor region and the source region through the metal material filled in the contact holes. Then, using a deposition process, a metal material is deposited on the side of the semiconductor substrate away from the drift layer to form the drain.

[0092] In some possible implementations, after forming the trench structure in the drift layer to form the third P-type semiconductor region and the fourth P-type semiconductor region, the fabrication method further includes:

[0093] First, a third P-type semiconductor region is formed at the bottom of each first trench and each second trench of the trench structure using a self-aligned process and a vertical ion implantation process. Exemplarily, a self-aligned process and a vertical ion implantation process can be used to dope the bottom of each first trench and each second trench of the trench structure with P-type impurities, forming a third P-type semiconductor region consistent with the bottom pattern of each first trench and each second trench of the trench structure. This application does not limit the thickness of the third P-type semiconductor region (i.e., the thickness in the third direction). In practical applications, the specific value of the thickness of the third P-type semiconductor region can be determined according to the requirements of the actual application environment. Furthermore, the thickness of the third mask layer in the third direction is typically set to around 100 nm, so the third mask layer can be temporarily retained in the above steps. When forming the third P-type semiconductor region, the sidewalls of the first and second trenches can be protected by the retained third mask layer, preventing ions scattered to the sidewalls of the first and second trenches during the vertical ion implantation process from entering the sidewalls. In the vertical ion implantation process, ions directly implanted into the bottom of the trench are not blocked by the third mask layer, allowing them to enter the bottom of the first and second trenches normally, forming the third P-type semiconductor region. After the third P-type semiconductor region is formed, the third mask layer is removed.

[0094] Alternatively, a self-aligned process and a vertical ion implantation process can be used to dop the bottom of each first trench and each second trench of the trench structure with P-type impurities. Afterward, the semiconductor device doped with P-type impurities is subjected to ion-activated annealing and surface cleaning treatments to form the third P-type semiconductor region 91.

[0095] Subsequently, using a tilted ion implantation process, a fourth P-type semiconductor region is formed at at least one sidewall of at least one of the first trenches along the first direction, respectively contacting the third P-type semiconductor region and the first P-type semiconductor region. Exemplarily, using a tilted ion implantation process, P-type impurity doping is performed on the surface of the second sidewall of each second trench in the second unit to form a fourth P-type semiconductor region contacting both the third P-type semiconductor region and the first P-type semiconductor region. Alternatively, using a tilted ion implantation process, P-type impurity doping is performed on the surface of the second sidewall of each second trench in the second unit. Afterwards, the semiconductor device after P-type impurity doping undergoes ion activation annealing and surface cleaning treatment sequentially to form a fourth P-type semiconductor region contacting both the third P-type semiconductor region and the first P-type semiconductor region.

[0096] In some possible implementations, to form a fifth P-type semiconductor region, after forming a first N-type semiconductor region, a first P-type semiconductor region, a second P-type semiconductor region, and a source region in the drift layer, the fabrication method further includes: forming a fifth P-type semiconductor region below each of the first P-type semiconductor regions, such that the fifth P-type semiconductor region extends into the first N-type semiconductor region along the third direction, and the fifth P-type semiconductor region is in contact with the first P-type semiconductor region to form a P-type semiconductor structure; wherein the distance between the bottom of the fifth P-type semiconductor region and the top of the drift layer is greater than the distance between the bottom of the trench structure and the top of the drift layer.

[0097] Exemplarily, firstly, two sides of the drift layer are etched to form a first shielding trench extending upward along the third direction into the first N-type semiconductor region in the drift layer; wherein the first shielding trench is respectively formed on the first and second sides of the trench structure. Exemplarily, a fifth mask layer (which may be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. The fifth mask layer is etched using a suitable etching process, either dry or wet, to form a fifth mask opening. The corresponding area in the drift layer where the first shielding trench needs to be formed is exposed through the fifth mask opening, while the remaining area of ​​the drift layer is covered by the retained fifth mask layer. Then, the drift layer exposed through the fifth mask opening is etched using a dry or wet etching process until it reaches the first N-type semiconductor region, to form a plurality of first shielding trenches extending along the second direction and arranged along the first direction in the drift layer. The fifth mask layer is temporarily retained.

[0098] Subsequently, ion implantation is performed on the sidewalls and bottom of the first shielding trench to form a fifth P-type semiconductor region. This fifth P-type semiconductor region is located below the first P-type semiconductor region and corresponds to and is in contact with it. Exemplarily, ion implantation is used to dope the sidewalls and bottom of each first shielding trench with P-type impurities. Then, the fifth mask layer is removed. Next, the semiconductor devices with P-type impurity doped on the sidewalls and bottom of each first shielding trench are sequentially subjected to ion activation annealing and surface cleaning to form a fifth P-type semiconductor region located below the first P-type semiconductor region. Since the first P-type semiconductor region is formed in the above steps, the fifth mask opening only exposes a portion of the first P-type semiconductor region, ensuring that the sidewalls of the first shielding trench near the top contain the first P-type semiconductor region. Therefore, ion implantation can be performed primarily on the sidewalls near the bottom of the first shielding trench to form a fifth P-type semiconductor region, making the fifth P-type semiconductor region contact the first P-type semiconductor region. Alternatively, ion implantation can be performed on the entire sidewall of the first shielding trench, making the fifth P-type semiconductor region and the first P-type semiconductor region contact each other as a single unit.

[0099] Thirdly, embodiments of this application also provide a power conversion circuit for converting alternating current (AC) and / or direct current (DC) to output direct current. For example, the power conversion circuit can be an AC-to-DC converter and / or a DC-to-DC converter. The power conversion circuit may include a circuit board and one or more semiconductor devices, with the semiconductor devices connected to the circuit board. The semiconductor devices may be those used in the first aspect or various possible designs of the first aspect, or those fabricated using the second aspect or various possible designs of the second aspect. Because the aforementioned semiconductor devices have good performance, the power conversion circuit including these semiconductor devices also has good performance. Furthermore, the principle by which this power conversion circuit solves the problem is similar to the principle by which the aforementioned semiconductor devices solve the problem; therefore, the technical effects of this power conversion circuit can be referred to the technical effects of the aforementioned semiconductor devices, and repetitions will not be repeated.

[0100] Fourthly, embodiments of this application also provide a vehicle that may include a load and a power conversion circuit. The power conversion circuit converts alternating current and / or direct current into direct current before inputting it to the load to supply power. This power conversion circuit can be as described in the third aspect or various possible designs of the third aspect. Because the power conversion circuit described above has good performance, the vehicle including such a circuit also has good circuit performance. Furthermore, the principle by which this vehicle solves the problem is similar to the principle by which the aforementioned power conversion circuit solves the problem; therefore, the technical effects of this vehicle can be referred to the technical effects of the aforementioned power conversion circuit, and repetitions will not be repeated. Attached Figure Description

[0101] Figure 1 This diagram shows the relationship between the channel resistance and the JFET resistance in a SiC MOSFET device.

[0102] Figure 2a This is a schematic diagram of the structure of an electric vehicle provided in one embodiment of this application;

[0103] Figure 2b This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application;

[0104] Figure 3 A top view of a semiconductor device provided in one embodiment of this application;

[0105] Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure along the tangent direction of AA'.

[0106] Figure 5 for Figure 3 A schematic cross-sectional view of the structure along the tangent direction of BB'.

[0107] Figure 6 for Figure 3 A schematic diagram of the cross-sectional structure along the VV' tangent direction;

[0108] Figure 7 for Figure 3 A schematic diagram of the three-dimensional structure in the selected area QB0 shown;

[0109] Figure 8 for Figure 7 The diagram shows a three-dimensional structure of a semiconductor device without a source electrode.

[0110] Figure 9 for Figure 7 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode.

[0111] Figure 10 for Figure 3 A partial top view of the contact hole structure of the semiconductor device shown;

[0112] Figure 11 Some flowcharts illustrating the fabrication method of the semiconductor device provided in the embodiments of this application;

[0113] Figures 12a to 12g This is a schematic diagram of a process for fabricating a semiconductor device, provided in an embodiment of this application.

[0114] Figure 13 A partial top view of a semiconductor device provided in another embodiment of this application;

[0115] Figure 14 for Figure 13 A schematic cross-sectional view of the semiconductor device along the AA' tangent direction;

[0116] Figure 15 for Figure 13 A schematic cross-sectional view of the semiconductor device along the BB' tangent direction;

[0117] Figure 16 for Figure 13 A schematic cross-sectional view of the semiconductor device along the CC' tangent direction;

[0118] Figure 17 for Figure 13 A schematic cross-sectional view of the semiconductor device along the VV' tangent direction;

[0119] Figure 18a for Figure 13 A schematic diagram of some three-dimensional structures in the selected area QB1 is shown;

[0120] Figure 18b for Figure 13 Other schematic diagrams of the three-dimensional structures in the selected area QB1 are shown;

[0121] Figure 19 It shows Figure 13 A schematic diagram of the three-dimensional structure in the selected area QB2 shown;

[0122] Figure 20 Other flowcharts illustrating the fabrication method of the semiconductor device provided in the embodiments of this application;

[0123] Figure 21 A partial top view of a semiconductor device provided in another embodiment of this application;

[0124] Figure 22 for Figure 21 A schematic cross-sectional view of the semiconductor device along the AA' tangent direction;

[0125] Figure 23 for Figure 21 A schematic cross-sectional view of the semiconductor device along the BB' tangent direction;

[0126] Figure 24 for Figure 21 A schematic cross-sectional view of the semiconductor device along the VV' tangent direction;

[0127] Figure 25 for Figure 21 A schematic diagram of the three-dimensional structure in the selected area QB3 is shown.

[0128] Figure 26 Further flowcharts illustrating the methods for fabricating semiconductor devices provided in embodiments of this application;

[0129] Figure 27 A partial top view of a semiconductor device provided in another embodiment of this application;

[0130] Figure 28 for Figure 27 A schematic cross-sectional view of the semiconductor device along the AA' tangent direction;

[0131] Figure 29 for Figure 27 A schematic cross-sectional view of the semiconductor device along the BB' tangent direction;

[0132] Figure 30 for Figure 27 A schematic cross-sectional view of the semiconductor device along the VV' tangent direction;

[0133] Figure 31 A partial top view of a semiconductor device provided in another embodiment of this application;

[0134] Figure 32 for Figure 31 A schematic cross-sectional view of the semiconductor device along the BB' tangent direction;

[0135] Figure 33 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application;

[0136] Figure 34 A top view of a semiconductor device provided in another embodiment of this application;

[0137] Figure 35 This is a top view of a semiconductor device provided in another embodiment of this application.

[0138] Figure label:

[0139] 010 - Electric vehicles; 012 - Batteries; 013 - Loads; 0100 - Electronic equipment; 011 / 0110 - Power conversion circuits; 0120 - Load modules; 0200 - Power supplies; 0111 - DC-DC converters;

[0140] GK1 / GK2 - Trench structure; 02 / 021 / 022 / 023 - Contact hole; 1 - Drain; 2 - Semiconductor substrate; 100 - Drift layer; 3 - First N-type semiconductor region; 4 / 4a / 4b / 4c - First P-type semiconductor region; 5 - Second P-type semiconductor region; 6 - Gate dielectric layer; 7 - Gate; 8 - Source region; 91 - Third P-type semiconductor region; 92 - Fourth P-type semiconductor region; 93 / 93a / 93b / 93c - Fifth P-type semiconductor region; 10 - Interlayer dielectric layer; 11 - Source; 12 - First shielding trench; 14 - Second N-type semiconductor region; 15 - Filling material; 101 / 101a / 101b - First trench; 102 - Second trench; 01a - First edge; 01b - Second edge; F1 - First direction; F2 - Second direction; F3 - Third direction; F4 - Fourth direction; F5 - Fifth direction; C - Trench spacing; D1 / D2 - Trench length; E1 / E2 - Trench width; F - Contact width; SK-P type semiconductor structure; S1 - First sidewall; S2 - Second sidewall; S3 - Third sidewall; S4 - Fourth sidewall; S5 - Fifth sidewall; S6 - Sixth sidewall; DS0 - Set thickness; hd1 / hd2 / hd3 - Distance; 8a - First part area; 8b - Second part area; 8c - Third part area; 8d0 / 8d1 / 8d2 / 8d3 / 8d4 - Fourth part area. Detailed Implementation

[0141] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "at least one" refers to one or more, where "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, it should be understood that in the description of this application, words such as "first" and "second" are only used for distinguishing the purpose of description and should not be construed as indicating or implying relative importance or order.

[0142] It should be noted that in the embodiments of this application, "connection" refers to electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components, such as the connection between A and B. Alternatively, it can be a direct connection between A and C, a direct connection between C and B, with A and B connected through C.

[0143] Furthermore, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them are omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0144] It should be noted that specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below. The following description is a preferred embodiment for carrying out this application; however, the description is for the purpose of illustrating the general principles of this application and is not intended to limit the scope of this application.

[0145] To facilitate understanding of the semiconductor devices, fabrication methods, power conversion circuits, and vehicles provided in the embodiments of this application, their application scenarios will be introduced first below.

[0146] The semiconductor devices provided in this application can be used in vehicles (e.g., electric vehicles), such as in onboard microcontroller units (MCUs) and onboard battery chargers (OBCs). It should be noted that the semiconductor devices proposed in this application are intended for use in these and any other suitable types of devices, including but not limited to. The following description uses an electric vehicle as an example.

[0147] Figure 2a This is a schematic diagram of the structure of an electric vehicle provided in an embodiment of this application. (Refer to...) Figure 2a The electric vehicle 010 may include a power conversion circuit 011 and a battery 012.

[0148] In one possible implementation, the power conversion circuit 011 may include an alternating current (AC) to direct current (DC) converter and a DC-DC converter. The power conversion circuit 011 can also be referred to as an inverter. For example, when an electric vehicle is charging, the electric vehicle 010 can be connected to a three-phase power grid and receive three-phase AC power from the grid. By controlling the operation of the power switch in the AC-DC converter in the power conversion circuit 011, the AC-DC converter can convert the three-phase AC power into DC power. Furthermore, by controlling the operation of the power switch in the DC-DC converter in the power conversion circuit 011, the DC-DC converter can regulate the voltage of the DC power output from the AC-DC converter, thereby providing voltage-matched DC power to the battery 012. This allows the battery 012 to store the DC power, thus achieving the charging function.

[0149] In another possible implementation, the power conversion circuit 011 can also be a DC-DC converter circuit, and the electric vehicle 010 can also include a load 013, which can be an on-board device, power system, etc. of the electric vehicle 010. For example, by controlling the operation of the power switch of the DC-DC converter circuit of the power conversion circuit 011, the power conversion circuit 011 can regulate the DC power output from the battery and output it to the load 013, thereby providing voltage-adapted DC power to the load 013.

[0150] The semiconductor device provided in this application embodiment is a trench-gate MOSFET, which can increase the conduction channel density without increasing the JFET region resistance, thereby reducing the total conduction resistance, improving device performance, and reducing device losses. Exemplarily, the semiconductor device provided in this application embodiment can be applied to the power conversion circuit 011 of a vehicle as a power switch in an AC-DC converter and / or a DC-DC converter. Because the semiconductor device provided in this application embodiment has good device performance, when applied to an AC-DC converter and / or a DC-DC converter, it can improve the performance of the AC-DC converter and / or the DC-DC converter and reduce drive losses, thereby improving the overall circuit performance and reducing drive losses.

[0151] The semiconductor devices provided in this application can also be widely used in various electronic devices, such as those with logic devices or memory devices. For example, such electronic devices can be smartphones, smart TVs, laptops, PDAs (personal digital assistants), wearable devices with wireless communication capabilities (such as smartwatches, smart glasses, and smart bracelets), etc. It should be noted that the semiconductor devices proposed in this application are intended for use in these and any other suitable types of electronic devices, including but not limited to.

[0152] Figure 2b This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. (Refer to...) Figure 2b The electronic device 0100 provided in this application embodiment includes a power conversion circuit 0110 and a load module 0120, with the power conversion circuit 0110 and load module 0120 electrically connected. Exemplarily, the electronic device 0100 can be any electrical device. Examples include smartphones, smart TVs, laptops, PDAs (personal digital assistants), wearable devices with wireless communication capabilities (such as smartwatches, smart glasses, and smart bracelets), in-vehicle microcontroller units (MCUs), and on-board battery chargers (OBCs). It should be noted that this application does not limit the specific type of electronic device.

[0153] In some embodiments, the power conversion circuit 0110 can be a DC-DC power conversion circuit, used to boost or buck DC power and output DC power to supply power to the load module 0120. For example, the power conversion circuit 0110 can convert the DC power (e.g., 48V) output from the power supply 0200 into DC power suitable for all types of load modules 0120 and output it to the load module 0120 for operation. This application does not impose any limitations on the power supply 0200 and the load module 0120. The power supply 0200 can be any device or component capable of outputting DC power. For example, the power supply 0200 can be a battery (e.g., a storage battery). The power conversion circuit 0110 can receive the battery voltage provided by the battery, convert the battery voltage into the operating voltage of the load module 0120, and output it to the load module 0120. The load module 0120 can be any functional module that uses DC power, such as a processor, chip, etc.

[0154] Reference Figure 2aThe power conversion circuit 0110 includes a DC-DC converter 0111. In operation, the MOSFETs in the DC-DC converter 0111 operate at a certain switching frequency, causing the DC-DC converter 0111 to boost or buck the DC power from the power supply 0200 and output DC power to provide the operating voltage for the load module 0120. For example, the DC-DC converter may be a Buck converter, a Boost converter, a half-bridge converter, a full-bridge converter, or an inductor-inductor-capacitor (LLC) resonant converter.

[0155] The semiconductor device provided in this application embodiment is a trench-gate MOSFET, which can increase the conduction channel density without increasing the JFET region resistance, thereby reducing the total conduction resistance, improving device performance, and reducing device losses. Exemplarily, the semiconductor device provided in this application embodiment can be applied to a DC-DC converter 0111 as a MOSFET in the DC-DC converter 0111. Because the semiconductor device provided in this application embodiment has good device performance, when applied to the MOSFET in the DC-DC converter 0111, it can improve the performance of the DC-DC converter 0111 and reduce drive losses, thereby improving the performance of the entire electronic device and reducing drive losses.

[0156] It should be noted that the above scenario descriptions are merely illustrative of some feasible application methods of the semiconductor device of this application. This application does not limit the specific application scenarios of the semiconductor device provided in the embodiments of this application, and can be determined according to the actual application requirements.

[0157] In some embodiments provided in this application, the semiconductor substrate 2 and the drift layer 100 are made of SiC. Therefore, the semiconductor device provided in the embodiments of this application is a SiC MOSFET.

[0158] It should be explicitly stated that, in this application, layers and regions prefixed with N or P represent electrons or holes as the majority carriers, respectively. Furthermore, a "+" sign marked with N or P indicates a higher doping concentration than layers or regions without a "+" sign, and the more "+" signs, the higher the doping concentration. The presence of the same number of "+" signs in N or P indicates similar doping concentrations, but is not limited to the same doping concentration. Similarly, a "-" sign marked with N or P indicates a lower doping concentration than layers or regions without a "-" sign, and the more "-" signs, the lower the doping concentration. The presence of the same number of "-" signs in N or P indicates similar doping concentrations, but is not limited to the same doping concentration.

[0159] It should also be noted that the comparison of doping concentration between the two regions in this application refers only to the comparison of the concentration of impurities doped in the two regions. The composition of the impurities is not limited to the substrate used to dope the impurities; that is, the composition of the impurities may be the same or different. The materials of the substrates used to dope the impurities may be the same or different.

[0160] Figure 3 This illustration shows a partial top view of a semiconductor device provided in one embodiment of the present application. Figure 4 It shows Figure 3 A schematic diagram of the cross-sectional structure along the tangent direction of AA'. Figure 5 It shows Figure 3 A schematic diagram of the cross-sectional structure along the tangent direction of BB'. Figure 6 It shows Figure 3 A schematic diagram of the cross-sectional structure along the VV' tangent direction. Figure 7 It shows Figure 3 The diagram shows the three-dimensional structure of the selected region QB0. Figure 8 It shows Figure 7 The diagram shows a three-dimensional structure of a semiconductor device without a source electrode. Figure 9 It shows Figure 7 The diagram shows a three-dimensional structure of a semiconductor device without an interlayer dielectric layer and a source electrode. Figure 10 It shows Figure 3 The diagram shows a partial top view of the contact hole structure of the semiconductor device. The semiconductor device in this application may have one or more trench structures. Figures 3 to 6 The illustration only uses a semiconductor device with two trench structures as an example.

[0161] Reference Figures 3 to 9The semiconductor device provided in this application includes: an N-type semiconductor substrate 2, a drift layer 100 disposed on the semiconductor substrate 2, two trench structures GK1 and GK2 disposed within the drift layer 100, a gate dielectric layer 6, a gate electrode 7, an interlayer dielectric layer 10, a source electrode 11, and a drain electrode 1. The drift layer 100 includes: a first N-type semiconductor region 3, a first P-type semiconductor region 4 (e.g., 4a, 4b, 4c), a second P-type semiconductor region 5, and a source region 8. The first N-type semiconductor region 3, the second P-type semiconductor region 5, and the source region 8 are sequentially stacked on the semiconductor substrate 2, i.e., the second P-type semiconductor region 5 is disposed between the first N-type semiconductor region 3 and the source region 8. Specifically, the first N-type semiconductor region 3 is in contact with the semiconductor substrate 2, and the source region 8 is disposed in the top region of the drift layer 100. Furthermore, the first P-type semiconductor region 4 (such as 4a, 4b, 4c) extends from the top of the drift layer 100 to the second P-type semiconductor region 5 along a third direction F3 perpendicular to the plane where the semiconductor substrate 2 is located, so the first P-type semiconductor regions 4a, 4b, 4c and the second P-type semiconductor region 5 are in contact with each other.

[0162] In this application, the semiconductor substrate 2 can be a silicon carbide substrate doped with pentavalent elements. The drift layer 100 can be formed by epitaxial growth of SiC material doped with corresponding impurities. For example, the first N-type semiconductor region 3 is a portion of the drift layer 100 formed by epitaxial growth. The source region 8 is an N-type semiconductor region, and the source region 8 can be formed by N-type impurity doping of the drift layer 100 using an ion implantation process.

[0163] For example, in this application, the N-type semiconductor region is mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P) or arsenic (As).

[0164] For example, in this application, the doping concentration of the semiconductor substrate 2 is greater than the doping concentration of the first N-type semiconductor region 3, and the doping concentration of the source region 8 is also greater than the doping concentration of the first N-type semiconductor region 3. Optionally, the doping concentration of the semiconductor substrate 2 is similar to or the same as the doping concentration of the source region 8. Of course, the doping concentration of the semiconductor substrate 2 and the doping concentration of the source region 8 can also be different; for example, the doping concentration of the semiconductor substrate 2 may be greater than or less than the doping concentration of the source region 8, which is not limited here.

[0165] In this application, the second P-type semiconductor region 5 can also be formed by epitaxially growing SiC material doped with P-type impurities; that is, the second P-type semiconductor region 5 can also be a portion of the drift layer 100 formed by epitaxial growth. Alternatively, the second P-type semiconductor region 5 can also be formed by ion implantation, through P-type impurity doping of the drift layer 100. This application does not limit the formation process of the second P-type semiconductor region 5.

[0166] For example, in this application, the P-type semiconductor region is mainly doped with P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga).

[0167] Continue to refer to Figure 3 and Figure 9 In this application, each trench structure (such as GK1, GK2) includes a plurality of first trenches 101 and a plurality of second trenches 102. Within the same trench structure (such as GK1, GK2), the plurality of first trenches 101 extend along a first direction F1 parallel to the plane of the semiconductor substrate 2, and are arranged along a second direction F2 parallel to the plane of the semiconductor substrate 2. The plurality of second trenches 102 extend along the second direction F2 and are staggered along the second direction F2. The plurality of first trenches 101 and the plurality of second trenches 102 extend along a third direction F3 into the first N-type semiconductor region 3. Furthermore, a second trench 102 is disposed between two adjacent first trenches 101, and the plurality of second trenches 102 are interconnected with the plurality of first trenches 101. That is, a closely spaced trench array is fabricated in the drift layer 100.

[0168] For example, continue to refer to Figure 3 and Figure 9 In this application, in the trench structure GK1, a second trench 102 is provided between two adjacent first trenches 101, and the second trench 102 is located on the sidewall of the first trench 101. Furthermore, in the trench structure GK2, a second trench 102 is also provided between two adjacent first trenches 101, and the second trench 102 is located on the sidewall of the first trench 101.

[0169] For example, continue to refer to Figures 3 to 9 In this application, each of the plurality of first trenches 101 has a first sidewall S1 and a second sidewall S2 disposed opposite to each other in a first direction F1. Specifically, in trench structure GK1, a first portion of the plurality of second trenches 102 is disposed at the first sidewall S1 of the first trench 101, and a second portion of the second trench 102 is disposed at the second sidewall S2 of the first trench 101, with the first and second portions of the second trenches 102 alternating along a second direction F2. Furthermore, in trench structure GK2, a first portion of the plurality of second trenches 102 is disposed at the first sidewall S1 of the first trench 101, and a second portion of the second trench 102 is disposed at the second sidewall S2 of the first trench 101, with the first and second portions of the second trenches 102 alternating along a second direction F2.

[0170] For example, continue to refer to Figure 3 and Figure 9In this application, the edge of the sidewall of the second trench 102 projected onto the semiconductor substrate 2 along the first direction F1 is straight. For example, the second trench 102 has opposing third sidewalls S3 and fourth sidewalls S4 along the first direction F1. The projection of the third sidewall S3 of the second trench 102 onto the semiconductor substrate 2 can be straight, and the projection of the fourth sidewall S4 of the second trench 102 onto the semiconductor substrate 2 can also be straight. Optionally, the third sidewall S3 of the second trench 102 can be the sidewall closer to the contact hole, and the fourth sidewall S4 of the second trench 102 can be the sidewall farther from the contact hole.

[0171] Alternatively, by way of example, in this application, the edge of the sidewall of the second trench along the first direction, projected onto the semiconductor substrate, is either a polygonal line or an arc. The second trench has opposing third and fourth sidewalls in the first direction. The projection of the third sidewall of the second trench onto the semiconductor substrate can be a straight line, and the projection of the fourth sidewall of the second trench onto the semiconductor substrate can also be a polygonal line or an arc. Optionally, the third sidewall of the second trench can be the sidewall of the second trench that is closer to the contact hole, and the fourth sidewall of the second trench can be the sidewall of the second trench that is farther from the contact hole.

[0172] Of course, in practical applications, the orthogonal projection of the sidewalls of the second trench in the first direction onto the semiconductor substrate can also be set to other shapes, and this application does not limit this.

[0173] Continue to refer to Figure 3 The first trench 101 has a trench width E1 in the second direction F2. This application does not limit the trench width E1; for example, the trench width E1 is not greater than 1 μm. Optionally, the trench width E1 is approximately one of: 0.9 μm, 0.8 μm, 0.5 μm, and 0.3 μm.

[0174] Continue to refer to Figure 3 The first trench 101 has a trench length D1 in the first direction F1. This application does not limit the trench length D1; for example, the trench length D1 is not greater than 10 μm. Optionally, the trench length D1 is not greater than 5 μm. For example, the trench length D1 is approximately one of 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0175] Assuming the electron mobility is uniform across different sides, simple estimation shows that the current density ratio of the SiC MOSFET structure in this application compared to the prior art SiC MOSFET structure with parallel trench and contact holes is approximately 1.25*(2D1+1) / (D1+2), where D1 ≤ 5µm. Simulation results show that when D1 is approximately 3µm, the gate layout structure of the SiC MOSFET in this application is almost 1.75 times more effective than the prior art SiC MOSFET structure. When D1 is approximately 4µm, the gate layout structure of the SiC MOSFET in this application is almost 1.88 times more effective than the prior art SiC MOSFET structure.

[0176] Continue to refer to Figure 3 The second trench 102 has a trench width E2 in the second direction F2. This application does not limit the trench width E2. Exemplarily, the trench width E2 can be approximately set to the trench spacing C. For example, the trench width E2 is not greater than 1 μm. Optionally, the trench width E2 ranges from 50 nm to 0.5 μm. For example, the trench width E2 can be approximately one of 50 nm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, or 0.5 μm.

[0177] Continue to refer to Figure 3 The second trench 102 has a trench length D2 in the first direction F1. This application does not limit the trench length D2; for example, the trench length D2 is not greater than 1 μm. Optionally, the trench length D2 is approximately one of 0.9 μm, 0.8 μm, 0.5 μm, or 0.3 μm.

[0178] For example, continue to refer to Figure 3 and Figure 9 In this application, the groove length D2 of the second groove 102 in the first direction F1 is the same as the groove width E1 of the first groove 101 in the second direction F2. Of course, the groove length D2 of the second groove 102 in the first direction F1 can also be greater than or less than the groove width E1 of the first groove 101 in the second direction F2, which is not limited here.

[0179] Reference Figure 3In the same trench structure (such as GK1 and GK2), two adjacent first trenches have a trench spacing C in the second direction F2. This application does not limit the specific value of the trench spacing C; for example, the trench spacing C is not greater than 1 μm. Optionally, the trench spacing C ranges from 50 nm to 0.5 μm. For example, the trench spacing C can be approximately one of 50 nm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, or 0.5 μm. It should be noted that when the trench spacing C is less than 100 nm, the semiconductor device provided in this application will form a Fin Field-Effect Transistor (Fin FET) effect, which can significantly improve the carrier channel mobility and further reduce the total on-resistance of the device.

[0180] Continue to refer to Figures 3 to 9 In this application, the gate 7 is filled in the plurality of second trenches 102 and the plurality of first trenches 101 through the gate dielectric layer 6, so that the gate 7 is embedded inside the drift layer 100 of SiC material. Thus, the semiconductor device provided in this application embodiment is formed as a SiC MOSFET with a trench gate structure.

[0181] For example, in this application, the gate 7 is disposed in the second trench 102 and the first trench 101 of the trench structure, which is equivalent to the gate 7 extending in a zigzag manner along the trench structure. That is, overall, it is equivalent to the gate 7 extending in a zigzag manner along the second direction F2.

[0182] This application does not limit the material of the gate 7. For example, the material of the gate 7 can be polycrystalline silicon, or other materials with good conductivity such as metals (e.g., W, Al, Ti, Cu, Mo or Pt).

[0183] Continue to refer to Figures 3 to 10The interlayer dielectric layer 10 covers the side of the gate 7 away from the semiconductor substrate 2, that is, the interlayer dielectric layer 10 covers the entire side of the semiconductor substrate 2 with the gate 7. The source 11 is disposed on the side of the interlayer dielectric layer 10 away from the semiconductor substrate 2, that is, the source 11 covers the entire interlayer dielectric layer 10. The drain 1 is disposed on the side of the semiconductor substrate 2 away from the drift layer 100, that is, the drain 1 covers the side of the semiconductor substrate 2 without the drift layer 100. The interlayer dielectric layer 10 covers the gate 7 and the first portion 8a of the source region 8, exposing the second portion 8b of the first P-type semiconductor region 4 and the source region 8. The source 11 can cover the entire interlayer dielectric layer 10 and the second portion 8b of the first P-type semiconductor region 4 and the source region 8, that is, the source 11 is in direct contact with the upper surfaces of the interlayer dielectric layer 10, the first P-type semiconductor region 4, and the second portion 8b of the source region 8. This is equivalent to providing a contact hole 02 extending along the second direction Y in the interlayer dielectric layer 10, exposing the second part of the source region 8b of the source region 8 through the contact hole 02, thereby enabling the source electrode 11 to contact the source region 8 through the contact hole 02, achieving the effect of connecting the source electrode 11 to the source region 8. Thus, when the gate 7 controls the channel to be turned on, a signal can be transmitted between the source electrode 11 and the drain electrode 1.

[0184] In practical applications, signal transmission is required between the source 11 and the drain 1. A contact hole 02 extending along the second direction F2 can be provided in the interlayer dielectric layer 10. To prevent the source 11 from contacting the gate 7, the orthographic projection of the contact hole 02 onto the semiconductor substrate 2 and the orthographic projection of the gate 7 onto the semiconductor substrate 2 can be made non-overlapping; that is, the contact hole 02 and the gate 7 are non-overlapping in the third direction F3. The contact hole 02 exposes a portion of the source region 8, allowing the source 11 to contact the source region 8 through the contact hole 02, thus achieving the connection between the source 11 and the source region 8. Therefore, when the gate 7 controls the channel to conduct, signal transmission can occur between the source 11 and the drain 1.

[0185] This application does not limit the material used to form the interlayer dielectric layer 10. For example, the material used to form the interlayer dielectric layer 10 can be a dielectric material, including but not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.

[0186] This application does not limit the materials used to form the source electrode 11 and the drain electrode 1. For example, the materials used to form the source electrode 11 and the drain electrode 1 can be metallic materials. Exemplarily, the metallic materials may include W, Al, Ti, Cu, Mo, or Pt.

[0187] Continue to refer to Figure 3 , Figures 7 to 9The first direction F1, the second direction F2, and the third direction F3 are arranged intersecting each other. For example, the first direction F1, the second direction F2, and the third direction F3 are arranged perpendicular to each other.

[0188] The semiconductor device provided in this application embodiment has a closely spaced trench array fabricated in a drift layer, with gates disposed in the first and second trenches, and the region at the boundary between the second P-type semiconductor region and the gate dielectric layer forming a channel. Furthermore, the extension direction of the contact holes disposed in the interlayer dielectric layer is a second direction, and the extension direction of the first gate is a first direction. Therefore, the extension direction of the contact holes is perpendicular to the extension direction of the first gate, meaning the contact holes are placed in a direction perpendicular to the first gate. Compared to the prior art where the gate trenches and contact holes are parallel, the semiconductor device provided in this application embodiment reduces the restriction of the contact holes on the trench spacing C of adjacent first trenches in the second direction, allowing for a more compact fabrication of the first trenches, resulting in a more compact gate. This facilitates reducing the trench spacing between the first trenches, thereby miniaturizing the cells and improving cell density and device current carrying capacity. Therefore, the gate trench array density of the semiconductor device provided in this application embodiment can be much higher than the gate trench array density of the device structure in the prior art, thereby increasing the channel density of the SiC MOSFET with trench gate structure, significantly reducing the total on-resistance per unit area of ​​the device, improving the current carrying capacity and device performance, and reducing device losses.

[0189] Reference Figure 10 In some embodiments of this application, one or more trench structures are provided, and two or more contact holes are provided. Furthermore, a trench structure is provided between two adjacent contact holes. This allows for more uniform signal flow. For example, multiple trench structures can be provided in the semiconductor device, thus providing multiple contact holes. These multiple trench structures are arranged along a first direction F1, and the multiple contact holes are also arranged along the first direction F1. For example, taking two trench structures as an example, referring to… Figure 3 and Figure 10 The two groove structures are GK1 and GK2, respectively, and are arranged along the first direction F1. There are three contact holes 02: 021, 022, and 023, also arranged along the first direction F1. A groove structure GK1 is provided between contact holes 021 and 022, and a groove structure GK2 is provided between contact holes 022 and 023. Alternatively, there may be one groove structure, such as GK1. In this case, there may be two contact holes 02, such as 021 and 022. A groove structure GK1 is provided between contact holes 021 and 022.

[0190] In some embodiments of this application, the number of second trenches 102 and the number of first trenches 101 in different trench structures can be the same. This allows for a uniform distribution of the trench structures. Figure 3 and Figure 10 The number of second trenches 102 and first trenches 101 shown in trench structures GK1 and GK2 is for illustrative purposes only and does not represent the actual number of second trenches 102 and first trenches 101 in the fabricated semiconductor device. In practical applications, the specific number of second trenches 102 and first trenches 101 in the trench structure can be determined according to the requirements of the actual application, and this application does not impose any limitations on this.

[0191] In some embodiments of this application, the number of second grooves and the number of first grooves may be the same in some trench structures, while the number of second grooves and the number of first grooves may differ in the remaining trench structures. Alternatively, the number of second grooves and the number of first grooves may differ in different trench structures. In practical applications, the specific number of second and first grooves in the trench structure can be determined according to the needs of the actual application, and this application does not limit this.

[0192] In some embodiments of this application, in the second direction F2, the trench structure has a first edge and a second edge disposed opposite to each other, and the contact hole extends from the first edge to the second edge along the second direction F2. For example, referring to... Figure 3 and Figure 10 Taking the groove structure GK2 as an example, in the second direction F2, the contact hole 02 extends from the first edge 01a to the second edge 01b along the second direction F2. That is to say, the contact hole 02 is a continuous opening, and the second grooves 102 in different groove structures are not interconnected.

[0193] Reference Figure 10 In the first direction X, the contact hole 02 has a contact width F, which can ensure that the groove spacing C is not greater than the contact width F. Of course, the groove spacing C can also be greater than the contact width F. In practical applications, the groove spacing C and the contact width F can be determined according to the environmental requirements of the actual application, and are not limited here.

[0194] Reference Figure 3 The trench structure (such as GK1, GK2) has a fourth region with a source between the first trench 101 and the second trench 102 and the corresponding first P-type semiconductor region. That is, the fourth region (such as 8d1, 8d2, 8d3, 8d4) with a source between the orthogonal projection of the first trench 101 and the second trench 102 in the trench structure (such as GK1, GK2) on the semiconductor substrate and the orthogonal projection of the corresponding first P-type semiconductor region on the semiconductor substrate.

[0195] Figure 11 Some flowcharts illustrating the fabrication method of the semiconductor device provided in the embodiments of this application are shown. (Refer to...) Figure 11 To prepare Figure 7 Taking the structure shown as an example, the preparation method may include the following steps:

[0196] S10. An epitaxial drift layer is grown on an N-type semiconductor substrate, and a first N-type semiconductor region, a second P-type semiconductor region, and a source region are sequentially stacked on the semiconductor substrate in the drift layer, as well as a first P-type semiconductor region disposed on two sides of the drift layer. The second P-type semiconductor region is disposed between the first N-type semiconductor region and the source region, and the first P-type semiconductor region extends from the top of the drift layer into the second P-type semiconductor region along a third direction F3 perpendicular to the plane of the semiconductor substrate.

[0197] In some examples, step S10 may include:

[0198] First, an epitaxial layer 100 is grown on an N-type semiconductor substrate 2 using an epitaxial process.

[0199] For example, refer to Figure 12a Using an epitaxial process, SiC material doped with N-type impurities is epitaxially grown on an N-type SiC semiconductor substrate 2 to form a drift layer 100 with a set thickness DS0.

[0200] This application does not limit the specific value of the thickness DS0. In practical applications, the specific value of the thickness DS0 can be determined according to the requirements of the actual application environment.

[0201] Subsequently, an ion implantation process is used to implant ions into a portion of the drift layer 100 to form a first P-type semiconductor region 4 (such as 4a, 4b), a second P-type semiconductor region 5, and a source region 8. The regions of the drift layer 100 that have not been ion implanted form a first N-type semiconductor region 3, and the formed second P-type semiconductor region 5 is disposed between the first N-type semiconductor region 3 and the source region 8.

[0202] For example, refer to Figure 12bFirst, an ion implantation process is used to dope the surface of the drift layer 100 with P-type impurities, forming a second P-type semiconductor region 5. Next, a first mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer 100. The first mask layer is etched using a suitable etching process, either dry or wet, to form a first mask opening. This opening exposes the corresponding region in the drift layer 100 where the source region needs to be formed, while the remaining areas of the drift layer 100 are covered by the retained first mask layer. Then, an ion implantation process is used to dope the surface of the drift layer 100 with N-type impurities, forming a source region 8. Finally, the first mask layer is removed. Next, a second mask layer is formed on the drift layer 100 (this second mask layer can be a mask formed of silicon dioxide, polysilicon, or silicon nitride). The second mask layer is etched using a suitable etching process, either dry or wet, to form a second mask opening. This opening exposes the corresponding region in the drift layer 100 where the first P-type semiconductor region 4 (e.g., 4a, 4b) needs to be formed, while the remaining regions of the drift layer 100 are covered by the retained second mask layer. Then, an ion implantation process is used to dope the surface of the drift layer 100 with P-type impurities to form the first P-type semiconductor region 4 (e.g., 4a, 4b). Finally, the second mask layer is removed.

[0203] In other examples, step S10 may also include:

[0204] First, an epitaxial layer of a predetermined thickness is grown on an N-type semiconductor substrate using an epitaxial process.

[0205] For example, using an epitaxial process, SiC material doped with N-type impurities is epitaxially grown on an N-type SiC semiconductor substrate to form a drift layer reaching a first predetermined thickness.

[0206] This application does not limit the specific value of the first preset thickness. In practical applications, the specific value of the first preset thickness can be determined according to the needs of the actual application environment.

[0207] Subsequently, an epitaxial process is used to epitaxially grow a second P-type semiconductor region of a second predetermined thickness on a drift layer of a first predetermined thickness.

[0208] For example, using an epitaxial process, SiC material doped with P-type impurities is epitaxially grown on a drift layer to form a second P-type semiconductor region reaching a second predetermined thickness.

[0209] This application does not limit the specific value of the second preset thickness. In practical applications, the specific value of the second preset thickness can be determined according to the requirements of the actual application environment.

[0210] Subsequently, an epitaxial growth process is used to continue epitaxial growth on the second P-type semiconductor region until a drift layer with a third predetermined thickness is formed.

[0211] For example, using an epitaxial process, SiC material doped with N-type impurities is further epitaxially grown on the second P-type semiconductor region to form a drift layer reaching a third predetermined thickness.

[0212] This application does not limit the specific value of the third set thickness. In practical applications, the specific value of the third set thickness can be determined according to the needs of the actual application environment.

[0213] Subsequently, an ion implantation process is used to implant ions into a portion of the drift layer to form a first P-type semiconductor region and a source region. The regions in the drift layer that are not ion implanted form a first N-type semiconductor region, and the formed second P-type semiconductor region is positioned between the first N-type semiconductor region and the source region.

[0214] For example, firstly, a first mask layer (which can be a mask made of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. The first mask layer is then etched using a suitable etching process, either dry or wet, to form a first mask opening. This opening exposes the corresponding region in the drift layer where the source region needs to be formed, while the remaining areas of the drift layer are covered by the retained first mask layer. Next, an ion implantation process is used to dope the surface of the drift layer with N-type impurities to form the source region. Finally, the first mask layer is removed. Next, a second mask layer is formed on the drift layer (this second mask layer can be a mask formed of silicon dioxide, polysilicon, or silicon nitride). The second mask layer is etched using a suitable etching process, either dry or wet, to form a second mask opening. This opening exposes the corresponding region in the drift layer where the first P-type semiconductor region needs to be formed, while the remaining areas of the drift layer are covered by the retained second mask layer. Then, an ion implantation process is used to dope the surface of the drift layer with P-type impurities, forming the first P-type semiconductor region. Finally, the second mask layer is removed.

[0215] S20. Etch the drift layer to form a trench structure. The trench structure includes multiple first trenches and multiple second trenches. The multiple first trenches are arranged along a second direction parallel to the plane of the semiconductor substrate. The multiple second trenches extend along the second direction. The multiple second trenches and the multiple first trenches extend from the top of the drift layer to the first N-type semiconductor region along a third direction. A second trench is disposed between two adjacent first trenches, and the multiple second trenches are interconnected with the multiple first trenches.

[0216] In some examples, step S20 may include: referring to Figure 12c A third mask layer (which can be a mask made of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer 100. The third mask layer is etched using a suitable etching process, either dry or wet, to form a third mask opening. This opening exposes the corresponding region in the drift layer 100 where the trench structure needs to be formed, while the remaining areas of the drift layer 100 are covered by the retained third mask layer. Then, the drift layer 100 exposed through the second mask opening is etched using either dry or wet etching until it reaches the first N-type semiconductor region 3, forming the first trench 101 and the second trench 102 in the trench structure within the drift layer 100. Finally, the third mask layer is removed.

[0217] S30. A gate dielectric layer is formed in the trench structure.

[0218] In some examples, step S30 may include: referring to Figure 12d An oxidation process is used to oxidize the entire drift layer 100, forming a gate dielectric layer 6 on the surface of the drift layer 100. Specifically, the gate dielectric layer 6 is formed on the surface of each first trench and each second trench 102, and a gate dielectric layer 6 is also formed on the surface of the drift layer 100 facing away from the semiconductor substrate 2 (the gate dielectric layer 6 at this location is only partially formed). Figure 12d (Not shown in the image).

[0219] S40. A gate is formed in a trench structure in which a gate dielectric layer is formed.

[0220] In some examples, step S40 may include: First, using a deposition process, depositing polysilicon material on the entire drift layer 100 where gate trenches are formed, and filling each first trench 101 and each second trench 102 with the polysilicon material, and after filling each first trench 101 and each second trench 102 with the polysilicon material, covering the entire drift layer 100 with a polysilicon film. Then, using a planarization process, planarizing the polysilicon film, stopping when the top of the drift layer 100 (e.g., the source region of the drift layer 100) is exposed, retaining the polysilicon material disposed in the first trenches 101 and second trenches 102, removing the remaining polysilicon material, and forming the gate 7, as shown below. Figure 12d For example, planarization processes such as Chemical Mechanical Polishing (CMP) are used to planarize polycrystalline silicon film layers.

[0221] S50. An interlayer dielectric layer covering the entire drift layer is formed on the gate.

[0222] In some examples, step S50 may include: referring to Figure 12e An interlayer medium layer 10 is deposited on the entire drift layer using a deposition process, and the interlayer medium layer 10 covers the entire drift layer.

[0223] S60. Etch the interlayer dielectric layer to expose the second portion of the first P-type semiconductor region and the source region, and the interlayer dielectric layer covers the first portion of the source region and completely covers the gate.

[0224] In some examples, step S60 may include: first, forming a fourth mask layer on the drift layer (the fourth mask layer may be a mask formed of silicon dioxide, polysilicon, or silicon nitride), etching the fourth mask layer using a suitable etching process, either dry or wet, to form a fourth mask opening. The fourth mask layer is then used to cover the first portion of the interlayer dielectric layer that needs to cover the source region and the region that completely covers the gate (i.e., the region where contact holes 02 do not need to be formed) through the retained fourth mask layer. The fourth mask opening exposes the second portion of the interlayer dielectric layer that needs to expose the first P-type semiconductor region and the source region (i.e., the region where contact holes 02 are formed). Then, a dry or wet etching process is used to etch the region exposed through the fourth mask opening in the interlayer dielectric layer 10 to form contact holes 02, thereby exposing the second portion of the source region 8 and the first P-type semiconductor region 4. (Refer to...) Figure 12f .

[0225] S70. A source electrode is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, so that the source electrode is in contact with the second part of the first P-type semiconductor region and the source region, and a drain electrode is formed on the side of the semiconductor substrate away from the drift layer.

[0226] In some examples, step S70 may include: depositing a metal material on the side of the interlayer dielectric layer 10 away from the semiconductor substrate 2 using a deposition process to form a source 11, such that the source 11 contacts not only the interlayer dielectric layer 10 but also a second portion of the first P-type semiconductor region and the source region. That is, the source 11 contacts the first P-type semiconductor region and the source region 8 through the metal material filling the contact holes 02. Furthermore, when forming the source 11, a metal material is also deposited on the side of the semiconductor substrate 2 away from the drift layer 100 using a deposition process to form a drain 1, as shown below. Figure 12g .

[0227] In other examples, step S70 may also include: depositing a metal material on the side of the interlayer dielectric layer 10 away from the semiconductor substrate 2 using a deposition process to form a source 11, such that the source 11 contacts not only the interlayer dielectric layer 10 but also a second portion of the first P-type semiconductor region and the source region. That is, the source 11 contacts the first P-type semiconductor region and the source region 8 through the metal material filling the contact holes 02. Afterwards, a metal material is deposited on the side of the semiconductor substrate 2 away from the drift layer 100 using a deposition process to form a drain 1, referring to... Figure 12g .

[0228] Figure 13 A partial top view of a semiconductor device provided in another embodiment of this application is shown. Figure 14 It shows Figure 13 The diagram shows a cross-sectional view of the semiconductor device along the AA' tangent direction. Figure 15 It shows Figure 13 The diagram shows a cross-sectional view of the semiconductor device along the BB' tangent direction. Figure 16 It shows Figure 13 The diagram shows a cross-sectional view of the semiconductor device along the CC' tangent direction. Figure 17 It shows Figure 13 The diagram shows a cross-sectional view of the semiconductor device along the VV' tangent direction. Figure 18a It shows Figure 13 The diagram shows some three-dimensional structures in the selected area QB1. Figure 18b It shows Figure 13 Other schematic diagrams of three-dimensional structures in the selected area QB1 are shown. Figure 19 It shows Figure 13 A schematic diagram of the three-dimensional structure in the selected area QB2 is shown.

[0229] Reference Figures 13 to 19 In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, a trench structure, a gate dielectric layer 6, a gate electrode 7, an interlayer dielectric layer 10, a source electrode 11, and a drain electrode 1. Furthermore, the drift layer 100 includes: a first N-type semiconductor region 3, a first P-type semiconductor region 4, a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0230] The semiconductor device provided in this application is a trench-gate SiC MOSFET device. In a trench-gate SiC MOSFET device, the gate dielectric layer at the bottom and corners of the trench gate structure is subjected to extremely high electric field strength during device operation, which are weak points for electric field breakdown and easily cause long-term reliability failure. Therefore, how to effectively shield the gate dielectric layer from high electric field stress is the key to the design of a device with high robustness and reliability. In this application embodiment, refer to... Figures 13 to 19 The drift layer 100 also includes a third P-type semiconductor region 91. This third P-type semiconductor region 91 is located below the trench structure and is in direct contact with the bottom of the first trench 101 and the second trench 102 in the trench structure. Furthermore, in this application, the third P-type semiconductor region 91 can be connected to the source 11. When the SiC MOSFET device is operating, a voltage is applied to the source 11. Since the third P-type semiconductor region 91 is connected to the source 11, the voltage applied to the source 11 is input to the third P-type semiconductor region 91, giving it a corresponding voltage. This effectively shields the gate dielectric layer electric field at the bottom of the first trench 101 and the second trench 102 in the trench structure, thereby improving the robustness of the device operation.

[0231] For example, refer to Figures 13 to 19 Each trench structure is provided with a third P-type semiconductor region 91, and the third P-type semiconductor regions 91 corresponding to different trench structures are spaced apart, that is, the third P-type semiconductor regions 91 corresponding to different trench structures do not contact each other. For example, the third P-type semiconductor region 91 provided at the bottom of trench structure GK1 and the third P-type semiconductor region 91 provided at the bottom of trench structure GK2 do not contact each other.

[0232] For example, refer to Figures 13 to 19 The orthographic projection of the third P-type semiconductor region 91 onto the semiconductor substrate 2 covers the orthographic projection of the bottom of the trench structure onto the semiconductor substrate 2. For example, the orthographic projection of the third P-type semiconductor region 91 disposed at the bottom of the trench structure GK1 onto the semiconductor substrate 2 covers the orthographic projection of each first trench 101 and each second trench 102 of the trench structure GK1 onto the semiconductor substrate 2. This can further effectively shield the gate dielectric layer electric field at the bottom of the first trench 101 and the second trench 102, thereby improving the robustness of device operation.

[0233] For example, the edge of the orthographic projection of the third P-type semiconductor region onto the semiconductor substrate can overlap with the edge of the orthographic projection of the bottom of the corresponding first trench and second trench onto the semiconductor substrate. Alternatively, the edge of the orthographic projection of the third P-type semiconductor region onto the semiconductor substrate can be disposed outside the edge of the orthographic projection of the bottom of the corresponding first trench and second trench onto the semiconductor substrate, further effectively shielding the gate dielectric layer electric field at the bottom of the first trench and second trench, thereby improving the robustness of device operation.

[0234] In actual manufacturing processes, due to limitations in process conditions or other factors, the aforementioned overlapping relationships may not be completely identical and may have some deviations. Therefore, as long as the aforementioned overlapping relationships roughly meet the above conditions, they are all within the scope of protection of this application. For example, the aforementioned overlapping relationships can be those that are permissible within the allowable error range.

[0235] In some examples of this application, the third P-type semiconductor region is formed at the bottom of the trench structure using a self-aligned process and a vertical ion implantation process after the trench structure is formed. Therefore, in the third direction, the third P-type semiconductor region can cover the trench structure. Furthermore, due to the diffusivity of ions during the ion implantation process, the third P-type semiconductor region diffuses towards the outer periphery of the bottom of the trench structure, meaning that the orthogonal projection edge of the third P-type semiconductor region on the semiconductor substrate is located outside the orthogonal projection edge of the trench structure on the semiconductor substrate.

[0236] This application does not limit the thickness of the third P-type semiconductor region in the third direction. For example, the thickness of the third P-type semiconductor region in the third direction may be less than 1 μm, or the thickness of the third P-type semiconductor region in the third direction may be 0.3 μm to 0.8 μm.

[0237] For example, when the SiC MOSFET provided in this application is applied to a power conversion circuit, its source can be grounded and its drain can be connected to other components. In this case, the voltage at the source of the SiC MOSFET is the ground voltage (0V). Since the third P-type semiconductor region is connected to the source, the voltage of the third P-type semiconductor region is also the ground voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0238] For example, when the SiC MOSFET provided in this application is applied to a power conversion circuit, its source can also be connected to other components, and its drain can also be connected to other components. In this case, the voltage at the source of the SiC MOSFET is the voltage of the signal input to the other components. Since the third P-type semiconductor region is connected to the source, the voltage of the third P-type semiconductor region is also the voltage of the input signal, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0239] In some embodiments of this application, reference is made to Figures 13 to 18a The drift layer 100 further includes a fourth P-type semiconductor region 92. The fourth P-type semiconductor region 92 is disposed at the second sidewall S2 of one or more first trenches 101. Alternatively, the fourth P-type semiconductor region 92 is disposed at the first sidewall S1 of one or more first trenches 101. Or, refer to... Figure 18b The fourth P-type semiconductor region 92 is disposed at the first sidewall S1 and the second sidewall S2 of one or more first trenches 101. In this application, the fourth P-type semiconductor region 92 is disposed at the second sidewall S2 of the first trench 101 as an example.

[0240] For example, the fourth P-type semiconductor region 92 may be formed by doping the drift layer 100 using an ion implantation process. Furthermore, the dopants in the P-type semiconductor region are primarily P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga).

[0241] For example, the doping concentrations of the first P-type semiconductor region 4, the third P-type semiconductor region 91, and the fourth P-type semiconductor region 92 are greater than the doping concentration of the second P-type semiconductor region 5. Optionally, the doping concentrations of the first P-type semiconductor region 4, the third P-type semiconductor region 91, and the fourth P-type semiconductor region 92 can be the same or similar. Of course, at least two of the doping concentrations of the first P-type semiconductor region 4, the third P-type semiconductor region 91, and the fourth P-type semiconductor region 92 can be different. It should be noted that the doping concentrations of the first P-type semiconductor region 4, the third P-type semiconductor region 91, and the fourth P-type semiconductor region 92 can be determined according to the requirements of the actual application environment, and are not limited here.

[0242] In this application, reference is made to Figure 16 , Figure 18a , Figure 18b The fourth P-type semiconductor region 92 is in contact with the third P-type semiconductor region 91 and the first P-type semiconductor region 4 (e.g., 4a, 4b), respectively. That is, the fourth P-type semiconductor region 92, the third P-type semiconductor region 91 and the first P-type semiconductor region 4 (e.g., 4a, 4b) are respectively connected to the source 11, so that the voltage applied to the source 11 can be input to the third P-type semiconductor region 91 through the first P-type semiconductor region 4 (e.g., 4a, 4b) and the fourth P-type semiconductor region 92, thereby effectively shielding the gate dielectric layer electric field at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0243] Exemplarily, in this application, within the same trench structure, multiple first trenches are divided into at least one first unit and at least one second unit, with each first unit and second unit having at least one first trench. The first unit and second unit are alternately arranged along a second direction. Furthermore, the first trenches in the first unit have the same trench width in the second direction, and the first trenches in the second unit have the same trench width in the second direction, but the trench width of the first trench in the second unit is greater than the trench width of the first trench in the first unit in the second direction. That is, each trench structure contains two different trench widths for the first trenches. Additionally, a fourth P-type semiconductor region is disposed on the first sidewall and / or the second sidewall of the first trench in each second unit. For example, refer to... Figure 13 , Figure 14 , Figures 16 to 18b Taking the trench structure GK1 as an example, the first trench 101a is the first trench in the first unit, and the first trench 101b is the first trench in the second unit. The trench width of the first trench 101b in the second direction F2 is greater than the trench width of the first trench 101a in the second direction F2. In this way, by setting the fourth P-type semiconductor region 92 on the second sidewall S2 of the first trench 101b, the third P-type semiconductor region 91 can be effectively connected to the source electrode 11 through the fourth P-type semiconductor region 92 and the first P-type semiconductor region 4b.

[0244] For example, the groove width of the first groove in the second unit in the second direction is not less than 1.5 times the groove width of the first groove in the first unit in the second direction. For instance, the groove width of the first groove in the second unit in the second direction is approximately equal to 1.5 times the groove width of the first groove in the first unit in the second direction. Alternatively, the groove width of the first groove in the second unit in the second direction is approximately equal to 2 times the groove width of the first groove in the first unit in the second direction. Alternatively, the groove width of the first groove in the second unit in the second direction is approximately equal to 3 times the groove width of the first groove in the first unit in the second direction. Alternatively, the groove width of the first groove in the second unit in the second direction is approximately equal to 4 times the groove width of the first groove in the first unit in the second direction.

[0245] For example, the number of first grooves 101 in different first units is the same. Alternatively, the number of first grooves 101 in some first units is the same, while the number of first grooves 101 in the remaining first units is different. Alternatively, the number of first grooves 101 in different first units is different, and this application does not limit this.

[0246] For example, each first unit has one or more first grooves. For instance, each first unit has multiple first grooves.

[0247] For example, the number of first grooves 101 in different second units is the same. Alternatively, the number of first grooves 101 in some second units is the same, while the number of first grooves 101 in the remaining second units is different. Alternatively, the number of first grooves 101 in different second units is different, and this application does not limit this.

[0248] For example, each second unit has one or more first grooves. For instance, each second unit has one first groove.

[0249] For example, a fourth P-type semiconductor region 92 is disposed on the first sidewall S1 and / or the second sidewall S2 of the first trench 101 in each second cell. For example, refer to Figure 16 and Figure 18a The fourth P-type semiconductor region 92 is disposed on the second sidewall S2 of the first trench 101 in each second unit. Alternatively, the fourth P-type semiconductor region 92 is disposed on the first sidewall S1 of the first trench 101 in each second unit. Or, refer to... Figure 18b The fourth P-type semiconductor region 92 is disposed on the first sidewall S1 and the second sidewall S2 of the first trench 101 in each second unit.

[0250] To prepare Figure 18a Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 20 The preparation method may include steps S10-S20, S81, S82, and S30-S70. Steps S10-S20 and S30-S70 can be referred to the description of the preparation method above, and will not be repeated here.

[0251] In this embodiment, steps S81 and S82 are set after step S20 and before step S30.

[0252] In this embodiment, step S81 is: using a self-aligned process and a vertical ion implantation process, a third P-type semiconductor region is formed at the bottom of each first trench and each second trench of the trench structure.

[0253] For example, a self-aligned process and a vertical ion implantation process can be used to dope the bottom of each first trench 101 and each second trench 102 of the trench structure with P-type impurities to form a third P-type semiconductor region 91 that is consistent with the bottom pattern of each first trench 101 and each second trench 102 of the trench structure. Alternatively, a self-aligned process and a vertical ion implantation process can be used to dope the bottom of each first trench 101 and each second trench 102 of the trench structure with P-type impurities. Afterwards, the semiconductor device doped with P-type impurities undergoes ion activation annealing and surface cleaning treatment sequentially to form the third P-type semiconductor region 91.

[0254] This application does not limit the thickness of the third P-type semiconductor region 91 (i.e., the thickness on the third direction F3). In practical applications, the specific value of the thickness of the third P-type semiconductor region 91 can be determined according to the requirements of the actual application environment.

[0255] Furthermore, since the thickness of the third mask layer on the third-direction F3 is typically set to around 100 nm, the third mask layer can be temporarily retained in step S20. When forming the third P-type semiconductor region 91, the retained third mask layer can protect the sidewalls of the first trench 101 and the second trench 102, preventing ions scattered to the sidewalls of the first trench 101 and the second trench 102 during the vertical ion implantation process from entering the sidewalls. Since ions directly hitting the bottom of the trench during the vertical ion implantation process are not blocked by the third mask layer, they can normally enter the bottom of the first trench and the second trench to form the third P-type semiconductor region 91. After forming the third P-type semiconductor region 91, the third mask layer is then removed.

[0256] In this embodiment, step S82 is: using a tilted ion implantation process, a fourth P-type semiconductor region is formed at at least one sidewall of at least one first trench along a first direction, which is in contact with the third P-type semiconductor region and the first P-type semiconductor region respectively.

[0257] For example, a tilted ion implantation process is used to perform P-type impurity doping on the surface of the second sidewall S2 of each second trench 102 in the second unit, forming a fourth P-type semiconductor region that contacts the third P-type semiconductor region 91 and the first P-type semiconductor region 4, respectively. Alternatively, a tilted ion implantation process is used to perform P-type impurity doping on the surface of the second sidewall S2 of each second trench 102 in the second unit. Afterwards, the semiconductor device with P-type impurity doping undergoes ion activation annealing and surface cleaning treatment sequentially to form a fourth P-type semiconductor region that contacts the third P-type semiconductor region 91 and the first P-type semiconductor region 4, respectively.

[0258] Figure 21 This illustration shows a partial top view of a semiconductor device provided in another embodiment of the present application. Figure 22 It shows Figure 21 The diagram shows a cross-sectional view of the semiconductor device along the AA' tangent direction. Figure 23 It shows Figure 21 The diagram shows a cross-sectional view of the semiconductor device along the BB' tangent direction. Figure 24 It shows Figure 21 The diagram shows a cross-sectional view of the semiconductor device along the VV' tangent direction. Figure 25 It shows Figure 21 The diagram shows the three-dimensional structure of the selected area QB3.

[0259] Reference Figures 21 to 25 In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, a trench structure, a gate dielectric layer 6, a gate electrode 7, an interlayer dielectric layer 10, a source electrode 11, and a drain electrode 1. Furthermore, the drift layer 100 includes: a first N-type semiconductor region 3, a first P-type semiconductor region 4 (e.g., 4a, 4b, 4c), a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0260] The semiconductor device provided in this application is a trench-gate SiC MOSFET device. In a trench-gate SiC MOSFET device, the gate dielectric layer at the bottom and corners of the trench gate structure is subjected to extremely high electric field strength during device operation, which are weak points for electric field breakdown and easily cause long-term reliability failure. Therefore, how to effectively shield the gate dielectric layer from high electric field stress is the key to the design of a device with high robustness and reliability. In this application embodiment, refer to... Figures 21 to 25 The drift layer 100 also includes a fifth P-type semiconductor region 93 (e.g., 93a, 93b, 93c). The trench structure has a first side and a second side arranged opposite to each other in the second direction F2, and the first and second sides of the trench structure are respectively provided with the fifth P-type semiconductor region 93 (e.g., 93a, 93b, 93c). Below each first P-type semiconductor region 4 (e.g., 4a, 4b, 4c), a fifth P-type semiconductor region 93 (e.g., 93a, 93b, 93c) is provided, and the fifth P-type semiconductor region 93 (e.g., 93a, 93b, 93c) is in contact with the first P-type semiconductor region 4 (e.g., 4a, 4b, 4c), forming a P-type semiconductor structure GP. That is, the mutually contacting fifth P-type semiconductor regions 93 (e.g., 93a, 93b, 93c) and the first P-type semiconductor regions 4 (e.g., 4a, 4b, 4c) are in contact with each other, forming an integral P-type semiconductor structure SK. Furthermore, the fifth P-type semiconductor region 93 (such as 93a, 93b, 93c) extends along the third direction F3 into the first N-type semiconductor region 3, and the distance hd1 between the bottom of the fifth P-type semiconductor region 93 (such as 93a, 93b, 93c) and the top of the drift layer 100 is greater than the distance hd2 between the bottom of the trench structure and the top of the drift layer 100.

[0261] In other words, the depth of the P-type semiconductor structure SK in the third direction F3 is greater than the depth of the trench structure in the third direction F3. Furthermore, the source 11 can also contact the first P-type semiconductor region 4 (e.g., 4a, 4b, 4c) through the contact hole 02. The first P-type semiconductor region 4 (e.g., 4a, 4b, 4c) can contact the fifth P-type semiconductor region 93 (e.g., 93a, 93b, 93c), thus the source 11 and the fifth P-type semiconductor region 93 (e.g., 93a, 93b, 93c) are also electrically connected. That is, in this application, the source 11 can be electrically connected to the fifth P-type semiconductor region 93 (e.g., 93a, 93b, 93c), meaning the source 11 is electrically connected to the P-type semiconductor structure SK. In practical applications, when a SiC MOSFET device is operating, a voltage is applied to the source 11. Since the fifth P-type semiconductor region 93 (such as 93a, 93b, 93c) is connected to the source 11, the voltage applied to the source 11 is input to the fifth P-type semiconductor region 93 (such as 93a, 93b, 93c), so that the fifth P-type semiconductor region 93 (such as 93a, 93b, 93c) also has a corresponding voltage. This allows the fifth P-type semiconductor region 93 (such as 93a, 93b, 93c) to act as a shielding structure, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the trench structure, and thus improving the robustness of the device operation.

[0262] Reference Figure 22 , Figure 23 as well as Figure 25 In this application, the orthographic projection of the first P-type semiconductor region onto the semiconductor substrate 2 is located within the orthographic projection of the fifth P-type semiconductor region 93 (such as 93a, 93b, 93c) disposed directly below the first P-type semiconductor region onto the semiconductor substrate 2.

[0263] For example, when the SiC MOSFET provided in this application embodiment is applied to a power conversion circuit, its source can be grounded and its drain can be connected to other components. In this case, the voltage of the source of the SiC MOSFET is the ground voltage (0V). Since the fifth P-type semiconductor region is connected to the source, the voltage of the fifth P-type semiconductor region is also the ground voltage, which can effectively shield the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0264] For example, when the SiC MOSFET provided in this application is applied to a power conversion circuit, its source can also be connected to other components, and its drain can also be connected to other components. In this case, the voltage at the source of the SiC MOSFET is the voltage of the signal input to the other components. Since the fifth P-type semiconductor region is connected to the source, the voltage of the fifth P-type semiconductor region is also the voltage of the input signal, thereby effectively shielding the electric field of the gate dielectric layer at the bottom of the trench structure, thereby improving the robustness of the device operation.

[0265] This application does not limit the specific values ​​of hd1 and hd2, only requiring that hd1 > hd2. For example, 1.5hd2 ≤ hd1 ≤ 2.5hd2 can be used. Alternatively, hd1 can be similar to or the same as twice the value of hd2; that is, when the depth of the P-type semiconductor structure is approximately twice the depth of the trench structure and D1 ≤ 5 μm, the electric field of the gate dielectric layer 6 at the bottom of the trench structure can be controlled within 3 MV / cm, meeting the device's reliability requirements.

[0266] For example, refer to Figure 23 and Figure 25 In this application, each of the plurality of second trenches 102 has a third sidewall S3 and a fourth sidewall S4 disposed opposite to each other in the first direction F1. The orthographic projection of the P-type semiconductor structure SK on the first plane formed by the second direction F2 and the third direction F3 covers the orthographic projection of the corresponding second trench 102 on the first plane. Alternatively, the first plane can be parallel to the second direction F2 and the third direction F3, respectively.

[0267] For example, in this application, the P-type semiconductor structures disposed on the two sides of the drift layer can each be a single integral region, and the orthogonal projection of the P-type semiconductor structure onto the semiconductor substrate is a strip-shaped region extending along the second direction. For instance, the P-type semiconductor structures SK disposed on the first and second sides of the trench structure can each be a single integral region, that is, the P-type semiconductor structures SK disposed on the first side of the same trench structure are set as a single integral region, and the P-type semiconductor structures disposed on the second side of the same trench structure are also set as a single integral region. Furthermore, the orthogonal projection of each P-type semiconductor structure SK onto the semiconductor substrate 2 is a strip-shaped region extending along the second direction F2, meaning each P-type semiconductor structure SK extends from the first edge 01a to the second edge 01b along the second direction F2. Moreover, the orthogonal projection of the P-type semiconductor structure SK onto the first plane covers the orthogonal projection of the trench structure onto the first plane. For example, referring to… Figures 21 to 25In trench structure GK1, a strip-shaped P-type semiconductor structure (i.e., a P-type semiconductor structure composed of a fifth P-type semiconductor region 93a and a first P-type semiconductor region 4a) is provided on the first side of the gate trench. The orthogonal projection of this P-type semiconductor structure onto the first plane covers the orthogonal projection of trench structure GK1 onto the first plane. Similarly, in trench structure GK2, a strip-shaped P-type semiconductor structure (i.e., a P-type semiconductor structure composed of a fifth P-type semiconductor region 93b and a first P-type semiconductor region 4b) is provided on the second side of the gate trench. The orthogonal projection of this P-type semiconductor structure onto the first plane covers the orthogonal projection of trench structure GK2 onto the first plane. A strip-shaped P-type semiconductor structure (i.e., a P-type semiconductor structure composed of a fifth P-type semiconductor region 93c and a first P-type semiconductor region 4c) is provided on the second side of the gate trench in the trench structure GK2. The orthogonal projection of the P-type semiconductor structure on the first plane covers the orthogonal projection of the trench structure GK2 on the first plane.

[0268] For example, refer to Figures 21 to 25 In this application, the orthographic projection of each P-type semiconductor structure onto the semiconductor substrate 2 does not overlap with the orthographic projection of each trench structure onto the semiconductor substrate 2. That is, in the third direction F3, there is no overlapping region between each P-type semiconductor structure and each trench structure.

[0269] For example, in this application, a fourth portion of the source region can be provided between the P-type semiconductor structure and the corresponding trench structure, that is, the fourth portion of the source region is projected onto the semiconductor substrate 2 between the orthographic projection of the P-type semiconductor structure onto the semiconductor substrate 2 and the orthographic projection of the trench structure onto the semiconductor substrate 2. For example, referring to... Figures 21 to 25The P-type semiconductor structure (i.e., the P-type semiconductor structure composed of the fifth P-type semiconductor region 93a and the first P-type semiconductor region 4a) and the trench structure GK1 have a fourth part region 8d1 of the source region 8. That is, the orthographic projection of the P-type semiconductor structure (i.e., the P-type semiconductor structure composed of the fifth P-type semiconductor region 93a and the first P-type semiconductor region 4a) onto the semiconductor substrate 2 and the orthographic projection of the first sidewall S1 of the first trench in the trench structure GK1 onto the semiconductor substrate 2 have a fourth part region 8d1 of the source region 8 onto the semiconductor substrate 2. Therefore, the gate dielectric layer 6 disposed on the surface of the first sidewall S1 of the first trench in the trench structure GK1 is not in contact with the P-type semiconductor structure. The P-type semiconductor structure (i.e., the P-type semiconductor structure composed of the fifth P-type semiconductor region 93b and the first P-type semiconductor region 4b) and the trench structure GK1 have a fourth part region 8d2 of the source region 8. That is, the orthogonal projection of the P-type semiconductor structure (i.e., the P-type semiconductor structure composed of the fifth P-type semiconductor region 93b and the first P-type semiconductor region 4b) onto the semiconductor substrate 2 and the orthogonal projection of the second sidewall S2 of the first trench in the trench structure GK1 onto the semiconductor substrate 2 have a fourth part region 8d2 of the source region 8 onto the semiconductor substrate 2. Therefore, the gate dielectric layer 6 disposed on the surface of the second sidewall S2 of the first trench in the trench structure GK1 is not in contact with the P-type semiconductor structure. The P-type semiconductor structure (i.e., the P-type semiconductor structure composed of the fifth P-type semiconductor region 93b and the first P-type semiconductor region 4b) and the trench structure GK2 have a fourth part region 8d3 of the source region 8. That is, the orthographic projection of the P-type semiconductor structure (i.e., the P-type semiconductor structure composed of the fifth P-type semiconductor region 93b and the first P-type semiconductor region 4b) onto the semiconductor substrate 2 and the orthographic projection of the first sidewall S1 of the first trench in the trench structure GK2 onto the semiconductor substrate 2 have a fourth part region 8d3 of the source region 8 onto the semiconductor substrate 2. Therefore, the gate dielectric layer 6 disposed on the surface of the first sidewall S1 of the first trench in the trench structure GK2 is not in contact with the P-type semiconductor structure. The P-type semiconductor structure (i.e., the P-type semiconductor structure composed of the fifth P-type semiconductor region 93c and the first P-type semiconductor region 4c) and the trench structure GK2 have a fourth part region 8d4 of the source region 8. That is, the orthogonal projection of the P-type semiconductor structure (i.e., the P-type semiconductor structure composed of the fifth P-type semiconductor region 93c and the first P-type semiconductor region 4c) onto the semiconductor substrate 2 and the orthogonal projection of the second sidewall S2 of the first trench in the trench structure GK2 onto the semiconductor substrate 2 have a fourth part region 8d4 of the source region 8 onto the semiconductor substrate 2. Therefore, the gate dielectric layer 6 disposed on the surface of the second sidewall S2 of the first trench in the trench structure GK2 is not in contact with the P-type semiconductor structure.

[0270] For example, refer to Figures 21 to 25 In this application, the drift layer 100 further includes a first shielding trench 12. Figure 21 Taking a first shielding trench 12 disposed between trench structures GK1 and GK2 as an example, the first shielding trench 12 extends from the top of the drift layer 100 to the first N-type semiconductor region 3 along a third direction F3. The first shielding trench 12 is disposed on both sides of the drift layer 100, and P-type semiconductor structures are disposed on the sidewalls and bottom of the first shielding trench. For example, the first shielding trench 12 is disposed on the first side and the second side of the trench structure, respectively. For example, the first shielding trench 12 is disposed between the second sidewall S2 of the first trench 101 in trench structure GK1 and the first sidewall S1 of the first trench 101 in trench structure GK2.

[0271] In this application, Figure 21 This example only illustrates the first shielding trench disposed between trench structures GK1 and GK2. In practical applications, a first shielding trench is also provided on the side of the first sidewall S1 of the first trench of trench structure GK1 facing away from the gate it fills. The implementation of this method can refer to the implementation method of the first shielding trench disposed between trench structures GK1 and GK2. Furthermore, a first shielding trench is also provided on the side of the second sidewall S2 of the first trench of trench structure GK2 facing away from the gate it fills. The implementation of this method can refer to the implementation method of the first shielding trench disposed between trench structures GK1 and GK2, and will not be elaborated here.

[0272] For example, refer to Figures 21 to 25 In this application, the orthographic projection of the first shielding trench 12 onto the semiconductor substrate 2 can be a strip-shaped region extending along the second direction F2.

[0273] For example, refer to Figures 21 to 25 Each first shielding trench 12 has a P-type semiconductor region on its sidewall. That is, each sidewall of each first shielding trench 12 has a P-type semiconductor region. Optionally, the P-type semiconductor region on the sidewall of each first shielding trench 12 in the first direction F1 can serve as a P-type semiconductor structure. For example, in the first direction F1, the first shielding trench 12 has a fifth sidewall S5 and a sixth sidewall S6 disposed opposite to each other. The P-type semiconductor regions disposed at the fifth sidewall S5 and the sixth sidewall S6 of the first shielding trench 12 can serve as a P-type semiconductor structure.

[0274] For example, refer to Figure 22 and Figure 23 Each first shielding trench 12 also has a P-type semiconductor region at its bottom. By providing a P-type semiconductor region at the bottom of the first shielding trench 12, this application further effectively shields the gate dielectric layer electric field at the bottom of the trench structure, thereby improving the robustness of device operation.

[0275] For example, the doping concentration of the P-type semiconductor region at the bottom of the first shielding trench 12 is similar to or the same as the doping concentration of the P-type semiconductor region at its sidewall. Optionally, an ion implantation process can be used to form P-type semiconductor regions at the bottom and sidewall of the first shielding trench 12 to form a fifth P-type semiconductor region.

[0276] For example, refer to Figure 22 The distance hd3 between the first shielding trench 12 and the top of the drift layer 100 is greater than the distance hd2 between the trench structure and the top of the drift layer 100. That is, the depth of the first shielding trench 12 in the third direction F3 is greater than the depth of the trench structure in the third direction F3. Thus, when using ion implantation to dope the sidewalls and bottom of the first shielding trench with P-type impurities, the diffused doped ions will allow the depth of the formed fifth P-type semiconductor region in the third direction F3 to be greater than the depth of the trench structure in the third direction F3.

[0277] For example, the distance between the first shielding trench and the top of the drift layer can also be approximately equal to the distance between the trench structure and the top of the drift layer. That is, the depth of the first shielding trench in the third direction is similar to or the same as the depth of the trench structure in the third direction. In this way, when the sidewalls and bottom of the first shielding trench are doped using an ion implantation process, the doped ions will diffuse, thereby allowing the depth of the formed fifth P-type semiconductor region in the third direction to be greater than the depth of the trench structure in the third direction F3.

[0278] Exemplarily, in this application, when there are multiple trench structures, two adjacent trench structures share a P-type semiconductor structure disposed between them. Exemplarily, two adjacent trench structures share a first shielding trench disposed between them. Further, two adjacent trench structures share the third and fourth sidewalls of the first shielding trench disposed between them, as well as the P-type semiconductor region disposed at the bottom. For example, refer to... Figures 18a to 19 The trench structures GK1 and GK2 share the third and fourth sidewalls of the first shielding trench 12 and the P-type semiconductor region at the bottom.

[0279] For example, refer to Figures 21 to 23In this application, each first shielding trench 12 is filled with a filler material 15, and this application does not limit the filler material 15. Exemplarily, the filler material 15 can be the gate material, that is, each first shielding trench can be filled with the gate material. For example, in actual process fabrication, when forming the gate, the gate material can be filled into the first shielding trench 12. Of course, each first shielding trench can also be filled with the interlayer dielectric layer material. Alternatively, each first shielding trench can also be filled with the source or drain material.

[0280] To prepare Figure 25 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 26 The preparation method may include steps S10-S70 and S91-S92. Steps S10-S70 can be referred to the description of the preparation method above, and will not be repeated here.

[0281] In this embodiment, steps S91-S92 are set after step S10 and before step S20. It also includes: forming a fifth P-type semiconductor region below each first P-type semiconductor region, extending the fifth P-type semiconductor region along a third direction into the first N-type semiconductor region, and making the fifth P-type semiconductor region contact the first P-type semiconductor region to form a P-type semiconductor structure; wherein the distance between the bottom of the fifth P-type semiconductor region and the top of the drift layer is greater than the distance between the bottom of the trench structure and the top of the drift layer.

[0282] In this embodiment, forming a fifth P-type semiconductor region below each first P-type semiconductor region may include:

[0283] Step S91 involves etching both sides of the drift layer to form a first shielding trench extending upward along a third direction into the first N-type semiconductor region within the drift layer. The first shielding trench is formed on both the first and second sides of the trench structure. Furthermore, the orthogonal projection of the first shielding trench onto the semiconductor substrate is a strip-shaped region extending along a second direction.

[0284] For example, refer to Figure 25A fifth mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer. The fifth mask layer is etched using a suitable etching process, either dry or wet, to form a fifth mask opening. This opening exposes the corresponding region in the drift layer 100 where the first shielding trench 12 needs to be formed, while the remaining regions of the drift layer 100 are covered by the retained fifth mask layer. Then, a dry or wet etching process is used to etch the drift layer 100 exposed through the fifth mask opening until etching reaches the first N-type semiconductor region 3, forming a plurality of first shielding trenches 12 extending along the second direction F2 and arranged along the first direction F1 in the drift layer 100. The fifth mask layer is temporarily retained.

[0285] In this embodiment, step S92 is: using an ion implantation process, ion implantation is performed on the sidewalls and bottom of the first shielding trench to form a fifth P-type semiconductor region, such that the fifth P-type semiconductor region is disposed below the first P-type semiconductor region, and the fifth P-type semiconductor region corresponds to and is in contact with the first P-type semiconductor region.

[0286] For example, refer to Figure 25 The sidewalls and bottom of each first shielding trench 12 are p-type doped using an ion implantation process. Then, the fifth mask layer is removed. Afterwards, the semiconductor devices with p-type doped sidewalls and bottoms of each first shielding trench 12 are sequentially subjected to ion activation annealing and surface cleaning to form a fifth p-type semiconductor region located below the first p-type semiconductor region.

[0287] In step S20, a first P-type semiconductor region is formed. Therefore, the fifth mask opening only exposes a portion of the first P-type semiconductor region, allowing the first shielding trench 12 to have a first P-type semiconductor region near its top sidewall. Therefore, in step S92, ion implantation can be primarily performed on the sidewall near the bottom of the first shielding trench 12 to form a fifth P-type semiconductor region there, making the fifth P-type semiconductor region contact the first P-type semiconductor region. Alternatively, ion implantation can be performed on the entire sidewall of the first shielding trench 12, making the fifth P-type semiconductor region and the first P-type semiconductor region contact each other as a single unit.

[0288] Figure 27 This illustration shows a partial top view of a semiconductor device provided in another embodiment of the present application. Figure 28 It shows Figure 27 The diagram shows a cross-sectional view of the semiconductor device along the AA' tangent direction. Figure 29 It shows Figure 27The diagram shows a cross-sectional view of the semiconductor device along the BB' tangent direction. Figure 30 It shows Figure 27 The diagram shows a cross-sectional view of the semiconductor device along the VV' tangent direction.

[0289] Reference Figures 27 to 30 In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, a trench structure (such as GK1, GK2), a gate dielectric layer 6, a gate electrode 7, an interlayer dielectric layer 10, a source electrode 11, and a drain electrode 1. Furthermore, the drift layer 100 includes: a first N-type semiconductor region 3, a first P-type semiconductor region 4 (such as 4a, 4b, 4c), a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0290] In this embodiment, the P-type semiconductor structures disposed on both sides of the drift layer are multiple regions, and these multiple P-type semiconductor structures and the third portion region of the source region are spaced apart from each other. For example, the P-type semiconductor structures disposed on the first and second sides of the trench structure are multiple regions, and the multiple P-type semiconductor structures disposed on the same side of the trench structure and the third portion region of the source region are spaced apart from each other. That is, the third portion region of the source region is projected onto the semiconductor substrate between the orthogonal projections of two adjacent P-type semiconductor structures disposed on the same side of the multiple trench structures onto the semiconductor substrate.

[0291] For example, refer to Figures 27 to 30 Multiple P-type semiconductor structures SK are disposed on the first and second sides of the trench structure GK1, and each second trench 102 in the trench structure GK1 corresponds to one P-type semiconductor structure SK. Furthermore, the multiple P-type semiconductor structures and the third portion region 8c of the source region are spaced apart from each other, meaning that between each pair of adjacent P-type semiconductor structures SK projected onto the semiconductor substrate 2, there is a projected image of the third portion region 8c of the source region 8 onto the semiconductor substrate 2.

[0292] For example, refer to Figures 27 to 30 Multiple P-type semiconductor structures SK are disposed on the first and second sides of the trench structure GK2, and each second trench 102 in the trench structure GK2 corresponds to one P-type semiconductor structure SK. Furthermore, the multiple P-type semiconductor structures and the third portion of the source region are spaced apart from each other, meaning that between each pair of adjacent P-type semiconductor structures SK projected onto the semiconductor substrate 2, there is a projection of the third portion of the source region 8c onto the semiconductor substrate 2.

[0293] In this embodiment, the edge of the orthogonal projection of the P-type semiconductor structure SK onto the first plane formed by the second direction F2 and the third direction F3 is disposed around the edge of the orthogonal projection of the corresponding second trench 102 onto the first plane. For example, referring to... Figures 27 to 30 The edge of the orthographic projection of each P-type semiconductor structure SK on the first plane is located outside the edge of the orthographic projection of the corresponding second trench 102 in the trench structure GK1 on the first plane. Also, the edge of the orthographic projection of each P-type semiconductor structure SK on the first plane is located outside the edge of the orthographic projection of the corresponding second trench 102 in the trench structure GK2 on the first plane.

[0294] For example, in this application, a fourth portion of the source region 8 is present between the P-type semiconductor structure SK and the trench structure, that is, the fourth portion of the source region 8 is projected onto the semiconductor substrate 2 between the orthographic projection of the P-type semiconductor structure SK onto the semiconductor substrate 2 and the orthographic projection of the trench structure onto the semiconductor substrate 2. For example, referring to... Figures 27 to 30 Between the P-type semiconductor structure SK and the trench structure GK2, there is a fourth part of the source region 8d0, that is, between the orthographic projection of the P-type semiconductor structure SK onto the semiconductor substrate 2 and the orthographic projection of the second sidewall S2 of the first trench in the trench structure GK2 onto the semiconductor substrate 2, there is a fourth part of the source region 8d0 onto the semiconductor substrate 2. That is, the gate dielectric layer 6 disposed at the second sidewall S2 of the first trench in the trench structure GK2 is not in contact with the P-type semiconductor structure SK.

[0295] For example, refer to Figures 27 to 30 In this application, the drift layer 100 further includes a first shielding trench 12. Figure 27 Taking multiple first shielding trenches disposed between trench structures GK1 and GK2 as an example, these multiple first shielding trenches 12 extend from the top of the drift layer 100 to the first N-type semiconductor region 3 along a third direction F3. Furthermore, the first shielding trenches are disposed on two sides of the drift layer, and P-type semiconductor structures are disposed on the sidewalls and bottom of the first shielding trenches. For example, multiple first shielding trenches 12 are respectively disposed on the first side and the second back side of the trench structure. For example, multiple first shielding trenches 12 are disposed between trench structure GK1 and trench structure GK2.

[0296] For example, refer to Figures 27 to 30 Each of the first shielding trenches 12 has a P-type semiconductor region on its sidewall. That is, each sidewall of each first shielding trench 12 has a P-type semiconductor region. Optionally, the P-type semiconductor region on the sidewall of each first shielding trench 12 can serve as a P-type semiconductor structure.

[0297] For example, refer to Figures 27 to 30Each first shielding trench 12 also has a P-type semiconductor region at its bottom. By providing a P-type semiconductor region at the bottom of the first shielding trench 12, this application further effectively shields the gate dielectric layer electric field at the bottom of the trench structure, thereby improving the robustness of device operation.

[0298] For example, the doping concentration of the P-type semiconductor region at the bottom of the first shielding trench 12 is similar to or the same as the doping concentration of the P-type semiconductor region at its sidewall. Optionally, an ion implantation process can be used to form P-type semiconductor regions at the bottom and sidewall of the first shielding trench 12 in the same step.

[0299] For example, refer to Figures 27 to 30 The distance hd3 between the first shielding trench 12 and the top of the drift layer 100 is greater than the distance hd2 between the trench structure and the top of the drift layer 100. That is, the depth of the first shielding trench 12 in the third direction F3 is greater than the depth of the trench structure in the third direction F3. Thus, when using ion implantation to dope the sidewalls and bottom of the first shielding trench with P-type impurities, the diffused doped ions will allow the depth of the formed fifth P-type semiconductor region in the third direction F3 to be greater than the depth of the trench structure in the third direction F3.

[0300] For example, the distance between the first shielding trench and the top of the drift layer 100 can also be approximately equal to the distance between the trench structure and the top of the drift layer 100. That is, the depth of the first shielding trench in the third direction F3 is similar to or the same as the depth of the trench structure in the third direction F3. In this way, when the sidewalls and bottom of the first shielding trench are doped using an ion implantation process, the doped ions will diffuse, thereby allowing the depth of the formed fifth P-type semiconductor region in the third direction F3 to be greater than the depth of the trench structure in the third direction F3.

[0301] Exemplarily, in this application, when there are multiple trench structures, two adjacent trench structures share a P-type semiconductor structure disposed between them. Exemplarily, two adjacent trench structures share a first shielding trench disposed between them. Further, two adjacent trench structures share the third and fourth sidewalls of the first shielding trench disposed between them, as well as the P-type semiconductor region disposed at the bottom. For example, refer to... Figures 27 to 30 The trench structures GK1 and GK2 share the P-type semiconductor region set on the sidewall and bottom of the first shielding trench 12.

[0302] For example, refer to Figures 27 to 30In this application, each first shielding trench is filled with a filler material 15, and this application does not limit the filler material 15. Exemplarily, the filler material 15 can be the gate material, that is, each first shielding trench can be filled with the gate material. For example, in actual process fabrication, when forming the gate, the gate material can be filled into the first shielding trench 12. Of course, each first shielding trench can also be filled with the interlayer dielectric layer material. Alternatively, each first shielding trench can also be filled with the source or drain material.

[0303] To prepare Figures 27 to 30 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 26 The preparation method may include steps S10-S70 and S91-S92. Steps S10-S70 can be referred to the description of the preparation method above, and will not be repeated here.

[0304] In this embodiment, step S91 involves etching two sides of the drift layer to form a first shielding trench extending upward along a third direction into the first N-type semiconductor region within the drift layer. The first and second sides of the trench structure are respectively provided with first shielding trenches. Furthermore, multiple first shielding trenches are provided at intervals on the same side of each trench structure.

[0305] For example, refer to Figures 27 to 30 A sixth mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer 100. The fifth mask layer is etched using a suitable etching process, either dry or wet, to form an opening in the sixth mask. This opening exposes the corresponding region of the drift layer 100 where the first shielding trench 12 needs to be formed, while the remaining region of the drift layer 100 is covered by the retained sixth mask layer. Then, the drift layer 100 exposed through the sixth mask opening is etched using either dry or wet etching until it reaches the first N-type semiconductor region 3. This forms multiple first shielding trenches on the same side of each trench structure, with a portion of the source region projected onto the semiconductor substrate 2 between the orthogonal projections of two adjacent first shielding trenches onto the semiconductor substrate 2. The sixth mask layer is temporarily retained.

[0306] In this embodiment, step S92 is: using an ion implantation process, ion implantation is performed on the sidewall and bottom of each of the multiple first shielding trenches to form a fifth P-type semiconductor region. The fifth P-type semiconductor region is disposed below the first P-type semiconductor region, and the fifth P-type semiconductor region corresponds to and is in contact with the first P-type semiconductor region.

[0307] For example, refer to Figures 27 to 30The sidewalls and bottom of each first shielding trench 12 are p-type doped using an ion implantation process. Then, the sixth mask layer is removed. Afterward, the semiconductor devices with p-type doped sidewalls and bottoms of each first shielding trench 12 are sequentially subjected to ion activation annealing and surface cleaning to form a fifth p-type semiconductor region located below the first p-type semiconductor region.

[0308] In step S20, a first P-type semiconductor region is formed. Therefore, the fifth mask opening only exposes a portion of the first P-type semiconductor region, allowing the first shielding trench 12 to have a first P-type semiconductor region near its top sidewall. Specifically, in step S92, ion implantation can be performed primarily on the sidewall near the bottom of the first shielding trench 12 to form a fifth P-type semiconductor region there, making the fifth P-type semiconductor region contact the first P-type semiconductor region. Alternatively, ion implantation can be performed on the entire sidewall of the first shielding trench 12, making the fifth P-type semiconductor region and the first P-type semiconductor region contact each other as a single unit.

[0309] Figure 31 This illustration shows a partial top view of a semiconductor device provided in another embodiment of the present application. Figure 32 It shows Figure 31 The diagram shows a cross-sectional view of the semiconductor device along the BB' tangent direction.

[0310] Reference Figure 31 In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, trench structures GK1 and GK2, a gate dielectric layer 6, a gate electrode 7, an interlayer dielectric layer 10, a source electrode 11, and a drain electrode 1. Furthermore, the drift layer 100 includes: a first N-type semiconductor region 3, a first P-type semiconductor region 4 (e.g., 4a, 4b, 4c), a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0311] In this embodiment, the P-type semiconductor structures disposed on both sides of the drift layer are multiple regions. For example, the P-type semiconductor structures disposed on the first and second sides of the trench structure are multiple regions, and the multiple P-type semiconductor structures disposed on the same side of the trench structure and the third portion region of the source region are spaced apart from each other. Furthermore, the multiple P-type semiconductor structures and the third portion region of the source region are spaced apart from each other, meaning that the orthographic projection of the third portion region of the source region onto the semiconductor substrate exists between the orthographic projections of two adjacent P-type semiconductor structures disposed on the same side of the multiple trench structures. Moreover, the trench structure contacts the corresponding P-type semiconductor structure through the corresponding gate dielectric layer; that is, when there are multiple P-type semiconductor structures disposed on the first and second sides of the trench structure, the orthographic projection of the P-type semiconductor structure onto the semiconductor substrate contacts the orthographic projection of the gate dielectric layer of the trench structure onto the semiconductor substrate.

[0312] For example, refer to Figures 31 to 32 The gate dielectric layer on the first side of the trench structure GK1 is in direct contact with the orthographic projection of the corresponding P-type semiconductor structure SK on the semiconductor substrate 2. That is, there is no orthographic projection of the third portion region 8c of the source region 8 onto the semiconductor substrate 2 between the orthographic projection of the first sidewall S1 of each first trench 101 in the trench structure GK1 and the orthographic projection of the corresponding P-type semiconductor structure SK on the semiconductor substrate 2. Similarly, the gate dielectric layer on the second side of the trench structure GK1 is in direct contact with the orthographic projection of the corresponding P-type semiconductor structure SK on the semiconductor substrate 2. That is, there is no orthographic projection of the third portion region 8c of the source region 8 onto the semiconductor substrate 2 between the orthographic projection of the second sidewall S2 of each first trench 101 in the trench structure GK1 and the orthographic projection of the corresponding P-type semiconductor structure SK on the semiconductor substrate 2. The orthographic projection of the gate dielectric layer on the first side of the trench structure GK2 onto the semiconductor substrate 2 is in direct contact with the orthographic projection of the corresponding P-type semiconductor structure SK onto the semiconductor substrate 2. That is, there is no orthographic projection of the third portion region 8c of the source region 8 onto the semiconductor substrate 2 between the orthographic projection of the first sidewall S1 of each first trench 101 in the trench structure GK2 onto the semiconductor substrate 2 and the orthographic projection of the corresponding P-type semiconductor structure SK onto the semiconductor substrate 2. Similarly, the orthographic projection of the gate dielectric layer on the second side of the trench structure GK2 onto the semiconductor substrate 2 is in direct contact with the orthographic projection of the corresponding P-type semiconductor structure SK onto the semiconductor substrate 2. That is, there is no orthographic projection of the third portion region 8c of the source region 8 onto the semiconductor substrate 2 between the orthographic projection of the second sidewall S2 of each first trench 101 in the trench structure GK2 onto the semiconductor substrate 2 and the orthographic projection of the corresponding P-type semiconductor structure SK onto the semiconductor substrate 2.

[0313] preparation Figure 31 and Figure 32The preparation method of the semiconductor structure shown can be referred to the above preparation method, and will not be repeated here.

[0314] Figure 33 A three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this application is shown.

[0315] Reference Figure 33 In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, a plurality of gate trenches spaced apart from each other, a gate dielectric layer 6, a gate 7, an interlayer dielectric layer 10, a source 11, and a drain 1. Furthermore, the drift layer 100 includes: a first N-type semiconductor region 3, a second N-type semiconductor region 14, a first P-type semiconductor region 4 (e.g., 4a, 4b), a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0316] In this embodiment, the drift layer 100 further includes a second N-type semiconductor region 14, which is disposed between the first N-type semiconductor region 3 and the second P-type semiconductor region 5. Furthermore, the doping concentration of the second N-type semiconductor region 14 is greater than the doping concentration of the first N-type semiconductor region 3, and the doping concentration of the second N-type semiconductor region 14 is less than the doping concentration of the source region 8.

[0317] In this application, by providing a second N-type semiconductor region in the drift layer 100, the diffusion resistance of the current in the device at the upper end of the drift layer 100 can be reduced.

[0318] This application does not limit the doping concentration of the second N-type semiconductor region 14; its doping concentration can meet the above requirements.

[0319] To prepare Figure 33 Taking the structure shown as an example, the corresponding preparation method flowchart can be found in the following diagram. Figure 11 Steps S20 to S70 can be referred to the description of the preparation method above, and will not be repeated here.

[0320] In this embodiment, step S10 is: epitaxially growing a drift layer on an N-type semiconductor substrate, and forming a first N-type semiconductor region, a second N-type semiconductor region, a first P-type semiconductor region, a second P-type semiconductor region, and a source region in the drift layer.

[0321] In some examples, step S10 may include:

[0322] First, an epitaxial layer 100 is grown on an N-type semiconductor substrate 2 using an epitaxial process.

[0323] For example, using an epitaxial process, SiC material doped with N-type impurities is epitaxially grown on an N-type SiC semiconductor substrate 2 to form a drift layer 100 of a set thickness.

[0324] This application does not limit the specific value of the set thickness. In practical applications, the specific value of the set thickness can be determined according to the needs of the actual application environment.

[0325] Subsequently, an ion implantation process is used to implant ions into a portion of the drift layer 100 to form a second N-type semiconductor region, a first P-type semiconductor region, a second P-type semiconductor region 5, and a source region. The regions of the drift layer 100 that are not ion implanted form the first N-type semiconductor region 3, and the formed second P-type semiconductor region 5 is disposed between the second N-type semiconductor region and the source region. The first N-type semiconductor region 3 is disposed between the second N-type semiconductor region and the semiconductor substrate 2.

[0326] For example, firstly, an ion implantation process is used to dope the surface of the drift layer 100 with N-type impurities to form a second N-type semiconductor region. Then, an ion implantation process is used to dope the surface of the drift layer 100 with P-type impurities to form a second P-type semiconductor region 5. Next, a seventh mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer 100. The seventh mask layer is etched using a suitable etching process, either dry or wet, to form a seventh mask opening. This opening exposes the corresponding region in the drift layer 100 where the source region needs to be formed, while the remaining areas of the drift layer 100 are covered by the retained seventh mask layer. Then, an ion implantation process is used to dope the surface of the drift layer 100 with N-type impurities to form the source region. Finally, the seventh mask layer is removed. Next, an eighth mask layer (which can be a mask formed of silicon dioxide, polysilicon, or silicon nitride) is formed on the drift layer 100. The eighth mask layer is etched using a suitable etching process, either dry or wet, to form an opening in the eighth mask. This opening exposes the corresponding region in the drift layer 100 where the first P-type semiconductor region needs to be formed, while the remaining regions of the drift layer 100 are covered by the retained eighth mask layer. Then, an ion implantation process is used to dope the surface of the drift layer 100 with P-type impurities to form the first P-type semiconductor region. Finally, the eighth mask layer is removed.

[0327] Figure 34 A top view of a semiconductor device provided in another embodiment of this application is shown.

[0328] Reference Figure 34In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, a trench structure, a gate dielectric layer 6, a gate electrode 7, an interlayer dielectric layer 10, a source electrode 11, and a drain electrode 1. Furthermore, the drift layer 100 includes: a first N-type semiconductor region 3, a first P-type semiconductor region, a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0329] For example, refer to Figure 34 In this application, the first portion of the first trench 101 extends along a fourth direction F4 parallel to the plane of the semiconductor substrate 2, and the second portion of the first trench 101 extends along a fifth direction F5 parallel to the plane of the semiconductor substrate 2. The fourth direction F4, the fifth direction F5, the second direction F2, and the first direction F1 are intersecting each other. For example, the first direction F1 is perpendicular to the second direction F2, the fourth direction F4 forms an angle with the first direction F1 and is biased towards the second direction F2 from the first direction F1, and the fifth direction F5 forms an angle with the first direction F1 and is away from the second direction F2 from the first direction F1. That is, the first trench 101 does not extend along the first direction F1, but extends partly along the fourth direction F4 and the rest along the fifth direction F5.

[0330] For example, refer to Figure 34 In this application, the edge of the second trench 102 projected onto the semiconductor substrate 2 is trapezoidal. Alternatively, the edge of the second trench 102 projected onto the semiconductor substrate 2 may also be arc-shaped. This application does not limit this aspect.

[0331] Figure 35 A top view of a semiconductor device provided in another embodiment of this application is shown.

[0332] Reference Figure 35 In this embodiment, the semiconductor device includes: an N-type semiconductor substrate 2, a drift layer 100, a trench structure, a gate dielectric layer 6, a gate electrode 7, an interlayer dielectric layer 10, a source electrode 11, and a drain electrode 1. Furthermore, the drift layer 100 includes: a first N-type semiconductor region 3, a first P-type semiconductor region, a second P-type semiconductor region 5, and a source region 8. This embodiment is a modification of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; the similarities will not be repeated here.

[0333] For example, refer to Figure 35In this application, in the same trench structure, multiple second trenches 102 are disposed at the first sidewall S1 of the first trench 101. Alternatively, in the same trench structure, multiple second trenches 102 may also be disposed at the second sidewall S2 of the first trench 101. Alternatively, in the same trench structure, multiple second trenches 102 may also be disposed at both the second sidewall S2 and the first sidewall S1 of the first trench 101.

[0334] In this application, features in different embodiments may be combined with each other without contradiction.

[0335] This application also provides a power conversion circuit for converting alternating current (AC) and / or direct current (DC) to output direct current (DC). For example, the power conversion circuit can be an AC-to-DC converter and / or a DC-to-DC converter. Exemplarily, the power conversion circuit may include a circuit board and one or more semiconductor devices, with the semiconductor devices connected to the circuit board. Because the semiconductor devices described above have good performance, the power conversion circuit including these semiconductor devices also has good performance. Furthermore, the principle by which this power conversion circuit solves the problem is similar to the principle by which the aforementioned semiconductor devices solve the problem; therefore, the technical effects of this power conversion circuit can be referred to the technical effects of the aforementioned semiconductor devices, and repetitions will not be repeated.

[0336] This application also provides a vehicle, which includes a load and a power conversion circuit provided in this application embodiment. The power conversion circuit converts alternating current and / or direct current into direct current before inputting it into the load to supply power. Because the power conversion circuit has good performance, the vehicle including the power conversion circuit also has good circuit performance. Furthermore, the principle by which this vehicle solves the problem is similar to the principle by which the aforementioned power conversion circuit solves the problem; therefore, the technical effect of this vehicle can be referred to the technical effect of the aforementioned power conversion circuit, and repeated details will not be elaborated further.

[0337] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: N-type semiconductor substrate; A drift layer, comprising: a first N-type semiconductor region, a second P-type semiconductor region, and a source region sequentially stacked on the semiconductor substrate, and the first P-type semiconductor region; the first P-type semiconductor region is disposed on two sides of the drift layer, and the first P-type semiconductor region extends from the top of the drift layer to the second P-type semiconductor region along a third direction perpendicular to the plane of the semiconductor substrate; A trench structure, comprising a plurality of first trenches and a plurality of second trenches, wherein the plurality of first trenches are arranged along a second direction parallel to the plane of the semiconductor substrate, the plurality of second trenches extend along the second direction, and the plurality of second trenches and the plurality of first trenches extend from the top of the drift layer to the first N-type semiconductor region along a third direction, wherein a second trench is disposed between two adjacent first trenches, and the plurality of second trenches are interconnected with the plurality of first trenches; A gate, wherein the gate is disposed in the plurality of first trenches and the plurality of second trenches through a gate dielectric layer; An interlayer dielectric layer covers the side of the gate away from the semiconductor substrate, and covers the gate and a first portion of the source region; The source electrode covers the side of the interlayer dielectric layer away from the semiconductor substrate, and covers the interlayer dielectric layer, the first P-type semiconductor region, and a second portion of the source region; Drain electrode, wherein the drain electrode is disposed on the side of the semiconductor substrate away from the drift layer and covers the semiconductor substrate; The second direction and the third direction are arranged to intersect each other.

2. The semiconductor device as claimed in claim 1, characterized in that, In the trench structure, a second trench is provided between two adjacent first trenches, and the second trench is provided on the side wall of the first trench.

3. The semiconductor device as described in claim 2, characterized in that, Each of the plurality of first trenches has a first sidewall and a second sidewall disposed opposite to each other in a first direction; the first direction, the second direction, and the third direction are intersecting each other. In the trench structure, the first part of the second trench is disposed at the first sidewall of the first trench, and the second part of the second trench is disposed at the second sidewall of the first trench, and the first part of the second trench and the second part of the second trench are alternately arranged along the second direction; Alternatively, in the trench structure, the plurality of second trenches are disposed on the first sidewall or the second sidewall of the first trench.

4. The semiconductor device according to any one of claims 1-3, characterized in that, The drift layer further includes: The third P-type semiconductor region is disposed below the trench structure and in contact with the bottom of the trench structure, and the third P-type semiconductor region is connected to the source electrode.

5. The semiconductor device as claimed in claim 4, characterized in that, The first trench has a first sidewall and a second sidewall disposed opposite to each other in the first direction; The drift layer further includes: A fourth P-type semiconductor region is disposed on at least one first sidewall and / or second sidewall of the first trench, and the fourth P-type semiconductor region is in contact with the third P-type semiconductor region and the first P-type semiconductor region, respectively.

6. The semiconductor device as claimed in claim 5, characterized in that, The plurality of first trenches are divided into at least one first unit and at least one second unit, and the first unit and the second unit are alternately arranged along the second direction; The first grooves in the first unit have the same groove width in the second direction, the first grooves in the second unit have the same groove width in the second direction, and the first grooves in the second unit have a greater groove width in the second direction than the first grooves in the first unit. The fourth P-type semiconductor region is disposed on the first sidewall and / or the second sidewall of the first trench in each of the second units.

7. The semiconductor device according to any one of claims 1-3, characterized in that, The drift layer further includes: A fifth P-type semiconductor region is provided below each of the first P-type semiconductor regions, and the fifth P-type semiconductor region is in contact with the first P-type semiconductor region to form a P-type semiconductor structure. The fifth P-type semiconductor region extends into the first N-type semiconductor region along the third direction. The distance between the bottom of the fifth P-type semiconductor region and the top of the drift layer is greater than the distance between the bottom of the trench structure and the top of the drift layer.

8. The semiconductor device as claimed in claim 7, characterized in that, Each of the plurality of second trenches has a third sidewall and a fourth sidewall disposed opposite to each other in the first direction; The orthogonal projection of the P-type semiconductor structure onto the first plane formed by the second direction and the third direction covers the orthogonal projection of the corresponding second trench onto the first plane.

9. The semiconductor device as claimed in claim 8, characterized in that, The P-type semiconductor structures disposed on the two sides of the drift layer are each an integral region, and the orthogonal projection of the P-type semiconductor structure on the semiconductor substrate is a strip-shaped region extending along the second direction.

10. The semiconductor device as claimed in claim 8, characterized in that, The P-type semiconductor structures disposed on both sides of the drift layer are multiple regions, and the third part of the source region is also multiple regions. The multiple regions of the multiple P-type semiconductor structures and the multiple regions of the third part of the source region are arranged alternately.

11. The semiconductor device according to any one of claims 8-10, characterized in that, The orthographic projection of the P-type semiconductor structure onto the semiconductor substrate and the orthographic projection of the trench structure onto the semiconductor substrate do not overlap.

12. The semiconductor device as claimed in claim 11, characterized in that, The P-type semiconductor structure and the trench structure have a fourth portion of the source region.

13. The semiconductor device as claimed in claim 11, characterized in that, When the P-type semiconductor structure disposed on both sides of the drift layer is a plurality of regions, the trench structure contacts the corresponding P-type semiconductor structure through the corresponding gate dielectric layer.

14. The semiconductor device according to any one of claims 7-13, characterized in that, The drift layer further includes: a first shielding trench; The first shielding trench is disposed on two sides of the drift layer, and the P-type semiconductor structure is disposed on the sidewall and bottom of the first shielding trench.

15. The semiconductor device according to any one of claims 1-14, characterized in that, The drift layer further includes: a second N-type semiconductor region, wherein the second N-type semiconductor region is disposed between the first N-type semiconductor region and the second P-type semiconductor region; The doping concentration of the second N-type semiconductor region is greater than that of the first N-type semiconductor region, and the doping concentration of the second N-type semiconductor region is less than that of the source region.

16. The semiconductor device according to any one of claims 1-15, characterized in that, The semiconductor substrate and the drift layer are made of SiC.

17. A method for fabricating a semiconductor device, characterized in that, include: A drift layer is epitaxially grown on an N-type semiconductor substrate, and a first N-type semiconductor region, a second P-type semiconductor region, and a source region are sequentially stacked on the semiconductor substrate in the drift layer, as well as a first P-type semiconductor region disposed on two sides of the drift layer; wherein, the first P-type semiconductor region extends from the top of the drift layer to the second P-type semiconductor region along a third direction perpendicular to the plane of the semiconductor substrate. The drift layer is etched to form a trench structure in the drift layer. The trench structure includes a plurality of first trenches and a plurality of second trenches. The plurality of first trenches are arranged along a second direction parallel to the plane of the semiconductor substrate. The plurality of second trenches extend along the second direction. The plurality of second trenches and the plurality of first trenches extend from the top of the drift layer to the first N-type semiconductor region along the third direction. A second trench is disposed between two adjacent first trenches, and the plurality of second trenches are interconnected with the plurality of first trenches. A gate dielectric layer is formed in the trench structure; A gate is formed in a trench structure in which a gate dielectric layer is formed; An interlayer dielectric layer covering the entire drift layer is formed on the gate; The interlayer dielectric layer is etched to expose the first P-type semiconductor region and a second portion of the source region, and the interlayer dielectric layer covers a first portion of the source region and completely covers the gate. A source electrode is formed on the side of the interlayer dielectric layer away from the semiconductor substrate, such that the source electrode is in contact with the first P-type semiconductor region and the second portion of the source region, and a drain electrode is formed on the side of the semiconductor substrate away from the drift layer.

18. The method for fabricating a semiconductor device as described in claim 17, characterized in that, The preparation method further includes: After forming the trench structure in the drift layer, a third P-type semiconductor region is formed at the bottom of each first trench and each second trench of the trench structure using a self-aligned process and a vertical ion implantation process. Using a tilted ion implantation process, a fourth P-type semiconductor region is formed at at least one sidewall of at least one of the first trenches along a first direction, which is in contact with the third P-type semiconductor region and the first P-type semiconductor region, respectively.

19. The method for fabricating a semiconductor device as described in claim 17, characterized in that, The preparation method further includes: After forming a first N-type semiconductor region, a first P-type semiconductor region, a second P-type semiconductor region, and a source region in the drift layer, a fifth P-type semiconductor region is formed below each of the first P-type semiconductor regions, such that the fifth P-type semiconductor region extends into the first N-type semiconductor region along the third direction, and is in contact with the first P-type semiconductor region to form a P-type semiconductor structure; wherein, the distance between the bottom of the fifth P-type semiconductor region and the top of the drift layer is greater than the distance between the bottom of the trench structure and the top of the drift layer.

20. The method for fabricating a semiconductor device as described in claim 19, characterized in that, The step of forming a fifth P-type semiconductor region below each of the first P-type semiconductor regions includes: The two sides of the drift layer are etched to form a first shielding trench extending upward along the third side into the first N-type semiconductor region in the drift layer; Ion implantation is performed on the sidewalls and bottom of the first shielding trench to form the fifth P-type semiconductor region. The fifth P-type semiconductor region is disposed below the first P-type semiconductor region, and the fifth P-type semiconductor region corresponds to and is in contact with the first P-type semiconductor region.

21. A power conversion circuit, characterized in that, The power conversion circuit is used to convert AC and / or DC power and output DC power. The power conversion circuit includes a circuit board and one or more semiconductor devices as described in any one of claims 1-16, wherein the semiconductor devices are connected to the circuit board.

22. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 21, the power conversion circuit being used to convert AC and / or DC power into DC power before inputting it to the load.

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