Structure, manufacturing method and electronic device of silicon carbide mosfet

Abstract

The application discloses a structure of a silicon carbide MOSFET, a manufacturing method and an electronic device, belongs to the technical field of semiconductors, and comprises an epitaxial layer, a channel layer, an active layer, a gate structure, a P-type semiconductor column and a P-type column; the channel layer is arranged on the upper surface of the epitaxial layer; the active layer is arranged on the upper surface of the channel layer; the gate structure vertically penetrates the active layer and the channel layer from the upper surface of the active layer downwards; the P-type semiconductor column is located on the lower surface of the gate structure; the P-type column is located on the lower surface of the channel layer and is away from the gate structure by a preset distance; wherein the cross-sectional area of the upper surface of the P-type semiconductor column is greater than the cross-sectional area of the lower surface of the P-type semiconductor column; the cross-sectional area of the upper surface of the P-type column is greater than the cross-sectional area of the lower surface of the P-type column; the short-circuit resistance of the silicon carbide MOSFET is improved, and the on-resistance is reduced.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to the structure, manufacturing method and electronic device of a silicon carbide MOSFET. Background Technology

[0002] Due to human factors and machine failures, power devices may sometimes operate under short-circuit faults. Normally, once a short circuit is detected, the external protection circuit will trigger the protection mechanism to immediately shut down the circuit. However, within the response time of the protection circuit, the device is required to withstand a certain period of short circuit, i.e., short-circuit withstand capability.

[0003] The related silicon carbide metal-oxide-semiconductor field-effect transistor (MOSFET) device includes an epitaxial layer, a channel layer, an active layer, and a gate structure arranged from bottom to top; the gate structure extends vertically downward from the upper surface of the active layer through the active layer and the channel layer.

[0004] Due to the high gate oxide reliability and current density of silicon carbide MOSFETs, electrons accumulate in the junction region of the epitaxial layer, channel layer, and gate structure, causing the temperature in this junction region to be too high and leading to thermal failure. Therefore, the short-circuit withstand capability of related silicon carbide MOSFETs is low. For example, the short-circuit withstand capability of Infineon's 1200V silicon carbide MOSFET is only 3µs. Summary of the Invention

[0005] The purpose of this application is to provide a structure, manufacturing method and electronic device for silicon carbide MOSFETs, in order to solve the problem of low short-circuit withstand capability of silicon carbide MOSFETs.

[0006] This application provides a structure for a silicon carbide MOSFET, including:

[0007] Epitaxial layer;

[0008] A channel layer disposed on the upper surface of the epitaxial layer;

[0009] An active layer disposed on the upper surface of the channel layer;

[0010] A gate structure extending longitudinally downwards from the upper surface of the active layer through the active layer and the channel layer;

[0011] P-type semiconductor pillars located on the lower surface of the gate structure;

[0012] A P-type pillar located on the lower surface of the channel layer and at a predetermined distance from the gate structure;

[0013] Wherein, the cross-sectional area of ​​the upper surface of the P-type semiconductor pillar is greater than the cross-sectional area of ​​the lower surface of the P-type semiconductor pillar; the cross-sectional area of ​​the upper surface of the P-type pillar is greater than the cross-sectional area of ​​the lower surface of the P-type pillar.

[0014] In one embodiment, the side surface of the P-type semiconductor pillar is stepped or inclined; the side surface of the P-type pillar is stepped or inclined.

[0015] In one embodiment, it further includes:

[0016] It extends longitudinally downwards from the upper surface of the active layer through the heavily doped P-type region of the active layer.

[0017] In one embodiment, the gate structure includes:

[0018] A first trench extends longitudinally downward from the upper surface of the active layer through the active layer and the channel layer;

[0019] A first dielectric layer covering the inner surface of the sidewall of the first trench and the bottom of the first trench;

[0020] Conductive pillars filling the interior of the dielectric layer.

[0021] In one embodiment, the epitaxial layer is an N-type epitaxial layer, the channel layer is a P-type channel layer, and the active layer is an N-type active layer.

[0022] In one embodiment, the channel layer is the gate of the silicon carbide MOSFET, the epitaxial layer is the drain of the silicon carbide MOSFET, and the active layer is the source of the silicon carbide MOSFET.

[0023] The P-type semiconductor pillar and the epitaxial layer form a superjunction structure; the P-type pillar and the epitaxial layer form a superjunction structure.

[0024] This application also provides a method for manufacturing a silicon carbide MOSFET, the method comprising:

[0025] A composite structure is formed on the upper surface of a substrate; the composite structure includes an epitaxial layer, a first P-type pillar, a P-type semiconductor pillar, and a second P-type pillar; wherein the first P-type pillar, the P-type semiconductor pillar, and the second P-type pillar all extend downward from the upper surface of the epitaxial layer, and are arranged sequentially at a predetermined distance from each other on the upper surface; the cross-sectional area of ​​the upper surface of the P-type semiconductor pillar is greater than the cross-sectional area of ​​the lower surface of the P-type semiconductor pillar; the cross-sectional area of ​​the upper surface of the P-type pillar is greater than the cross-sectional area of ​​the lower surface of the P-type pillar.

[0026] A channel layer is formed on the upper surface of the composite structure;

[0027] Ion implantation is performed on the upper surface of the channel layer to form an active layer;

[0028] A gate structure is formed at the upward projection position of the P-type semiconductor pillar; wherein, it extends longitudinally downward from the upper surface of the active layer through the active layer and the channel layer.

[0029] In one embodiment, forming the composite structure on the upper surface of the substrate includes:

[0030] A zero-drift layer is formed on the upper surface of the substrate;

[0031] When i is 1, the i-th composite layer is formed on the upper surface of the zero-drift layer; when i is greater than 1, the i-th composite layer is formed on the upper surface of the (i-1)-th composite layer; this step is repeated n times; n is a natural number greater than 1; i is a positive integer less than or equal to n;

[0032] The i-th composite layer comprises a first P-type region, a first N-type region, a P-type semiconductor region, a second N-type region, and a second P-type region arranged sequentially; the cross-sectional area of ​​the P-type semiconductor region in the i-th composite layer is greater than the cross-sectional area of ​​the P-type semiconductor region in the (i-1)-th composite layer; the cross-sectional area of ​​the P-type region in the i-th composite layer is greater than the cross-sectional area of ​​the P-type region in the (i-1)-th composite layer.

[0033] The P-type semiconductor regions in the first composite layer to the P-type semiconductor regions in the nth composite layer together constitute a P-type semiconductor pillar; the first P-type region in the first composite layer to the first P-type region in the nth composite layer together constitute a first P-type pillar; the second P-type region in the first composite layer to the second P-type region in the nth composite layer together constitute a second P-type pillar; the zero-drift layer, the first N-type region in the first composite layer to the first N-type region in the nth composite layer, and the second N-type region in the first composite layer to the second N-type region in the nth composite layer together constitute the composite structure.

[0034] In one embodiment, forming the gate structure at the upward projection position of the P-type semiconductor pillar includes:

[0035] Remove a portion of the active layer and a portion of the channel layer to form a first trench;

[0036] A second dielectric layer is formed on the upper surface of the active layer and the upper surface of the second trench;

[0037] Remove the second dielectric layer on the upper surface of the active layer and retain the second dielectric layer on the upper surface of the first trench to form a first dielectric layer;

[0038] The interior of the first dielectric layer is filled to form conductive pillars.

[0039] This application also provides an electronic device, which includes the structure of the silicon carbide MOSFET described above.

[0040] The beneficial effects of this invention compared to the prior art are as follows: Since the P-type semiconductor pillars are located on the lower surface of the gate structure, and the P-type pillars are located on the lower surface of the channel layer at a predetermined distance from the gate structure, and both the P-type semiconductor pillars and the P-type pillars satisfy the condition that the cross-sectional area of ​​the upper surface is greater than the cross-sectional area of ​​the lower surface, thus forming P-type semiconductor pillars and P-type pillars with sloping or stepped sides, when electrons flow into the junction region of the epitaxial layer, channel layer, and gate structure, they are squeezed by the sloping or stepped sides and quickly displaced below the epitaxial layer. This prevents electrons from concentrating excessively in the junction region, thus reducing the thermal effect and improving the short-circuit withstand capability of the silicon carbide MOSFET. Simultaneously, the P-type semiconductor pillars and P-type pillars form a superjunction structure with the epitaxial layer, improving the withstand voltage capability of the silicon carbide MOSFET. Furthermore, the improved withstand voltage capability of the silicon carbide MOSFET allows for an increase in the doping concentration of the epitaxial layer during the manufacturing process, thereby reducing the on-resistance. Attached Figure Description

[0041] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A schematic diagram of the structure of a silicon carbide MOSFET provided in an embodiment of this application;

[0043] Figure 2 This is a schematic diagram of another structure of the silicon carbide MOSFET provided in one embodiment of this application;

[0044] Figure 3 This is a schematic diagram of another structure of the silicon carbide MOSFET provided in one embodiment of this application;

[0045] Figure 4 This is a schematic diagram illustrating the formation of the zero-drift layer in a method for manufacturing a silicon carbide MOSFET according to an embodiment of this application.

[0046] Figure 5 This is a schematic diagram of the formation of the first composite layer in the manufacturing method of the silicon carbide MOSFET provided in the embodiments of this application;

[0047] Figure 6 This is a schematic diagram illustrating the formation of a second composite layer and conductive pillars in a method for manufacturing a silicon carbide MOSFET according to an embodiment of this application.

[0048] Figure 7 This is a schematic diagram of the formation of the third composite layer in the manufacturing method of the silicon carbide MOSFET provided in the embodiments of this application;

[0049] Figure 8 This is a schematic diagram of the formation of a channel layer in a method for manufacturing a silicon carbide MOSFET according to an embodiment of this application;

[0050] Figure 9 This is a schematic diagram illustrating the formation of an active layer in a method for manufacturing a silicon carbide MOSFET according to an embodiment of this application.

[0051] Figure 10 This is a schematic diagram illustrating the formation of a gate structure in a method for manufacturing a silicon carbide MOSFET according to an embodiment of this application.

[0052] Figure 11 This is a schematic diagram illustrating the formation of a heavily doped P-type region in a method for manufacturing a silicon carbide MOSFET according to an embodiment of this application. Detailed Implementation

[0053] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0054] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0055] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0057] Figure 1 The module structure of a silicon carbide MOSFET provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0058] The structure of a silicon carbide MOSFET includes an epitaxial layer 11, a channel layer 12, an active layer 13, a gate structure 14, a P-type semiconductor pillar 15, and a P-type pillar 16.

[0059] A channel layer 12 is disposed on the upper surface of the epitaxial layer 11; an active layer 13 is disposed on the upper surface of the channel layer 12; a gate structure 14 extends vertically downward from the upper surface of the active layer 13 through the active layer 13 and the channel layer 12; a P-type semiconductor pillar 15 is located on the lower surface of the gate structure 14; a P-type pillar 16 is located on the lower surface of the channel layer 12 and at a predetermined distance from the gate structure 14; wherein, the cross-sectional area of ​​the upper surface of the P-type semiconductor pillar 15 is greater than the cross-sectional area of ​​the lower surface of the P-type semiconductor pillar 15; and the cross-sectional area of ​​the upper surface of the P-type pillar 16 is greater than the cross-sectional area of ​​the lower surface of the P-type pillar 16.

[0060] In specific implementations, the structure of a silicon carbide MOSFET also includes a substrate 80 and a buffer layer 90.

[0061] A buffer layer 90 is disposed on the lower surface of the epitaxial layer 11; a substrate 80 is disposed on the lower surface of the buffer layer 90.

[0062] By way of example and not limitation, the side surface of the P-type semiconductor pillar 15 is stepped or beveled; the side surface of the P-type pillar 16 is stepped or beveled.

[0063] like Figure 2 As shown, the structure of the silicon carbide MOSFET also includes a heavily doped P-type region 17.

[0064] The heavily doped P-type region 17 extends longitudinally downwards from the upper surface of the active layer 13 through the active layer 13.

[0065] By setting a heavily doped P-type region 17 connected to the active layer 13 and the channel layer 12, the parasitic effect caused by the parasitic transistor is avoided. The parasitic transistor is composed of the epitaxial layer 11, the channel layer 12 and the active layer 13.

[0066] like Figure 3 As shown, the gate structure 14 includes a first trench 141, a first dielectric layer 142, and a conductive pillar 143.

[0067] The first trench 141 extends longitudinally downward from the upper surface of the active layer 13 through the active layer 13 and the channel layer 12; the first dielectric layer 142 covers the inner surface of the sidewall of the first trench 141 and the bottom of the first trench 141; the conductive pillar 143 fills the interior of the dielectric layer.

[0068] It should be noted that the first dielectric layer 142 is made of silicon dioxide and silicon nitride; the conductive pillar 143 is made of polycrystalline silicon.

[0069] The gate structure 14 is simple and reliable.

[0070] It should be noted that the epitaxial layer 11 is an N-type epitaxial layer 11, the channel layer 12 is a P-type channel layer 12, and the active layer 13 is an N-type active layer 13. Thus, an N-type silicon carbide MOSFET is formed.

[0071] It is worth emphasizing that the channel layer 12 is the gate of the silicon carbide MOSFET, the epitaxial layer 11 is the drain of the silicon carbide MOSFET, and the active layer 13 is the source of the silicon carbide MOSFET; the P-type semiconductor pillar 15 and the epitaxial layer 11 form a superjunction structure; the P-type pillar 16 and the epitaxial layer 11 form a superjunction structure.

[0072] The superjunction structure forms a longitudinal electric field, which improves the breakdown voltage of silicon carbide MOSFETs. Furthermore, the improved breakdown voltage of silicon carbide MOSFETs can be achieved by increasing the doping concentration of the epitaxial layer 11 in the process, thereby reducing the on-resistance.

[0073] Corresponding to one embodiment of a silicon carbide MOSFET, the present invention also provides an embodiment of a method for manufacturing a silicon carbide MOSFET.

[0074] A method for manufacturing a silicon carbide MOSFET, the method comprising steps 401 to 406.

[0075] In step 401, a composite structure is formed on the upper surface of the substrate 80. The composite structure includes an epitaxial layer 11, a first P-type pillar 16, a P-type semiconductor pillar 15, and a second P-type pillar 16. The first P-type pillar 16, the P-type semiconductor pillar 15, and the second P-type pillar 16 all extend downward from the upper surface of the epitaxial layer 11 and are arranged sequentially at a predetermined distance from each other on the upper surface. The cross-sectional area of ​​the upper surface of the P-type semiconductor pillar 15 is greater than the cross-sectional area of ​​the lower surface of the P-type semiconductor pillar 15. The cross-sectional area of ​​the upper surface of the P-type pillar 16 is greater than the cross-sectional area of ​​the lower surface of the P-type pillar 16.

[0076] It should be noted that a buffer layer 90 can be formed on the upper surface of the substrate 80, and then a composite structure can be formed on the upper surface of the buffer layer 90.

[0077] In specific implementation, step 401 includes step A1 and step B1.

[0078] In step A1, as Figure 4 As shown, a zero-drift layer 20 is formed on the upper surface of the substrate 80.

[0079] The zero drift layer 20 can be formed on the upper surface of the substrate 80 by processes such as vapor deposition or sputtering.

[0080] In step B1, when i is 1, the i-th composite layer is formed on the upper surface of the zero-drift layer 20; when i is greater than 1, the i-th composite layer is formed on the upper surface of the (i-1)-th composite layer; step B1 is repeated n times; n is a natural number greater than 1; i is a positive integer less than or equal to n; for example, taking n as 3 as an example... Figures 5 to 7 As shown, the first composite layer 21, the second composite layer 22, and the third composite layer 23 are formed sequentially.

[0081] It should be noted that forming the i-th composite layer on the upper surface of the zero drift layer 20 includes: forming the i-th drift layer on the upper surface of the zero drift layer 20 by processes such as vapor deposition or sputtering, and then performing ion implantation at the first preset position of the i-th drift layer to form a first P-type region 211, a first N-type region 212, a P-type semiconductor region 213, a second N-type region 214, and a second P-type region 215 arranged in sequence.

[0082] It should be noted that forming the i-th composite layer on the upper surface of the i-1 composite layer includes: forming the i-th drift layer on the upper surface of the i-1 composite layer by processes such as vapor deposition or sputtering, and then performing ion implantation at the first preset position of the i-th drift layer to form a first P-type region 211, a first N-type region 212, a P-type semiconductor region 213, a second N-type region 214, and a second P-type region 215 arranged in sequence.

[0083] The i-th composite layer includes a first P-type region 211, a first N-type region 212, a P-type semiconductor region 213, a second N-type region 214, and a second P-type region 215 arranged sequentially; the cross-sectional area of ​​the P-type semiconductor region 213 in the i-th composite layer is greater than the cross-sectional area of ​​the P-type semiconductor region 213 in the (i-1)-th composite layer; the cross-sectional area of ​​the P-type region in the i-th composite layer is greater than the cross-sectional area of ​​the P-type region in the (i-1)-th composite layer.

[0084] It should be noted that the first P-type semiconductor region 213 in the first composite layer 21 to the P-type semiconductor region 213 in the nth composite layer together constitute the P-type semiconductor pillar 15; the first P-type region 211 in the first composite layer 21 to the first P-type region 211 in the nth composite layer together constitute the first P-type pillar 16; the second P-type region 215 in the first composite layer 21 to the second P-type region 215 in the nth composite layer together constitute the second P-type pillar 16; the zero drift layer 20, the first N-type region 212 in the first composite layer 21 to the first N-type region 212 in the nth composite layer, the second N-type region 214 in the first composite layer 21 to the second N-type region 214 in the nth composite layer together constitute the composite structure.

[0085] In step 402, as Figure 8 As shown, a channel layer 12 is formed on the upper surface of the composite structure.

[0086] A channel layer 12 can be formed on the upper surface of the composite structure by processes such as vapor deposition or sputtering.

[0087] In step 403, as Figure 9 As shown, ion implantation is performed on the upper surface of the channel layer 12 to form the active layer 13.

[0088] Among them, the channel layer 12 has the opposite semiconductor type to the epitaxial layer 11 and the active layer 13; the epitaxial layer 11 and the active layer 13 have the same semiconductor type.

[0089] In step 404, as Figure 10 As shown, a gate structure 14 is formed at the upward projection position of the P-type semiconductor pillar 15; wherein, it extends vertically downward from the upper surface of the active layer 13 through the active layer 13 and the channel layer 12.

[0090] In specific implementation, step 404 includes steps A2 to D2.

[0091] In step A2, a portion of the active layer 13 and a portion of the channel layer 12 are removed to form the first trench 141;

[0092] A portion of the active layer 13 and a portion of the channel layer 12 are removed by an etching process to form the first trench 141;

[0093] In step B2, a second dielectric layer is formed on the upper surface of the active layer 13 and the upper surface of the second trench;

[0094] A second dielectric layer can be formed on the upper surface of the active layer 13 and the upper surface of the second trench through processes such as vapor deposition or sputtering.

[0095] In step C2, the second dielectric layer on the upper surface of the active layer 13 is removed while the second dielectric layer on the upper surface of the first trench 141 is retained to form the first dielectric layer 142.

[0096] The second dielectric layer on the upper surface of the active layer 13 is etched back without a mask, and the second dielectric layer on the upper surface of the first trench 141 is retained to form the first dielectric layer 142.

[0097] In step D2, the interior of the first dielectric layer 142 is filled to form conductive pillars 143.

[0098] The interior of the first dielectric layer 142 can be filled by processes such as vapor deposition or sputtering to form conductive pillars 143.

[0099] It should be noted that step 404 may be followed by step 405.

[0100] In step 405, as Figure 11 As shown, ion implantation is performed at a predetermined position on the upper surface of the active layer 13 to form a heavily doped P-type region 17.

[0101] This invention includes an epitaxial layer, a channel layer, an active layer, a gate structure, a P-type semiconductor pillar, and a P-type pillar. The channel layer is disposed on the upper surface of the epitaxial layer. The active layer is disposed on the upper surface of the channel layer. The gate structure extends vertically downward from the upper surface of the active layer through the active layer and the channel layer. The P-type semiconductor pillar is located on the lower surface of the gate structure. The P-type pillar is located on the lower surface of the channel layer and at a predetermined distance from the gate structure. The cross-sectional area of ​​the upper surface of the P-type semiconductor pillar is larger than the cross-sectional area of ​​the lower surface of the P-type semiconductor pillar. The cross-sectional area of ​​the upper surface of the P-type semiconductor pillar is larger than the cross-sectional area of ​​the lower surface of the P-type semiconductor pillar. The P-type semiconductor pillar is located on the lower surface of the gate structure. The P-type pillar is located on the lower surface of the channel layer and at a predetermined distance from the gate structure. The P-type semiconductor pillar... Both the body pillar and the P-type pillar satisfy the condition that the cross-sectional area of ​​the upper surface is greater than that of the lower surface, thus forming P-type semiconductor pillars and P-type pillars with sloping or stepped sides. Therefore, when electrons flow into the junction region of the epitaxial layer, the channel layer, and the gate structure, they are squeezed by the sloping or stepped sides and quickly displaced to the bottom of the epitaxial layer. This prevents electrons from being overly concentrated in the junction region, thus avoiding the thermal effect and improving the short-circuit withstand capability of the silicon carbide MOSFET. At the same time, the P-type semiconductor pillar and the P-type pillar form a superjunction structure with the epitaxial layer, which improves the voltage withstand capability of the silicon carbide MOSFET. Furthermore, the improved voltage withstand capability of the silicon carbide MOSFET can be achieved by increasing the doping concentration of the epitaxial layer in the process, thereby reducing the on-resistance.

[0102] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0103] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A structure of a silicon carbide MOSFET, characterized in that, include: Epitaxial layer; A channel layer disposed on the upper surface of the epitaxial layer; An active layer disposed on the upper surface of the channel layer; A gate structure extending longitudinally downwards from the upper surface of the active layer through the active layer and the channel layer; P-type semiconductor pillars located on the lower surface of the gate structure; A P-type pillar located on the lower surface of the channel layer and at a predetermined distance from the gate structure; Wherein, the cross-sectional area of ​​the upper surface of the P-type semiconductor pillar is greater than the cross-sectional area of ​​the lower surface of the P-type semiconductor pillar; the cross-sectional area of ​​the upper surface of the P-type pillar is greater than the cross-sectional area of ​​the lower surface of the P-type pillar. The side surface of the P-type semiconductor pillar is stepped or inclined; the side surface of the P-type pillar is stepped or inclined. When electrons flow into the junction region of the epitaxial layer, the channel layer and the gate structure, they are squeezed by the inclined or stepped side surface and quickly displaced to the bottom of the epitaxial layer, so that the electrons do not concentrate too much in the junction region and cause thermal effects.

2. The structure of the silicon carbide MOSFET as described in claim 1, characterized in that, Also includes: It extends longitudinally downwards from the upper surface of the active layer through the heavily doped P-type region of the active layer.

3. The structure of the silicon carbide MOSFET as described in claim 1, characterized in that, The gate structure includes: A first trench extends longitudinally downward from the upper surface of the active layer through the active layer and the channel layer; A first dielectric layer covering the inner surface of the sidewall of the first trench and the bottom of the first trench; Conductive pillars filling the interior of the dielectric layer.

4. The structure of the silicon carbide MOSFET as described in claim 1, characterized in that, The epitaxial layer is an N-type epitaxial layer, the channel layer is a P-type channel layer, and the active layer is an N-type active layer.

5. The structure of the silicon carbide MOSFET as described in claim 1, characterized in that, The epitaxial layer is the drain of the silicon carbide MOSFET, and the active layer is the source of the silicon carbide MOSFET. The P-type semiconductor pillar and the epitaxial layer form a superjunction structure; the P-type pillar and the epitaxial layer form a superjunction structure.

6. A method for manufacturing a silicon carbide MOSFET, characterized in that, The manufacturing method includes: A composite structure is formed on the upper surface of a substrate; the composite structure includes an epitaxial layer, a first P-type pillar, a P-type semiconductor pillar, and a second P-type pillar; wherein the first P-type pillar, the P-type semiconductor pillar, and the second P-type pillar all extend downward from the upper surface of the epitaxial layer, and are arranged sequentially at a predetermined distance from each other on the upper surface; the cross-sectional area of ​​the upper surface of the P-type semiconductor pillar is larger than the cross-sectional area of ​​the lower surface of the P-type semiconductor pillar; the cross-sectional area of ​​the upper surface of the P-type pillar is larger than the cross-sectional area of ​​the lower surface of the P-type pillar; the P-type pillar includes the first P-type pillar and the second P-type pillar; a channel layer is formed on the upper surface of the composite structure; Ion implantation is performed on the upper surface of the channel layer to form an active layer; A gate structure is formed at the upward projection position of the P-type semiconductor pillar; wherein, the gate structure extends longitudinally downward from the upper surface of the active layer through the active layer and the channel layer; The side surface of the P-type semiconductor pillar is stepped or inclined; the side surface of the P-type pillar is stepped or inclined. When electrons flow into the junction region of the epitaxial layer, the channel layer and the gate structure, they are squeezed by the inclined or stepped side surface and quickly displaced to the bottom of the epitaxial layer, so that the electrons do not concentrate too much in the junction region and cause thermal effects.

7. The method for manufacturing a silicon carbide MOSFET according to claim 6, characterized in that, The formation of the composite structure on the upper surface of the substrate includes: A zero-drift layer is formed on the upper surface of the substrate; When i is 1, the i-th composite layer is formed on the upper surface of the zero-drift layer; when i is greater than 1, the i-th composite layer is formed on the upper surface of the (i-1)-th composite layer; this step is repeated n times; n is a natural number greater than 1; i is a positive integer less than or equal to n; The i-th composite layer comprises a first P-type region, a first N-type region, a P-type semiconductor region, a second N-type region, and a second P-type region arranged sequentially; the cross-sectional area of ​​the P-type semiconductor region in the i-th composite layer is greater than the cross-sectional area of ​​the P-type semiconductor region in the (i-1)-th composite layer; the cross-sectional area of ​​the P-type region in the i-th composite layer is greater than the cross-sectional area of ​​the P-type region in the (i-1)-th composite layer. The P-type semiconductor regions in the first composite layer to the P-type semiconductor regions in the nth composite layer together constitute a P-type semiconductor pillar; the first P-type region in the first composite layer to the first P-type region in the nth composite layer together constitute a first P-type pillar; the second P-type region in the first composite layer to the second P-type region in the nth composite layer together constitute a second P-type pillar; the zero-drift layer, the first N-type region in the first composite layer to the first N-type region in the nth composite layer, and the second N-type region in the first composite layer to the second N-type region in the nth composite layer together constitute the composite structure.

8. The method for manufacturing a silicon carbide MOSFET according to claim 6, characterized in that, The formation of the gate structure at the upward projection position of the P-type semiconductor pillar includes: Remove a portion of the active layer and a portion of the channel layer to form a first trench; A second dielectric layer is formed on the upper surface of the active layer and the upper surface of the first trench; Remove the second dielectric layer on the upper surface of the active layer and retain the second dielectric layer on the upper surface of the first trench to form a first dielectric layer; The interior of the first dielectric layer is filled to form conductive pillars.

9. An electronic device, characterized in that, The electronic device includes the structure of a silicon carbide MOSFET as described in any one of claims 1 to 5.

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