Epitaxial structure of light-emitting diode and preparation method thereof

Abstract

The present invention relates to the field of light-emitting semiconductor technology, and more specifically, to an epitaxial structure for a light-emitting diode (LED), comprising a substrate. The epitaxial structure further comprises a buffer layer, a 3D nucleation layer, a 2D leveling layer, an N-type layer, a transition layer, an active layer, and a P-type layer sequentially disposed on the substrate. The 3D nucleation layer and the 2D leveling layer are both n-type doped, and the concentration of n-type doping in the 3D nucleation layer is higher than that in the 2D leveling layer. The present invention achieves a higher Si doping concentration in the nucleation layer than in the leveling layer, and introduces highly doped Si through the nucleation layer to obtain a greater number of intercalated dislocations, thereby facilitating an increase in the Pits density in the subsequent transition layer, thereby reducing voltage and increasing brightness.

Description

Technical Field

[0001] The present invention relates to the technical field of light-emitting semiconductors, and in particular to an epitaxial structure of a light-emitting diode and a preparation method thereof. Background Art

[0002] A light-emitting diode (LED) is a solid-state semiconductor diode light-emitting device widely used in lighting applications such as indicator lights and display screens. Currently, the primary method for producing LED wafers is through metal-organic chemical vapor deposition (MOCVD). The process can be summarized as follows: an epitaxial wafer substrate (such as a sapphire substrate or Si substrate) is placed in the groove of a graphite carrier. This carrier is then introduced into the MOCVD reaction chamber. The chamber is heated to a predetermined temperature, and organometallic compounds and Group V gases are introduced to break chemical bonds on the wafer substrate and repolymerize to form the LED epitaxial layer. However, the current LED structure's brightness and voltage have been a persistent challenge, with high brightness typically associated with high voltage.

[0003] In current LED epitaxy structures, several approaches are commonly used to reduce voltage: 1. Increasing the Si doping in the N-type layer and quantum wells achieves this goal, but this can easily compromise brightness, and current doping concentrations have reached saturation. Overdoping can significantly damage material quality, and thus brightness. Therefore, the Si doping concentration in the N-type layer is generally controlled between 1E19 and 3E19, and the Si doping in the quantum wells is generally controlled between 5E17 and 5E18. 2. Improving current spreading capability by creating Pits in the transition layer reduces voltage, but the size of the Pits is difficult to control: too large can damage the light-emitting area, while too small can have no effect on voltage reduction or brightness improvement.

[0004] In the prior art, the invention is titled "Light Emitting Diode Epitaxial Wafer and Preparation Method Thereof" and the invention patent publication number is CN112366255A. The invention comprises a substrate and a GaN buffer layer, a nucleation layer, a GaN filling layer, an n-type GaN layer, an active layer, and a p-type GaN layer sequentially stacked on the substrate. The nucleation layer and the GaN filling layer are both doped with n-type impurities. The doping concentration of the n-type impurities in the nucleation layer, the doping concentration of the n-type impurities in the GaN filling layer, and the doping concentration of the n-type impurities in the n-type GaN layer increase in sequence, and the doping concentration of the n-type impurities in the n-type GaN layer is 2E8 to 6E18 / cm 3 However, its use of too low N-type doping results in significantly poor ESD, making it impossible to achieve sufficient socket misalignment. As the white light market becomes increasingly demanding, in addition to high brightness requirements, lower VF1 requirements are also required. Without sacrificing brightness, there is an urgent need for LED structures to reduce voltage. Summary of the Invention

[0005] In view of this, the object of the present invention is to provide an epitaxial structure of a light emitting diode and a method for manufacturing the same, so as to solve the problem of being unable to improve the misalignment of the socket and reduce the voltage without losing brightness.

[0006] Based on the above objectives, the present invention provides an epitaxial structure of a light-emitting diode, including a substrate. The epitaxial structure also includes a buffer layer, a 3D nucleation layer, a 2D leveling layer, an N-type layer, a transition layer, an active layer and a P-type layer sequentially arranged on the substrate. The 3D nucleation layer and the 2D leveling layer are both n-type doped, and the concentration of the n-type doping in the 3D nucleation layer is higher than that in the n-type doping in the 2D leveling layer.

[0007] Optionally, the n-type doping elements include Si, Ge, and Sn. The present invention does not exclude the doping of other elements that are equivalent substitutes.

[0008] Preferably, the 3D nucleation layer and the 2D filling layer are both doped with Si, and the concentration of Si doped in the 2D filling layer is 5E17-E19 / cm 3 , the concentration of Si doped in the N-type layer is greater than 1E19 / cm 3 .

[0009] Optionally, the concentration of Si doped in the 3D nucleation layer is greater than 1E18 / cm 3 .

[0010] Preferably, the concentration of Si doped in the 3D nucleation layer is greater than 5E18 / cm 3 .

[0011] Preferably, the concentration of Si doped in the N-type layer is greater than 2E19 / cm 3 .

[0012] Preferably, the 3D nucleation layer and the 2D leveling layer are both n-type Si-doped GaN layers.

[0013] Optionally, at least one of the 3D nucleation layer, the 2D filling layer, and the N-type layer is a gradient layer with a gradient Si concentration or a stable layer with a stable Si concentration.

[0014] Optionally, among the 3D nucleation layer, the 2D filling layer, and the N-type layer, two layers are gradient layers and one layer is a stable layer; or two layers are stable layers and one layer is a gradient layer.

[0015] Optionally, the transition layer is an n-type doped Si transition layer, and the concentration of doped Si is 5E17-5E19 / cm 3 , C concentration <1E18 / cm 3 .

[0016] Preferably, the C concentration is 1E17-1E18 / cm 3 .

[0017] Preferably, a plurality of spaced-apart protrusions are provided on the substrate, the buffer layer and the 3D nucleation layer are sequentially arranged from bottom to top in the gap spaces between adjacent protrusions, and the buffer layer is attached to the outer sidewalls of the protrusions.

[0018] Optionally, the substrate is made of sapphire, silicon carbide, silicon or zinc oxide.

[0019] Optionally, the lower material of the protrusion is one of sapphire, silicon carbide, silicon or zinc oxide, and the upper material of the protrusion is one or more of silicon dioxide, silicon nitride, zinc oxide, silicon, silicon carbide, gallium arsenide, titanium pentoxide, and titanium dioxide.

[0020] The present invention also provides a method for preparing the epitaxial structure of the light-emitting diode, comprising the following steps:

[0021] S1. Place the substrate into the chamber of the machine and deposit a buffer layer on the surface of the substrate using PVD or MOCVD.

[0022] S2. Depositing and growing a 3D nucleation layer on the buffer layer, maintaining a growth temperature of 950-1080°C, a reaction chamber pressure of 100-300 Torr, and a V / III ratio of 800-1000;

[0023] S3, depositing and growing a 2D filling layer on the 3D nucleation layer, maintaining a growth temperature of 1080-1140°C, a reaction chamber pressure of 100-300 Torr, and a V / III ratio of 1000-1200;

[0024] S4, depositing and growing an N-type layer on the 2D filling layer;

[0025] S5, depositing a growth transition layer on the N-type layer;

[0026] S6. depositing and growing an active layer on the transition layer;

[0027] S7. Deposit and grow a P-type layer on the active layer.

[0028] The present invention achieves beneficial effects by adjusting the Si doping concentration in the nucleation layer to a higher level than that in the fill layer. This method, through the introduction of highly doped Si into the nucleation layer, produces a greater number of intercalated dislocations, facilitating increased Pits density in the subsequent transition layer, reducing voltage and improving brightness. The present invention also effectively enhances current spreading and ESD through the highly doped N-type layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only for the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 It is a structural schematic diagram of the present invention.

[0031] The following are marked in the figure:

[0032] 1. Substrate; 2. Buffer layer; 3. 3D nucleation layer; 4. 2D fill layer; 5. N-type layer; 6. Transition layer; 7. Active layer; 8. P-type layer. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to specific embodiments.

[0034] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should have the usual meanings understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0035] like Figure 1 As shown, an epitaxial structure of a light-emitting diode includes a substrate 1, and the epitaxial structure further includes a buffer layer 2, a 3D nucleation layer 3, a 2D leveling layer 4, an N-type layer 5, a transition layer 6, an active layer 7, and a P-type layer 8 sequentially arranged on the substrate 1. The 3D nucleation layer and the 2D leveling layer are both n-type doped, and the concentration of n-type doping in the 3D nucleation layer is higher than that in the 2D leveling layer. The n-type doping impurity type can be Si, Ge, or Sn, etc., and the present invention does not exclude the doping of other elements that are equivalently substituted. Preferably, the 3D nucleation layer 3 and the 2D leveling layer 4 are both doped with Si, and the concentration of Si doping in the 3D nucleation layer 3 is higher than that in the 2D leveling layer 4. The present invention achieves more intercalated dislocations by doping Si in the 3D nucleation layer and the 2D leveling layer, and introducing high Si doping through the nucleation layer, that is, adjusting the Si doping concentration in the nucleation layer to be higher than that in the leveling layer, so as to facilitate the subsequent transition layer to increase the Pits density, reduce voltage, and improve brightness.

[0036] The substrate may be made of one or more of sapphire (Al2O3), silicon carbide, silicon, zinc oxide, or a heterojunction substrate (Al2O3+SIO2), preferably sapphire.

[0037] In a preferred embodiment, the substrate is a composite substrate, wherein the lower portion of the composite substrate is made of one of sapphire, silicon carbide, silicon, or zinc oxide, and the upper portion of the composite substrate is made of one or more of silicon dioxide, silicon nitride, zinc oxide, silicon, silicon carbide, gallium arsenide, titanium pentoxide, or titanium dioxide. Silicon dioxide is preferably used.

[0038] As an optional embodiment, the concentration of Si doped in the 2D filling layer 4 is 5E17-E19 / cm 3 , the concentration of Si doped in the N-type layer 5 is greater than 1E19 / cm 3 Using this concentration range can further reduce voltage and increase brightness.

[0039] As an optional embodiment, the concentration of Si doped in the 3D nucleation layer 3 is greater than 1E18 / cm 3 When setting this concentration, it is still necessary to ensure that the concentration of Si doped in the 3D nucleation layer is higher than that of Si doped in the 2D filling layer, that is, the concentration of Si doped in the 2D filling layer is 5E17~1E18 / cm 3 , ensuring the improvement of the number of insertion defects. Preferably, the concentration of Si doped in the 3D nucleation layer is greater than 5E18 / cm 3 When this concentration range is set, the number of intercalation defects can be relatively maximized, which is beneficial to deposition growth and enhances the deposition interaction between the two.

[0040] Furthermore, the concentration of Si doped in the N-type layer 5 is greater than 2E19 / cm 3 When setting, the concentration of Si doped in the N-type layer is greater than the concentration of Si doped in the 2D fill layer. By using a highly doped N-type layer, the current expansion capability is effectively improved, thereby improving the ESD level. This doped Si concentration setting not only meets the requirements of improving the ESD level, but also does not affect the insertion dislocation. On the basis of no interference, it synergistically achieves the effect of brightening and reducing voltage.

[0041] In the present invention, both the 3D nucleation layer 3 and the 2D leveling layer 4 are GaN layers doped with n-type Si. Specifically, the 3D nucleation layer can be a first GaN layer, and the 2D leveling layer can be a second GaN layer, where the concentration of n-type Si doped in the first GaN layer is greater than the concentration of n-type Si doped in the second GaN layer.

[0042] In the present invention, at least one of the 3D nucleation layer 3, the 2D leveling layer 4, and the N-type layer 5 is a gradient layer with a gradual change in Si concentration or a stable layer with a stable Si concentration. The Si concentration can be stable or gradient, and the thicknesses of the three layers can be defined, such as 3D layer: 2-3μm; 2D layer: 1.5-2μm. In the specific setting, one of the layer structures among the 3D nucleation layer, the 2D leveling layer, and the N-type layer can be set as a gradient layer with a gradual change in Si concentration. Of course, two gradient layers or three gradient layers can also be used. For the same reason, one of the layer structures among the 3D nucleation layer, the 2D leveling layer, and the N-type layer can be set as a stable layer with a stable Si concentration. It is also possible to use two stable layers or three stable layers.

[0043] As an optional embodiment, two of the 3D nucleation layer 3, 2D leveling layer 4, and N-type layer 5 are graded layers and one is a stabilizing layer. Alternatively, two of the 3D nucleation layer, 2D leveling layer, and N-type layer are stabilizing layers and one is a graded layer. This combination creates an epitaxial structure with improved voltage reduction and brightness enhancement.

[0044] Furthermore, as a preferred embodiment, the 2D fill layer 4 is a 2D graded layer with a gradual Si concentration change, the 3D nucleation layer is a 3D graded layer with a gradual Si concentration change, and the N-type layer is an N-type stable layer with a stable Si concentration. This structural combination can further improve the synergistic brightness enhancement effect while reducing voltage.

[0045] In another preferred embodiment, the 3D nucleation layer 3 is a 3D stable layer with a stable Si concentration, the 2D leveling layer is a 2D graded layer or a 2D stable layer with a gradual or stable Si concentration, and the N-type layer is an N-type graded layer or an N-type stable layer with a gradual or stable Si concentration. This structural combination can further enhance the synergistic brightness enhancement effect while reducing voltage.

[0046] Optionally, the transition layer 6 is an n-type doped Si transition layer, the doped Si concentration is 5E17-5E19, and the C concentration is less than 1E18 / cm 3 The function of the transition layer is to release stress and control the size of the v-pit. This concentration setting can better meet the epitaxial structure requirements of actual products. Among them, the transition layer adopts low-temperature N-type GaN (temperature 700-850°C). Preferably, the C concentration is 1E17-1E18 / cm 3 , combined with the setting of the concentration of other layer structures, it can maximize the release of stress, and at the same time synergistically achieve the effect of brightening and lowering blood pressure to a certain extent.

[0047] As a preferred embodiment, a plurality of spaced protrusions are provided on the substrate 1, and the buffer layer and the 3D nucleation layer are sequentially arranged in the gap space between adjacent protrusions from bottom to top, and the outer wall of the protrusion is attached with a buffer layer. This can reduce the generation of a large number of defects caused by lattice mismatch. The buffer layer can be deposited on the surface of the substrate by PVD or MOCVD, and the buffer layer is preferably PVD. When setting, the material of the upper tip part of the protrusion is preferably silicon dioxide. The material of the lower part of the protrusion and the other parts of the substrate is preferably sapphire. This structure can achieve the effect of light transmission and brightening.

[0048] The method for preparing the epitaxial structure of a light emitting diode of the present invention comprises the following steps:

[0049] S1. Place the substrate into the chamber of the machine and deposit a buffer layer on the surface of the substrate using PVD or MOCVD.

[0050] S2. Depositing and growing a 3D nucleation layer on the buffer layer, maintaining a growth temperature of 950-1080°C, a reaction chamber pressure of 100-300 Torr, and a V / III ratio of 800-1000;

[0051] S3, depositing and growing a 2D filling layer on the 3D nucleation layer, maintaining a growth temperature of 1080-1140°C, a reaction chamber pressure of 100-300 Torr, and a V / III ratio of 1000-1200;

[0052] S4, depositing and growing an N-type layer on the 2D filling layer;

[0053] S5, depositing a growth transition layer on the N-type layer;

[0054] S6. depositing and growing an active layer on the transition layer;

[0055] S7. Deposit and grow a P-type layer on the active layer.

[0056] The following is a detailed explanation through specific examples.

[0057] Example 1

[0058] In this embodiment, the N-type layer is a stable layer (the concentration of Si doping is 3E19 / cm 3 ), the 2D layer is a graded layer (the graded concentration of doped Si is 1E18-1E19 / cm 3 ), 3D is a gradient layer (the gradient concentration of doped Si is 1E18-4E19 / cm 3 ).

[0059] The method for preparing the epitaxial structure of a light-emitting diode of this embodiment includes the following steps:

[0060] S1. Place the substrate into the chamber of the machine and deposit a buffer layer (AlN layer) on the surface of the substrate using PVD method;

[0061] S2. A 3D nucleation layer (GaN layer) is deposited on the buffer layer by MOCVD deposition, maintaining a growth temperature of 1000°C, a reaction chamber pressure of 200 Torr, and a V / III ratio of 900;

[0062] S3. Growing a 2D fill layer (GaN layer) on the 3D nucleation layer by MOCVD deposition, maintaining a growth temperature of 1110°C, a reaction chamber pressure of 200 Torr, and a V / III ratio of 1100;

[0063] S4. Depositing and growing an N-type layer (N-type GaN layer) on the 2D fill layer by MOCVD deposition;

[0064] S5. Depositing a transition layer (low-temperature N-type GaN) on the N-type layer by MOCVD deposition; the growth temperature is 800° C. and the growth pressure is 150 Torr;

[0065] S6. Growing an active layer on the transition layer by MOCVD deposition; the active layer is formed by alternating stacking of quantum well layers InGaN and quantum barrier layers GaN;

[0066] S7. A P-type layer is deposited and grown on the active layer by an MOCVD deposition method at a temperature of 800° C. The P-type layer adopts GaN / ALGaN.

[0067] Example 2

[0068] In this embodiment, the N-type layer is a stable layer (the concentration of Si doping is 3E19 / cm 3 ), the 2D layer is a stable layer (the gradient concentration of Si doping is 1E18-1E19 / cm 3 ), 3D is a gradient layer (the gradient concentration of doped Si is 1E18-3E19 / cm 3 ).

[0069] The method for preparing the epitaxial structure of a light-emitting diode of this embodiment includes the following steps:

[0070] S1. Place the substrate into the chamber of the machine and deposit a buffer layer (AlN layer) on the surface of the substrate using PVD method;

[0071] S2. A 3D nucleation layer (GaN layer) is deposited on the buffer layer by MOCVD deposition, maintaining a growth temperature of 1000°C, a reaction chamber pressure of 200 Torr, and a V / III ratio of 900;

[0072] S3. Growing a 2D fill layer (GaN layer) on the 3D nucleation layer by MOCVD deposition, maintaining a growth temperature of 1110°C, a reaction chamber pressure of 200 Torr, and a V / III ratio of 1100;

[0073] S4. Depositing and growing an N-type layer (N-type GaN layer) on the 2D fill layer by MOCVD deposition;

[0074] S5. Depositing a transition layer (low-temperature N-type GaN) on the N-type layer by MOCVD deposition; the growth temperature is 850° C. and the growth pressure is 200 Torr;

[0075] S6. Growing an active layer on the transition layer by MOCVD deposition; the active layer is composed of a quantum well layer InGaN;

[0076] S7. A P-type layer is deposited and grown on the active layer by an MOCVD deposition method at a temperature of 800° C. The P-type layer adopts GaN / ALGaN.

[0077] The following table compares the epitaxial structure data obtained from the existing solution and the solution of the present invention. The current epitaxial structure material quality is relatively good, and it is necessary to appropriately increase defects to brighten it, open V-Pits, and introduce Si to reduce voltage. [002HW is generally a defect from the substrate, while 102HW is a defect from subsequent epitaxial growth (representing screw dislocations and some vertical interfaces).] Larger values indicate more defects.

[0078] 002HW 102HW Chip Lop(mW) Chip vf1 ESD Old plan 115.6 147.3 178.3 3.132 99.3 Example 1 120.3 155.4 179.1 3.124 99.5

[0079] As can be seen from the table above, as 002 / 102HW becomes larger, defects increase. By increasing Si in the 3D layer to improve 002 / 102HW and appropriately increasing the defect density (this helps to open V-Pits in the transition layer, because V-Pits are opened based on the defects in the underlying layer), and gradually increasing the Si in the 2D layer by a small amount, current expansion can be enhanced, brightness can be increased, voltage can be reduced, and ESD effects can be improved.

[0080] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present invention (including the claims) is limited to these examples. Within the scope of the present invention, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity.

[0081] The present invention is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An epitaxial structure of a light-emitting diode, comprising a substrate, characterized in that: The epitaxial structure also includes a buffer layer, a 3D nucleation layer, a 2D leveling layer, an N-type layer, a transition layer, an active layer and a P-type layer sequentially arranged on the substrate. The 3D nucleation layer and the 2D leveling layer are both n-type doped, and the concentration of n-type doping in the 3D nucleation layer is higher than the n-type doping in the 2D leveling layer; the n-type doping element includes Si, the concentration of Si doping in the 3D nucleation layer is greater than 5E18 / cm3, the concentration of Si doping in the 2D leveling layer is 5E17~E19 / cm3, and the concentration of Si doping in the N-type layer is greater than 2E19 / cm3. A plurality of spaced-apart protrusions are provided on the substrate, and the buffer layer and the 3D nucleation layer are sequentially arranged from bottom to top in the gap space between adjacent protrusions, and the buffer layer is attached to the outer wall of the protrusion.

2. The epitaxial structure of the light emitting diode according to claim 1, characterized in that: The 3D nucleation layer and the 2D filling layer are both n-type Si-doped GaN layers.

3. The epitaxial structure of the light emitting diode according to claim 1, characterized in that: At least one of the 3D nucleation layer, the 2D filling layer, and the N-type layer is a gradient layer with a gradual Si concentration or a stable layer with a stable Si concentration.

4. The epitaxial structure of the light emitting diode according to claim 3, characterized in that: Among the 3D nucleation layer, the 2D filling layer, and the N-type layer, two layers are gradient layers and one layer is a stable layer; or two layers are stable layers and one layer is a gradient layer.

5. The epitaxial structure of the light emitting diode according to claim 1, characterized in that: The transition layer is an n-type doped Si transition layer, the doped Si concentration is 5E17-5E19 / cm3, and the C concentration is less than 1E18 / cm3.

6. The epitaxial structure of the light emitting diode according to claim 5, characterized in that: The C concentration is 1E17~1E18 / cm3.

7. The epitaxial structure of a light emitting diode according to claim 1, characterized in that: The substrate is made of sapphire, silicon carbide, silicon or zinc oxide.

8. The epitaxial structure of a light emitting diode according to claim 1, characterized in that: The lower part of the protrusion is made of one of sapphire, silicon carbide, silicon or zinc oxide, and the upper part of the protrusion is made of one or more of silicon dioxide, silicon nitride, zinc oxide, silicon, silicon carbide, gallium arsenide, titanium pentoxide and titanium dioxide.

9. The method for preparing an epitaxial structure of a light emitting diode according to any one of claims 1 to 8, characterized in that: The steps include: S1. Place the substrate into the chamber of the machine and deposit a buffer layer on the surface of the substrate using PVD or MOCVD. S2. Depositing and growing a 3D nucleation layer on the buffer layer, maintaining a growth temperature of 950-1080°C, a reaction chamber pressure of 100-300 Torr, and a V / III ratio of 800-1000; S3, depositing and growing a 2D filling layer on the 3D nucleation layer, maintaining a growth temperature of 1080-1140°C, a reaction chamber pressure of 100-300 Torr, and a V / III ratio of 1000-1200; S4, depositing and growing an N-type layer on the 2D filling layer; S5, depositing a growth transition layer on the N-type layer; S6. depositing and growing an active layer on the transition layer; S7. Deposit and grow a P-type layer on the active layer.

Images