Rotary variable differential transformer signal decoding method, apparatus, device, and medium

Abstract

The application relates to the field of new energy automobile control, and discloses a resolver signal decoding method, a resolver signal decoding device, a resolver signal decoding equipment and a medium, the device comprises a first processing core and a second processing core, the method comprises the following steps: a resolver signal of a resolver is acquired through the second processing core, the resolver signal is decoded and calculated, and decoding information is obtained; and the first processing core carries out current closed-loop control on a motor according to the decoding information. According to the application, the second processing core assists in calculation to realize a decoding scheme to determine decoding information, and the first processing core carries out current closed-loop control based on a decoding angle in the decoding information, so that a soft decoding scheme based on dual-core communication interaction is realized, high costs caused by a hard decoding chip are saved, decoding difficulty is reduced, and the soft decoding function is freed from the dependence on a DSADC module.

Description

Technical Field

[0001] This invention relates to the field of new energy vehicle control, and in particular to a method, apparatus, device, and medium for decoding resolver signals. Background Technology

[0002] In the process of motor control of new energy vehicles, it is necessary to acquire motor position signals in real time. The main technology for acquiring motor position signals is to install a resolver on the motor shaft to collect resolver signals. By decoding and calculating the resolver signals, the current resolver position in the current motor can be determined, and the coaxial motor position signal corresponding to the resolver position can be determined, thereby realizing motor control of the vehicle.

[0003] Existing decoding technologies for resolver signals include two main approaches: hardware decoding and software decoding. Hardware decoding requires the purchase of additional hardware decoding chips, resulting in high costs. Furthermore, the new energy vehicle industry has stringent requirements for chip functional safety, and chip shortages or quality issues can lead to time-consuming and labor-intensive chip replacement processes, extending the development cycle and increasing costs. While software decoding effectively alleviates the high costs and long development cycles associated with hardware decoding, it relies heavily on a main control chip with an integrated DSADC module, requiring extensive decoding algorithm calculations. This reliance on a DSADC-integrated main control chip for decoding calculations makes existing software decoding complex, costly to integrate, and subject to numerous limitations, hindering widespread application and limiting the further development of current electric drive system control performance. Summary of the Invention

[0004] The main objective of this invention is to provide a method, apparatus, device, and medium for decoding resolver signals, aiming to eliminate the dependence of software decoding schemes on DSADC modules and reduce the difficulty of decoding schemes.

[0005] To achieve the above objectives, the present invention also provides a method for decoding resolver signals, applied to a decoding device, the device comprising a first processing core and a second processing core, including:

[0006] The second processing core obtains the resolver recovery signal of the resolver and performs decoding calculations on the resolver recovery signal to obtain decoded information.

[0007] The first processing core performs current closed-loop control on the motor based on the decoded information.

[0008] Optionally, the step of obtaining the resolver recovery signal of the resolver through the second processing core and performing decoding calculations on the resolver recovery signal to obtain decoded information includes:

[0009] The second processing core generates an excitation modulation signal;

[0010] Based on the excitation modulation signal, the sine and cosine winding signals of the resolver are sampled, and phase delay compensation is performed on the sampled transceiver signals to determine the corresponding resolver recovery signal.

[0011] Based on the preset phase of the emitted signal, the resolver recovery signal is periodically flipped and integrated to determine the corresponding sine and cosine envelopes.

[0012] The sine and cosine envelopes are demodulated to obtain the corresponding decoding information, wherein the decoding information includes at least the decoding angle and the rotation speed.

[0013] Optionally, after the step of decoding the resolver recovery signal to obtain decoded information, the method further includes:

[0014] The first processing core monitors the heartbeat of the second processing core, obtains the heartbeat variable of the second processing core, and determines whether the second processing core is malfunctioning based on whether the heartbeat variable is updated.

[0015] If the second processor has a heartbeat abnormality, the decoded information will be marked as invalid.

[0016] Optionally, the step of the first processing core performing current closed-loop control on the motor based on the decoded information includes:

[0017] If the second processor does not have a heartbeat abnormality, the decoded information is transmitted to the first processing core;

[0018] The first processing core performs angle compensation on the decoding angle in the decoding information based on the decoding timestamp in the decoding information and the current timestamp of the first processing core, and obtains the compensated decoding angle.

[0019] The first processing core performs closed-loop current control on the motor based on the compensated decoding angle.

[0020] Optionally, before the step of the first processing core performing current closed-loop control on the motor based on the decoded information, the method further includes:

[0021] The fault diagnosis threshold is obtained from the first processing core through the second processing core;

[0022] Based on the decoded information and the fault diagnosis threshold, it is determined whether the motor has a resolver fault;

[0023] If present, a fault flag is determined based on the decoded information, and the fault flag is input into the first processing core.

[0024] Optionally, before the step of transmitting the decoded information to the first processing core, the method further includes:

[0025] The second processor accesses a preset counter CTR to obtain the decoding timestamp of the second processing core decoding the resolver recovery signal, records the decoding timestamp, and determines the corresponding decoding information.

[0026] Optionally, the first processing core and the second processing core include: a first transmission channel and a second transmission channel, and the step of the first processing core and the second processing core interacting with each other based on the first transmission channel and the second transmission channel includes:

[0027] When the first processing core performs a write operation to the second processing core through the first transmission channel, the permission for the second processing core to perform a read operation to the first processing core through the first transmission channel is disabled.

[0028] When the first processing core performs a write operation to the second processing core through the first transmission channel, permission is granted for the second processing core to perform a read operation to the first processing core through the second transmission channel;

[0029] When the first processing core performs a write operation to the second processing core through the second transmission channel, the permission for the second processing core to perform a read operation to the first processing core through the second transmission channel is disabled.

[0030] When the first processing core performs a write operation to the second processing core through the second transmission channel, permission is granted for the second processing core to perform a read operation to the first processing core through the first transmission channel;

[0031] When the second processing core performs a write operation to the first processing core through the first transmission channel, the permission for the first processing core to perform a read operation to the second processing core through the first transmission channel is disabled.

[0032] When the second processing core performs a write operation to the first processing core through the first transmission channel, permission is granted for the first processing core to perform a read operation to the second processing core through the second transmission channel;

[0033] When the second processing core performs a write operation to the first processing core through the second transmission channel, the permission for the first processing core to perform a read operation to the second processing core through the second transmission channel is disabled.

[0034] When the second processing core performs a write operation to the first processing core through the second transmission channel, permission is granted for the first processing core to perform a read operation to the second processing core through the first transmission channel.

[0035] To achieve the above objectives, the present invention also provides a decoding device, the decoding device comprising:

[0036] The decoding module is used to obtain the resolver recovery signal of the resolver through the second processing core, and to perform decoding calculations on the resolver recovery signal to obtain decoding information;

[0037] The control module is used by the first processing core to perform closed-loop current control on the motor based on the decoded information.

[0038] Each functional module of the decoding device of the present invention implements the steps of the resolver signal decoding method described above during operation.

[0039] To achieve the above objectives, the present invention also provides an apparatus comprising: a memory, a processor, and a decoding program stored in the memory and executable on the processor, wherein the decoding program, when executed by the processor, implements the steps of the resolver signal decoding method as described above.

[0040] To achieve the above objectives, the present invention also proposes a computer-readable storage medium storing a decoding program, which, when executed by a processor, implements the steps of the resolver signal decoding method described above.

[0041] This invention provides a method, apparatus, device, and medium for decoding resolver signals. The method is applied to a decoding apparatus, which includes a first processing core and a second processing core. The method includes: acquiring a resolver recovery signal from a resolver through the second processing core, and performing decoding calculations on the resolver recovery signal to obtain decoding information; the first processing core performing current closed-loop control on a motor based on the decoding information.

[0042] Compared to existing hardware and software decoding schemes that perform decoding calculations on resolver signals, this scheme uses a second processing core to assist in the calculation to achieve decoding, and the first processing core performs current closed-loop control based on the decoded information to realize a software decoding scheme based on dual-core communication interaction. This scheme replaces the existing hardware decoding scheme, eliminates the use of a hardware decoding chip, saves the high cost associated with hardware decoding chips, enhances product competitiveness, and reduces development cycle and development costs caused by hardware decoding chip shortages. In addition, by using dual cores to assist in the decoding calculation, the limitations of decoding usage are reduced, the speed and flexibility of software development are improved, the decoding difficulty is reduced, and the software decoding function is freed from dependence on the DSADC module. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the hardware operating environment involved in the embodiments of the present invention;

[0044] Figure 2 This is a flowchart illustrating the first embodiment of the resolver signal decoding method of the present invention;

[0045] Figure 3 This is a schematic diagram of a module in an exemplary embodiment of the resolver signal decoding method of the present invention;

[0046] Figure 4 This is a schematic diagram of a 10kHz excitation modulation signal emitted by the discrete resolver signal in the first embodiment of the resolver signal decoding method of the present invention.

[0047] Figure 5 This is a schematic diagram of the resolver recovery signal involved in the first embodiment of the resolver signal decoding method of the present invention;

[0048] Figure 6 This is a schematic diagram illustrating the specific process of interrupted sampling involved in the resolver signal decoding method of the present invention;

[0049] Figure 7 This is a schematic diagram of the envelope calculation process involved in the resolver signal decoding method of the present invention;

[0050] Figure 8 This is a schematic diagram illustrating the calculation process of the decoding angle and rotation speed involved in the resolver signal decoding method of the present invention;

[0051] Figure 9 This is a schematic diagram of the specific process for heartbeat monitoring in the second embodiment of the resolver signal decoding method of the present invention;

[0052] Figure 10 This is an exemplary flowchart illustrating the heartbeat monitoring process in the second embodiment of the resolver signal decoding method of the present invention.

[0053] Figure 11 This is a schematic diagram of the specific process for angle compensation in the second embodiment of the resolver signal decoding method of the present invention;

[0054] Figure 12 This is an exemplary detailed flowchart of angle compensation in the second embodiment of the resolver signal decoding method of the present invention;

[0055] Figure 13 This is a schematic diagram of the specific process for fault diagnosis in the second embodiment of the resolver signal decoding method of the present invention;

[0056] Figure 14 This is a schematic diagram illustrating an exemplary data transmission process of the first processing core in the third embodiment of the resolver signal decoding method of the present invention.

[0057] Figure 15 This is a schematic diagram illustrating an exemplary data transmission process of the second processing core in the third embodiment of the resolver signal decoding method of the present invention;

[0058] Figure 16 This is a schematic diagram of an exemplary data transmission method in the fourth embodiment of the resolver signal decoding method of the present invention;

[0059] Figure 17 This is a schematic diagram of the functional modules of the decoding device involved in the resolver signal decoding method of the present invention.

[0060] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0061] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0062] The main solution of this invention is: to install a resolver on the motor shaft, to interrupt and collect the resolver recovery signal through a second processing core, to decode the resolver recovery signal, to determine the decoding angle corresponding to the resolver recovery signal, and to control the motor current based on the decoding angle.

[0063] Currently, there are two main methods for decoding and calculating resolver signals: 1. Hardware decoding scheme: The resolver decoding chip sends a high-frequency sinusoidal excitation signal to the EXC winding of the resolver, and at the same time, the hardware decoding chip receives the sine and cosine winding signals to complete the motor angle decoding calculation. Then, the motor angle information is sent to the main control MCU chip through SPI communication to realize the control of the motor; 2. Software decoding scheme: The DSADC module is integrated into the MCU main control chip. DSADC is a functional module suitable for software decoding. The software decoding of the resolver angle is realized through the relevant registers configured in each part.

[0064] The existing decoding methods described above have the following drawbacks:

[0065] 1. Hardware decoding solutions require the purchase of a large number of high-performance, high-precision decoding chips, resulting in high hardware costs;

[0066] 2. The decoding chip is subjected to harsh operating conditions and has a high failure rate, which makes chip replacement time-consuming and labor-intensive, increases the R&D cycle and procurement costs, and results in high product costs.

[0067] 3. In software decoding schemes, the accuracy and bandwidth of software decoding heavily depend on the performance of the integrated DSADC module itself, which imposes many limitations and restricts the application scope of software decoding.

[0068] Neither of the two solutions can perfectly solve the problems of high cost and numerous limitations.

[0069] This invention provides a method, apparatus, device, and medium for decoding resolver signals. This solution implements software decoding through a second processing core and performs current closed-loop control based on the decoded information using a first processing core, achieving a software decoding scheme based on dual-core communication interaction. This solution replaces existing hardware decoding schemes, eliminating the use of hardware decoding chips, saving the high costs associated with them, enhancing product competitiveness, and reducing development cycles and costs caused by hardware decoding chip shortages. Furthermore, this solution uses dual cores to assist in decoding calculations, reducing limitations on decoding usage, improving the speed and flexibility of software development, and eliminating the dependence of software decoding functions on the DSADC module.

[0070] Specifically, refer to Figure 1 , Figure 1 This is a schematic diagram of the device structure of the hardware operating environment involved in the embodiments of the present invention. For example... Figure 1 As shown, the device may include: a processor 1001, such as a CPU; a network interface 1004; a user interface 1003; a memory 1005; and a communication bus 1002. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be high-speed RAM or stable non-volatile memory, such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0071] like Figure 1 As shown, the memory 1005, as a computer storage medium, may include an operating system, a network communication module, a user interface module, and a decoding program. The operating system is a program that manages and controls the device's hardware and software resources, supporting the operation of the decoding program and other software or programs. The network communication module manages and controls the network interface 1002. The user interface 1003 is mainly used for data communication with clients. The network interface 1004 is mainly used for establishing communication connections with servers. The processor 1001 can be used to call the decoding program stored in the memory 1005.

[0072] Reference Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the resolver signal decoding method of the present invention.

[0073] This embodiment provides an example of a resolver signal decoding method. It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0074] In this embodiment, the resolver signal decoding method is applied to a decoding device, including:

[0075] Step S10: Obtain the resolver recovery signal of the resolver through the second processing core, and perform decoding calculation on the resolver recovery signal to obtain decoding information;

[0076] It needs to be explained in detail that, in this embodiment, the second processing core independently performs high-frequency data acquisition and demodulation, acquiring and calculating the resolver information used for decoding. The second processing core acquires the resolver recovery signal from the resolver mounted on the motor shaft, and decodes the acquired resolver recovery signal to determine the current decoding angle and rotation speed of the motor shaft (motor).

[0077] Reference Figure 3 As a specific exemplary embodiment, taking the DSP28377 chip as an example, the chip includes a main core C28 and an auxiliary computing core CLA. The auxiliary computing core CLA executes the acquisition and decoding algorithms independently of the main core C28.

[0078] Further, the step of obtaining the resolver recovery signal of the resolver through the second processing core and decoding the resolver recovery signal to obtain decoded information includes:

[0079] The second processing core generates an excitation modulation signal;

[0080] Based on the excitation modulation signal, the sine and cosine winding signals of the resolver are sampled, and phase delay compensation is performed on the sampled transceiver signals to determine the corresponding resolver recovery signal.

[0081] Based on the preset phase of the emitted signal, the resolver recovery signal is periodically flipped and integrated to determine the corresponding sine and cosine envelopes.

[0082] The sine and cosine envelopes are demodulated to obtain the corresponding decoding information, wherein the decoding information includes at least the decoding angle and the rotation speed.

[0083] It needs to be explained in detail that, in this embodiment, the auxiliary computing core CLA executes the acquisition algorithm independently of the main core C28. This includes sampling and recovering sine and cosine signals from the rotary transformer mounted on the motor shaft. Specifically, for example, after generating a PWM wave with a 160kHz carrier frequency, the signal is filtered by the decoding circuit to generate a 10kHz excitation modulation signal. The 10kHz excitation modulation signal is referenced to... Figure 4 The excitation modulation signal is then sent to the resolver excitation EXC winding, and a 160k interrupt function is used for sampling and recovery. The sampled resolver recovery signal is then determined, and the resolver recovery signal is referenced. Figure 5 .

[0084] Furthermore, in this embodiment, since the excitation frequency of the dual-core soft decoding scheme is 160kHz, while the excitation modulation signal frequency and the decoding calculation frequency are both 10kHz, a scheme of 160kHz interrupt sampling and 10kHz interrupt decoding is selected. However, there is a potential interrupt priority conflict between the 160kHz interrupt sampling signal and the 10kHz soft decoding interrupt, which could lead to interrupt preemption and decoding timing logic anomalies. Therefore, this embodiment chooses to complete signal sampling and decoding within the 160kHz interrupt function, without adding an additional 10kHz interrupt, to perform interrupt sampling and corresponding decoding of the resolver recovery signal. (Refer to...) Figure 6 Specifically, in this embodiment, the software decoding code is decomposed into 160k tasks, each task having a time slice of 6.25us, and 16 task time slices are used to complete 10k (100us cycle) of software decoding data processing.

[0085] Furthermore, the sampled resolver recovery signal is inverted and integrated to calculate the corresponding sine and cosine envelopes, referring to... Figure 7 , Figure 7 This is a schematic diagram for calculating the sine and cosine envelopes. The motor position and speed signals are then observed by decoding the envelopes, and the corresponding decoding angles and rotational speeds are further confirmed. (Refer to...) Figure 8 , Figure 8 This describes the calculation process for decoding angle and rotation speed.

[0086] Step S20: The first processing core performs current closed-loop control on the motor based on the decoded information.

[0087] It should be noted that in this embodiment, the first processing core calculates the decoding angle from the decoding information obtained by the second processing core, and based on this decoding angle, completes the closed-loop current control of the motor.

[0088] Specifically, refer to Figure 3As a specific exemplary embodiment, taking the DSP28377 chip as an example, the chip includes a main core C28 and an auxiliary computing core CLA (control law accelerator). The main core C28 executes the motor control algorithm independently of the auxiliary computing core CLA. The main core C28 receives the decoded angle calculated by the auxiliary computing core CLA and realizes closed-loop current control of the current motor based on the decoded angle.

[0089] This embodiment independently completes high-frequency data acquisition and demodulation based on the second processing core, reducing the burden on the first processing core connected to the second processing core, making full use of on-chip resources, and realizing data transmission through dual-core data interaction. It also increases the way to implement software decoding, reduces the software decoding scheme's reliance on a single integrated module, and reduces the restrictions on the control of the electric drive system.

[0090] Furthermore, based on the first embodiment of the resolver signal decoding method of the present invention described above, a second embodiment of the resolver signal decoding method of the present invention is proposed.

[0091] In this embodiment, after the step of "decoding and calculating the resolver recovery signal to obtain decoded information", the resolver signal decoding method further includes: a scheme for heartbeat monitoring by verifying the first processing with a second processing step, referring to... Figure 9 Specifically, it includes:

[0092] Step S101: The first processing core monitors the heartbeat of the second processing core, obtains the heartbeat variable of the second processing core, and determines whether the second processing core is running abnormally based on whether the heartbeat variable is updated.

[0093] Step S102: If the second processor has a heartbeat abnormality, the decoded information is marked as invalid information.

[0094] It should be noted that in this embodiment, a heartbeat variable is added during the dual-core data interaction process to monitor for errors that occur during signal sampling and angle decoding of the second processing core. Specifically, during the operation of the second processing core, the heartbeat variable is changed periodically, while the first processing core monitors the heartbeat variable that is periodically updated by the second processing core.

[0095] Reference Figure 10 , Figure 10The following is an exemplary flowchart of heartbeat monitoring for dual-core processors. Specifically, before the first processing core monitors the heartbeat of the second processing core, the second processing core CLA periodically updates the heartbeat CNT count. The first processing core C28 monitors the heartbeat count of the second processing core. If the real-time heartbeat update count of the second processing core is abnormal, the heartbeat of the second processing core CLA is abnormal, and an abnormal signal is transmitted to the first processing core C28, controlling the first processing core C28 to enter a safe state.

[0096] Furthermore, prior to the step of transmitting the decoded information to the first processing core, the method further includes:

[0097] The second processor accesses a preset counter CTR to obtain the decoding timestamp of the second processing core decoding the resolver recovery signal, records the decoding timestamp, and determines the corresponding decoding information.

[0098] In this embodiment, the second processing core CLA can access the PWM module but not the CpuTimer module. Therefore, in this embodiment, the second processing core CLA determines the timestamp reference by using the CTR counter of the PWM module and configures the PWM module frequency, which serves as the timestamp reference, to a 50MHz incrementing counting mode. Further, when the second processing core CLA decodes the resolver recovery information, it acquires the corresponding decoding timestamp and records it, transmitting it to the first processing core C28 as part of the resolver information acquired by the second processing core CLA.

[0099] Furthermore, the resolver signal decoding method also includes: a scheme for angle compensation of the decoding angle through a second processing core, referring to... Figure 11 Specifically, it includes:

[0100] Step S103: If the second processor does not have a heartbeat abnormality, then the decoding information is transmitted to the first processing core;

[0101] Step S104: The first processing core performs angle compensation on the decoding angle in the decoding information based on the decoding timestamp in the decoding information and the current timestamp of the first processing core, and obtains the compensated decoding angle.

[0102] Step S105: The first processing core performs current closed-loop control on the motor based on the compensated decoding angle.

[0103] It needs to be explained in detail that, in this embodiment, since the first processing core C28 and the second processing core CLA operate independently, the decoding angle calculated by the second processing core CLA and the decoding angle used by the first processing core C28 for motor control are independent of each other. That is, the calculation time point and the usage time point of the decoding angle are separate. Therefore, the decoding angle and the usage angle are relatively independent in time. In order to avoid the problem of misalignment of the angle in time due to the independent operation of the first processing core C28 and the second processing core CLA, it is necessary to perform angle compensation on the decoding angle of the first processing core C28 for motor control. The compensation factor is calculated based on the decoding timestamp calculated by the second processing core CLA at the decoding time and the current timestamp of the first processing core C28 for motor control. The difference between the decoding timestamp and the current timestamp is determined. Based on this difference, the angle compensation calculation is performed on the decoding angle after decoding by the second processing core CLA to determine the compensated decoding angle. The first processing core C28 performs current closed-loop control on the motor according to the above-mentioned compensated decoding angle.

[0104] Specifically, refer to Figure 12 When the second processing core CLA transmits the decoding angle to the first processing core C28, it also transmits the corresponding decoding time (i.e., timestamp) to the first processing core C28. After receiving the first decoding angle and decoding time, the first processing core C28 compensates for the angle based on the time difference between the current time and the decoding time of the first decoding angle, and obtains the compensated second decoding angle.

[0105] Furthermore, the resolver signal decoding method also includes: a scheme for fault diagnosis of the current signal decoding through a second processing check, referring to... Figure 13 Specifically, it includes:

[0106] Step S106: Obtain the fault diagnosis threshold from the first processing core through the second processing core;

[0107] Step S107: Based on the decoded information and the fault diagnosis threshold, determine whether the motor has a resolver fault;

[0108] Step S108: If the fault flag exists, determine the fault flag bit based on the decoded information and input the fault flag bit into the first processing core.

[0109] It should be noted that, in this embodiment, the first processing core sends the resolver decoding fault judgment information, such as the zero drift threshold of the recovered signal and the abnormal amplitude threshold of the recovered signal, to the second processing core. The second processing core then completes the fault diagnosis based on the aforementioned resolver decoding fault judgment information, determines the corresponding resolver fault information, and sends the resolver fault information to the first processing core to complete the fault action processing, so as to ensure that the electronic control system can enter a safe state when the resolver decoding is abnormal.

[0110] Furthermore, the control algorithm in the first processing core performs corresponding fault handling based on the resolver fault information. If the decoding core of the current resolver decoding malfunctions and an error occurs in the decoding process, a corresponding safety status signal is generated. Based on this safety status signal, the second processing core is controlled to enter a safety state, and the angle signal obtained from the second processing core is also marked as an invalid signal.

[0111] Reference Figure 14 , Figure 14 This is a schematic diagram illustrating the data processing flow of the first processing core as an example. Specifically, the first processing core C28 triggers a PWM interrupt to run the second processing core CLA for software decoding. It transmits the fault diagnosis threshold (fault threshold initialization information) to the second processing core CLA and simultaneously monitors the heartbeat variable of the second processing core CLA. Based on whether the heartbeat variable of the second processing core CLA is updated, it determines whether the second processing core CLA has an anomaly. If an anomaly is found, the first processing core is controlled to enter a safe state and a fault is reported. If no anomaly is found, the first processing core receives the decoding information such as the decoding angle, timestamp, and fault information transmitted by the second processing core CLA, and determines whether there is a resolver anomaly. If not, the decoding angle is compensated according to the timestamp and sent to the current loop for motor vector control.

[0112] Reference Figure 15 , Figure 15 This is a schematic diagram illustrating the data processing flow of an exemplary second processing core. Specifically, the second processing core CLA obtains initialization information and diagnostic fault thresholds from the first processing core C28. The second processing core CLA generates an SPWM excitation signal and performs heartbeat updates. The second processing core CLA terminal receives sine and cosine signals and performs zero-drift processing. It calculates the decoded angle and records the timestamp. The observer detects the motor angle and motor speed and determines whether a resolver fault exists. If a fault exists, the estimated speed and fault flag are sent to the first processing core C28 to request a shutdown. If no fault exists, the angle and speed are sent to the first processing core C28 for motor vector control.

[0113] This invention uses a second processing core (CLA) to assist in software decoding, while the first processing core (C28) uses the decoding angle for motor control. This does not rely on the DSADC module, reducing the burden on the main core (C28), making full use of on-chip resources, and using the second processing core (CLA) to assist in fault diagnosis, reducing the computational task of the main core and lowering the limitations of the decoding work.

[0114] Furthermore, based on the first and second embodiments of the resolver signal decoding method of the present invention described above, a third embodiment of the resolver signal decoding method of the present invention is proposed.

[0115] This embodiment includes a first transmission channel and a second transmission channel between the first processing core and the second processing core. Based on the data interaction between the first processing core and the second processing core using the first transmission channel and the second transmission channel, the soft decoding method also includes a scheme for mutual exclusion of data interaction channels.

[0116] It needs to be explained in detail that this embodiment is applied to a dual-core software decoding architecture. The first processing core C28 and the second processing core CLA in this architecture need to exchange and transmit data. In this embodiment, the data exchange channel between the first processing core C28 and the second processing core CLA includes a first transmission channel and a second transmission channel. The specific steps for data exchange between the first transmission channel and the second transmission channel include:

[0117] When the first processing core performs a write operation to the second processing core through the first transmission channel, the permission for the second processing core to perform a read operation to the first processing core through the first transmission channel is disabled.

[0118] When the first processing core performs a write operation to the second processing core through the first transmission channel, permission is granted for the second processing core to perform a read operation to the first processing core through the second transmission channel;

[0119] When the first processing core performs a write operation to the second processing core through the second transmission channel, the permission for the second processing core to perform a read operation to the first processing core through the second transmission channel is disabled.

[0120] When the first processing core performs a write operation to the second processing core through the second transmission channel, permission is granted for the second processing core to perform a read operation to the first processing core through the first transmission channel;

[0121] When the second processing core performs a write operation to the first processing core through the first transmission channel, the permission for the first processing core to perform a read operation to the second processing core through the first transmission channel is disabled.

[0122] When the second processing core performs a write operation to the first processing core through the first transmission channel, permission is granted for the first processing core to perform a read operation to the second processing core through the second transmission channel;

[0123] When the second processing core performs a write operation to the first processing core through the second transmission channel, the permission for the first processing core to perform a read operation to the second processing core through the second transmission channel is disabled.

[0124] When the second processing core performs a write operation to the first processing core through the second transmission channel, permission is granted for the first processing core to perform a read operation to the second processing core through the first transmission channel.

[0125] It needs to be explained in detail that, in this embodiment, the DMA and the second processing core CLA of the DSP28377 chip, as an exemplary embodiment, do not share a RAM area. Therefore, the DMA cannot directly transfer data to the second processing core CLA, but needs to be relayed through the first processing core C28 to achieve data transfer. The peripheral access restrictions of the running chip objectively force the dual-core decoding scheme to choose between the second processing core CLA and the DMA. However, if the DMA is chosen for data transfer, the second processing core CLA cannot access peripherals, which increases the difficulty of program upgrades when peripheral access is required. Therefore, in this embodiment, the second processing core CLA is chosen to independently complete high-frequency data acquisition and demodulation to achieve software decoding. After the second processing core CLA completes the corresponding data acquisition and demodulation and achieves software decoding, the decoded information is transmitted to the first processing core C28 through the data transmission channel.

[0126] Furthermore, since the first processing core C28 and the second processing core CLA cannot directly use DMA for data transfer, in this embodiment, the first processing core C28 and the second processing core CLA adopt a dual-channel data interaction method to realize data interaction and data control between the two cores during data transfer. That is, there is a first transmission channel and a second transmission channel between the first processing core C28 and the second processing core CLA to realize data interaction between the two channels.

[0127] In this embodiment, when the first processing core C28 transmits decoded information data to the second processing core CLA through the first transmission channel, the second processing core CLA cannot receive the decoded data through the first transmission channel because simultaneous reading and writing on the same transmission channel would cause data anomalies. Therefore, when the first processing core C28 transmits decoded information data to the second processing core CLA through the first transmission channel, the second processing core CLA can only read the decoded information data through the second transmission channel.

[0128] Furthermore, when the first processing core C28 transmits the decoded information data to the second processing core CLA through the second transmission channel, the second processing core CLA can only read the decoded information data through the first transmission channel.

[0129] Specifically, refer to Figure 16 During data writing to channel A, only read access to channel B is enabled, and vice versa. Channels A and B are written alternately and read in a complementary manner. This redundant data interaction avoids data transmission anomalies caused by simultaneous data operations on both cores. The dual-channel data interaction method increases the security of data transfer between the two cores, reduces the risk of data corruption or loss, and avoids data corruption caused by simultaneous read and write operations.

[0130] Furthermore, embodiments of the present invention also propose a decoding device, referring to... Figure 17 , Figure 17 The diagram below illustrates the functional modules of the decoding device of the present invention. The decoding device includes:

[0131] The decoding module 10 is used to obtain the resolver recovery signal of the resolver through the second processing core, and to perform decoding calculations on the resolver recovery signal to obtain decoding information;

[0132] Control module 20 is used by the first processing core to perform current closed-loop control on the motor based on the decoded information.

[0133] Furthermore, this embodiment of the invention also proposes an apparatus comprising a memory, a processor, and a decoding program stored in the memory and executable on the processor, wherein the decoding program, when executed by the processor, implements the steps of the resolver signal decoding method as described above.

[0134] The various embodiments of the decoding device and computer-readable storage medium of the present invention can be referred to the various embodiments of the resolver signal decoding method of the present invention, and will not be repeated here.

[0135] The specific embodiments of the computer program product of the present invention are basically the same as the embodiments of the above-described resolver signal decoding method, and will not be described in detail here.

[0136] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0137] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0138] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0139] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A method for decoding resolver signals, characterized in that, The method is applied to a decoding device, which includes a dual-core processor, comprising a first processing core and a second processing core, including: The second processing core obtains the resolver recovery signal of the resolver and performs decoding calculations on the resolver recovery signal to obtain decoded information. The first processing core monitors the heartbeat of the second processing core, obtains the heartbeat variable of the second processing core, and determines whether the second processing core is malfunctioning based on whether the heartbeat variable is updated. If the second processing core has an abnormal heartbeat, the decoded information is marked as invalid. The first processing core performs closed-loop current control on the motor based on the decoded information.

2. The resolver signal decoding method as described in claim 1, characterized in that, The step of acquiring the resolver recovery signal of the resolver through the second processing core and decoding the resolver recovery signal to obtain decoded information includes: The second processing core generates an excitation modulation signal; Based on the excitation modulation signal, the sine and cosine winding signals of the resolver are sampled, and phase delay compensation is performed on the sampled transceiver signals to determine the corresponding resolver recovery signal. Based on the preset phase of the emitted signal, the resolver recovery signal is periodically flipped and integrated to determine the corresponding sine and cosine envelopes. The sine and cosine envelopes are demodulated to obtain the corresponding decoding information, wherein the decoding information includes at least the decoding angle and the rotation speed.

3. The resolver signal decoding method as described in claim 1, characterized in that, The step of performing current closed-loop control of the motor by the first processing core based on the decoded information includes: If the second processing core does not have a heartbeat abnormality, the decoding information is transmitted to the first processing core; The first processing core performs angle compensation on the decoding angle in the decoding information based on the decoding timestamp in the decoding information and the current timestamp of the first processing core, and obtains the compensated decoding angle. The first processing core performs closed-loop current control on the motor based on the compensated decoding angle.

4. The resolver signal decoding method as described in claim 1, characterized in that, Before the step of performing current closed-loop control of the motor based on the decoded information by the first processing core, the method further includes: The fault diagnosis threshold is obtained from the first processing core through the second processing core; Based on the decoded information and the fault diagnosis threshold, it is determined whether the motor has a resolver fault; If present, a fault flag is determined based on the decoded information, and the fault flag is input into the first processing core.

5. The resolver signal decoding method as described in claim 3, characterized in that, Prior to the step of transmitting the decoded information to the first processing core, the method further includes: The second processing core accesses a preset counter CTR to obtain the decoding timestamp of the second processing core decoding the resolver recovery signal, records the decoding timestamp, and determines the corresponding decoding information.

6. The resolver signal decoding method according to any one of claims 1-5, characterized in that, The first processing core and the second processing core are connected by a first transmission channel and a second transmission channel. The steps for the first processing core and the second processing core to interact with each other based on the first transmission channel and the second transmission channel include: When the first processing core performs a write operation to the second processing core through the first transmission channel, the permission for the second processing core to perform a read operation to the first processing core through the first transmission channel is disabled. When the first processing core performs a write operation to the second processing core through the first transmission channel, permission is granted for the second processing core to perform a read operation to the first processing core through the second transmission channel; When the first processing core performs a write operation to the second processing core through the second transmission channel, the permission for the second processing core to perform a read operation to the first processing core through the second transmission channel is disabled. When the first processing core performs a write operation to the second processing core through the second transmission channel, permission is granted for the second processing core to perform a read operation to the first processing core through the first transmission channel; When the second processing core performs a write operation to the first processing core through the first transmission channel, the permission for the first processing core to perform a read operation to the second processing core through the first transmission channel is disabled. When the second processing core performs a write operation to the first processing core through the first transmission channel, permission is granted for the first processing core to perform a read operation to the second processing core through the second transmission channel; When the second processing core performs a write operation to the first processing core through the second transmission channel, the permission for the first processing core to perform a read operation to the second processing core through the second transmission channel is disabled. When the second processing core performs a write operation to the first processing core through the second transmission channel, permission is granted for the first processing core to perform a read operation to the second processing core through the first transmission channel.

7. A decoding device, characterized in that, The decoding device includes a dual-core processor, the dual-core processor including a first processing core and a second processing core, the decoding device comprising: The decoding module is used to obtain the resolver recovery signal of the resolver through the second processing core, and to perform decoding calculations on the resolver recovery signal to obtain decoding information; The control module is used to perform closed-loop current control of the motor based on the decoded information through the first processing core; After the step of decoding and calculating the resolver recovery signal to obtain the decoded information, the decoding device is further configured to: The first processing core monitors the heartbeat of the second processing core, obtains the heartbeat variable of the second processing core, and determines whether the second processing core is malfunctioning based on whether the heartbeat variable is updated. If the second processing core has a heartbeat abnormality, the decoded information is marked as invalid.

8. A device, characterized in that, The device includes a memory, a processor, and a decoding program stored in the memory and executable on the processor, wherein the decoding program, when executed by the processor, implements the steps of the resolver signal decoding method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a decoding program, which, when executed by a processor, implements the steps of the resolver signal decoding method as described in any one of claims 1 to 6.

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