Duty cycle correction circuit and memory device

Abstract

The application discloses a duty cycle correction circuit and a memory device. The duty cycle correction circuit comprises: a delay circuit configured to receive an input clock and output a delayed clock of the input clock; a sampling circuit connected with the delay circuit, configured to obtain a phase difference between the input clock and the delayed clock, and generate a first pulse width signal and a second pulse width signal according to the phase difference; a duty cycle detection circuit connected with the sampling circuit, configured to obtain a voltage on an integration capacitor in the duty cycle detection circuit; and a duty cycle adjustment circuit connected with the delay circuit and the duty cycle detection circuit, configured to compare the voltage on the integration capacitor with a reference voltage when the voltage on the integration capacitor is less than or equal to an absolute value of a difference between the reference voltage and a cumulative voltage difference, and adjust a time delay of the delay circuit based on a comparison result, so as to correct a duty cycle of an output clock corresponding to the input clock. In this way, the resolution and accuracy of the duty cycle correction circuit can be improved.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a duty cycle correction circuit and a memory device. Background Technology

[0002] With the widespread use of computers and various electronic devices, the demand for memory products (such as memory devices) is increasing. When the memory clock is disturbed, the duty cycle of the input clock will change significantly, and changes in the duty cycle of the memory input clock can easily lead to memory malfunction.

[0003] To address the issue of reducing duty cycle variation in memory input clocks, a duty cycle correction (DCC) circuit is typically used to adjust the duty cycle of the input clock.

[0004] In traditional DCC, to achieve higher resolution and accuracy, the integration module requires a large bias current and a small integration capacitor, while the comparator module requires a small current and a large capacitor to operate. Therefore, the resolution and accuracy of DCC are limited. Summary of the Invention

[0005] The main technical problem addressed by this application is to provide a duty cycle correction circuit and a storage device to improve the resolution and accuracy of the duty cycle correction circuit.

[0006] To solve the above-mentioned technical problems, this application adopts a technical solution as follows: providing a duty cycle correction circuit. The duty cycle correction circuit includes: a delay circuit for receiving an input clock and outputting a delayed clock of the input clock; a sampling circuit connected to the delay circuit for acquiring the phase difference between the input clock and the delayed clock, and generating a first pulse width signal and a second pulse width signal based on the phase difference; a duty cycle detection circuit connected to the sampling circuit for acquiring the voltage on the integrating capacitor within the duty cycle detection circuit; and a duty cycle adjustment circuit connected to both the delay circuit and the duty cycle detection circuit, for comparing the voltage of the integrating capacitor with the reference voltage when the voltage of the integrating capacitor is less than or equal to the absolute value of the difference between the reference voltage and the cumulative voltage difference, and adjusting the delay of the delay circuit based on the comparison result to correct the duty cycle of the output clock corresponding to the input clock.

[0007] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a storage device. The storage device includes the duty cycle correction circuit described above.

[0008] The beneficial effects of this application are as follows: Unlike existing technologies, this application uses a sampling circuit to acquire a first pulse width signal and a second pulse width signal that reflect the phase difference between the input clock and its delayed clock. It also acquires the voltage of the integrating capacitor through a duty cycle detection circuit. Furthermore, when the voltage of the integrating capacitor is less than or equal to the absolute value of the difference between the reference voltage and the cumulative voltage difference (the cumulative value of the difference between the discharge voltage of the integrating capacitor caused by the first pulse width signal and the charging voltage of the integrating capacitor caused by the second pulse width signal), the duty cycle adjustment circuit compares the voltage of the integrating capacitor with the reference voltage and adjusts the delay circuit accordingly. The delay is used to adjust the duty cycle of the output clock. Compared with the prior art, which uses the comparison of the voltages of two integrating capacitors to adjust the delay, this application compares the absolute value of the difference between the voltage of the integrating capacitor and the reference voltage and the cumulative voltage difference. That is, the voltage of the integrating capacitor and the reference voltage have a certain voltage threshold. Therefore, the voltage fluctuation range of the integrating capacitor in each cycle can be reduced, and the duty cycle detection circuit can use a larger current and a smaller capacitor to increase the resolution and accuracy. Therefore, this application can improve the resolution and accuracy of the duty cycle correction circuit. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of an embodiment of the duty cycle correction circuit of this application;

[0011] Figure 2 yes Figure 1 A schematic diagram of the circuit structure of the duty cycle detection circuit and duty cycle adjustment circuit in the duty cycle correction circuit of the embodiment;

[0012] Figure 3 yes Figure 1 A schematic diagram of the signal waveform of the duty cycle correction circuit in the embodiment;

[0013] Figure 4 This is a schematic diagram of another circuit structure of the duty cycle detection circuit and duty cycle adjustment circuit in another embodiment of the duty cycle correction circuit of this application;

[0014] Figure 5 This is a schematic diagram of another embodiment of the duty cycle correction circuit of this application;

[0015] Figure 6 This is a schematic diagram of the structure of an embodiment of the storage device of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] The terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly specified. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0018] This application first proposes a duty cycle correction circuit, such as Figures 1 to 3 The above, Figure 1 This is a schematic diagram of an embodiment of the duty cycle correction circuit of this application; Figure 2 yes Figure 1 A schematic diagram of the circuit structure of the duty cycle detection circuit and duty cycle adjustment circuit in the duty cycle correction circuit of the embodiment; Figure 3 yes Figure 1A schematic diagram of the signal waveform of the duty cycle correction circuit in this embodiment. The duty cycle correction circuit 10 in this embodiment includes: a delay circuit 110, a sampling circuit 120, a duty cycle detection circuit 130, and a duty cycle adjustment circuit 140; wherein, the delay circuit 110 is used to receive the input clock clk0 and output a delayed clock clk180 of the input clock clk0; the sampling circuit 120 is connected to the delay circuit 110 and is used to obtain the phase difference between the input clock clk0 and the delayed clock clk180, and generate a first pulse width signal clkr_p (i.e., clkr) and a second pulse width signal clkf_n (clkf_n is the inverse signal of clkf) based on the phase difference; the duty cycle detection circuit 130 is connected to the sampling circuit 120 and is used to obtain the phase difference of the duty cycle detection circuit 130. The voltage VX on the integrating capacitor C is 0. The duty cycle adjustment circuit 140 is connected to the delay circuit 110 and the duty cycle detection circuit 130 respectively. When the voltage VX on the integrating capacitor C is less than or equal to the absolute value of the difference between the reference voltage vref (i.e., Vref, the voltage at point Y) and the cumulative voltage difference VY, the voltage VX on the integrating capacitor C is compared with the reference voltage vref, and the delay of the delay circuit 110 is adjusted based on the comparison result to correct the duty cycle of the output clock corresponding to the input clock clk0. The cumulative voltage difference VY is the cumulative value of the difference between the discharge voltage of the integrating capacitor C by the first pulse width signal clkr_p and the charging voltage of the integrating capacitor C by the second pulse width signal clkf_n.

[0019] Unlike existing technologies, this embodiment uses a sampling circuit 120 to acquire a first pulse width signal clkr_p and a second pulse width signal clkf_n that reflect the phase difference between the input clock clk0 and its delayed clock clk180. The voltage of the integrating capacitor C is acquired through a duty cycle detection circuit 130. Furthermore, when the voltage VX of the integrating capacitor C is less than or equal to the absolute value of the difference between the reference voltage vref and the cumulative voltage difference VY, the duty cycle adjustment circuit 140 compares the voltage VX of the integrating capacitor C with the reference voltage vref. Based on the comparison result, the delay of the delay circuit 110 is adjusted to achieve the desired output clock duty cycle. The duty cycle is adjusted by comparing the voltages of two integrating capacitors to adjust the time delay in the prior art. This embodiment compares the absolute value of the difference between the voltage VX of the integrating capacitor C and the reference voltage vref and the cumulative voltage difference VY. That is, there is a certain voltage threshold between the voltage VX of the integrating capacitor C and the reference voltage vref. Therefore, the fluctuation range of the voltage VX of the integrating capacitor C in each cycle can be reduced. This allows the duty cycle detection circuit 130 to use a larger current and a smaller capacitor to increase the resolution and accuracy. Therefore, the resolution and accuracy of the duty cycle correction circuit 10 can be improved.

[0020] Specifically, the delay circuit 110 in this embodiment can delay the input clock by 180° phase difference.

[0021] Specifically, sampling circuit 120 samples the rising edge of input clock clk0 and the subsequent rising edge of delayed clock clk180 adjacent to the rising edge, and uses the phase difference between the two as the pulse width 'a' of the first pulse width signal clkr_p. Sampling circuit 120 generates the first pulse width signal clkr_p using pulse width 'a'. Sampling circuit 120 also samples the rising edge of delayed clock clk180 and the subsequent rising edge of input clock clk0 adjacent to the rising edge, and uses the phase difference between the two as the pulse width 'b' of the second pulse width signal clkf_n. Sampling circuit 120 generates the second pulse width signal clkf_n using pulse width 'b'. In this embodiment, sampling circuit 120 can be a pulse generator.

[0022] The duty cycle detection circuit 130 in this embodiment is used to amplify the pulse width signal corresponding to the clock phase difference and convert the pulse width signal into a cumulative voltage difference VY.

[0023] Optionally, the duty cycle detection circuit 130 of this embodiment includes an integrating circuit 131. The first input terminal and the second input terminal of the integrating circuit 131 are respectively connected to the sampling circuit 120. The first input terminal of the integrating circuit 131 is connected to a first pulse width signal clkr_p for discharging the integrating capacitor C. The second input terminal of the integrating circuit 131 is connected to a second pulse width signal clkf_n for charging the integrating capacitor C.

[0024] As the above analysis shows, a change in the duty cycle of the output clock corresponding to the input clock clk0 will cause the phase difference between the input clock clk0 and the delayed clock clk180 to be greater than or less than 180°. This results in the pulse width 'a' of the first pulse width signal clkr_p being unequal to the pulse width 'b' of the second pulse width signal clkf_n. Consequently, the time for the first pulse width signal clkr_p to discharge the integrating capacitor C is different from the time for the second pulse width signal clkf_n to charge the integrating capacitor C. Since the same capacitor has the same charging and discharging speed, there will be a certain voltage difference after the integrating capacitor C completes one charge and discharge cycle. This voltage difference can reflect the change in the duty cycle of the output clock.

[0025] As the number of charge-discharge cycles of the integrating capacitor C increases, the voltage difference between charge and discharge will accumulate on the integrating capacitor C, i.e., the cumulative voltage difference VY.

[0026] Optionally, the duty cycle adjustment circuit 140 of this embodiment includes: a comparator circuit 141 and a logic control circuit 142; wherein, the first input terminal of the comparator circuit 141 is connected to one end of the integrating capacitor C, and the second input terminal of the comparator circuit 141 is connected to a reference voltage vref (i.e., Vref), used to generate a first adjustment signal when the voltage VX of the integrating capacitor C is less than or equal to the absolute value of the difference between the reference voltage vref and the cumulative voltage difference VY, and the voltage VX of the integrating capacitor C is less than the reference voltage vref, and when the voltage VX of the integrating capacitor C is less than or equal to the absolute value of the difference between the reference voltage vref and the cumulative voltage difference VY, and when the voltage VX of the integrating capacitor C is less than or equal to the reference voltage vref and the cumulative voltage difference VY, the first adjustment signal is generated. When the absolute value of the difference between the cumulative voltage difference VY and the voltage VX of the integrating capacitor C is greater than the reference voltage vref, a second adjustment signal is generated. The input terminal of the logic control circuit 142 is connected to the output terminal of the comparator circuit 141, and the output terminal of the logic control circuit 142 is connected to the delay circuit 110. It is used to generate a control code based on the cumulative voltage difference VY, the number of pulses corresponding to the cumulative voltage difference VY, and the first adjustment signal or the second adjustment signal, and adjust the time delay of the delay circuit 110 according to the control code. The time delay adjustment direction corresponding to the first adjustment signal is opposite to the time delay adjustment direction corresponding to the second adjustment signal.

[0027] As can be seen from the above analysis, the cumulative voltage difference VY between the first pulse width signal clkr_p and the second pulse width signal clkf_n, which have different pulse widths, on the charging and discharging of the integrating capacitor C can reflect the change in the duty cycle of the output clock; the cumulative voltage difference VY is related to the number of charging and discharging pulses.

[0028] Specifically, the logic control circuit 142 sets the accumulated voltage difference VY and its corresponding number of pulses ( Figure 3 By comparing the number of pulses (8) in the input clock, the voltage difference generated by the single charge and discharge of the integrating capacitor C can be obtained. This voltage difference is the difference between the pulse width a of the first pulse width signal clkr_p and the pulse width b of the second pulse width signal clkf_n. In other words, it is the difference between the pulse width between the rising edge of the input clock clk0 and the next rising edge of the delayed clock clk180 and the pulse width between the rising edge of the delayed clock clk180 and the next rising edge of the input clock clk0. The logic control circuit 142 can adjust the delay of the delay circuit 110 through the corresponding control code, that is, the phase difference between the input pulse clk0 and the delayed pulse clk180, so that the width difference is zero, thereby correcting the duty cycle of the output clock to 50%.

[0029] In this embodiment, the pulse width 'a' of the first pulse width signal clkr_p obtained from the input clock clk0 and the delayed clock clk180 is greater than the pulse width 'b' of the second pulse width signal clkf_n. This causes the discharge time of the integrating capacitor C to be greater than the charging time. Consequently, when the voltage VX of the integrating capacitor C is less than or equal to the absolute value of the difference between the reference voltage vref and the cumulative voltage difference VY, the voltage VX of the integrating capacitor C is less than the reference voltage vref. Figure 3 As shown; at this time, the comparator circuit 141 generates a first adjustment signal to reduce the duty cycle of the output clock to 50%. In another embodiment, the pulse width of the first pulse width signal obtained based on the input clock and the delayed clock may be smaller than the pulse width of the second pulse width signal, causing the discharge time of the integrating capacitor to be less than the charging time. This results in the voltage VX of the integrating capacitor being greater than the reference voltage when the voltage of the integrating capacitor is less than or equal to the absolute value of the difference between the reference voltage and the accumulated voltage difference. At this time, the comparator circuit generates a second adjustment signal to increase the duty cycle of the output clock to 50%. The delay adjustment direction corresponding to the first adjustment signal is opposite to the delay adjustment direction corresponding to the second adjustment signal.

[0030] Of course, in other embodiments, similar methods can be used to correct clocks with other duty cycles.

[0031] Optionally, the integrating circuit 131 in this embodiment includes: a first switching transistor Mp, a second switching transistor Mn, a current mirror 132, and an integrating capacitor C; wherein, the second switching transistor Mn, the current mirror 132, and the first switching transistor Mp are connected in series between the power supply terminal VDD and the ground terminal (not shown in the figure), and the control terminal of the first switching transistor Mp is connected to the sampling circuit 120 for receiving the first pulse width signal clkr_p, the control terminal of the second switching transistor Mn is connected to the sampling circuit 120 for receiving the second pulse width signal clkf_n, one end of the integrating capacitor C is connected to another output branch of the current mirror 132, and the other end of the integrating capacitor C is connected to the ground terminal.

[0032] Specifically, the input terminal of the second switch Mp is connected to the power supply terminal VDD, and the output terminal of the second switch Mp is connected to the input branch of the current mirror 132; the input terminal of the first switch Mn is connected to one output branch of the current mirror 132, and the output terminal of the first switch Mn is connected to the ground terminal.

[0033] In this embodiment, the second switching transistor Mp is placed at the source terminal of the current mirror 132, which can eliminate the effect of charge injection on the integrating capacitor C.

[0034] Of course, in other embodiments, other types of switching transistors can be used instead of the first switching transistor Mp and the second switching transistor Mn in the embodiment. The connection relationship between the components in the integrating circuit can be determined according to the working characteristics of the switching transistors, as long as one switching transistor charges the integrating capacitor and the other switching transistor discharges the integrating capacitor.

[0035] The current in the input branch of the current mirror 132 is equal to the current in the output branch, that is, the input-output current transfer ratio is equal to 1. Therefore, the use of the current mirror 132 in this embodiment can improve the charging and discharging accuracy of the integrating capacitor C and reduce fluctuations, thus improving the accuracy of the duty cycle correction circuit 10. One output branch of the current mirror 132 is connected to the input terminal of the second switching transistor Mn. The matching performance of the ip (input) and in (output) currents of the current mirror 132 directly determines the accuracy of the duty cycle correction circuit 10.

[0036] Optionally, the integrating circuit 131 in this embodiment further includes: a third switch M, the control terminal of the third switch M is connected to an initialization control signal pre_n (pre_n is the inverse signal of lpre_p), the input terminal of the third switch M is connected to one end of the integrating capacitor C, the output terminal of the third switch M is connected to a reference voltage vref (i.e., Vref), and the third switch M is used to control the initial voltage of the integrating capacitor C to be the reference voltage vref.

[0037] When the comparator circuit 141 determines that the voltage VX of the integrating capacitor C is less than or equal to the absolute value of the difference between the reference voltage vref and the cumulative voltage difference VY, it controls the third switch M to work through the initialization control signal pre_n to restore the initial voltage of the integrating capacitor C to the reference voltage vref.

[0038] It is known that the voltage VX of the integrating capacitor C in each cycle only contains net error information (duty cycle error). The voltage VX has a small range of variation. Therefore, a larger current and a smaller capacitor can be used to increase the resolution and accuracy of the duty cycle correction circuit 10.

[0039] Optionally, the current mirror 132 in this embodiment adopts a common source and common gate structure, and the integrator circuit 131 in this embodiment further includes a negative feedback circuit (not shown) disposed in the input branch of the current mirror 132.

[0040] This embodiment employs a common-source, common-gate current mirror 132, which can mitigate the modulation of current accuracy by the voltage VX fluctuation of the integrating capacitor C; and the introduction of a negative feedback circuit can further increase the output impedance of the current mirror 132, thereby improving the accuracy of the current mirror 132.

[0041] In other embodiments, the negative feedback circuit can also be set in another output branch of the current mirror, namely the charging and discharging circuit of the integrating capacitor C, which can increase the output impedance of the current mirror and improve the accuracy of the current mirror.

[0042] Further, the comparison circuit 141 of this embodiment includes: switching transistors M1-M6 and switching transistors N1 and N2; wherein, the input terminals of switching transistors M1-M4 are respectively connected to the power supply terminal VDD, and the control terminals of switching transistors M1 and M4 are respectively connected to the initialization control signal pre_n; the output terminals of switching transistors M1, M2, and M3 are respectively connected to the input terminal of switching transistor M5 and the control terminal of switching transistor M6, and serve as the first output terminal of the comparison circuit 141, outputting the first comparison result dec; The output terminals of transistor M3, M4, and M2 are all connected to the input terminals of transistors M6 and M5, respectively, and serve as the second output terminal of comparator circuit 141, outputting the second comparison result inc. The output terminal of transistor M5 is connected to the input terminal of transistor N1, and the output terminal of transistor M6 is connected to the input terminal of transistor N2. The control terminal of transistor N1 is connected to one end of the integrating capacitor C, serving as the first input terminal of comparator circuit 141. The control terminal of transistor N2 is connected to the reference voltage vref.

[0043] Furthermore, the output terminals of switching transistors N1 and N2 can also be connected to the ground terminal through two switching transistors (not shown in the figure). These two switching transistors are used to control the operation or shutdown of the comparator circuit 141.

[0044] The comparator circuit 141 is used to compare the voltage VX of the integrating capacitor C with the reference voltage vref when the voltage VX of the integrating capacitor C is less than or equal to the absolute value of the difference between the reference voltage vref and the cumulative voltage difference VY, and outputs a first comparison result dec and a second comparison result inc (dec and inc can indicate whether the phase is leading or lagging), so that the logic control circuit 142 generates a control code based on the first comparison result dec, the second comparison result inc, the cumulative voltage difference VY and the number of pulses corresponding to the cumulative voltage difference VY.

[0045] This application further proposes another embodiment of the duty cycle correction circuit, such as Figure 4 As shown, Figure 4This is a schematic diagram of another circuit structure of the duty cycle detection circuit and duty cycle adjustment circuit in another embodiment of the duty cycle correction circuit of this application. The difference between the duty cycle correction circuit (not shown) in this embodiment and the duty cycle correction circuit 10 in the above embodiment is that the integrator circuit 410 in this embodiment further includes: a capacitor C1 and a transmission gate TG; one end of the capacitor C1 is connected to the second input terminal of the comparator circuit 141, and the other end of the capacitor C1 is connected to the ground terminal; one end of the transmission gate TG is connected to one end of the capacitor C1, and the other end of the transmission gate TG is connected to the reference voltage vref (Vref).

[0046] This embodiment adds a capacitor C1 and a transmission gate TG to the reference signal input terminal, i.e. the second input terminal, of the comparator circuit 141. This makes the capacitor C1 symmetrical with the integrating capacitor C, and the transmission gate TG symmetrical with the first switch Mp and the second switch Mn. This improves the symmetry of the circuit and can compensate for factors such as capacitor leakage loss and parasitic capacitance mismatch, making the common-mode influencing factors as similar as possible.

[0047] It should be noted that the integrator circuit and the comparator circuit of this application can be integrated on the same circuit module. Therefore, the above-mentioned capacitor and transmission gate can also be classified as a comparator circuit.

[0048] In another embodiment, such as Figure 5 As shown, Figure 5 This is a schematic diagram of another embodiment of the duty cycle correction circuit of this application. The difference between the duty cycle correction circuit 50 in this embodiment and the duty cycle correction circuit 10 in the above embodiment is that the duty cycle correction circuit 50 in this embodiment further includes a pulse correction circuit 150, which is connected to the sampling circuit 120 and the duty cycle detection circuit 130 respectively, and is used to correct the first pulse width signal and the second pulse charging voltage, so that the corrected first pulse width signal discharges the integrating capacitor and the corrected second pulse width voltage charges the integrating capacitor.

[0049] This application uses a pulse correction circuit 150 to suppress the influence of changes in pressure, volume, and temperature on the current mirror 132, thereby further improving the accuracy of the current mirror 132.

[0050] Optionally, the duty cycle correction circuit 50 in this embodiment further includes a clock gating circuit 160, which is connected to the pulse correction circuit 150 and the duty cycle detection circuit 130 respectively. When the duty cycle correction circuit 50 corrects multiple loop clocks, a loop clock can be selected through the clock gating circuit 160, and the pulse width signal containing phase difference information corresponding to the selected loop clock can be transmitted to the duty cycle detection circuit 130 for processing, so as to perform duty cycle correction on the selected loop clock.

[0051] In other embodiments, the clock gating circuit and the pulse correction circuit may be used selectively depending on the actual situation.

[0052] Of course, the duty cycle correction circuit 50 (and the duty cycle correction circuit described above) in this embodiment further includes other circuits 20, which are respectively connected to the input clock and the delayed clock, and generate an output clock with a certain duty cycle (which can be 50%) based on the input clock and the delayed clock. For the specific circuit structure of the other circuits 20, please refer to the prior art.

[0053] This application further proposes a storage device, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of a storage device according to an embodiment of this application. The storage device 60 in this embodiment includes a duty cycle correction circuit 61. The structure and working principle of the duty cycle correction circuit 61 in this embodiment can be found in the duty cycle correction circuit of the above embodiment, and will not be repeated here.

[0054] Furthermore, the storage device 60 in this embodiment may also include an input clock receiving circuit, a DLL delay circuit, and an output clock generating circuit, etc.

[0055] In this embodiment, the storage device 60 is a dynamic random access memory (DRAM). In other embodiments, the storage device may also be a static random access memory (SRAM), etc.

[0056] Unlike existing technologies, this application uses a sampling circuit to acquire a first pulse width signal and a second pulse width signal that reflect the phase difference between the input clock and its delayed clock. It also acquires the voltage of the integrating capacitor through a duty cycle detection circuit. When the voltage of the integrating capacitor is less than or equal to the absolute value of the difference between the reference voltage and the cumulative voltage difference (the cumulative value of the difference between the discharge voltage of the integrating capacitor by the first pulse width signal and the charging voltage of the integrating capacitor by the second pulse width signal), the duty cycle adjustment circuit compares the voltage of the integrating capacitor with the reference voltage. Based on this comparison, the delay of the delay circuit is adjusted to regulate the output clock duty cycle. Compared to existing technologies that adjust the delay by comparing the voltages of two integrating capacitors, this application compares the voltage of the integrating capacitor with the absolute value of the difference between the reference voltage and the cumulative voltage difference. This means that the voltage of the integrating capacitor and the reference voltage have a certain voltage threshold, which reduces the voltage fluctuation range of the integrating capacitor in each cycle. This allows the duty cycle detection circuit to use a larger current and a smaller capacitor to increase resolution and accuracy. Therefore, this application improves the resolution and accuracy of the duty cycle correction circuit.

[0057] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A duty cycle correction circuit, characterized in that, include: A delay circuit is used to receive an input clock and output a delayed clock of the input clock; A sampling circuit, connected to the delay circuit, is used to obtain the phase difference between the input clock and the delayed clock, and generate a first pulse width signal and a second pulse width signal based on the phase difference; A duty cycle detection circuit, connected to the sampling circuit, is used to acquire the voltage on the integrating capacitor within the duty cycle detection circuit. A duty cycle adjustment circuit, connected to the delay circuit and the duty cycle detection circuit respectively, is used to compare the voltage of the integrating capacitor with the reference voltage when the voltage of the integrating capacitor is less than or equal to the absolute value of the difference between the reference voltage and the cumulative voltage difference, and adjust the delay of the delay circuit based on the comparison result to correct the duty cycle of the output clock corresponding to the input clock. Wherein, the cumulative voltage difference is the cumulative value of the difference between the discharge voltage of the first pulse width signal on the integrating capacitor and the charging voltage of the second pulse width signal on the integrating capacitor; The duty cycle adjustment circuit includes: The comparator circuit has a first input terminal connected to one end of the integrating capacitor and a second input terminal connected to the reference voltage. It generates a first adjustment signal when the voltage of the integrating capacitor is less than or equal to the absolute value of the difference and the voltage of the integrating capacitor is less than the reference voltage, and generates a second adjustment signal when the voltage of the integrating capacitor is less than or equal to the absolute value of the difference and the voltage of the integrating capacitor is greater than the reference voltage. A logic control circuit, whose input terminal is connected to the output terminal of the comparator circuit and whose output terminal is connected to the delay circuit, is used to generate a control code based on the cumulative voltage difference, the number of pulses corresponding to the cumulative voltage difference, and the first adjustment signal or the second adjustment signal, and to adjust the delay of the delay circuit based on the control code. The time delay adjustment direction corresponding to the first adjustment signal is opposite to the time delay adjustment direction corresponding to the second adjustment signal.

2. The duty cycle correction circuit according to claim 1, characterized in that, The duty cycle detection circuit includes an integrating circuit, whose first input terminal and second input terminal are respectively connected to the sampling circuit. The first input terminal is connected to the first pulse width signal for discharging the integrating capacitor, and the second input terminal is connected to the second pulse width signal for charging the integrating capacitor.

3. The duty cycle correction circuit according to claim 2, characterized in that, The integrating circuit includes: a first switching transistor, a second switching transistor, a current mirror, and an integrating capacitor; wherein, the second switching transistor, the current mirror, and the first switching transistor are connected in series between the power supply terminal and the ground terminal, and the control terminal of the first switching transistor is connected to the sampling circuit for receiving the first pulse width signal, the control terminal of the second switching transistor is connected to the sampling circuit for receiving the second pulse width signal, the output terminal of the second switching transistor is connected to the input branch of the current mirror, the input terminal of the first switching transistor is connected to one output branch of the current mirror, one end of the integrating capacitor is connected to another output branch of the current mirror, and the other end of the integrating capacitor is connected to the ground terminal.

4. The duty cycle correction circuit according to claim 3, characterized in that, The integrating circuit further includes a third switching transistor, whose control terminal is connected to an initialization control signal, whose input terminal is connected to one end of the integrating capacitor, and whose output terminal is connected to the reference voltage, for controlling the initial voltage of the integrating capacitor to be the reference voltage when the voltage of the integrating capacitor is less than or equal to the absolute value of the difference.

5. The duty cycle correction circuit according to claim 3, characterized in that, The current mirror adopts a common source and common gate structure, and the integrator circuit further includes a negative feedback circuit, which is disposed on the input branch of the current mirror or the other output branch.

6. The duty cycle correction circuit according to claim 3, characterized in that, The input terminal of the second switching transistor is connected to the power supply terminal, and its output terminal is connected to the input branch of the current mirror; the input terminal of the first switching transistor is connected to an output branch of the current mirror, and its output terminal is connected to the ground terminal.

7. The duty cycle correction circuit according to claim 3, characterized in that, The integrating circuit further includes: A capacitor, one end of which is connected to the second input terminal of the comparator circuit, and the other end of which is connected to the ground terminal; The transmission gate has one end connected to one end of the capacitor and the other end connected to the reference voltage.

8. The duty cycle correction circuit according to any one of claims 1 to 7, characterized in that, Further includes: A pulse correction circuit is connected to the sampling circuit and the duty cycle detection circuit, respectively, and is used to correct the first pulse width signal and the second pulse width signal so that the corrected first pulse width signal discharges the integrating capacitor and the corrected second pulse width signal charges the integrating capacitor.

9. A storage device, characterized in that, Includes the duty cycle correction circuit as described in any one of claims 1 to 8.

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