Bootlace switch

Abstract

A boot strap switch includes a first transistor, a second transistor, a first capacitor, three switches and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor and a resistor. The first transistor receives an input voltage and outputs an output voltage. A first end of the second transistor receives the input voltage and a second end of the second transistor is coupled to a first end of the first capacitor. A control end of the first switch receives a clock. The second switch is coupled between a control end of the first transistor and the first switch. The second capacitor is coupled between the control end of the first switch and a control end of the second switch. The resistor is coupled between the control end of the second switch and a reference voltage.

Description

Technical Field

[0001] This application relates to a bootstrapped switch. Background Technology

[0002] Figure 1 This is a circuit diagram of an existing bootstrap switch. The bootstrap switch 10 includes switches 101, 102, 103, 104, and 105; an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) 106; and a bootstrap capacitor 107. The input terminal VI and output terminal VO of the bootstrap switch 10 are coupled to the source and drain of the NMOS transistor 106, respectively. The gate of the NMOS transistor 106 is coupled to a voltage source V3 via switch 105, and to one end of the bootstrap capacitor 107 and one end of switch 101 via switch 104. The other end of switch 101 is coupled to a voltage source V1. The other end of the lifting capacitor 107 is coupled to voltage source V2 via switch 102, and to the source of NMOS transistor 106 and input terminal VI of bootie switch 10 via switch 103. Voltage source V1 is at a high voltage level VDD, while voltage sources V2 and V3 are at ground levels. The operation of bootie switch 10 is well known to those skilled in the art and will not be described further.

[0003] The state of switch 105 (on or off) determines the state of NMOS transistor 106 (on or off). In other words, the shorter the response time of switch 105 (i.e., the faster the gate of NMOS transistor 106 reaches the target voltage), the more synchronized the state of NMOS transistor 106 is with the system clock, resulting in better performance of the bootie switch 10 (e.g., faster speed and more accurate sampling). In other words, the design of switch 105 plays a crucial role in the bootie switch 10. Summary of the Invention

[0004] In view of the shortcomings of the prior art, one object of the present invention is to provide a bootie switch to improve the shortcomings of the prior art.

[0005] One embodiment of the present invention provides a bootie switch for receiving an input voltage and outputting an output voltage, comprising a first transistor, a first capacitor, a second transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a second capacitor, and a resistor. The first transistor has a first terminal, a second terminal, and a first control terminal, wherein the first transistor receives the input voltage at the first terminal and outputs the output voltage at the second terminal. The first capacitor has a third terminal and a fourth terminal. The second transistor has a fifth terminal, a sixth terminal, and a second control terminal, wherein the second transistor receives the input voltage at the fifth terminal, the sixth terminal is electrically connected to the third terminal of the first capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor. The first switch is coupled between the third terminal of the first capacitor and a first reference voltage. The second switch is coupled between the fourth terminal of the first capacitor and a second reference voltage. The third switch is coupled between the fourth terminal of the first capacitor and the first control terminal of the first transistor. A fourth switch is coupled to the first control terminal of the first transistor and has a third control terminal. A fifth switch is coupled between the fourth switch and the first reference voltage and has a fourth control terminal. A second capacitor has a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the third control terminal and the eighth terminal is coupled to the fourth control terminal. A resistor is coupled between the third control terminal and the second reference voltage.

[0006] Another embodiment of the present invention provides a bootie switch for receiving an input voltage and outputting an output voltage, comprising a first transistor, a capacitor, a second transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a resistor, and a logic circuit. The first transistor has a first terminal, a second terminal, and a first control terminal, wherein the first transistor receives the input voltage at the first terminal and outputs the output voltage at the second terminal. The capacitor has a third terminal and a fourth terminal. The second transistor has a fifth terminal, a sixth terminal, and a second control terminal, wherein the second transistor receives the input voltage at the fifth terminal, the sixth terminal is electrically connected to the third terminal of the capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor. The first switch is coupled between the third terminal of the capacitor and a first reference voltage. The second switch is coupled between the fourth terminal of the capacitor and a second reference voltage. The third switch is coupled between the fourth terminal of the capacitor and the first control terminal of the first transistor. A fourth switch is coupled to the first transistor and has a third control terminal. A fifth switch is coupled between the fourth switch and the first reference voltage and has a fourth control terminal. A sixth switch is coupled between the third control terminal and a third reference voltage and has a fifth control terminal. A resistor is coupled between the third control terminal and the second reference voltage. The logic circuit has a first input terminal and a first output terminal, wherein the first output terminal is coupled to the fifth control terminal. The fourth control terminal receives a clock, and the first input terminal of the logic circuit receives the clock or an inverted signal of the clock.

[0007] The bootie switch of this invention can be quickly closed. Compared with conventional technology, the bootie switch of this invention can operate at a higher speed.

[0008] The features, implementation, and effects of this invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0009] Figure 1 The circuit diagram for an existing bootie switch;

[0010] Figure 2 This is a circuit diagram of one embodiment of the bootie switch of the present invention;

[0011] Figure 3 An example showing clock Φ1 and clock Φ1b;

[0012] Figure 4 It is a computer-simulated waveform diagram of the voltage at several nodes of a bootie switch;

[0013] Figure 5 This is a circuit diagram of another embodiment of the bootie switch of the present invention;

[0014] Figure 6 This is a circuit diagram of another embodiment of the bootie switch of the present invention;

[0015] Figure 7 This is a circuit diagram of another embodiment of the bootie switch of the present invention;

[0016] Figure 8 A circuit diagram of another embodiment of the bootie switch of the present invention; and

[0017] Figure 9 This is a circuit diagram of another embodiment of the bootie switch of the present invention. Detailed Implementation

[0018] The technical terms used in the following description are based on the customary terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0019] The disclosure of this invention includes a bootie switch. Since some of the components included in the bootie switch of this invention may be known components individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention.

[0020] Figure 2 This is a circuit diagram of one embodiment of the bootie switch of the present invention. The bootie switch 100 receives an input voltage Vin from the input terminal IN and outputs an output voltage Vout from the output terminal OUT. The bootie switch 100 includes switches 110, 120, 130, 140, 150, 160, and 170, a lifting capacitor Cb, a capacitor Cq, and a resistor Rq. Switch circuit SW1 corresponds to... Figure 1 Switch 105. Switches 110, 120, 130, 140, 150, 160, and 170 can be implemented using transistors M1, M7, M2, M3, M8, M4, and M11, respectively. Each transistor has a first terminal, a second terminal, and a control terminal; the first and second terminals are the two ends of the switch formed by the transistor. For a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the first terminal can be either the source or the drain, the second terminal is either the source or the drain, and the control terminal is the gate. For a bipolar junction transistor (BJT), the first terminal can be either the collector or the emitter, the second terminal is either the collector or the emitter, and the control terminal is the base.

[0021] like Figure 2 As shown, the control terminals of transistor M1 and M7 are electrically connected to each other. Transistor M1 receives the input voltage Vin at its first terminal and outputs the output voltage Vout from its second terminal. The first terminal of transistor M7 receives the input voltage Vin, while the second terminal of transistor M7 is electrically connected to the first terminal of the lifting capacitor Cb. The first terminal of transistor M2 is coupled to the first terminal of the lifting capacitor Cb, and the second terminal of transistor M2 is coupled to the first reference voltage (in...). Figure 2 In this example, the ground level is GND. The first terminal of transistor M3 is coupled to the second reference voltage (in... Figure 2 In this example, the power supply voltage is VDD (which is higher than the ground level GND), and the second terminal of transistor M3 is coupled to the second terminal of the lifting capacitor Cb. The first terminal of transistor M8 is coupled to the control terminal of transistor M1, and the second terminal of transistor M8 is coupled to the second terminal of the lifting capacitor Cb. The first terminal of transistor M4 is coupled to or electrically connected to the control terminals of transistors M1 and M7, and the control terminal of transistor M4 is coupled to the first terminal of capacitor Cq and coupled to the second reference voltage (power supply voltage VDD) through resistor Rq. The first terminal of transistor M11 is coupled to the second terminal of transistor M4, and the second terminal of transistor M11 is coupled to or electrically connected to the first reference voltage (ground level GND), and the control terminal of transistor M11 is coupled to the second terminal of capacitor Cq. The control terminal of transistor M11 receives the clock Φ1b.

[0022] Switches 130, 140, 150 and 170 are turned on (corresponding transistors are turned on) or off (corresponding transistors are turned off) according to clocks Φ1 and Φ1b. Figure 3 An example of displaying clocks Φ1 and Φ1b, where clocks Φ1 and Φ1b are inverted signals. Controlled by clocks Φ1 and Φ1b, the bootie switch 100 operates alternately between a first clock phase Ph1 (when clock Φ1 is at a first level (e.g., low level) and clock Φ1b is at a second level (e.g., high level)) and a second clock phase Ph2 (when clock Φ1 is at a second level and clock Φ1b is at a first level). The operational details of the bootie switch 100 will be described in detail below.

[0023] refer to Figure 2 and Figure 3During the first clock phase Ph1 (when clock Φ1 is at a low level and clock Φ1b is at a high level), switches 130, 140, 160, and 170 are turned on, while switch 150 is not turned on. When switches 160 and 170 are turned on, the voltages at the control terminals of transistors M1 and M7 are substantially equal to the first reference voltage (GND), causing switches 110 and 120 to not turn on; in other words, switches 110 and 120 are not turned on during the first clock phase Ph1. When switches 130 and 140 are turned on, the voltages across the lifting capacitor Cb are substantially equal to the first reference voltage (GND) and the second reference voltage (power supply voltage VDD), respectively; in other words, the lifting capacitor Cb is charged during the first clock phase Ph1, and after the first clock phase Ph1 ends, the voltage across the lifting capacitor Cb is substantially equal to the voltage difference between the first and second reference voltages.

[0024] During the second clock phase Ph2 (when clock Φ1 is at a high level and clock Φ1b is at a low level), switches 130, 140, 160, and 170 are not conducting, while switch 150 is conducting. When switch 150 is conducting, the control terminals of transistors M1 and M7 are essentially at the same potential as the second terminal of the lifting capacitor Cb, causing transistors M1 and M7 to turn on due to the voltage across the lifting capacitor Cb, Vcb. When transistor M7 is on, the voltage across the second terminal of the lifting capacitor Cb and the control terminal of transistor M1 is essentially equal to the sum of the input voltage Vin and the voltage across Vcb. When transistor M1 is on, the output voltage Vout is essentially equal to the input voltage Vin, i.e., bootie switch 100 is conducting.

[0025] The voltage at the control terminal of transistor M1 may be greater than the power supply voltage VDD (even close to twice the power supply voltage VDD). One purpose of transistor M4 is to isolate the control terminal of transistor M1 from transistor M11, preventing the first terminal of transistor M11 from bearing this high voltage. Because the control terminal of transistor M4 is coupled or electrically connected to the power supply voltage VDD, transistor M4 can withstand this high voltage. However, transistor M4 slows down the transition speed of the control terminal of transistor M1 from the second level (e.g., high level) to the first level (e.g., low level), causing the bootie switch 100 to fail to immediately change from the on state to the off state after entering the first clock phase Ph1.

[0026] One of the purposes of capacitor Cq and resistor Rq is to instantly raise the voltage at the control terminal of switch 160, thereby accelerating the switching speed of transistor M4 (i.e., increasing the voltage switching speed at the control terminal of transistor M1).

[0027] When clock Φ1b is at the first level (i.e., the second clock phase Ph2), transistor M11 is not turned on, and capacitor Cq is charged. When clock Φ1b transitions from the first level to the second level (e.g., ... Figure 3 At time point T1, the voltage across capacitor Cq helps to momentarily raise the voltage at the control terminal of transistor M4, improving the conduction capability of transistor M4 and enabling it to turn on faster. When clock Φ1b is at the second level (i.e., the first clock phase Ph1), the voltage at the control terminal of transistor M4 will gradually approach the second reference voltage. In other words, the voltage across capacitor Cq helps transistor M4 turn on faster, thus allowing the voltage at the control terminal of transistor M1 to drop faster (i.e., accelerating the turning-off speed of bootie switch 100).

[0028] Figure 4 yes Figure 2 The computer-simulated waveforms of the voltages at several nodes of a bootie switch are shown. Curve g1 represents the voltage at the control terminal of transistor M11, curve g2 represents the voltage at the control terminal of transistor M4, and curves g3 and g4 represent the voltages at the control terminal of transistor M1. Curve g3 corresponds to a bootie switch without capacitor Cq and resistor Rq, while curve g4 corresponds to a bootie switch with capacitor Cq and resistor Rq (e.g., bootie switch 100). At time T1, the clock Φ1b transitions from a low level to a high level, therefore the voltage at the control terminal of transistor M11 (i.e., curve g1) begins to rise, and the voltage at the control terminal of transistor M4 (i.e., curve g2) is boosted (the boost is equal to or close to the voltage across capacitor Cq). Then, the voltages at the control terminals of transistor M11 (i.e., curve g1) and transistor M4 (i.e., curve g2) gradually stabilize (approximately equal to the supply voltage VDD at time T2). The time difference between time point T1 and time point T2 is about 0.2 nanoseconds (representing that the shoelace switch 100 operates at a very high speed). However, even in such a short time, the effects of capacitor Cq and resistor Rq can still be seen (i.e., curve g4 reaches the low level earlier than curve g3).

[0029] Figure 5 This is a circuit diagram of another embodiment of the bootie switch of the present invention. The bootie switch 500 is similar to the bootie switch 100, except that transistor M4 is implemented as a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) (hereinafter referred to as a PMOS transistor), and the bootie switch 500 further includes a switch 210 implemented by transistor M12. Because transistor M4 is implemented as a PMOS transistor, the bootie switch 500 further includes an inverter circuit 180. The inverter circuit 180 includes an odd number of inverters (…). Figure 5Taking one as an example, the input terminal of the inverter circuit 180 receives the clock Φ1b, and the output terminal is coupled or electrically connected to the capacitor Cq. The inverter circuit 180, the capacitor Cq, and the resistor Rq help to quickly reduce the voltage at the control terminal of the transistor M4, causing the transistor M4 to conduct faster, so as to more quickly pull down the voltage at the control terminal of the transistor M1. The transistor M12 is an NMOS transistor. The first terminal of the transistor M12 is coupled to the control terminals of the transistor M1 and the transistor M7. The second terminal of the transistor M12 is coupled to the first terminal of the transistor M11, and the control terminal of the transistor M12 is coupled to a second reference voltage (such as the power supply voltage VDD). The resistor Rq is coupled to the third reference voltage Vref (VDD < Vref < 2*VDD). The switch circuit SW2 corresponds to Figure 1 switch 105.

[0030] Figure 6 is a circuit diagram of another embodiment of the bootstrap switch of the present invention. The bootstrap switch 600 is similar to the bootstrap switch 500, except that the bootstrap switch 600 further includes a capacitor Cq' and a resistor Rq'. The resistor Rq' is coupled between the control terminal of the transistor M12 and the second reference voltage (such as the power supply voltage VDD). The first terminal of the capacitor Cq' is coupled or electrically connected to the control terminal of the transistor M12, and the second terminal of the capacitor Cq' is coupled or electrically connected to the control terminal of the transistor M11. The capacitor Cq' and the resistor Rq' can help the transistor M12 to conduct faster, so that the voltage at the control terminal of the transistor M1 can drop faster (that is, accelerate the switching speed of the bootstrap switch 100). The switch circuit SW3 corresponds to Figure 1 switch 105.

[0031] Figure 7 is a circuit diagram of another embodiment of the bootstrap switch of the present invention. The bootstrap switch 700 is similar to the bootstrap switch 100, except that the bootstrap switch 700 does not include the capacitor Cq, but includes a switch 220 and a logic circuit 230. The switch 220 is implemented by the transistor M13. The first terminal of the transistor M13 is coupled or electrically connected to the control terminal of the transistor M4. The second terminal of the transistor M13 is coupled or electrically connected to the third reference voltage Vref. The control terminal of the transistor M13 is coupled or electrically connected to the output terminal of the logic circuit 230. The input terminal of the logic circuit 230 receives the clock Φ1b. The logic circuit 230 outputs a control signal Ctrl according to the clock Φ1b, and the control signal Ctrl is used to turn on or off the transistor M13. The switch circuit SW4 corresponds to Figure 1 switch 105.

[0032] Such as Figure 3As shown, the control signal Ctrl is at a low level for a period of time td after the clock Φ1b transitions from a low level to a high level (i.e., time point T1), and at other times it is at a high level. That is, logic circuit 230 causes a level transition (e.g., from high level to low level) in the control signal Ctrl when the clock Φ1b transitions from a low level to a high level (i.e., time point T1), and causes another level transition (e.g., from low level to high level) in the control signal Ctrl before the clock Φ1b transitions from a high level to a low level (i.e., time point T2). Transistor M13 is turned on during time td, causing a momentary voltage rise at the control terminal of transistor M4.

[0033] Figure 7 The computer simulation waveforms of the voltages at several nodes of the shoelace switch are similar to... Figure 4 At time T1, transistor M13 turns on to instantaneously pull the voltage at the control terminal of transistor M4 up to substantially equal to the third reference voltage Vref, causing transistor M4 to turn on faster or more easily.

[0034] In some embodiments, td < (T2-T1) / 2. In other embodiments, the control signal Ctrl is a pulse signal (i.e., the time td is extremely short (td << (T2-T1))).

[0035] like Figure 7 As shown, in some embodiments, the logic circuit 230 includes an inverter 232 and an inverter 234. The output of the inverter 232 is coupled to or electrically connected to the control terminal of the transistor M13. The first input of the inverter 232 receives the clock Φ1b, and the second input of the inverter 232 is coupled to or electrically connected to the inverter 234. The input of the inverter 234 is coupled to or electrically connected to the first input of the inverter 232 and the control terminal of the transistor M11.

[0036] Figure 8 This is a circuit diagram of another embodiment of the bootie switch of the present invention. The bootie switch 800 is similar to the bootie switch 700, except that the logic circuit 230 of the bootie switch 700 is replaced by the logic circuit 240 of the bootie switch 800. The function of the logic circuit 240 is similar to that of the logic circuit 230. The logic circuit 240 includes an OR gate 242 and an inverter 244. The output terminal of the OR gate 242 is coupled or electrically connected to the control terminal of the transistor M13. The first input terminal of the OR gate 242 receives the inverted signal of clock Φ1b (i.e., clock Φ1). The second input terminal of the OR gate 242 is coupled or electrically connected to the inverter 244. The input terminal of the inverter 244 is coupled or electrically connected to the first input terminal of the OR gate 242 and receives clock Φ1. Switch circuit SW5 corresponds to... Figure 1Switch 105. In some embodiments, the low level of logic circuit 240 is ground (e.g., ground level GND), and the high level of logic circuit 240 is 2*VDD.

[0037] Figure 9 This is a circuit diagram of another embodiment of the bootie switch of the present invention. The bootie switch 900 includes a switching circuit SWx, switch 185, switch 190, and switch 195. Switches 185, 190, and 195 are implemented by transistors M9, M5, and M6, respectively. Switch 185 is coupled between a second reference voltage and the control terminal of transistor M8 and is controlled by clock Φ1. Switch 190 is coupled between the first terminal of lifting capacitor Cb and the control terminal of transistor M8 and is controlled by clock Φ1. Switch 195 is coupled between the first terminal of lifting capacitor Cb and the control terminal of transistor M8, and the control terminal of transistor M6 is electrically connected to the control terminals of transistors M1 and M7. Transistors M5, M6, and M9 are used to provide overvoltage protection during the operation of the bootie switch 500 to extend the service life of the components. Their operating principle is well known to those skilled in the art and will not be described in detail here. Those skilled in the art can use the above description to... Figure 2 and Figures 5 to 8 Replace the switching circuits SW1, SW2, SW3, SW4, or SW5 Figure 9 The switching circuit SWx.

[0038] In summary, this invention uses additional passive or active components to instantaneously boost the voltage at the control terminal of transistor M4, causing the voltage at the control terminal of transistor M1 to drop earlier and / or faster. Therefore, the bootie switch of this invention has a faster response speed (i.e., it can operate at higher speeds).

[0039] In other embodiments, the PMOS transistor and NMOS transistor in the foregoing embodiments can be replaced by NMOS transistor and PMOS transistor respectively. Those skilled in the art know how to adjust the phase or level of clock Φ1 and clock Φ1b accordingly, and adjust the first reference voltage, the second reference voltage and the third reference voltage Vref accordingly to achieve the above-described implementation.

[0040] Please note that the shapes, sizes, and proportions of the components in the aforementioned illustrations are merely illustrative and intended for those skilled in the art to understand the invention, and are not intended to limit the invention.

[0041] Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.

[0042] [Symbol Explanation]

[0043] 10, 100, 500, 600, 700, 800, 900: Shoelace switch

[0044] 101, 102, 103, 104, 105, 110, 120, 130, 140, 150, 160, 170, 210, 220, 185, 190, 195: Switches

[0045] 106: N-type metal-oxide-semiconductor field-effect transistor

[0046] 107,Cb: Lifting Capacitor

[0047] VI, IN: Input terminals

[0048] VO, OUT: Output terminals

[0049] V1, V2, V3: Voltage sources

[0050] Cq,Cq': Capacitors

[0051] M1, M7, M2, M3, M8, M4, M11, M12, M13, M9, M5, M6: Transistors

[0052] Vin: Input voltage

[0053] Vout: Output voltage

[0054] VDD: Power supply voltage

[0055] GND: Grounding level

[0056] Rq,Rq': Resistance

[0057] SW1, SW2, SW3, SW4, SW5, SWx: Switching circuits

[0058] Φ1, Φ1b: Clock

[0059] Ph1: First clock phase

[0060] Ph2: Second clock phase

[0061] Vcb: Transpressure

[0062] g1, g2, g3, g4: Curves

[0063] T1, T2: Time points

[0064] 180: Inverter circuit

[0065] Vref: Reference voltage

[0066] 230, 240: Logic circuits

[0067] Ctrl: Control signal

[0068] td: time

[0069] 232: Reverse and gate

[0070] 234, 244: Inverters

[0071] 242: or gate.

Claims

1. A bootie switch for receiving an input voltage and outputting an output voltage, comprising: A first transistor has a first terminal, a second terminal, and a first control terminal, wherein, The first transistor receives the input voltage at its first terminal and outputs the output voltage at its second terminal; A first capacitor has a third terminal and a fourth terminal; A second transistor has a fifth terminal, a sixth terminal and a second control terminal, wherein the second transistor receives the input voltage through the fifth terminal, the sixth terminal is electrically connected to the third terminal of the first capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor. A first switch is coupled between the third terminal of the first capacitor and a first reference voltage; A second switch is coupled between the fourth terminal of the first capacitor and a second reference voltage; A third switch is coupled between the fourth terminal of the first capacitor and the first control terminal of the first transistor; A fourth switch is coupled to the first control terminal of the first transistor and has a third control terminal; A fifth switch is coupled between the fourth switch and the first reference voltage, and has a fourth control terminal; A second capacitor has a seventh terminal and an eighth terminal, wherein the seventh terminal is coupled to the third control terminal, and the eighth terminal is coupled to the fourth control terminal; and A resistor is coupled between the third control terminal and the second reference voltage.

2. The bootie switch according to claim 1, wherein, The fourth switch is an N-type metal-oxide-semiconductor field-effect transistor.

3. The bootie switch according to claim 1, wherein, The fourth switch is a P-type metal-oxide-semiconductor field-effect transistor. The bootie switch also includes an inverter circuit that is coupled between the fourth control terminal and the second capacitor.

4. The bootie switch according to claim 3, further comprising: A sixth switch is coupled between the first control terminal and the fifth switch and has a fifth control terminal coupled to the second reference voltage.

5. The bootie switch according to claim 4, wherein, The resistor is a primary resistor, and the bootie switch also includes: A third capacitor has a ninth terminal and a tenth terminal, wherein the ninth terminal is coupled to the fifth control terminal and the tenth terminal is coupled to the fourth control terminal; and A second resistor is coupled between the fifth control terminal and the second reference voltage.

6. A bootie switch for receiving an input voltage and outputting an output voltage, comprising: A first transistor has a first terminal, a second terminal, and a first control terminal, wherein, The first transistor receives the input voltage at its first terminal and outputs the output voltage at its second terminal; A capacitor having a third terminal and a fourth terminal; A second transistor has a fifth terminal, a sixth terminal and a second control terminal, wherein the second transistor receives the input voltage through the fifth terminal, the sixth terminal is electrically connected to the third terminal of the capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor. A first switch is coupled between the third terminal of the capacitor and a first reference voltage; A second switch is coupled between the fourth terminal of the capacitor and a second reference voltage; A third switch is coupled between the fourth terminal of the capacitor and the first control terminal of the first transistor; A fourth switch is coupled to the first transistor and has a third control terminal; A fifth switch is coupled between the fourth switch and the first reference voltage, and has a fourth control terminal; A sixth switch is coupled between the third control terminal and a third reference voltage, and has a fifth control terminal; A resistor is coupled between the third control terminal and the second reference voltage; and A logic circuit having a first input terminal and a first output terminal, wherein the first output terminal is coupled to the fifth control terminal; The fourth control terminal receives a clock signal, and the first input terminal of the logic circuit receives the clock signal or an inverted signal of the clock signal.

7. The bootie switch according to claim 6, wherein, This logic circuit includes: A gate with a second output terminal, a second input terminal, and a third input terminal, wherein the second output terminal is coupled to the fifth control terminal, and the second input terminal receives the clock; and An inverter has a third output terminal and a fourth input terminal, wherein the third output terminal is coupled to the third input terminal, and the fourth input terminal is coupled to the second input terminal and the fourth control terminal.

8. The bootie switch according to claim 6, wherein, This logic circuit includes: An OR gate has a second output terminal, a second input terminal, and a third input terminal, wherein the second output terminal is coupled to the fifth control terminal, and the second input terminal receives the inverted signal of the clock; and An inverter has a third output terminal and a fourth input terminal, wherein the third output terminal is coupled to the third input terminal, and the fourth input terminal is coupled to the second input terminal and receives the inverted signal.

9. The bootie switch according to claim 6, wherein, The logic circuit outputs a pulse signal.

10. The bootie switch according to claim 6, wherein, The logic circuit outputs a control signal, and when the clock switches from a first level to a second level, the logic circuit causes the control signal to undergo a level switch.

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