Chip pin function reconstruction method and chip

Abstract

The application provides a chip pin function reconstruction method and a chip, and relates to the technical field of electronic circuits. The application can transmit an enable signal to each input / output circuit and a reconstruction control signal to each switch circuit according to the obtained configuration information by a software configuration mode, so as to flexibly adjust the pins of the input / output interface of each input / output circuit connected to be turned on by controlling the closing or opening of different switch circuits, and further realize the reuse and migration of the functions of different pins on the chip, so that the function expansion of the chip is more flexible, the functions of each input / output interface on the chip can be maximally used without being limited by packaging, in addition, the packaging can be more flexible and changeable, the same effect of packaging the pins PIN out of multiple input / output interface PAD can be easily realized, and the problem that when new functions need to be added on several pins of a chip, a new chip circuit needs to be redesigned, resulting in serious resource waste in the prior art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a chip pin function reconstruction method and a chip. BACKGROUND

[0002] With the development of chip technology, the integration of chips is getting higher and higher, and the functions supported by chips are getting more and more complex. There are more and more interface signals in the functional modules inside the chip that need to be led out to the chip pins to realize the input and output of the interface signals.

[0003] At present, the functions of each pin on the chip are defined according to the pre-defined functions, and then the registers of the corresponding pins are configured through software programs, so as to design the chip circuit.

[0004] However, in actual application, when new functions need to be added to some pins of the chip, new chip circuits need to be redesigned, which causes serious waste of resources. SUMMARY

[0005] The present application aims at the deficiencies in the prior art, and provides a chip pin function reconstruction method and a chip to solve the problems in the prior art.

[0006] To achieve the above-mentioned purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0007] In a first aspect, the embodiments of the present application provide a chip pin function reconstruction method applied to a processing unit on a chip. The processing unit is connected with a first input-output circuit, a second input-output circuit and a switch circuit on the chip respectively. The first input-output circuit and the second input-output circuit are connected by one or more switch circuits. The first input-output circuit and the second input-output circuit are connected with corresponding first input-output interfaces and second input-output interfaces respectively. The method comprises the following steps:

[0008] Obtaining configuration information, wherein the configuration information comprises a first enable signal of the first input-output circuit, a second enable signal of the second input-output circuit and a reconstruction control signal of the switch circuit;

[0009] According to the configuration information, transmitting the first enable signal to the first input-output circuit, transmitting the second enable signal to the second input-output circuit, and transmitting the reconstruction control signal to the switch circuit, wherein the reconstruction control signal is used to control the closing or opening of the switch circuit, and the transmission of signals between the first input-output circuit and the second input-output interface is controlled through the closing or opening of the switch circuit.

[0010] Optionally, the switch circuit comprises an AND gate and a NOR gate.

[0011] The enable end of the first input-output circuit connected with the switch circuit is connected with the first input end of the AND gate, and the enable end of the second input-output circuit connected with the switch circuit is connected with the second input end of the AND gate.

[0012] The output end of the AND gate is connected with the first input end of the NAND gate, the second input end of the NAND gate is connected with the processing unit, and the output end of the NAND gate is used for controlling the closing or opening of the switch circuit.

[0013] Optionally, the transmission of the first enable signal to the first input-output circuit, the transmission of the second enable signal to the second input-output circuit, and the transmission of the reconstruction control signal to the switch circuit according to the configuration information comprises:

[0014] The first enable signal is transmitted to the first input-output circuit and the second enable signal is transmitted to the second input-output circuit according to the configuration information, so that the enable end of the first input-output circuit transmits the first enable signal to the first input end of the AND gate and the enable end of the second input-output circuit transmits the second enable signal to the second input end of the AND gate.

[0015] The reconstruction control signal is transmitted to the second input end of the NAND gate, so that the output end of the NAND gate controls the closing or opening of the switch circuit according to the first enable signal, the second enable signal and the reconstruction control signal.

[0016] Optionally, if the first enable signal controls the first input-output circuit to be enabled, the second enable signal controls the second input-output circuit to be disabled, and the reconstruction control signal is a first preset value, the switch circuit is controlled to be closed, and the first input-output interface and / or the second input-output interface transmits signals with the first input-output circuit.

[0017] If the first enable signal controls the first input-output circuit to be disabled, the second enable signal controls the second input-output circuit to be enabled, and the reconstruction control signal is a first preset value, the switch circuit is controlled to be closed, and the first input-output interface and / or the second input-output interface transmits signals with the second input-output circuit.

[0018] If the first enable signal controls the first input-output circuit to be enabled, the second enable signal controls the second input-output circuit to be enabled, and the reconstruction control signal is a second preset value, the switch circuit is controlled to be opened, the first input-output interface transmits signals with the first input-output circuit, and the second input-output interface transmits signals with the second input-output circuit.

[0019] Optionally, the method further comprises:

[0020] transmitting a third enable signal to a third input-output circuit on the chip;

[0021] wherein the third input-output circuit is connected to the second input-output circuit through a second switch circuit, and the third input-output circuit is connected to a corresponding third input-output interface;

[0022] transmitting the reconstruction control signal to the switch circuit connected between the first input-output circuit and the second input-output circuit and the second switch circuit respectively, to control the third input-output interface to transmit signals with the first input-output circuit or control the first input-output interface to transmit signals with the third input-output circuit.

[0023] Optionally, the first input-output circuit is connected to a first bus through a third switch circuit, and the second input-output circuit is connected to the first bus through a fourth switch circuit.

[0024] Optionally, the transmitting a third enable signal to a third input-output circuit on the chip comprises:

[0025] wherein the third input-output circuit is connected to the first bus through a fifth switch circuit, and the third input-output circuit is connected to a corresponding third input-output interface;

[0026] transmitting the reconstruction control signal to the third switch circuit, the fourth switch circuit and the fifth switch circuit respectively, to control the third input-output interface to transmit signals with the first input-output circuit or control the first input-output interface to transmit signals with the third input-output circuit.

[0027] Optionally, each input-output circuit is connected to M buses in sequence through M switch circuits corresponding to the input-output circuit, where M is an integer greater than 1.

[0028] In a second aspect, the embodiments of the present application further provide a chip, applied to the chip pin function reconstruction method provided in the first aspect, and the chip comprises: a processing unit, a plurality of input-output circuits and a plurality of switch circuits, wherein each input-output circuit is connected to a corresponding input-output interface;

[0029] The output end of the processing unit is connected to the enable end of the first input-output circuit, the enable end of the second input-output circuit and the control end of the switch circuit connected between the first input-output circuit and the second input-output circuit respectively;

[0030] The enable end of the first input-output circuit is connected with the first input end of the switch circuit, and the enable end of the second input-output circuit is connected with the second input end of the switch circuit.

[0031] The processing unit is configured to acquire configuration information, and transmit a first enable signal to the first input-output circuit, a second enable signal to the second input-output circuit, and a reconstruction control signal to the switch circuit according to the configuration information, so that the reconstruction control signal controls closing or opening of the switch circuit, and the first input-output circuit transmits signals with the second input-output interface through the closing or opening of the switch circuit.

[0032] Optionally, the chip further comprises a third input-output circuit and a second switch circuit.

[0033] The third input-output circuit is connected with the second input-output circuit through the second switch circuit, and the third input-output circuit is connected with a corresponding third input-output interface.

[0034] The output end of the processing unit is further connected with the enable end of the third input-output circuit and the control end of the second switch circuit.

[0035] The enable end of the second input-output circuit is connected with the first input end of the second switch circuit, and the enable end of the third input-output circuit is connected with the second input end of the second switch circuit.

[0036] The processing unit is further configured to transmit a third enable signal to the third input-output circuit and a reconstruction control signal to the second switch circuit according to the configuration information, so that the reconstruction control signal controls closing or opening of the second switch circuit, and the third input-output interface transmits signals with the first input-output circuit through the closing or opening of the second switch circuit, or the first input-output interface transmits signals with the third input-output circuit.

[0037] Optionally, the chip further comprises a third switch circuit, a fourth switch circuit and a first bus.

[0038] The first input-output circuit is connected to the first bus through the third switch circuit, and the second input-output circuit is connected to the first bus through the fourth switch circuit.

[0039] Optionally, the chip further comprises a fifth switch circuit.

[0040] The third input-output circuit is connected to the first bus through the fifth switch circuit.

[0041] The beneficial effects of the present application are:

[0042] The application provides a chip pin function reconstruction method and a chip. When a user expects to realize function multiplexing and migration of any pin on the chip, the software configuration mode can be used. A processing unit transmits an enable signal to each input and output circuit and transmits a reconstruction control signal to each switch circuit according to acquired configuration information, so as to flexibly adjust the pins through which the output interface of each input and output circuit is conducted by controlling the closing or opening of different switch circuits, and then realize the function multiplexing and migration of different pins on the chip, so that the function expansion of the chip is more flexible, the functions of each input and output interface on the chip can be maximally used without being limited by packaging, in addition, the packaging can be more flexible and changeable, the same effect of packaging the pin PIN out of the multiple input and output interface PAD can be easily realized, and the problem that when new functions need to be added to some pins on the chip, a new chip circuit needs to be redesigned, thereby causing serious resource waste is solved. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0044] Figure 1 The structure of the chip provided by the embodiment of the application is shown in the following figure Figure One ;

[0045] Figure 2 The flowchart of the chip pin function reconstruction method provided by the embodiment of the application is shown in the following figure

[0046] Figure 3 The structure of the chip provided by the embodiment of the application is shown in the following figure Figure Two ;

[0047] Figure 4 The structure of the switch circuit in the chip provided by the embodiment of the application is shown in the following figure

[0048] Figure 5 The flowchart of another chip pin function reconstruction method provided by the embodiment of the application is shown in the following figure

[0049] Figure 6 The structure of the chip provided by the embodiment of the application is shown in the following figure Figure Three ;

[0050] Figure 7 The flowchart of another chip pin function reconstruction method provided by the embodiment of the application is shown in the following figure

[0051] Figure 8 Structure diagram of a chip provided for an embodiment of the present application Figure Four ;

[0052] Figure 9 Structure diagram of a chip provided for an embodiment of the present application Figure Five ;

[0053] Figure 10 Structure diagram of a chip provided for an embodiment of the present application Figure Six ;

[0054] Figure 11 Structure diagram of a chip provided for an embodiment of the present application Figure Seven ;

[0055] Figure 12 Structure diagram of a chip provided for an embodiment of the present application Figure Eight ;

[0056] Figure 13 Structure diagram of a chip provided for an embodiment of the present application Figure Nine ;

[0057] Figure 14 Structure diagram of a chip provided for an embodiment of the present application Figure Ten .

[0058] Icon: 100 - chip; 101 - processing unit; 102 - input / output circuit; 103 - switch circuit. DETAILED DESCRIPTION

[0059] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of description and illustration, and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn according to the actual proportions. The flowcharts show the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can not be implemented in sequence, and the steps without logical context relationship can be reversed in sequence or implemented simultaneously. In addition, one or more other operations can be added to the flowcharts or one or more operations can be removed from the flowcharts under the guidance of the content of the present application.

[0060] In addition, the described embodiments are only some embodiments of the present application, rather than all embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0061] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0062] First, before the technical solutions provided by the present application are described in detail, the internal structure of the chip provided by the present application is simply described.

[0063] Figure 1 The structure of the chip provided by the embodiments of the present application Figure One As shown in Figure 1 , the chip 100 includes a processing unit 101, a plurality of input / output circuits 102 and a plurality of switch circuits 103, wherein the processing unit 101 is connected with the plurality of input / output circuits 102 and the plurality of switch circuits 103 on the chip, and one or more switch circuits 103 are connected between two adjacent input / output circuits 102 (only the case of one switch circuit connected between two adjacent input / output circuits is shown in Figure 1 ), and each input / output circuit 102 is connected with a corresponding output interface.

[0064] It should be noted that in the present embodiment, the number and circuit structure of the switch circuits between two adjacent input / output circuits 102 are not specifically limited.

[0065] Among them, each input / output circuit 102 is a circuit module that can perform input and / or input functions within the chip.

[0066] For example, the processing unit 101 can be an internal register or a programmable memory unit (such as FLASH / ROM / EFUSE / OTP, etc.) of the chip, or a combination thereof.

[0067] It should be understood that the input / output interface corresponding to each input / output circuit 102 can be an un-packaged pin on the chip, also known as PAD, and the pin corresponding to each input / output interface is a packaged pin on the chip, also known as PIN.

[0068] In the embodiment, the user can configure the software, and the processing unit 101 transmits the enable signals to the input / output circuits 102 and the reconstruction control signals to the switch circuits 103 according to the obtained configuration information, so as to flexibly adjust the pins of the input / output interface connected to the input / output circuits 102 by controlling the closing of the switch circuits 103.

[0069] For example, it is assumed that the input / output circuit 1 connected to the corresponding input / output interface PAD0 does not package the corresponding pin PIN0, the input / output circuit 3 connected to the corresponding input / output interface PAD2 has a packaged pin PIN2, and the system application needs to use the function of the input / output interface PAD0. The processing unit 101 can transmit the enable signals to the input / output circuits and the reconstruction control signals to the switch circuits according to the obtained configuration information, so as to control the switch circuit 1 and the switch circuit 2 to be closed, wherein the first enable signal transmitted to the input / output circuit 1 is 1, the second enable signal transmitted to the input / output circuit 2 and the third enable signal transmitted to the input / output circuit 3 are both 0, and then the output signal DO_0 of the input / output circuit 1 can be output to the pin 3 through the switch circuit 1, the switch circuit 2 and the input / output interface PAD2, so as to realize the reuse and migration of the function of the pin 1 on the chip. In this way, the function signal in the chip can be output to any pin, the function expansion of the chip is more flexible, the functions of the input / output interfaces on the chip can be maximized without being limited by packaging, and in addition, the packaging can be more flexible and variable, and the same effect of packaging the pins PIN from the input / output interfaces PAD can be easily realized.

[0070] The implementation principle and the beneficial effects of the chip pin function reconstruction method provided by the present application will be described below through a plurality of specific embodiments.

[0071] In the following embodiments, in order to facilitate the understanding of the chip pin function reconstruction method provided by the present application, the first input / output circuit, the second input / output circuit and the switch circuit connected between the first input / output circuit and the second input / output circuit are taken as an example, and the chip pin function reconstruction method provided by the present application is introduced as follows. Figure 1

[0072] Figure 2 A flowchart of a chip pin function reconstruction method provided by an embodiment of the present application; optionally, the execution subject of the method can be the processing unit shown in Figure 1 .

[0073] ​It should be understood that in other embodiments, the order of some steps of the chip pin function reconfiguration method can be exchanged according to actual needs, or some steps can be omitted or deleted. Figure 2 As shown in the following table 1, the method comprises the following steps.

[0074] S201, obtaining configuration information.

[0075] The configuration information comprises a first enable signal of a first input-output circuit, a second enable signal of a second input-output circuit, and a reconfiguration control signal of a switch circuit. The enable signal of each input-output circuit comprises an input enable signal IBE and an output enable signal OBE. In addition, the input-output circuit can also be referred to as an output buffer.

[0076] In the embodiment, the configuration information can be determined according to a predefined pin function multiplexing table.

[0077] Figure 3 The structure of the chip provided in the embodiment of the present application is shown in the following table 1. Figure Two As shown in the following table 1, the method comprises the following steps. Figure 3 For example, taking input-output circuit 1 and input-output circuit 2 and the switch circuit (i.e. switch circuit 1) connected between input-output circuit 1 and input-output circuit 2 on a certain chip as an example.

[0078] The structure of input-output circuit 1 and input-output circuit 2 is the same, and input-output circuit 1 comprises a NAND gate, a NOR gate, an inverter, a first transistor, and a second transistor, the first input end of the NAND gate is used to access the output enable signal OBE_0 (or the input enable signal IBE_0, not marked in the following table 2) of input-output circuit 1, Figure 2 the second input end of the NAND gate is used to access the output signal DO_0 (or the input signal DI_0, not marked in the following table 2) of input-output circuit 1, Figure 2 the first input end of the NOR gate accesses the output signal DO_0 (or the input signal DI_0, not marked in the following table 2) of input-output circuit 1, Figure 2 the input end of the inverter is used to input the output enable signal OBE_0 (or the input enable signal IBE_0, not marked in the following table 2) of input-output circuit 1, Figure 2 the output end of the inverter is connected with the second input end of the NOR gate, and the output end of the NAND gate is connected with the output interface PAD0 of input-output circuit 1 via the first transistor, and the output end of the NOR gate is connected with the output interface PAD0 of input-output circuit 1 via the second transistor.

[0079] The following table 1 is a pin function multiplexing table for pin 1 and pin 2 on a certain type of chip.

[0080] Table 1 Pin function multiplexing table for pin 1 and pin 2

[0081]

[0082] When the user expects the output signal DO_0 of the input output circuit 1 to be output to the pin PIN0 and the pin PIN1, the configuration information including the output enable signal OBE_0 of the input output circuit 1 being 1, the output enable signal OBE_1 of the input output circuit 2 being 0, and the reconfiguration control signal REC_EN of the switch circuit 1 being 1 can be obtained by querying the pin function multiplexing table shown in Table 1, that is, the pin multiplexing code file can be generated according to the configuration information, and the pin multiplexing code file is downloaded to the processing unit, so that the processing unit can obtain the configuration information.

[0083] S202, according to the configuration information, the first enable signal is transmitted to the first input output circuit, the second enable signal is transmitted to the second input output circuit, and the reconfiguration control signal is transmitted to the switch circuit, the reconfiguration control signal is used to control the closing or opening of the switch circuit, and the first input output circuit and the second input output interface transmit signals through the closing or opening of the switch circuit.

[0084] On the basis of the above embodiment, the processing unit transmits the first enable signal OBE_0 to the input output circuit 1 and the second output enable signal OBE_1 to the input output circuit 2 according to the configuration information, and at the same time, the reconfiguration control signal REC_EN is transmitted to the switch circuit 1, and the switch circuit 1 controls the switch circuit 1 to be in the closed state according to the received reconfiguration control signal REC_EN=1, and then the pin PIN0 and the pin PIN1 are connected, the input output circuit 1 and the input output interface PAD1 transmit signals, that is, the output signal DO_0 of the input output circuit 1 can be output to the pin PIN1 through the switch circuit 1 and the input output interface PAD1, realizing the multiplexing and migration of the pin 0 function on the chip, so that the pin corresponding to the input output circuit 1 can be flexibly adjusted. The input output interface PAD0 conducts. In this way, the functional signals in the chip can be output to any pin, making the chip function expansion more flexible, which can maximize the use of the functions of each input output interface on the chip without being limited by packaging, and also makes the packaging more flexible and variable, and can easily realize the same effect of packaging the pin PIN out of multiple input output interfaces PAD.

[0085] In summary, the chip pin function reconstruction method is provided. When a user expects to realize function multiplexing and migration of any pin on a chip, a processing unit can transmit an enable signal to each input and output circuit and transmit a reconstruction control signal to each switch circuit according to acquired configuration information in a software configuration mode, so as to flexibly adjust pins of an input and output interface of each input and output circuit connected to be turned on by controlling closing or opening of different switch circuits, and then realize function multiplexing and migration of different pins on the chip, so that function expansion of the chip is more flexible, the functions of each input and output interface on the chip can be maximized without being limited by packaging, and in addition, the packaging can be more flexible and changeable, the same effect of packaging pins PIN of multiple input and output interface PAD can be easily realized, and the problem that when new functions need to be added to some pins of a chip, a new chip circuit needs to be redesigned, causing serious resource waste in the prior art is solved.

[0086] The structure of each switch unit shown in the above Figure 1 will be described in detail.

[0087] Optionally, each switch circuit in the above embodiment includes an AND gate and a NOR gate.

[0088] In this embodiment, the switch circuit 1 between the input and output circuit 1 and the input and output circuit 2 shown in the above Figure 3 will be taken as an example for explanation.

[0089] Figure 4 The structure schematic diagram of the switch circuit in the chip provided by the embodiment of the present application is shown in the above Figure 4 . The enable end of the input and output circuit 1 connected to the switch circuit 1 is connected to the first input end of the AND gate, so that the enable end of the input and output circuit 1 and the first input end of the AND gate can both receive the output enable signal OBE_0 of the input and output circuit 1 transmitted by the processing unit.

[0090] The enable end of the input and output circuit 2 connected to the switch circuit 1 is connected to the second input end of the AND gate, so that the enable end of the input and output circuit 2 and the second input end of the AND gate can both receive the output enable signal OBE_1 of the input and output circuit 2 transmitted by the processing unit. The output end of the AND gate is connected to the first input end of the NOR gate, the second input end of the NOR gate is connected to the processing unit, and the output end of the NOR gate is used to control closing or opening of the switch circuit.

[0091] The above Figure 4As shown, the processing unit is connected to the second input end of the NOR gate to input the negated signal of the reconstruction control signal REC EN transmitted by the processing unit to the switch circuit 1 to the NOR gate, and the output end of the NOR gate outputs the on-off signal REC FINAL. The closing or opening of the switch circuit 1 can be controlled through the on-off signal REC FINAL. If the on-off signal REC FINAL is 1, the switch circuit 1 is controlled to be closed. At this time, the pin PIN0 is connected to the pin PIN1, and the output signal DO_0 of the input-output circuit 1 or the output signal DO_1 of the input-output circuit 2 can be output to the pin PIN0 / pin PIN1, realizing the function multiplexing and migration of the pin PIN0 (or the pin PIN1). The pin PIN0 can no longer output only the output signal DO_0 of the input-output circuit 1 (or the pin PIN1 can no longer output only the output signal DO_1 of the input-output circuit 2).

[0092] The following embodiments will be specifically explained how to transmit the first enable signal to the first input-output circuit, transmit the second enable signal to the second input-output circuit, and transmit the reconstruction control signal to the switch circuit according to the configuration information in the above step S202.

[0093] Optionally, Figure 5 Another chip pin function reconstruction method provided by the embodiment of the application is shown in the flowchart. Referring to Figure 5 As shown, the above step S202 includes:

[0094] S501, according to the configuration information, transmitting the first enable signal to the first input-output circuit and the second enable signal to the second input-output circuit, so that the enable end of the first input-output circuit transmits the first enable signal to the first input end of the AND gate, and the enable end of the second input-output circuit transmits the second enable signal to the second input end of the AND gate.

[0095] S502, transmitting the reconstruction control signal to the second input end of the NOR gate, so that the output end of the NOR gate controls the closing or opening of the switch circuit according to the first enable signal, the second enable signal and the reconstruction control signal.

[0096] For example, continuing to refer to 4, the processing unit transmits the first enable signal OBE_0 to the input-output circuit 1 and the second enable signal OBE_1 to the input-output circuit 2 according to the obtained configuration information, so that the enable end of the input-output circuit 1 transmits the first enable signal OBE_0 to the first input end of the AND gate, and the enable end of the input-output circuit 2 transmits the second enable signal OBE_1 to the second input end of the AND gate.

[0097] Meanwhile, the processing unit transmits a reconstruction control signal REC_EN to the second input end of the NOR gate according to the obtained configuration information, and the NOR gate can obtain a pass-fail signal REC_FINAL according to the first enable signal OBE_0 transmitted by the input-output circuit 1, the second enable signal OBE_1 transmitted by the input-output circuit 2, and the reconstruction control signal REC_EN, and output the pass-fail signal REC_FINAL from the output end of the NOR gate, so as to control the closing or opening of the switch circuit 1 by the pass-fail signal REC_FINAL.

[0098] Optionally, if the first enable signal controls the first input-output circuit to be enabled, the second enable signal controls the second input-output circuit to be disabled, and the reconstruction control signal is a first preset value, the switch circuit is controlled to be closed, and the first input-output interface and / or the second input-output interface transmits signals with the first input-output circuit.

[0099] In the embodiment, for example, continuing to refer to Figure 4 As shown in the figure, if the first enable signal OBE_0 transmitted to the input-output circuit 1 is 1, that is, the first enable signal OBE_0 = 1, the input-output circuit 1 is controlled to be enabled; the second enable signal OBE_1 transmitted to the input-output circuit 2 is 0, that is, the second enable signal OBE_1 = 0, the input-output circuit 2 is controlled to be disabled, and the first preset value of the reconstruction control signal REC_EN transmitted to the switch circuit 1 is 1; at this time, the output signal output from the output end of the NOR gate is 0, that is, the signal input to the first input end of the NOR gate is 0, the signal input to the second input end of the NOR gate is the inverse value of the reconstruction control signal, that is, the signal input to the second input end of the NOR gate is 0, and it can be determined that the pass-fail signal REC_FINAL output from the output end of the NOR gate in the switch circuit 1 is 1, that is, the switch circuit 1 is controlled to be in a closed state, so that the input-output interface PAD1 and / or the second input-output interface PAD2 can transmit signals with the input-output circuit 1, and the superposition input-output of the functions of multiple pins on the chip is realized.

[0100] In another implementable manner, if the first enable signal controls the first input-output circuit to be disabled, the second enable signal controls the second input-output circuit to be enabled, and the reconstruction control signal is a first preset value, the switch circuit is controlled to be closed, and the first input-output interface and / or the second input-output interface transmits signals with the second input-output circuit.

[0101] In the embodiment, for example, continuing to refer to Figure 4As shown, if the first enable signal OBE_0 transmitted to the input-output circuit 1 is 0, i.e., the first enable signal OBE_0 = 0, the input-output circuit 1 is controlled to be disabled; if the second enable signal OBE_1 transmitted to the input-output circuit 2 is 1, i.e., the second enable signal OBE_1 = 1, the input-output circuit 2 is controlled to be enabled, and the first preset value of the reconstruction control signal REC_EN transmitted to the switch circuit 1 is 1; at this time, the output signal outputted from the output end of the NAND gate is 0, i.e., the signal inputted into the first input end of the NAND gate is 0, the signal inputted into the second input end of the NAND gate is the negated value of the reconstruction control signal, i.e., the signal inputted into the second input end of the NAND gate is 0, and it can be determined that the on-off signal REC_FINAL outputted from the output end of the NAND gate in the switch circuit 1 is 1, i.e., the switch circuit 1 is controlled to be in the closed state, so that the input-output interface PAD1 and / or the second input-output interface PAD2 and the input-output circuit 2 can realize the transmission of signals, and the superposition input-output of the functions of multiple pins on the chip is realized.

[0102] In another implementable manner, if the first enable signal controls the first input-output circuit to be enabled, the second enable signal controls the second input-output circuit to be enabled, and the reconstruction control signal is the second preset value, the switch circuit is controlled to be opened, and the first input-output interface transmits signals with the first input-output circuit, and the second input-output interface transmits signals with the second input-output circuit.

[0103] In the embodiment, for example, continuing to refer to Figure 4 As shown, if the first enable signal OBE_0 transmitted to the input-output circuit 1 is 1, i.e., the first enable signal OBE_0 = 1, the input-output circuit 1 is controlled to be enabled; if the second enable signal OBE_1 transmitted to the input-output circuit 2 is 1, i.e., the second enable signal OBE_1 = 1, the input-output circuit 2 is controlled to be enabled, and the second preset value of the reconstruction control signal REC_EN transmitted to the switch circuit 1 is 0; at this time, the output signal outputted from the output end of the NAND gate is 1, i.e., the signal inputted into the first input end of the NAND gate is 1, the signal inputted into the second input end of the NAND gate is the negated value of the reconstruction control signal, i.e., the signal inputted into the second input end of the NAND gate is 0, and it can be determined that the on-off signal REC_FINAL outputted from the output end of the NAND gate in the switch circuit 1 is 0, i.e., the switch circuit 1 is controlled to be in the opened state. In this way, the input-output interface PAD1 and the input-output circuit 1 can realize the transmission of signals, and the input-output interface PAD1 and the input-output circuit 2 can realize the transmission of signals, and the independent input-output of the functions of pins on the chip is realized.

[0104] It should be understood that when all the switch circuits on the chip are turned off, the output signals of the input / output circuits can be output to the pins connected to the output interfaces of the input / output circuits. For example, the output signal DO_0 of the input / output circuit 1 is output to the pin PIN0, and the output signal DO_1 of the input / output circuit 2 is output to the pin PIN1, to realize independent input / output.

[0105] Alternatively, if the first enable signal controls the first input / output circuit to be enabled, the second enable signal controls the second input / output circuit to be enabled, and the reconstruction control signal is the first preset value, the switch circuit is controlled to be turned off, and the first input / output interface transmits signals with the first input / output circuit, and the second input / output interface transmits signals with the second input / output circuit.

[0106] In this embodiment, for example, continuing to refer to Figure 4 As shown in the figure, if the first enable signal OBE_0 transmitted to the output circuit 1 is 1, that is, the first enable signal OBE_0=1, the input / output circuit 1 is controlled to be enabled; if the second enable signal OBE_1 transmitted to the output circuit 2 is 1, that is, the second enable signal OBE_1=1, the input / output circuit 2 is controlled to be enabled; and the first preset value of the reconstruction control signal REC_EN transmitted to the switch circuit 1 is 1, the output signal output from the output end of the NOR gate is 1, that is, the signal input to the first input end of the NOR gate is 1; the signal input to the second input end of the NOR gate is the negated value of the reconstruction control signal, that is, the signal input to the second input end of the NOR gate is 0, it can be determined that the on-off signal REC_FINAL output from the output end of the NOR gate in the switch circuit 1 is 0, that is, the switch circuit 1 is controlled to be turned off. In this way, the input / output interface PAD1 and the input / output circuit 1 can realize signal transmission, the input / output interface PAD1 and the input / output circuit 2 can realize signal transmission, and the situation that the input / output interface PAD1 and / or the second input / output interface PAD2 and the input / output circuit 2 realize signal transmission, or the input / output interface PAD1 and / or the second input / output interface PAD2 and the input / output circuit 1 realize signal transmission is avoided, to realize prevention of multiple output driving of functions of pins on the chip.

[0107] Alternatively, two adjacent input / output circuits are connected by one or more switch circuits, and the plurality of input / output circuits are connected in series by one or more switch circuits.

[0108] Referring to Figure 6The input / output circuit 1 is connected with the input / output interface PAD0, the input / output circuit 2 is connected with the input / output interface PAD1, and the input / output circuit n+1 is connected with the input / output interface PADn. The input / output circuit 1, the input / output circuit 2, …, and the input / output circuit n+1 are connected in series by a switch circuit, which is referred to as a bridge connection mode.

[0109] In the embodiment, n=3 is taken as an example to realize the functions of four general purpose input / output ports (GPIO), i.e., the functions of the input / output interface PAD0 connected with the input / output circuit 1, the input / output interface PAD1 connected with the input / output circuit 2, the input / output interface PAD2 connected with the input / output circuit 3, and the input / output interface PAD3 connected with the input / output circuit 4, which can also be referred to as the functions of PAD0 / 1 / 2 / 3.

[0110] Suppose that the input / output interface PAD0 connected with the input / output circuit 1 has no corresponding pin PIN, and the output interface PAD3 connected with the input / output circuit 4 has a packaged pin PIN. If the function of the input / output interface PAD0 connected with the input / output circuit 1 is to be used, the first enable signal OBE[0] transmitted to the input / output circuit 1 is set to 1, the enable signals transmitted to the remaining input / output circuits are set to 0, i.e., OBE[1]=OBE[2]=OBE[3]=0, the reconstruction control signal REC_EN[0] transmitted to the switch circuit 1, the reconstruction control signal REC_EN[1] transmitted to the switch circuit 2, and the reconstruction control signal REC_EN[2] transmitted to the switch circuit 3 are all set to 1, i.e., REC_EN[2:0]=0x111, i.e., the switch circuit 1, the switch circuit 2, and the switch circuit 3 are all closed. In this way, the output signal DO_0 of the input / output circuit 1 can be output to the packaged pin PIN3 of the input / output interface PAD3 connected with the input / output circuit 4, and the function of the input / output interface PAD0 connected with the input / output circuit 1 is multiplexed and migrated.

[0111] Continuing with the example, assuming that the input / output interface PAD0 connected to the input / output circuit 1 does not have a pin PIN0 packaged out, and the input / output interface PAD3 connected to the input / output circuit 4 has a packaged pin PIN3, if the input signal of the pin PIN3 is to be used for the input / output interface PAD0, the first enable signal IBE[0] transmitted to the input / output circuit 1 can be set to 1, the transmission enable signals of the remaining input / output circuits are all 0, that is, OBE[1]=OBE[2]=OBE[3]=0, and the reconstruction control signals REC_EN[0] transmitted to the switch circuit 1, the reconstruction control signals REC_EN[1] transmitted to the switch circuit 2, and the reconstruction control signals REC_EN[2] transmitted to the switch circuit 3 are all 1, that is, REC_EN[2:0]=0x111, that is, the switch circuit 1, the switch circuit 2, and the switch circuit 3 are all in the closed state. In this way, the input signal DI_3 of the pin PIN3 can be input to the input / output interface PAD0 connected to the input / output circuit 1, and the multiplexing and migration of the function of the input / output interface PAD0 of the input / output circuit 1 are realized.

[0112] In the embodiment, the GPIO function on the chip can be maximized without being limited by packaging. In addition, the packaging can be more flexible and diverse, and the same effect of packaging multiple PADs out of PINs can be easily realized.

[0113] It is worth noting that, Figure 6 When the bridge scheme shown bridges the input / output interfaces PAD connected by the input / output circuits, the input / output interfaces PAD in the middle cannot be used independently. All the input / output interfaces PAD are connected, similar to multiple PAD packaging together.

[0114] In the following embodiment, with reference to any three adjacent input / output circuits and the switch circuits connected between the three adjacent input / output circuits in the multiple input / output circuits shown in Figure 6 , that is, the first input / output circuit, the second input / output circuit, the third input / output circuit, the switch circuit, and the second switch circuit, the chip pin function reconstruction method provided by the present application is further introduced, and the details are as follows.

[0115] Optionally, with reference to Figure 7 , the method further includes:

[0116] S701, transmitting a third enable signal to a third input / output circuit on the chip.

[0117] The third input / output circuit is connected to the second input / output circuit through the second switch circuit, and the third input / output circuit is connected to a corresponding third input / output interface.

[0118] For example, the third input / output circuit can be directly connected to the second input / output circuit via the second switching circuit, or the third input / output circuit can be connected to the second input / output circuit via the second switching circuit and other components.

[0119] S702. Send reconstruction control signals to the switching circuit and the second switching circuit that connect the first input / output circuit and the second input / output circuit respectively, so as to control the transmission of signals between the third input / output interface and the first input / output circuit, or control the transmission of signals between the first input / output interface and the third input / output circuit.

[0120] In this embodiment, reference Figure 8 As shown, the third enable signal OBE_2 transmitted by the processing unit to the input / output circuit 3 on the chip is 1, meaning that when the third enable signal OBE_2=1, the input / output circuit 3 is enabled; and the reconstruction control signal REC_EN0 transmitted to the switch circuit 1 and the reconstruction control signal REC_EN1 transmitted to the switch circuit 2 are both 1, meaning that both switch circuit 1 and switch circuit 2 are in a closed state. This allows signal transmission between input / output interface PAD2 and input / output circuit 1, or between input / output interface PAD0 and input / output circuit 3, realizing the multiplexing and migration of the functions of input / output interface PAD2 connected to input / output circuit 3, or the multiplexing and migration of the functions of input / output interface PAD0 connected to input / output circuit 1.

[0121] Optionally, the first input / output circuit is connected to the first bus via a third switch, and the second input / output circuit is connected to the first bus via a fourth switch.

[0122] refer to Figure 9 As shown, in this embodiment, when a certain type of chip includes n+1 output circuits, input / output circuit 1 is connected to input / output interface PAD0, input / output circuit 2 is connected to input / output interface PAD1, and input / output circuit n+1 is connected to input / output interface PADn.

[0123] The input / output circuit 1 and input / output circuit 2 will be described in detail as examples. Input / output circuit 1 is connected to the first bus via switch circuit 3, and input / output circuit 2 is connected to the first bus via switch circuit 4.

[0124] In this embodiment, taking the input / output interface PAD connected to four input / output circuits as an example, the implementation of function reconfiguration is explained in detail. Table 2 below is a function multiplexing table for the input / output interface PAD connected to four input / output circuits.

[0125] Table 2 Function Multiplexing Table for PADs with 4 Input / Output Circuit Connections

[0126]

[0127] The third row in Table 2 is taken as an example for illustration, wherein the reconstruction control signal REC_PAD0[0] of the switch circuit 1 and the reconstruction control signal REC_PAD2[0] of the switch circuit 3 are 1, and the reconstruction control signal REC_PAD1[0] of the switch circuit 2 and the reconstruction control signal REC_PAD3[0] of the switch circuit 4 are 0, that is, the switch circuit 1 and the switch circuit 3 are closed, and the switch circuit 2 and the switch circuit 4 are disconnected. In this way, the input-output interface PAD0 connected to the input-output circuit 1 and the input-output interface PAD2 connected to the input-output circuit 3 are connected, and the function of the connection output interface PAD1 of the input-output circuit 2 is not affected. In this embodiment, the switch circuit 1 and the switch circuit 3 are connected to the first bus, and the switch circuit 2 and the switch circuit 4 are connected to the second bus. Figure 9 This bus connection mode can realize the connection between one PAD and any other PAD.

[0128] It is worth noting that the switch circuit 1 and the switch circuit 3 are connected to the first bus, and the switch circuit 2 and the switch circuit 4 are connected to the second bus. Figure 9 This bus connection mode only affects the PAD connected to the bus, and the chip function is not lost and the use is not limited. That is, the resource consumption of the bus connection mode is more than that of the bridge connection mode, but the resource consumption of one bus connection mode is close to that of the bridge connection mode.

[0129] In the following embodiment, any three of the plurality of input-output circuits and the switch circuits connected between the three input-output circuits shown in Figure 9 The first input-output circuit, the second input-output circuit, the third input-output circuit, the fourth switch circuit and the fifth switch circuit are taken as an example, and the chip pin function reconstruction method provided by the present application is further described as follows.

[0130] Optionally, the third enable signal transmitted to the third input-output circuit on the chip in the step S701 includes the following steps.

[0131] The third input-output circuit is connected to the first bus through the fifth switch circuit, and the third input-output circuit is connected to the corresponding third input-output interface.

[0132] The reconstruction control signals are respectively sent to the third switch circuit, the fourth switch circuit and the fifth switch circuit to control the third input-output interface to transmit signals with the first input-output circuit, or to control the first input-output interface to transmit signals with the third input-output circuit.

[0133] In this embodiment, reference is made to Figure 10As shown, the third enable signal OBE_2 transmitted by the processing unit to the input / output circuit 3 on the chip is 1, that is, when the third enable signal OBE_2 = 1, the input / output circuit 3 is enabled; and the reconstruction control signal REC_EN[2] transmitted to the switch circuit 3, the reconstruction control signal REC_EN[3] transmitted to the switch circuit 4, and the reconstruction control signal REC_EN[4] transmitted to the switch circuit 5 are all 1, that is, the switch circuit 3, the switch circuit 4, and the switch circuit 5 are all in the closed state. In this way, the input / output interface PAD2 and the input / output circuit 1 can realize signal transmission, or the input / output interface PAD0 and the input / output circuit 3 can realize signal transmission, realizing the multiplexing and migration of the function of the input / output interface PAD2 connected to the input / output circuit 3, or the multiplexing and migration of the function of the input / output interface PAD0 connected to the input / output circuit 1.

[0134] Optionally, the number of buses is M, and each input / output circuit is sequentially connected to M buses via one end of M switch circuits corresponding to the input / output circuit, where M is an integer greater than 1.

[0135] Reference Figure 11 As shown, for example, if the number of buses is 2, the input / output circuit 1 can be sequentially connected to two buses, that is, bus 0 and bus 1, via one end of two switch circuits corresponding to the input / output circuit 1.

[0136] In one embodiment, when the number of GPIO output circuits N is even, the number of buses is M = N / 2; when the number of GPIO output circuits N is odd, the number of buses is M = N+1 / 2. N GPIOs can be used to control the functions of N input / output interfaces on the chip. M switch circuits are connected to M buses to realize the reconfigurable requirements of any number of GPIOs.

[0137] Optionally, considering the complexity of the functions of the chip, the present application also proposes that multi-bit control can be used to reconfigure the functions of each input / output interface on the chip. Figures 12-14 As shown, multi-bit control is used to reconfigure the functions of each input / output interface on the chip.

[0138] Among them, Figure 12A one-bit reconfiguration control signal REC_EN is shown to control the reconfiguration of each output interface on the chip. The processing unit is connected with the input input circuit 1, the input input circuit 2 and the switch circuit 1, the input input circuit 1 and the input input circuit 2 are connected by the switch circuit 1, the processing unit transmits the first enable signal OBE_0 to the enable end of the input input circuit 1, the second enable signal OBE_1 to the enable end of the input input circuit 2, and the reconfiguration control signal REC_EN to the switch circuit 1. The closing or opening of the switch circuit 1 can be controlled by the reconfiguration control signal REC_EN to control the signal transmission between the input output circuit 1 and the input output interface PAD1, or the signal transmission between the input output circuit 2 and the input output interface PAD0. Table 3 is a function multiplexing table of the one-bit reconfiguration control signal as shown below. Figure 12

[0139] Table 3 is a function multiplexing table of the one-bit reconfiguration control signal as shown below.

[0140]

[0141] Figure 13 A two-bit reconfiguration control signal, i.e. MD and REC_EN, is shown to control the reconfiguration of each input output interface on the chip. The processing unit is connected with the input input circuit 1, the input input circuit 2 and the switch circuit 1, the input input circuit 1 and the input input circuit 2 are connected by the switch circuit 1, the processing unit transmits the first enable signal OBE_0 and the control bit MD to the enable end of the input input circuit 1, the second enable signal OBE_1 and the control bit MD to the enable end of the input input circuit 2, and the reconfiguration control signal REC_EN to the switch circuit 1. The closing or opening of the switch circuit 1 can be controlled by the reconfiguration control signal REC_EN to control the signal transmission between the input output circuit 1 and the input output interface PAD1, or the signal transmission between the input output circuit 2 and the input output interface PAD0. Table 4 is a function multiplexing table of the two-bit reconfiguration control signal as shown below. Figure 13

[0142] Table 4 is a function multiplexing table of the two-bit reconfiguration control signal as shown below.

[0143]

[0144] Figure 14 ​​The three-bit reconstruction control signal, i.e. MD[0], MD[1] and REC_EN, is shown to control the reconstruction of each input / output interface on the chip. The processing unit is connected with the input input circuit 1, the input input circuit 2 and the switch circuit 1, the input input circuit 1 and the input input circuit 2 are connected by the switch circuit 1, the processing unit transmits the first enable signal OBE_0 and the first control bit MD[0] to the enable end of the input input circuit 1, transmits the second enable signal OBE_1 and the second control bit MD[1] to the enable end of the input input circuit 2, and transmits the reconstruction control signal REC_EN to the switch circuit 1, the closing or opening of the switch circuit 1 can be controlled by the reconstruction control signal REC_EN, the first enable signal OBE_0, the first control bit MD[0], the second enable signal OBE_1 and the second control bit MD[1], so as to control the transmission of signals between the input / output circuit 1 and the input / output interface PAD1, or the transmission of signals between the input / output circuit 2 and the input / output interface PAD0. Table 5 is a function multiplexing table of the two-bit reconstruction control signal. Figure 14 The function multiplexing table of the two-bit reconstruction control signal is shown.

[0145] Table 5 is a function multiplexing table of the three-bit reconstruction control signal

[0146]

[0147] The above Figures 12-14 The control mode shown can realize independent input / output of the input / output interface corresponding to each input / output circuit, superposition function input / output, and prevent multiple output driving.

[0148] It is easy for those skilled in the art to understand that the above description is only a preferred embodiment of the present application, and is not intended to limit the present application, any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for reconfiguring the function of chip pins, characterized in that, A processing unit applied on a chip, wherein the processing unit is respectively connected to a first input / output circuit, a second input / output circuit and a switching circuit on the chip, the first input / output circuit and the second input / output circuit are connected by one or more switching circuits, and the first input / output circuit and the second input / output circuit are respectively connected to the corresponding first input / output interface and the second input / output interface. The method includes: Obtain configuration information, which includes: the enable signal of the first input / output circuit, the enable signal of the second input / output circuit, and the reconfiguration control signal of the switching circuit; According to the configuration information, a first enable signal is transmitted to the first input / output circuit, a second enable signal is transmitted to the second input / output circuit, and a reconfiguration control signal is transmitted to the switching circuit. The reconfiguration control signal is used to control the closing or opening of the switching circuit, and the closing or opening of the switching circuit controls the transmission of signals between the first input / output circuit and the second input / output interface. The switching circuit includes an AND gate and a NOR gate; The enable terminal of the first input / output circuit connected to the switching circuit is connected to the first input terminal of the AND gate, and the enable terminal of the second input / output circuit connected to the switching circuit is connected to the second input terminal of the AND gate. The output of the AND gate is connected to the first input of the NOR gate, the processing unit is connected to the second input of the NOR gate, and the output of the NOR gate is used to control the closing or opening of the switching circuit.

2. The method according to claim 1, characterized in that, The step of transmitting a first enable signal to the first input / output circuit, transmitting a second enable signal to the second input / output circuit, and transmitting a reconfiguration control signal to the switching circuit according to the configuration information includes: According to the configuration information, a first enable signal is transmitted to the first input / output circuit and a second enable signal is transmitted to the second input / output circuit, so that the enable terminal of the first input / output circuit transmits the first enable signal to the first input terminal of the AND gate and the enable terminal of the second input / output circuit transmits the second enable signal to the second input terminal of the AND gate. A reconstruction control signal is transmitted to the second input terminal of the NOR gate so that the output terminal of the NOR gate controls the closing or opening of the switching circuit according to the first enable signal, the second enable signal and the reconstruction control signal.

3. The method according to claim 1, characterized in that, If the first enable signal enables the first input / output circuit, and the second enable signal disables the second input / output circuit, and the reconfiguration control signal is a first preset value, then the switch circuit is closed, and the first input / output interface and / or the second input / output interface transmit signals with the first input / output circuit. If the first enable signal controls the first input / output circuit to be disabled, and the second enable signal controls the second input / output circuit to be enabled, and the reconstruction control signal is a first preset value, then the switch circuit is controlled to close, and the first input / output interface and / or the second input / output interface transmit signals with the second input / output circuit. If the first enable signal enables the first input / output circuit, the second enable signal enables the second input / output circuit, and the reconfiguration control signal is a second preset value, then the switching circuit is turned off, and the first input / output interface transmits signals with the first input / output circuit, and the second input / output interface transmits signals with the second input / output circuit.

4. The method according to any one of claims 1-3, characterized in that, The method further includes: Transmit a third enable signal to the third input / output circuit on the chip; The third input / output circuit is connected to the second input / output circuit via the second switching circuit, and the third input / output circuit is connected to the corresponding third input / output interface. The reconfiguration control signal is sent to the switching circuit connecting the first input / output circuit and the second input / output circuit, respectively, to control the transmission of signals between the third input / output interface and the first input / output circuit, or to control the transmission of signals between the first input / output interface and the third input / output circuit.

5. The method according to claim 4, characterized in that, The first input / output circuit is connected to the first bus via a third switch circuit, and the second input / output circuit is connected to the first bus via a fourth switch circuit.

6. The method according to claim 5, characterized in that, A third enable signal is transmitted to the third input / output circuit on the chip. include: The third input / output circuit is connected to the first bus via the fifth switch circuit, and the third input / output circuit is connected to the corresponding third input / output interface. The reconfiguration control signal is sent to the third switch circuit, the fourth switch circuit, and the fifth switch circuit respectively to control the transmission of signals between the third input / output interface and the first input / output circuit, or to control the transmission of signals between the first input / output interface and the third input / output circuit.

7. The method according to any one of claims 1-3, characterized in that, Each of the input / output circuits is sequentially connected to M buses via M switching circuits corresponding to the input / output circuit, where M is an integer greater than 1.

8. A chip, characterized in that, The chip pin function reconfiguration method according to any one of claims 1-7 is used, wherein the chip includes: a processing unit, multiple input / output circuits and multiple switching circuits, wherein each of the input / output circuits is connected to a corresponding input / output interface; The output terminal of the processing unit is connected to the enable terminal of the first input / output circuit, the enable terminal of the second input / output circuit, and the control terminal of the switching circuit connecting the first input / output circuit and the second input / output circuit, respectively. The enable terminal of the first input / output circuit is connected to the first input terminal of the switching circuit, and the enable terminal of the second input / output circuit is connected to the second input terminal of the switching circuit. The processing unit is used to acquire configuration information and, based on the configuration information, transmit a first enable signal to the first input / output circuit, a second enable signal to the second input / output circuit, and a reconfiguration control signal to the switching circuit, so that the reconfiguration control signal controls the closing or opening of the switching circuit, and controls the transmission of signals between the first input / output circuit and the second input / output interface through the closing or opening of the switching circuit.

9. The chip according to claim 8, characterized in that, The chip also includes: a third input / output circuit and a second switching circuit; The third input / output circuit is connected to the second input / output circuit through the second switching circuit, and the third input / output circuit is connected to the corresponding third input / output interface; The output terminal of the processing unit is also connected to the enable terminal of the third input / output circuit and the control terminal of the second switching circuit. The enable terminal of the second input / output circuit is connected to the first input terminal of the second switch circuit, and the enable terminal of the third input / output circuit is connected to the second input terminal of the second switch circuit. The processing unit is further configured to transmit a third enable signal to the third input / output circuit and a reconfiguration control signal to the second switch circuit according to the configuration information, so that the reconfiguration control signal controls the closing or opening of the second switch circuit, and controls the third input / output interface to transmit signals with the first input / output circuit, or controls the first input / output interface to transmit signals with the third input / output circuit, through the closing or opening of the second switch circuit.

10. The chip according to claim 8, characterized in that, The chip also includes: a third switching circuit, a fourth switching circuit, and a first bus; The first input / output circuit is connected to the first bus via the third switch circuit, and the second input / output circuit is connected to the first bus via the fourth switch circuit.

11. The chip according to claim 9, characterized in that, The chip also includes: a fifth switching circuit; The third input / output circuit is connected to the first bus via the fifth switch circuit.

Images