An encoder signal channel selection board

Abstract

This invention discloses an encoder signal channel selection board, which includes at least: an encoder signal input interface, a differential-to-single-ended signal chip, a single-ended signal channel selection chip, a single-ended-to-differential signal chip, and an encoder signal output interface. The signal output pins of the encoder signal input interface are connected to the differential-to-single-ended signal chip, the output pins of the differential-to-single-ended signal chip are connected to the single-ended signal channel selection chip, the output pins of the single-ended signal channel selection chip are connected to the single-ended-to-differential signal chip, and the single-ended-to-differential signal chip is connected to the signal input terminal of the encoder signal output interface. Using the encoder signal channel selection chip provided by this invention, multiple input signals can be selectively output as a single channel according to actual needs, suitable for one-to-many data interaction scenarios, reducing equipment development costs while improving production efficiency.

Description

Technical Field

[0001] This application relates to the field of input / output board technology, and in particular to an encoder signal channel selection board. Background Technology

[0002] During laser cutting, the position information of the stage motors is required, but a single laser can only receive the position information of one stage motor at a time. However, in actual processing, multiple stage motors often need to be cut, requiring multiple lasers. This one-to-one usage significantly increases production costs for enterprises. Therefore, a board is needed that can send the position information of multiple stage motors to a single laser and control that laser to cut the appropriate stage according to the user's actual needs, thus meeting the requirements of one-to-many data interaction. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an encoder signal channel selection board to solve the above problems.

[0004] The encoder signal channel selection board provided by this invention includes at least:

[0005] An encoder signal input interface, wherein the encoder signal input interface comprises at least two, each of the encoder signal input interfaces being used to receive at least one set of first differential signals;

[0006] A differential-to-single-ended signal chip, the number of which is the same as the number of encoder signal input interfaces, each differential-to-single-ended signal chip being electrically connected to a differential signal output pin of one encoder signal input interface, each differential-to-single-ended signal chip being used to convert at least one set of the first differential signals received by the encoder signal input interface connected to it into a corresponding single-ended signal;

[0007] A single-ended signal channel selection chip is electrically connected to the output terminal of the differential-to-single-ended signal chip. The single-ended signal channel selection chip is used to select at least one set of single-ended signals converted from a first differential signal received by an encoder signal input interface.

[0008] A single-ended to differential signal chip is electrically connected to the output of the single-ended signal channel selection chip. The single-ended to differential signal chip is used to restore the selected single-ended signal into the corresponding second differential signal.

[0009] The encoder signal output interface is connected to the output terminal of the single-ended to differential signal chip, and the second differential signal is output through the encoder signal output interface.

[0010] In an optional embodiment of the present invention, the board further includes an external input interface, the external input interface including two input terminals, each input terminal including a first sub-input terminal and a second sub-input terminal, the input terminal of each signal selection input circuit being connected to a first sub-input terminal and a second sub-input terminal respectively, and the output of the signal selection input circuit changing according to the level connected to the first sub-input terminal and the second sub-input terminal.

[0011] In an optional embodiment of the present invention, the board further includes a signal selection control circuit. The input terminal of the signal selection control circuit is connected to an external input signal, and the output terminal of the signal selection input circuit is electrically connected to the gating control pin of the single-ended signal channel selection chip. The signal selection input circuit is used to control the channel selection of the single-ended signal channel selection chip.

[0012] In an optional embodiment of the present invention, the signal selection control loop includes two circuits, each of which includes a first resistor, a first diode, an optocoupler, a light-emitting diode, a first capacitor, and a second resistor. Specifically:

[0013] The first end of the first resistor is connected to the first sub-input terminal, and the second end of the first resistor is connected to the negative terminal of the first diode and the first end of the optocoupler.

[0014] The positive terminal of the first diode, the negative terminal of the light-emitting diode, and the second sub-input terminal are connected;

[0015] The positive terminal of the light-emitting diode is connected to the second terminal of the optocoupler;

[0016] The first terminal of the second resistor is connected to the power supply VCC;

[0017] The fourth terminal of the optocoupler, the second terminal of the second resistor, and the first terminal of the first capacitor are connected;

[0018] The third terminal of the optocoupler and the second terminal of the first capacitor are grounded.

[0019] The fourth terminal of the optocoupler serves as the output terminal of the signal selection control loop.

[0020] In an optional embodiment of the present invention, when the first sub-input terminal is connected to a high voltage and the second sub-input terminal is connected to 0V, the output of the signal selection input circuit is a logic value of 1; when the first sub-input terminal is connected to a high voltage and the second sub-input terminal has no power input, the output of the signal selection input circuit is a logic value of 0.

[0021] In an optional embodiment of the present invention, the encoder signal gating board further includes a power supply circuit, through which an externally input power supply powers the circuitry inside the board.

[0022] In an optional embodiment of the present invention, the power supply circuit specifically includes:

[0023] Power connector, fuse, second diode, second capacitor, third capacitor, fourth capacitor, and inductor;

[0024] The first end of the fuse is connected to the first connection port of the power connector, and the second end of the fuse is connected to the negative terminal of the diode, the positive terminal of the second capacitor, the first end of the third capacitor, and the first end of the inductor.

[0025] The second end of the inductor and the first end of the fourth capacitor are connected to the internal power supply VCC.

[0026] The second connection port of the power connector is connected to the positive terminal of the second diode, the negative terminal of the second capacitor, the second terminal of the third capacitor, and the second terminal of the fourth capacitor is grounded.

[0027] In an optional embodiment of the present invention, the board further includes an indicator light circuit for displaying the power-on status of the circuit.

[0028] In an optional embodiment of the present invention, the single-ended signal channel selection chip is model 74HC153.

[0029] In an optional embodiment of the present invention, the voltage value of the differential signal is half the voltage value of the single-ended signal converted from the differential signal.

[0030] Beneficial effects of this invention:

[0031] This invention proposes an encoder signal channel selection board. First, it includes encoder signal input interfaces, at least two in total, each receiving at least one set of first differential signals. Then, the output of a differential-to-single-ended signal chip is connected to a single-ended signal selection chip. This single-ended signal channel selection chip selects one single-ended signal from the first differential signals received by the encoder signal input interfaces. Next, the output of the single-ended signal channel selection chip is connected to the signal input of a single-ended-to-differential signal chip, which restores the selected single-ended signal to a corresponding second differential signal. Finally, the selected second differential signal is output through the encoder signal output interface. Using the encoder signal channel selection chip provided by this invention, multiple input signals can be selectively output as a single channel according to actual needs, suitable for one-to-many data interaction scenarios, reducing equipment development costs while improving production efficiency. Attached Figure Description

[0032] Figure 1 A block diagram of an encoder signal channel selection board provided for an exemplary embodiment of this application.

[0033] Figure 2 A circuit diagram of an encoder signal input interface provided for an exemplary embodiment of this application.

[0034] Figure 3 This is a circuit diagram of a differential-to-single-ended chip provided for an exemplary embodiment of this application.

[0035] Figure 4-1 A circuit diagram of a single-ended signal gating chip U2 provided for an exemplary embodiment of this application.

[0036] Figure 4-2 A circuit diagram of a single-ended signal gating chip U5 provided for an exemplary embodiment of this application.

[0037] Figure 5 A circuit diagram of a signal selection control loop provided for an exemplary embodiment of this application.

[0038] Figure 6 A circuit diagram of a single-ended to differential signal chip provided for an exemplary embodiment of this application.

[0039] Figure 7 A circuit diagram of an encoder signal output interface provided for an exemplary embodiment of this application.

[0040] Figure 8 This is a schematic diagram of the power circuit inside an encoder signal channel selection board provided for an exemplary embodiment of this application. Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0042] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] In view of the problems existing in the prior art described above, this application provides an encoder signal channel selection board to solve the above problems. The encoder signal channel selection board includes at least:

[0044] An encoder signal input interface, wherein the encoder signal input interface comprises at least two, each of the encoder signal input interfaces being used to receive at least one set of first differential signals;

[0045] A differential-to-single-ended signal chip, the number of which is the same as the number of encoder signal input interfaces, each differential-to-single-ended signal chip being electrically connected to a differential signal output pin of one encoder signal input interface, each differential-to-single-ended signal chip being used to convert at least one set of the first differential signals received by the encoder signal input interface connected to it into a corresponding single-ended signal;

[0046] A single-ended signal channel selection chip is electrically connected to the output terminal of the differential-to-single-ended signal chip. The single-ended signal channel selection chip is used to select at least one set of single-ended signals converted from a first differential signal received by an encoder signal input interface.

[0047] A single-ended to differential signal chip is electrically connected to the output of the single-ended signal channel selection chip. The single-ended to differential signal chip is used to restore the selected single-ended signal into the corresponding second differential signal.

[0048] The encoder signal output interface is connected to the output terminal of the single-ended to differential signal chip, and the second differential signal is output through the encoder signal output interface.

[0049] It should be noted that the second differential signal and the first signal contain the same information.

[0050] The following explanation will be based on an example of a board that can select and output a single channel signal from four input channels:

[0051] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the encoder signal input interface includes four interfaces, namely ENC1, ENC2, ENC3 and ENC4. Each encoder signal input interface includes 15 pins. Each encoder signal input interface can receive one to four pairs of differential signals. Each encoder signal input interface corresponds to one channel.

[0052] Figure 2 A schematic diagram of the encoder signal input interface ENC1 is shown (the structure and circuit connections of ENC2, ENC3, and ENC4 are the same as ENC1). Please refer to [link / reference needed]. Figure 2 As shown, in an exemplary embodiment of the present invention, pins 1, 9, 4, 12, 5, 13, 6, and 14 are output pins of the encoder signal input interface, and CH1A and / CH1A, CH1B and / CH1B, CH1C and / CH1C, CH1D and / CH1D are four pairs of differential signals input to the encoder signal input interface ENC1. Specifically, the CH1A and / CH1A pair of differential signals input to the encoder signal input interface ENC1 are output through pins 14 and 6 of the encoder signal input interface, respectively; the CH1B and / CH1B pair of differential signals input to the encoder signal input interface ENC1 are output through pins 13 and 5 of the encoder signal input interface, respectively; the CH1C and / CH1C pair of differential signals input to the encoder signal input interface ENC1 are output through pins 12 and 4 of the encoder signal input interface, respectively; and the CH1D and / CH1D pair of differential signals input to the encoder signal input interface ENC1 are output through pins 9 and 1 of the encoder signal input interface, respectively.

[0053] Please see Figure 2 As shown, in this embodiment, grounding pin 3 or pin 7 of the encoder signal input interface ENC1 can provide power to the external circuit. Resistors R1 and R17 are used to balance the differential signal, and the voltage across R5 is the differential signal voltage difference.

[0054] Please see Figure 1 and Figure 3As shown, in one embodiment of the present invention, the differential-to-single-ended signal chip includes four chips, denoted as U1, U4, U6, and U7. Each differential-to-single-ended chip includes eight input pins: pin 2 INA+, pin 1 INA-, pin 14 INB+, pin 15 INB-, pin 6 INC+, pin 7 INC-, pin 10 IND+, and pin 9 IND-; and four output pins: pin 3 OUTA, pin 13 OUTB, pin 5 OUTC, and pin 11 OUTD.

[0055] In this embodiment, the differential-to-single-ended signal chip can be a 26C32 / SO, and it is understood that other models of chips can also be used in other embodiments.

[0056] Please see Figure 2 and Figure 3 As shown, in one specific embodiment, pins INA+ (2) and INA- (1) of the differential-to-single-ended signal chip U1 are connected to pins 1 and 9 of the encoder signal input interface ENC1, respectively, to receive differential signals CH1D and / CH1D; pins INB+ (14) and INB- (15) of the differential-to-single-ended signal chip U1 are connected to pins 4 and 12 of the encoder signal input interface ENC1, respectively, to receive differential signals CH1C and / CH1C; pins INC+ (6) and INC- (7) of the differential-to-single-ended signal chip U1 are connected to pins 4 and 12 of the encoder signal input interface ENC1, respectively, to receive differential signals CH1C and / CH1C; pins IND+ (10) and IND- (9) of the differential-to-single-ended signal chip U1 are connected to pins 6 and 14 of the encoder signal input interface ENC1, respectively, to receive differential signals CH1D and / CH1D. The four pairs of differential signals CH1A and / CH1A, CH1B and / CH1B, CH1C and / CH1C, CH1D and / CH1D are output as four corresponding single-ended signals CH1-A, CH1-B, CH1-C and CH1-D after being processed by a differential-to-single-ended signal chip. The single-ended signal CH1-A is output through pin 11 of the differential-to-single-ended signal chip U1, the single-ended signal CH1-B is output through pin 5 of the differential-to-single-ended signal chip U1, the single-ended signal CH1-C is output through pin 13 of the differential-to-single-ended signal chip U1, and the single-ended signal CH1-D is output through pin 3 of the differential-to-single-ended signal chip U1.

[0057] It should be noted that the voltage value of each differential signal pair is equal to half the voltage value of the single-ended signal generated by the differential-to-single-ended signal chip.

[0058] Please see Figure 1 , Figure 4-1as well as Figure 4-2 As shown, in one embodiment of the present invention, the single-ended signal channel selection chip includes two chips, denoted as U2 and U5 respectively. Each single-ended signal channel selection chip includes: eight input pins, namely pin 6 (1C0), pin 5 (1C1), pin 4 (1C2), pin 3 (1C3), pin 10 (2C0), pin 11 (2C1), pin 12 (2C2), and pin 13 (2C3); two output pins, namely pin 7 (1Y) and pin 9 (2Y); and two gating control pins, namely pin 14 (A) and pin 2 (B).

[0059] In this embodiment, the single-ended signal channel selection chip can be a 74HC153. It is understood that in other embodiments, the single-ended signal channel selection chip can be other models.

[0060] Please see Figure 3 , Figure 4-1 as well as Figure 4-2 As shown, in a specific embodiment, the single-ended signal CH1-A output by the differential-to-single-ended signal chip U1 is connected to pin 3 of the single-ended signal gating chip U2; the single-ended signal CH1-B output by the differential-to-single-ended signal chip U1 is connected to pin 13 of the single-ended signal gating chip U2; the single-ended signal CH1-B output by the differential-to-single-ended signal chip U1 is connected to pin 13 of the single-ended signal gating chip U2; the single-ended signal CH1-C output by the differential-to-single-ended signal chip U1 is connected to pin 3 of the single-ended signal gating chip U5; and the single-ended signal CH1-D output by the differential-to-single-ended signal chip U1 is connected to pin 13 of the single-ended signal gating chip U5.

[0061] To control the single-ended signal channel selection chip, please refer to [link / reference]. Figure 5 As shown, in one embodiment of the present invention, the board further includes an external input interface SEL_IN and a signal selection control loop. The input terminal of the signal selection input loop is connected to an external input signal, and the output terminal of the signal selection input loop is electrically connected to the gating control pin of the single-ended signal channel selection chip. The signal selection input loop is used to control the channel selection of the single-ended signal channel selection chip.

[0062] Please see Figure 5As shown, in one specific embodiment, the signal selection control loop includes two loops, and the external input interface SEL_IN includes two input terminals. Each input terminal includes one first sub-input terminal and one second sub-input terminal. The two signal input terminals of each signal selection control loop are respectively connected to one of the first sub-input terminals and one of the second sub-input terminals. The output of the signal selection control loop changes according to the level connected to the first sub-input terminal and the second sub-input terminal. For ease of description later, the first sub-input terminal connected to the input terminal of one signal selection control loop is denoted as +SEL0, the second sub-input terminal as -SEL0, and the output terminal as / SEL0; the first sub-input terminal connected to the input terminal of the other signal selection control loop is denoted as +SEL1, the second sub-input terminal as -SEL1, and the output terminal as / SEL1.

[0063] Please see Figure 4-1 , Figure 4-2 and Figure 5 As shown, the outputs / SEL0 and / SEL1 of the signal selection control loop are connected to the selection control pins 14 and 2 of the single-ended signal selection chips U2 and U5, respectively. In this embodiment, when the first sub-input terminal is connected to a high voltage and the second sub-input terminal is connected to 0V, the output of the signal selection input loop is a logic value 1; when the first sub-input terminal is connected to a high voltage and the second sub-input terminal has no power input, the output of the signal selection input loop is a logic value 0. For example, when the first sub-input terminal +SEL0 (or +SEL1) is connected to 24V and the second sub-input terminal -SEL0 (or -SEL1) is connected to 0V, / SEL0 (or / SEL1) is a digital logic value "1"; when the first sub-input terminal +SEL0 (or +SEL1) is connected to 24V and the second sub-input terminal -SEL0 (-SEL1) has no power input, / SEL0 (or / SEL1) is a digital logic value "0". In other words, by controlling whether -SEL0 (or -SEL1) is connected to 0V, the logic value output by / SEL0 (or / SEL1) can be controlled. Furthermore, / SEL0 and / SEL1 can form "00", "01", "10", and "11".

[0064] Four combinations.

[0065] Based on the four possible combinations of the input signals / SEL0 and / SEL1 received by the two gating control pins of single-ended signal gating chips U2 and U5, all differential signals of a given encoder can be selected. For example, it can be set as follows: / SEL0 = 0,

[0066] When / SEL1 = 0, single-ended signal gating chip U2 selects outputs CH1A and CH1B, and single-ended signal gating chip U5 selects outputs CH1C and CH1D; when / SEL0 = 0 and / SEL1 = 1, single-ended signal gating chip U2 selects outputs CH2A and CH2B, and single-ended signal gating chip U5 selects outputs CH2C and CH2D; when / SEL0 = 1 and / SEL1 = 0, single-ended signal gating chip U2 selects outputs CH3A and CH3B, and single-ended signal gating chip U5 selects outputs CH3C and CH3D; when / SEL0 = 1 and / SEL1 = 10, single-ended signal gating chip U2 selects outputs CH4A and CH4B, and single-ended signal gating chip U5 selects outputs CH4C and CH4D. Through the above settings, all single-ended signals corresponding to the differential signals in a specific encoder signal input interface channel can be selected.

[0067] Please see Figure 5 As shown, in one specific embodiment, each of the signal selection control loops includes a first resistor R39 (R49), a first diode D1 (D2), an optocoupler (coupled by a diode and a transistor PC1 (PC2)), a light-emitting diode LED1 (LED2), a first capacitor C1 (C2), and a second resistor R38 (R48). Specifically:

[0068] The first end of the first resistor R39 (R49) is connected to the first sub-input terminal +SEL0 (+SEL1), and the second end of the first resistor R39 (R49) is connected to the negative terminal of the first diode D1 (D2) and the first terminal 1 of the optocoupler.

[0069] The positive terminal of the first diode D1 (D2), the negative terminal of the light-emitting diode LED1 (LED2), and the second sub-input terminal -SEL0 (-SEL1) are connected;

[0070] The positive terminal of the light-emitting diode is connected to the second terminal 2 of the optocoupler;

[0071] The first terminal of the second resistor R38 (R48) is connected to the power supply VCC;

[0072] The third terminal 3 of the optocoupler and the second terminal of the first capacitor C1 (C2) are grounded;

[0073] The fourth terminal 4 of the optocoupler is connected to the second terminal of the second resistor R38 (R48) and the first terminal of the first capacitor C1 (C2), and serves as the output terminal of the signal selection input circuit.

[0074] Please see Figure 6As shown, in one embodiment, the single-ended to differential signal chip U3 includes 4 input pins and 8 input pins. The 4 input pins are pin 1A, pin 7A, pin 9A, and pin 15A; the 8 input pins are pin 2Y, pin 3Z, pin 6Y, pin 5Z, pin 10Y, pin 11Z, pin 14Y, and pin 13Z.

[0075] Please refer to Figure 4 and Figure 6 As shown, in one specific embodiment, signal output pins 7 and 9 of the single-ended signal gating chip U2 are respectively connected to input pins 1 and 7 of the single-ended to differential signal chip U3; signal output pins 7 and 9 of the single-ended signal gating chip U5 are respectively connected to input pins 9 and 15 of the single-ended to differential signal chip U3. The single-ended to differential chip converts the single-ended signal corresponding to the differential signal in a certain encoder signal input interface channel back to the differential signal initially received by that encoder signal input interface channel.

[0076] In this embodiment, the single-ended to differential signal chip can be a 26C31 / SO. It is understood that in other embodiments, the single-ended to differential signal chip can be other models.

[0077] Please see Figure 7 As shown, in one embodiment of the present invention, the encoder signal output interface ENC_SEL includes 15 pins, wherein pins 1, 9, 4, 12, 5, 13, 6 and 14 of the encoder signal input interface are signal input pins, and each encoder signal output interface can allow four pairs of differential signals to pass through.

[0078] Please see Figure 6 and Figure 7 As shown, the signal input pin of the encoder signal output interface ENC_SEL is connected to the output terminal of the single-ended to differential signal chip. The encoder signal output interface ENC_SEL outputs the differential signal received by a selected encoder signal input interface through the signal input pin.

[0079] It should be noted that the above embodiments are based on selecting one output from four encoder signal input interfaces. It is understood that the differential signals in each encoder signal input interface are not limited to four sets. Other embodiments are not limited to the above description. For example, if there are two encoder signal input interfaces, one output can be selected from the two; similarly, if there are three encoder signal input interfaces, one output can be selected from the three. Furthermore, the single-ended signal gating chip does not necessarily need to be two. For instance, if there are only two encoder signal input interfaces, and each encoder signal input interface receives only one set of differential signals, then only one single-ended signal gating chip is needed to meet the requirements.

[0080] In summary, the number of differential-to-single-ended signal chips, single-ended signal gating chips, encoder signal input interfaces, and single-ended-to-differential chips is not limited to the description in this specification. The appropriate settings should be made according to actual needs, and the principles are consistent with those described in the above embodiments.

[0081] In this embodiment, the encoder signal gating board also includes a power supply circuit, through which externally input power supplies the circuitry inside the board.

[0082] Please see Figure 8 As shown, in a specific embodiment of the present invention, the power supply circuit specifically includes:

[0083] Power connector PWR1, fuse F1, second diode D3, second capacitor C3, third capacitor C4, fourth capacitor C5, and inductor FB1;

[0084] The first end of the fuse F1 is connected to the first connection port 1 of the power connector PWR1, and the second end 2 of the fuse F1 is connected to the negative terminal of the diode D3, the positive terminal of the second capacitor C3, the first end of the third capacitor C4, and the first end of the inductor FB1.

[0085] The second terminal of the inductor FB1 and the first terminal of the fourth capacitor C5 are connected to the internal power supply VCC.

[0086] The second connection port 2 of the power connector is connected to the positive terminal of the second diode D3, the negative terminal of the second capacitor C3, the second terminal of the third capacitor C4, and the second terminal of the fourth capacitor C5 and the second terminal of the fourth capacitor are grounded.

[0087] In this embodiment, the board also includes an indicator light circuit, which is used to display the power status of the circuit.

[0088] This document has generally described the systems and methods in detail to aid in understanding the invention. Furthermore, various specific details have been set forth to provide a general understanding of embodiments of the invention. However, those skilled in the art will recognize that embodiments of the invention can be practiced without one or more specific details, or using other means, systems, accessories, methods, components, materials, parts, etc. In other instances, well-known structures, materials, and / or operations have not been specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.

[0089] Therefore, although the invention has been described herein with reference to specific embodiments thereof, freedom of modification, various changes and substitutions are also within the scope of the foregoing disclosure, and it should be understood that in some cases, certain features of the invention may be adopted without departing from the scope and spirit of the invention and without corresponding use of other features. Thus, many modifications can be made to adapt a particular environment or material to the essential scope and spirit of the invention. The invention is not intended to be limited to the specific terminology used in the following claims and / or the specific embodiments disclosed as the best mode for carrying out the invention, but the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Therefore, the scope of the invention will be defined only by the appended claims.

Claims

1. An encoder signal channel selection board, characterized in that, At least including: An encoder signal input interface, wherein the encoder signal input interface comprises at least two, each of the encoder signal input interfaces being used to receive at least one set of first differential signals; A differential-to-single-ended signal chip, the number of which is the same as the number of encoder signal input interfaces, each of which is electrically connected to a differential signal output pin of one encoder signal input interface, and each of which is used to convert at least one set of the first differential signals received by the encoder signal input interface connected to it into a corresponding single-ended signal. A single-ended signal channel selection chip is electrically connected to the output terminal of the differential-to-single-ended signal chip. The single-ended signal channel selection chip is used to select at least one set of single-ended signals converted from a first differential signal received by an encoder signal input interface. A single-ended to differential signal chip is electrically connected to the output of the single-ended signal channel selection chip. The single-ended to differential signal chip is used to restore the selected single-ended signal into the corresponding second differential signal. The encoder signal output interface is connected to the output terminal of the single-ended to differential signal chip, and the second differential signal is output through the encoder signal output interface; The board also includes an external input interface, which includes two input terminals. Each input terminal includes a first sub-input terminal and a second sub-input terminal. The input terminal of each signal selection input circuit is connected to one of the first sub-input terminals and one of the second sub-input terminals, respectively. The output of the signal selection input circuit changes according to the level of the first sub-input terminal and the second sub-input terminal. The board also includes a signal selection control circuit. The input terminal of the signal selection input circuit is connected to an external input signal, and the output terminal of the signal selection input circuit is electrically connected to the gating control pin of the single-ended signal channel selection chip. The signal selection input circuit is used to control the channel selection of the single-ended signal channel selection chip, and is used to select out the single-ended signals corresponding to the differential signals in a certain encoder signal input interface channel.

2. The encoder signal channel selection board according to claim 1, characterized in that, The signal selection control loop includes two components. Each signal selection control loop includes a first resistor, a first diode, an optocoupler, a light-emitting diode, a first capacitor, and a second resistor. Specifically: The first end of the first resistor is connected to the first sub-input terminal, and the second end of the first resistor is connected to the negative terminal of the first diode and the first end of the optocoupler. The positive terminal of the first diode, the negative terminal of the light-emitting diode, and the second sub-input terminal are connected; The positive terminal of the light-emitting diode is connected to the second terminal of the optocoupler; The first terminal of the second resistor is connected to the power supply VCC; The fourth terminal of the optocoupler, the second terminal of the second resistor, and the first terminal of the first capacitor are connected; The third terminal of the optocoupler and the second terminal of the first capacitor are grounded. The fourth terminal of the optocoupler serves as the output terminal of the signal selection control loop.

3. The encoder signal channel selection board according to claim 1, characterized in that, When the first sub-input terminal is connected to a high voltage and the second sub-input terminal is connected to 0V, the output of the signal selection input circuit is a logic value of 1. When the first sub-input terminal is connected to a high voltage and the second sub-input terminal has no power input, the output of the signal selection input circuit is a logic value of 0.

4. The encoder signal channel selection board according to claim 1, characterized in that, The encoder signal gating board also includes a power supply circuit, through which externally input power supplies the circuitry inside the board.

5. The encoder signal channel selection board according to claim 4, characterized in that, The power supply circuit includes: Power connector, fuse, second diode, second capacitor, third capacitor, fourth capacitor, and inductor; The first end of the fuse is connected to the first connection port of the power connector, and the second end of the fuse is connected to the negative terminal of the diode, the positive terminal of the second capacitor, the first end of the third capacitor, and the first end of the inductor. The second end of the inductor and the first end of the fourth capacitor are connected to the internal power supply VCC. The second connection port of the power connector is connected to the positive terminal of the second diode, the negative terminal of the second capacitor, the second terminal of the third capacitor, and the second terminal of the fourth capacitor is grounded.

6. The encoder signal channel selection board according to claim 1, characterized in that, The board also includes an indicator light circuit, which is used to display the power status of the circuit.

7. The encoder signal channel selection board according to claim 1, characterized in that, The single-ended signal channel selection chip is model 74HC153.

8. The encoder signal channel selection board according to claim 1, characterized in that, The voltage value of the differential signal is half the voltage value of the single-ended signal converted from the differential signal.

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