Data transmission method and device, and chip verification system

Abstract

The present application provides a data transmission method and device, and a chip verification system. The data transmission method includes: obtaining a first data packet, the first data packet is a data packet transmitted from a sending node to a receiving node through a first transmission channel, the first transmission channel is a transmission channel of a first bus, the first transmission channel includes multiple first transmission sub-channels, each of the first transmission sub-channels transmits a different first data packet; converting the first data packet into a second data packet, the second data packet is a data packet of a type corresponding to the second bus, and the second bus has a second transmission channel; transmitting the second data packet based on the second transmission channel; before the second transmission channel outputs the second data packet, converting the second data packet into the first data packet; outputting the first data packet to the receiving node. Through the above method, the efficiency of data transmission can be improved, thereby improving the efficiency of chip verification.

Description

Technical Field

[0001] The present application relates to the field of data transmission, and more specifically, to a data transmission method and device, and a chip verification system. Background Art

[0002] The CHI (Coherent Hub Interface) bus is used for internal chip signal data transmission. It has multiple data transmission channels. During the chip's FPGA (Field-Programmable Gate Array) verification phase, the CHI bus is often used to implement data transmission between FPGAs due to FPGA capacity limitations.

[0003] Because the CHI bus carries numerous interactive signals, direct transmission consumes significant FPGA pin resources. Therefore, time-division multiplexing is often used to control data transmission between different FPGAs over the CHI bus. However, time-division multiplexing requires both data integrity and timing. Therefore, time-division multiplexing requires the FPGA clock to operate at a relatively low frequency. This low clock frequency reduces FPGA verification efficiency and makes verification impossible with data at higher bandwidth frequencies. Summary of the Invention

[0004] In view of this, the present application aims to provide a data transmission method and device, and a chip verification system to improve the transmission efficiency of bus-based data between different transmission nodes, thereby improving the verification efficiency of the chip.

[0005] In a first aspect, an embodiment of the present application provides a data transmission method, including: obtaining a first data packet, the first data packet being a data packet transmitted from a sending node to a receiving node through a first transmission channel, the first transmission channel being a transmission channel of a first bus, the first transmission channel including a plurality of first transmission sub-channels, each of the first transmission sub-channels transmitting a different data packet; converting the first data packet into a second data packet, the second data packet being a data packet of a corresponding type of a second bus, the second bus having a second transmission channel; transmitting the second data packet based on the second transmission channel; converting the second data packet into the first data packet before the second transmission channel outputs the second data packet; and outputting the first data packet to the receiving node.

[0006] When data is transmitted between different transmission nodes, each first data packet of the transmission node can be transmitted via the first bus and the second bus. This eliminates the need to use different pins for data transmission for different data types, reducing the requirements for chip pins for data transmission. Furthermore, by converting the first data packet transmitted in the transmission sub-channel of the first bus into a second data packet, and using the second transmission channel of the second bus to transmit the second data packet, it is no longer necessary to control the transmission timing of each of the multiple transmission sub-channels of the first bus and the second bus, thereby avoiding the impact of controlling the transmission timing on chip verification efficiency. This improves data transmission efficiency and avoids the impact of controlling the transmission timing on chip verification efficiency.

[0007] In one embodiment, after converting the first data packet into the second data packet, the method further includes: adjusting the frequency and bit width of the second data packet to the frequency and bit width corresponding to the second bus; correspondingly, before converting the second data packet into the first data packet, the method further includes: adjusting the frequency and bit width of the second data packet to the frequency and bit width corresponding to the first bus.

[0008] In an embodiment of the present application, by adjusting the frequency and bit width of the second data packet to the frequency and bit width corresponding to the second bus, the second data packet can be transmitted more efficiently on the second bus, thereby improving data transmission efficiency.

[0009] In one embodiment, obtaining the first data packet includes: obtaining a plurality of the first data packets from different first transmission sub-channels respectively, and converting the plurality of the first data packets into respective corresponding second data packets.

[0010] The method provided in the present application can simultaneously obtain first data packets transmitted on multiple first transmission sub-channels and convert them into corresponding second data packets. Multiple first transmission sub-channels are carried out simultaneously, thereby improving the efficiency of data transmission.

[0011] In one embodiment, after converting the first data packet into a second data packet, the method further includes: temporarily storing multiple second data packets corresponding to multiple first data packets; correspondingly, transmitting the second data packet based on the second transmission channel includes: controlling the corresponding multiple second data packets to be transmitted in sequence on the second transmission channel.

[0012] In an embodiment of the present application, the converted second data packet is temporarily stored so that after the second transmission channel completes transmission of the current second data packet, it can directly obtain the next second data packet for transmission, avoiding waiting for the first data packet to be converted into the second data packet before transmission, thereby reducing the delay caused by data conversion between the first data packet and the second data packet, thereby improving the efficiency of data transmission.

[0013] In one embodiment, before controlling the corresponding multiple second data packets to be transmitted sequentially on the second transmission channel, the method further includes: receiving a credit value fed back from the output end of the second transmission channel, the credit value being used to characterize the number of second data packets that can be received by the output end; correspondingly, controlling the corresponding second data packets to be transmitted sequentially on the second transmission channel includes: controlling the corresponding multiple second data packets to be transmitted sequentially on the second transmission channel based on the credit value.

[0014] In an embodiment of the present application, the credit value is used to characterize the number of second data packets that can be received by the output end, and the transmission of the second data packet on the second transmission channel is controlled according to the credit value fed back by the output end. Thus, multiple second data packets can be sent, thereby reducing the temporary storage time of the second data packet and improving data transmission efficiency.

[0015] In one embodiment, the second data packet is temporarily stored in a buffer, and the receiving of the credit value signal fed back by the output end of the second transmission channel includes: sending remaining storage space information of the buffer to the output end; receiving a current credit value fed back by the output end, where the current credit value is a signal value generated by the output end based on the remaining storage space information and a previous credit value, so as to control the corresponding second data packet to be transmitted sequentially on the second transmission channel based on the current credit value.

[0016] In an embodiment of the present application, the output end can generate a current credit value based on the remaining storage space information of the buffer. Thus, the output of the second data packet can be controlled according to the current credit value, which can effectively balance the time for temporary storage and conversion of the data packet by the buffer and the output end, so that data transmission can make full use of the buffer to improve data transmission efficiency.

[0017] In a second aspect, an embodiment of the present application provides a data transmission device, comprising: a sending module and a receiving module; a transmission module for acquiring a first data packet, wherein the first data packet is a data packet transmitted from a sending node to a receiving node through a first transmission channel, wherein the first transmission channel is a transmission channel of a first bus, wherein the first transmission channel includes multiple first transmission sub-channels, and each of the first transmission sub-channels transmits a different first data packet; a first conversion module for converting the first data packet into a second data packet, wherein the second data packet is a data packet of a type corresponding to a second bus, and the second bus has a second transmission channel; the transmission module for transmitting the second data packet based on the second transmission channel; a second conversion module; for converting the second data packet into the first data packet before the second transmission channel outputs the second data packet; the transmission module is also used to output the first data packet to the receiving node.

[0018] In one embodiment, before the second data packet is transmitted over the second transmission channel based on the second bus, the second data packet is temporarily stored in a buffer; the transmission module includes: a credit value unit, configured to send remaining storage space information of the buffer to the output end; and receive a current credit value fed back by the output end, where the current credit value is a signal value generated by the output end based on the remaining storage space information and a previous credit value, so that the transmission module controls the corresponding second data packets to be transmitted sequentially over the second transmission channel based on the current credit value.

[0019] In the third aspect, an embodiment of the present application provides a chip verification system, comprising: a verification unit, used to access the chip to be tested to verify the chip to be tested, a communication unit, connected to the verification unit, the communication unit comprising a first bus and a second bus, the communication unit being used to transmit data during the verification process of the chip to be tested by the verification unit; and a control unit, used to execute the data transmission method as described in any one of the first aspects.

[0020] In one embodiment, the first bus is a CHI bus, and the second bus is an AXI-Stream (Advanced Extensible Interface-Stream) bus.

[0021] Other features and advantages of the present disclosure will be set forth in the following description, or some features and advantages may be inferred or unambiguously determined from the description, or may be learned by practicing the above-mentioned technology of the present disclosure.

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments of the present invention are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A schematic diagram of cross-node data transmission provided in an embodiment of the present application;

[0025] Figure 2 A flowchart of a data transmission method provided in one embodiment of the present application;

[0026] Figure 3 A schematic diagram of a data transmission device provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of a chip verification system provided in an embodiment of the present application.

[0028] Icons: data transmission device 200; transmission module 210; first conversion module 220; second conversion module 230; control unit 310; communication unit 320; verification unit 330. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0030] See also Figure 1 , Figure 1 A schematic diagram of cross-node data transmission provided in an embodiment of the present application.

[0031] The transmission nodes are FPGAs that perform data transmission, and each transmission node can use the first bus to perform data transmission. The transmission node that sends data is called a sending node, and the data node that receives data is called a receiving node.

[0032] In this embodiment, the first bus is a transmission bus having multiple transmission channels. For example, the first bus may be a CHI bus. All transmission channels of the first bus are collectively referred to as first transmission channels, and each different transmission channel is referred to as a first transmission sub-channel. Each first transmission sub-channel can be used to transmit a different data packet sent by a sending node.

[0033] In some embodiments, indication information may be sent in the first transmission channel to indicate that a data packet will be transmitted. In some embodiments, information indicating whether a data packet is valid or invalid may be sent to indicate whether the receiving node needs to receive the data packet.

[0034] The second bus has a second transmission channel, and the second transmission channel is used to transmit data packets of a type corresponding to the second bus, that is, to transmit second data packets.

[0035] In this embodiment, the second transmission channel of the second bus and each first transmission sub-channel of the first bus have a higher transmission efficiency for data packets than the transmission efficiency of the first bus. For example, when the first bus is a CHI bus, the second bus may be an AXI-Stream bus. The transmission frequency and bit width of the AXI-Stream bus are greater than those of the CHI bus, so that the efficiency of data packet transmission on the AXI-Stream bus is greater than that on the CHI bus.

[0036] Next, the data output method of the present application will be described in combination with the first bus and the second bus.

[0037] See also Figure 2 , Figure 2 A flowchart of a data output method provided in an embodiment of the present application, the data output method comprising:

[0038] S110: Obtain a first data packet.

[0039] Please combine Figure 1 In this embodiment, the first data packet is a data packet sent by the sending node. Different data packets can be transmitted simultaneously on the first transmission sub-channels of the first bus. The data contents of the first data packets transmitted on different channels can be the same or different. The first data packets transmitted on different first transmission sub-channels can be sent in parallel via their corresponding FPGA pins.

[0040] Each first transmission sub-channel has a different transmission frequency or bit width. Therefore, in some embodiments, the transmission frequency and bit width of the first data packet transmitted in each first transmission sub-channel may also be different.

[0041] S120: Convert the first data packet into a second data packet.

[0042] In this embodiment, the second data packet is a data packet that can be transmitted on the second transmission channel of the second bus, that is, a data packet of a type corresponding to the second bus. For example, when the second bus is an AXI-Stream bus, the second data packet is an AXI-Stream data packet.

[0043] In this embodiment, for multiple first transmission sub-channels, the first data packets transmitted in each first transmission sub-channel can be converted into corresponding second data packets, so that each first data packet can be transmitted through the second transmission channel.

[0044] In one embodiment, after the first data packet is converted into the second data packet, the frequency and bit width of the second data packet may be adjusted to the frequency and bit width corresponding to the second bus.

[0045] After the conversion, the second data packet can be transmitted via the second transmission channel, eliminating the need for the transmitting node to separately control the timing of each first data sub-channel, thereby enabling the transmitting node to operate at a higher frequency. However, since different second data packets correspond to different first data packets, different first data packets may have different frequencies, bit widths, etc. when transmitted on different first transmission sub-channels. Consequently, the converted second data packets may also have different frequencies and bit widths.

[0046] However, the transmission speeds of second data packets with different frequencies and bit widths on the second transmission channel may be different and may not reach the optimal transmission speed. Therefore, the frequency and bit width of the second data packets can be adjusted, and each second data packet can be adjusted to the frequency and bit width corresponding to the second bus, so that each second data packet can achieve a better transmission speed on the second transmission channel, thereby improving the efficiency of data transmission.

[0047] In some embodiments, after converting the plurality of first data packets into the corresponding plurality of second data packets, each second data packet may be temporarily stored.

[0048] The first transmission channel has multiple first transmission sub-channels. Therefore, multiple first data packets may be converted into second data packets and transmitted simultaneously. However, there is only one second transmission channel, which cannot transmit multiple second data packets simultaneously. Therefore, in this embodiment, the second data packets can be temporarily stored so that each second data packet can be transmitted sequentially. A buffer can be used to temporarily store the second data packets. For example, a FIFO (First In First Out) buffer can be used.

[0049] S130: Transmit the second data packet based on the second transmission channel.

[0050] In this embodiment, after the first data packet is converted into the second data packet, the second data packet may be transmitted on the second transmission channel.

[0051] It can be understood that since there is only one second transmission channel, each transmission node does not need to control the transmission timing of each transmission channel, so that each node can operate at a higher frequency. Among them, the transmission frequency and bit width of the second bus are greater than the frequency and bit width of each first transmission sub-channel of the first bus. Therefore, even if the multi-channel transmission is changed to single-channel transmission, the multiple second data packets still have a higher transmission efficiency. For example, the first bus can be a CHI bus, and the CHI bus has 4 first transmission sub-channels; the second bus can be an AXI-Stream bus, and the AXI-Stream bus has 1 second data transmission channel. The ratio of the efficiency of the data transmission channel of the AXI-Stream bus and the data transmission channel of the CHI bus to each other for transmitting data can be 64:1 or 32:1, etc. Therefore, even if there is only one second transmission channel of the second bus, compared with the multiple first data packets being transmitted separately on multiple first transmission channels, the second data packets are still transmitted on the second transmission channel with higher efficiency. The above is only an example and should not be a limitation of this application.

[0052] When a plurality of second data packets need to be transmitted through the second transmission channel, the order in which the second data packets are transmitted on the second transmission channel may be determined according to some preset order rules.

[0053] For example, in some embodiments, the order of the first transmission sub-channels may be set so that the second transmission channel transmits the second data packets corresponding to the first data packets in sequence according to the order.

[0054] In some embodiments, the second data packets can also be transmitted according to the order in which they are converted, that is, the second data packets that are converted first are transmitted first, and the second data packets that are converted later are temporarily stored, and the second data packets with earlier conversion completion times are transmitted in sequence according to the conversion completion time.

[0055] In some embodiments, a buffer may be used to control the transmission data of the second data packet. For example, a FIFO buffer has a first-in-first-out feature, that is, the data first stored in the FIFO buffer is transmitted first.

[0056] It can be understood that there are multiple ways to control the transmission order of the second data packet on the second transmission channel, and different ways can be selected according to different situations. The above are only examples and should not be considered as limitations of this application.

[0057] At present, different pins of the transmission node are used to transmit different data. In this embodiment, all data transmitted by the sending node can be transmitted through the first bus, and after the first data packet is converted into the second data packet, all data can be transmitted through the second transmission channel. After the second transmission channel converts the second data packet into the first data packet, the receiving node can also receive the first data packet through the first bus. Therefore, the above method only needs to set the pins corresponding to the first bus for data transmission, avoiding the waste of pin resources caused by different data being directly transmitted using different transmission node pins.

[0058] S140 , before outputting the second data packet through the second transmission channel, convert the second data packet into a first data packet.

[0059] Since the receiving node uses the first bus to receive data packets, before the second transmission channel outputs the second data to the receiving node, the second data packets can be converted into first data packets, and then each first data packet can be distributed to its corresponding first transmission sub-channel so that the receiving node can process the first data packet.

[0060] In one embodiment, when converting a second data packet into a first data packet, identification information indicating the first transmission subchannel corresponding to the first data packet can be set for each first data packet. During distribution, the first data packets can be distributed according to the identification information, and the first data packets can be distributed to their respective corresponding first transmission subchannels. It is understood that in some other embodiments, other distribution methods can be set, for example, setting the first data packets to be distributed to the corresponding first transmission subchannels based on the transmission order, etc. The above is merely an example and should not be construed as limiting the present application.

[0061] In one embodiment, if the second data packet is adjusted to a frequency and a bit width corresponding to the second bus before being transmitted through the second data transmission channel, the second data packet can be adjusted to a frequency and a bit width corresponding to the first transmission sub-channel corresponding to the second data packet before being converted into the first data packet, so that after the second data packet is converted into the first data packet, the first data packet can be transmitted on the respective corresponding first transmission sub-channels.

[0062] S150: Output the first data packet to a receiving node.

[0063] After the first data packet is distributed to each first transmission sub-channel, it can be transmitted to the receiving node through the corresponding first transmission sub-channel.

[0064] In the above embodiment, the second transmission channel includes an input end and an output end. After the first data packet is converted into the second data packet, the second data packet is transmitted to the output end through the input end of the second transmission channel. After the second data packet is converted into the first data packet, the first data packet is output to each first transmission sub-channel through the output end.

[0065] The input end will continue to send the next second data packet only after the output end receives the second data packet. Before the output end outputs the data packet, the second data packet needs to be converted into the first data packet, and the conversion takes a certain amount of time. At this time, the output end can continue to receive the next second data packet, thereby reducing the delay caused by data conversion to data transmission and improving the efficiency of data transmission.

[0066] Therefore, in some embodiments, the output end may feedback a credit value, where the credit value is used to indicate the number of second data packets that the output end can receive. Thus, upon receiving the credit value feedback from the output end of the second transmission channel, the corresponding plurality of second data packets are controlled to be sequentially transmitted on the second transmission channel based on the credit value.

[0067] In this embodiment, the credit value can be used to determine the number of second data packets that the output end can currently receive, so that the second data packets are controlled to be transmitted sequentially on the second transmission channel according to the credit value, thereby eliminating the need to wait for the second data packet to convert the first data packet before receiving the next second data packet. As a result, the waiting time for receiving the second data packet can be reduced, thereby improving data transmission efficiency.

[0068] For example, the credit value can be a count value representing the number of data packets that can be received by the output end of the second transmission channel. For example, the output end may feedback a credit value of 3. Each time a second data packet is received, the feedback credit value decreases by 1 until it reaches 0. When the feedback credit value reaches 0, it indicates that no further second data packets can be received. When the output end converts a received second data packet into a first data packet and sends it, the credit value increases by 1.

[0069] It can be understood that the above credit value method is only an example. In actual settings, the credit value can also be in other forms and setting methods, which will not be elaborated here.

[0070] In some embodiments, when a buffer is used to temporarily store the second data packet at the input end of the second transmission channel, the buffer has a certain storage space, resulting in a limited storage capacity for the second data packet. When the storage space is insufficient, the second data packet cannot be temporarily stored any further.

[0071] Therefore, in some embodiments, the remaining storage space information of the buffer may also be sent to the output end. After receiving the remaining storage space information, the output end generates and feeds back a new credit value, i.e., the current credit value, based on the credit value fed back last time and the remaining storage space information. After receiving the current credit value, the output end may adjust the number of first data packets converted before the input end, thereby reducing the delay caused by data conversion.

[0072] For example, if the buffer currently stores 3 second packets, and the maximum number of second packets the buffer can store is 5, then the remaining storage space information is the maximum number of second packets the buffer can store minus the number of second packets currently stored, i.e., remaining storage space information = 5 - 3. The transmitted remaining storage space information is 2. If the previous credit value fed back by the output end is 3, the maximum number of second packets that the output end can temporarily store and convert is 5. Upon receiving the second packet, the output end also receives the remaining storage space information. Based on the remaining storage space information 2 and the previous credit value 3, a current credit value is generated. The current credit value can be any integer from 1 to 3. At this point, the output end can receive the second packets temporarily stored in the buffer, the input end can convert the first packet into a second packet, the buffer can temporarily store all the converted second packets, and send the stored second packets one by one to the output end. This reduces the waiting time for converting the first packet into the second packet. Furthermore, the output end now has sufficient second packets for conversion, eliminating the need to wait for receiving the second packet, thereby reducing the impact on data transmission efficiency at the output end.

[0073] By feeding back the credit value in the above manner, the transmission of multiple second data packets on the second transmission channel can be controlled, thereby reducing the delay caused by the conversion between the first data packet and the second data packet, thereby improving data transmission efficiency.

[0074] In an embodiment of the present application, when data is transmitted between different transmission nodes, each first data packet of the transmission node can be transmitted through the first bus and the second bus. As a result, there is no need to use different pins for data transmission for different data, thereby reducing the requirements for chip pins for data transmission. At the same time, by converting the first data packet transmitted on the multiple transmission sub-channels of the first bus into a second data packet, and using the second transmission channel of the second bus to transmit the second data packet, there is no need to control the transmission timing of each multiple transmission sub-channel of the first bus and the second bus, thereby avoiding the impact of controlling the transmission timing on the chip verification efficiency, thereby improving data transmission efficiency and avoiding the impact of controlling the transmission timing on the chip verification efficiency.

[0075] Based on the same inventive concept, the present application also provides a data transmission device. Figure 3 , Figure 3 This is a schematic diagram of a data transmission device provided in an embodiment of the present application. The data transmission device includes: a transmission module 210, a first conversion module 220 and a second conversion module 230.

[0076] The transmission module 210 is configured to obtain a first data packet.

[0077] Among them, the first data packet is a data packet transmitted by the sending node to the receiving node through the first transmission channel. The first transmission channel is the transmission channel of the first bus. The first transmission channel includes multiple first transmission sub-channels, and each first transmission sub-channel transmits a different first data packet.

[0078] The first conversion module 220 is configured to convert the first data packet into a second data packet, where the second data packet is a data packet of a type corresponding to the second bus, and the second bus has a second transmission channel.

[0079] The transmission module 210 is configured to transmit the second data packet based on the second transmission channel.

[0080] The second conversion module 230 is used to convert the second data packet into the first data packet before outputting the second data packet through the second transmission channel;

[0081] The transmission module 210 is further configured to output the first data packet to a receiving node.

[0082] In one embodiment, the first conversion module 220 is further configured to adjust the frequency and bit width of the second data packet to the frequency and bit width corresponding to the second bus. The second conversion module 230 is further configured to adjust the frequency and bit width of the second data packet to the frequency and bit width corresponding to the first bus.

[0083] In one embodiment, the transmission module 210 is configured to obtain a plurality of first data packets from different first transmission sub-channels, and the second conversion module 230 is configured to convert the plurality of first data packets into corresponding second data packets.

[0084] In one embodiment, the first conversion module 220 is further configured to temporarily store a plurality of second data packets corresponding to the plurality of first data packets. The transmission module 210 is further configured to control the corresponding plurality of second data packets to be transmitted sequentially on the second transmission channel.

[0085] In one embodiment, the transmission module 210 is further used to receive a credit value fed back from the output end of the second transmission channel, where the credit value is used to represent the number of second data packets that can be received by the output end; and the transmission module is further used to control the corresponding multiple second data packets to be transmitted sequentially on the second transmission channel based on the credit value.

[0086] In one embodiment, the transmission module 210 is further used to send the remaining storage space information of the buffer to the output end; receive the current credit value fed back by the output end, the current credit value being a signal value generated by the output end based on the remaining storage space information and the previous credit value, so as to control the corresponding second data packet to be transmitted in sequence on the second transmission channel based on the current credit value.

[0087] Based on the same inventive concept, the present application also provides a chip verification system. Figure 4 , Figure 4 This is a schematic diagram of a chip verification system provided in an embodiment of the present application. The chip verification system includes: a control unit 310, a communication unit 320 and a verification unit 330.

[0088] The verification unit 330 is used to access the chip to be tested to verify the chip to be tested.

[0089] In this embodiment, the verification unit 330 may include one or more verification circuits or devices, such as a signal generation circuit, a timing test circuit, etc. The chip to be tested may be verified by various verification circuits or devices.

[0090] In this embodiment, the verification unit 330 can be connected to multiple chips under test at the same time to achieve interactive verification between the multiple chips under test.

[0091] The communication unit 320 is connected to the verification unit 330. The communication unit includes a first bus and a second bus. The communication unit is used to transmit data during the verification process of the chip to be tested by the verification unit.

[0092] In this embodiment, the chip under test is a transmission node. Through the communication unit 320, verification data or other data of any pair of chips under test can be transmitted to another chip under test, thereby realizing data interaction between multiple chips under test, thereby realizing interactive verification between each chip under test.

[0093] In one embodiment, the first bus is a CHI bus, and the second bus is an AXI-Stream bus.

[0094] The control unit 310 is configured to control the transmission of data during the verification process of the chip under test based on the data transmission method in the above embodiment.

[0095] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0096] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A data transmission method, characterized in that: include: Obtaining a first data packet, where the first data packet is transmitted from a sending node to a receiving node via a first transmission channel, where the first transmission channel is a transmission channel of a first bus, and the first transmission channel includes a plurality of first transmission sub-channels, each of the first transmission sub-channels transmitting a different first data packet; Converting the first data packet into a second data packet, where the second data packet is a data packet of a type corresponding to a second bus, and the second bus has a second transmission channel; Transmitting the second data packet based on the second transmission channel; Before the second transmission channel outputs the second data packet, converting the second data packet into the first data packet; Outputting the first data packet to a receiving node; The obtaining of the first data packet comprises: obtaining a plurality of the first data packets from different first transmission sub-channels respectively, and converting the plurality of the first data packets into respective corresponding second data packets; After converting the first data packet into a second data packet, the method further includes: temporarily storing a plurality of the second data packets corresponding to the plurality of the first data packets; The transmitting the second data packet based on the second transmission channel includes: controlling the corresponding plurality of second data packets to be transmitted sequentially on the second transmission channel; Before controlling the corresponding multiple second data packets to be transmitted sequentially on the second transmission channel, the method further includes: receiving a credit value fed back from the output end of the second transmission channel, the credit value being used to represent the number of second data packets that can be received by the output end; correspondingly, controlling the corresponding multiple second data packets to be transmitted sequentially on the second transmission channel includes: controlling the corresponding multiple second data packets to be transmitted sequentially on the second transmission channel based on the credit value.

2. The method according to claim 1, characterized in that After converting the first data packet into a second data packet, the method further includes: adjusting the frequency and bit width of the second data packet to the frequency and bit width corresponding to the second bus; Correspondingly, before converting the second data packet into the first data packet, the method further includes: adjusting the frequency and bit width of the second data packet to the frequency and bit width corresponding to the first bus.

3. The method according to claim 1, characterized in that The second data packet is temporarily stored in a buffer, and the receiving of a credit value signal fed back from an output end of the second transmission channel includes: Sending remaining storage space information of the buffer to the output end; Receive a current credit value fed back by the output end, where the current credit value is a signal value generated by the output end based on the remaining storage space information and the previous credit value, so as to control the corresponding second data packets to be transmitted sequentially on the second transmission channel based on the current credit value.

4. A data transmission device, characterized in that: include: a transmission module, configured to obtain a first data packet, where the first data packet is transmitted from a sending node to a receiving node via a first transmission channel, where the first transmission channel is a transmission channel of a first bus, and the first transmission channel includes a plurality of first transmission sub-channels, each of the first transmission sub-channels transmitting a different first data packet; a first conversion module, configured to convert the first data packet into a second data packet, where the second data packet is a data packet of a type corresponding to a second bus, and the second bus has a second transmission channel; a transmission module, configured to transmit the second data packet based on the second transmission channel; a second conversion module; for converting the second data packet into the first data packet before outputting the second data packet through the second transmission channel; The transmission module is further configured to output the first data packet to a receiving node; Before the second data packet is transmitted via the second transmission channel of the second bus, the second data packet is temporarily stored in a buffer; The transmission module includes: a credit value unit, configured to send the remaining storage space information of the buffer to the output end; Receive a current credit value fed back by the output end, where the current credit value is a signal value generated by the output end based on the remaining storage space information and the previous credit value, so that the transmission module controls the corresponding second data packets to be transmitted sequentially on the second transmission channel based on the current credit value.

5. A chip verification system, characterized in that: include: A verification unit, configured to access the chip to be tested to verify the chip to be tested; a communication unit connected to the verification unit, the communication unit comprising a first bus and a second bus, and configured to transmit data during the verification process of the chip under test by the verification unit; A control unit is connected to the verification unit and the communication unit respectively, and the control unit is used to execute the method according to any one of claims 1 to 3.

6. The chip verification system according to claim 5, characterized in that: The first bus is a CHI bus, and the second bus is an AXI-Stream bus.

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