A vertical electrode-based 3D 1S1C memory and a preparation method thereof
By adopting a three-dimensional 1S1C memory structure based on vertical electrodes, the fabrication process is simplified, the production cost is reduced, and the problems of complex processes and high costs in existing technologies are solved, thus realizing the fabrication of high-density memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAZHONG UNIV OF SCI & TECH
- Filing Date
- 2022-12-26
- Publication Date
- 2026-05-19
AI Technical Summary
In the existing technology, the existing three-dimensional 1S1C memory fabrication process is complex and too costly, making it difficult to meet the demand for high-density memory.
A three-dimensional 1S1C memory structure based on vertical electrodes is adopted. By forming multiple vertical electrode layers on a substrate, the three-dimensional 1S1C memory formed by the vertical electrode layers simplifies the fabrication process and reduces the production cost.
This technology enables the fabrication of high-density memory, simplifies the fabrication process, reduces production costs, and avoids problems such as inaccuracy and high costs caused by multiple overlays.
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Figure CN115915758B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of memory, and more specifically, relates to a three-dimensional 1S1C memory based on vertical electrodes and its fabrication method. Background Technology
[0002] In the von Neumann architecture of computers, DRAM (Dynamic Random Access Memory) serves as the main memory, directly exchanging data with the CPU. Currently, the performance requirements for memory, including storage density, are increasingly demanding. However, traditional methods of increasing storage density through miniaturization are insufficient to meet the rapidly growing data processing needs. Developing a third-dimensional architecture to circumvent planar scaling limitations is a mainstream solution. However, because DRAM has a 1T1C structure (one transistor and one memory cell connected in series), it is a three-port device, making three-dimensional stacking difficult. The external control circuitry also consumes significant area, hindering the development of DRAM towards higher storage densities.
[0003] To address the issue of low DRAM storage density, the academic and industrial communities in the memory field have explored many new types of memory that could potentially replace DRAM. Among them, the Chinese invention patent CN202111280349.1 mentions a memory cell (1S1C cell) composed of an OTS gate transistor and a capacitor connected in series. This cell can rival DRAM in terms of read, write, and erase speeds as well as power consumption, making it a promising new memory technology to replace DRAM.
[0004] The main method for increasing memory density is through three-dimensional stacking. Currently, the industry-proposed three-dimensional 1S1C memory solution uses a crossbar structure. This structure requires overlaying and etching out a perforated structure for each additional memory cell, filling the perforated structure with functional layers (storage capacitors and gate transistors). This introduces problems such as inaccuracy and high cost due to multiple overlays. Furthermore, each layer requires a photomask, and the cost increases significantly with the number of stacked layers. Typically, after four stacked layers, the density gain from increasing the number of layers is less than the cost increase. Therefore, implementing a three-dimensional 1S1C memory based on a crossbar structure is complex, and the cost increases dramatically with the number of layers, limiting the theoretical stacking number of three-dimensional 1S1C memory. To fully leverage the advantage of easily achieving high-density storage through three-dimensional stacking of 1S1C memory, there is an urgent need to propose an easily implementable three-dimensional 1S1C memory structure and its fabrication method. Summary of the Invention
[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a three-dimensional 1S1C memory based on vertical electrodes, which aims to solve the problems of inaccuracy and high cost caused by multiple overlays due to the use of crossbar structure in the prior art to improve storage density.
[0006] This invention provides a three-dimensional 1S1C memory based on vertical electrodes. The three-dimensional 1S1C memory includes a peripheral electrode layer and a vertical selector functional layer. The peripheral electrode layer is formed on a substrate and consists of alternating layers of a first dielectric layer and a first metal electrode layer from bottom to top, with the top layer being the first dielectric layer. The peripheral electrode layer has a plurality of vertically penetrating trenches, which are parallel to each other and whose bottoms are located within the substrate. Each first metal electrode layer is divided into several independent strip electrodes by the trenches, and these strip electrodes serve as word lines for the memory. The peripheral electrode layer also has a plurality of vertically penetrating holes arranged in an array according to a certain pattern, with the bottom of each hole extending at least to the bottommost first dielectric layer. Each hole is connected to each layer... The first metal electrode layer is recessed inward at all contact points. A second dielectric layer is uniformly covered on the inner wall of the hole, and the second dielectric layer is also recessed inward accordingly. A second metal electrode is formed at the recessed part of the second dielectric layer. Several second metal electrodes formed in each hole are independent of each other. A gate tube functional layer is formed on the surface formed by the second dielectric layer and the second metal electrode. A third metal electrode layer is formed on the surface of the gate tube functional layer. The bottom of the third metal electrode layer and the gate tube functional layer is lower than the first metal electrode layer in the bottom layer in the vertical direction. The top of the third metal electrode layer extends to the surface of the first dielectric layer at the top layer to form a bit line electrode and is connected to the bit line. The area where the third metal electrode layer and the first metal electrode layer are directly opposite each other constitutes a memory cell.
[0007] Furthermore, the first dielectric layer and the first metal electrode layer, which are stacked alternately, are periodically repeated in the vertical direction as needed, and the number of repetitions is the same as the number of storage cell layers required by the three-dimensional 1S1C memory.
[0008] Furthermore, all memory cells growing in the same vertical hole share the same third metal electrode as the bit line electrode, and all memory cells located on the same strip electrode share the same word line electrode.
[0009] In this 3D 1S1C memory, different rows are separated, and bit line electrodes in the same column extend to the surface and are connected together by column bit lines. The bit line electrodes extend to the surface, leaving interfaces on the surface, and then the interfaces of the same column are connected together to form the bit lines of the memory. The word line electrodes of each memory cell are arranged in the horizontal direction, and the capacitor layer in each memory cell is a ring-shaped region. The gate transistor layer in each memory cell is the functional layer part corresponding to the capacitor layer.
[0010] Furthermore, the thickness of the first metal electrode layer and the size of the hole satisfy the following relationship: h*w < 1µm 2 , where h is the thickness of the first metal electrode layer and w is the perimeter of the hole.
[0011] Furthermore, the holes arranged in an array according to a certain pattern in the outer electrode layer can be arranged in a rectangular pattern or in a parallelogram pattern.
[0012] Furthermore, each thin film constituting the memory cell is a ring-shaped region, forming a concentric sleeve structure. The innermost layer is a columnar third metal electrode, followed by an annular gate tube film, a second metal electrode film, and a second dielectric film, with the second dielectric film surrounded and wrapped by the first metal electrode layer.
[0013] The present invention also provides a method for fabricating the above-described three-dimensional 1S1C memory, comprising the following steps:
[0014] S1 forms a peripheral electrode layer on the substrate of the memory cell area, including alternating growth of a first dielectric layer and a first metal electrode layer, wherein the number of the first metal electrode layers is the same as the number of memory cell layers required by the three-dimensional 1S1C memory.
[0015] S2 etching forms several vertical through holes, which are arranged in an array according to a certain pattern, and the bottom of the holes extends at least to the bottom first dielectric layer.
[0016] S3 selectively etches away the first metal electrode layer from the hole, leaving multiple longitudinal annular grooves on the sidewall of the hole. The number of grooves in each hole is the same as the number of layers of the first metal electrode layer.
[0017] S4 forms a second dielectric layer on the sidewalls and bottom of the hole, which serves as the dielectric layer of the capacitor. The second dielectric layer film will form a depression at the groove generated in step S3.
[0018] S5 forms a second metal electrode in the recess formed in step S4, and each second metal electrode is independent of the others;
[0019] S6 sequentially forms a gate tube functional layer and a third metal electrode layer in the hole. The third metal electrode layer extends to the surface of the top first dielectric layer and connects with the bit line.
[0020] S7 performs multiple etchings at the edges to expose each first metal electrode layer, forming a multi-layer electrode step.
[0021] S8 etching forms several vertically penetrating trenches that are parallel to each other and whose bottoms are located in the substrate. The trenches divide the outer electrode layer into several independent strip-shaped sections.
[0022] Furthermore, the material of the second dielectric layer is any one or a combination of SiO2 or high-k materials. High-k materials include, but are not limited to, nitrides such as SiN, AlN, TiN; metal oxides, primarily oxides of transition metals and lanthanides such as MgO, Al2O3, Ta2O5, TiO2, ZnO, ZrO2, HfO2, CeO2, Y2O3, La2O3; nitrogen oxides such as SiON, HfSiON; and perovskite phase oxides such as PbZrxTi1-xO3 (PZT) and BaxSr1-xTiO3 (BST).
[0023] Furthermore, the hole structure can be a square hole structure or a circular hole structure.
[0024] More preferably, the perforated upper electrode is a square or round hole.
[0025] More preferably, when using magnetron sputtering to deposit the gate layer and bit line electrode layer, in order to prevent excessive energy from damaging the photoresist, it is necessary to perform the process for a period of time and then stop for a period of time.
[0026] The three-dimensional 1S1C memory structure proposed in this invention only requires depositing all word line electrode layers, photolithographically etching a hole structure once, and filling the hole structure with functional material once to complete the fabrication of all memory cells. This greatly simplifies the fabrication process, reduces the number of photolithography steps, lowers production costs, and avoids problems such as inaccuracy and high costs caused by multiple overlay etching.
[0027] The three-dimensional 1S1C memory structure proposed in this invention only requires increasing the number of word line electrode layers and isolation layers, without changing any other fabrication steps, to increase the number of storage cell layers of the three-dimensional 1S1C memory. Therefore, there is theoretically no limit to the number of three-dimensional stacked layers of the memory based on this structure. Attached Figure Description
[0028] Figure 1 This is a structural diagram of a three-dimensional 1S1C memory based on vertical electrodes provided in an embodiment of the present invention;
[0029] Figure 2 This is a flowchart of the fabrication process of a three-dimensional 1S1C memory based on vertical electrodes provided in an embodiment of the present invention.
[0030] In the figure, 1 is the first metal electrode layer, 2 is the first dielectric layer, 3 is the second dielectric layer, 4 is the second metal electrode, 5 is the gate transistor functional layer, and 6 is the third metal electrode layer. Detailed Implementation
[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0032] This invention proposes a structure and fabrication method for a three-dimensional 1S1C memory. First, all word line electrode layers of the memory are deposited. Then, through-holes are etched in the word line electrode layers by a single photolithography etching, which is equivalent to etching out the electrodes that contact each memory cell with the word line electrode layer. At this point, only the capacitor layer, the selector layer, and the bit line electrode layer need to be deposited once to complete the fabrication of all memory cells of the three-dimensional memory. This simplifies the fabrication process of the three-dimensional memory, reduces the fabrication cost, and theoretically allows for an unlimited number of stacked layers.
[0033] Figure 1 The diagram shows a three-dimensional 1S1C memory structure based on vertical electrodes provided in this embodiment of the invention. The bottom layer is a first dielectric layer 2 grown on a substrate. On the first dielectric layer 2, word line electrode layers (first metal electrode layer 1) and the first dielectric layer 2 are grown alternately. The number of memory cell layers required to fabricate the three-dimensional 1S1C memory is determined by the number of times the word line electrode layers and the first dielectric layer need to be grown.
[0034] The peripheral electrode layer contains several vertically penetrating trenches that are parallel to each other and whose bottoms are located in the substrate. The trenches divide the peripheral electrode layer into several blocks, and each word line electrode layer in the block is a word line.
[0035] Each block contains a row of holes that penetrate the outer electrode layer vertically. The array of holes is arranged according to a specific pattern, with the bottom of each hole extending at least to the bottommost first dielectric layer 2. The sidewalls of the holes form inward-facing annular grooves where they contact the word line electrode layer, serving as the bottom electrode of the capacitor. A second dielectric layer 3 is uniformly covered on the surface of the holes, acting as the capacitor's dielectric. The formed second dielectric layer 3 film also indents inward at the annular grooves, with a second metal electrode 4 filling each groove, serving as the top electrode of the capacitor and the corresponding memory cell. In the storage node, the second metal electrodes 4 of different layers in the hole are independent of each other, that is, the capacitance of each storage cell is independent of each other. A gate layer film 5 is formed on the sidewall formed by the second metal electrode 4 and the second dielectric layer 3. The hole depression formed by the gate layer film 5 is filled by the third metal electrode layer 6. The top of the third metal electrode layer 6 extends to the surface of the top first dielectric layer 2 and is connected to the bit line. The bottom of the third metal electrode layer 6 and the gate layer 5 is lower than the bottom first metal electrode layer in the vertical direction to ensure that each storage cell can have performance.
[0036] The area directly opposite the third metal electrode layer 6 and the word line electrode layer 1 constitutes a memory cell. When the memory cell is operated, the corresponding word line and bit line are selected. A voltage difference is formed between the top electrode and the bottom electrode of the memory cell by applying voltage to the word line and the bit line. This causes the thin film area of the selection tube layer in the area directly opposite the two electrodes to be turned on, and the capacitor of the memory cell is charged and discharged to realize the data writing and reading process.
[0037] Figure 1 All parts of the same color have the same numerical label, indicating they are made of the same material.
[0038] The holes that penetrate the outer electrode layer can be circular or square.
[0039] The thickness of the first metal electrode layer and the size of the pores satisfy the following relationship: h*w<1um 2 Where h is the thickness of the first metal electrode layer and w is the perimeter of the hole. This is to ensure that the size of the effective selection tube area facing the top and bottom electrodes in the memory cell conforms to the aperture size that the selection tube can work on.
[0040] The holes in the outer electrode layer are arranged in an array according to a certain pattern. They can be arranged in a rectangular pattern or in a parallelogram pattern. The purpose of this is to make it easier to etch through trenches to form bit lines and to make it easier to connect the memory cells to the top.
[0041] Each layer of the memory cell is a ring-shaped region, forming a concentric sleeve structure. The innermost layer is a columnar third metal electrode, followed by a ring-shaped gate tube film, a second metal electrode film, and a second dielectric film. The second dielectric film is surrounded and wrapped by the first metal electrode layer.
[0042] Figure 2 This invention illustrates a method for fabricating a three-dimensional 1S1C memory based on vertical electrodes, specifically including the following steps:
[0043] like Figure 2 As shown in (a), a first dielectric layer and a metal electrode material are alternately grown on a substrate, wherein the dielectric layer is 100 nm thick and the metal electrode is 75 nm thick, until the desired number of layers is reached. Deposition processes include, for example, LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, etc. For compatibility with existing IC manufacturing processes, the substrate is preferably a silicon-containing substrate, such as Si, SiO2, etc. The material of the insulating layer stack structure includes at least one of the following insulating media: silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, diamond-like carbon (DLC), germanium oxide, aluminum oxide, etc., and combinations thereof. For compatibility with existing IC manufacturing processes, SiO2 is preferentially selected as the insulating layer medium.
[0044] like Figure 2 As shown in (b), a columnar hole structure and cylindrical through-holes with a diameter of 4 μm were etched onto the prepared wafer using ultraviolet light. The etching process requires anisotropic etching, such as using a fluorocarbon-based (C) etching process. x H y F z Plasma dry etching or RIE (using fluorinated hydrocarbons as the etching gas) is used to etch alternating insulating and metal layers vertically downwards until the bottom metal electrode is completely etched. The photoresist is then stripped off. An upper electrode, larger than the area of the via, is then etched onto the columnar hole structure. Only the photoresist is developed; it is not stripped off immediately. The resulting columnar hole structure is centered on the upper electrode. The cross-sectional shape parallel to the substrate can be rectangular, square, rhomboid, circular, or other geometric shapes.
[0045] like Figure 2 As shown in (c), the metal word line electrode layer is selectively etched, causing a portion of the word line metal electrode in the via to be etched inward to form a groove. Since the material of the word line electrode layer is a metal material, while the material of the insulating layer is a dielectric such as silicon dioxide, there is a high etching selectivity between the electrode layer and the upper and lower layers. Therefore, an isotropic etching process can be used to perform lateral etching on the electrode layer to form a groove of a certain depth. The groove depth needs to be sufficient to deposit the dielectric layer and the top electrode of the capacitor.
[0046] like Figure 2 As shown in (d), a high-k dielectric layer is grown on the prepared wafer to serve as the dielectric layer for the capacitor. Due to the deep via depth, the high-k dielectric layer must be deposited using the ALD process. Furthermore, to reduce the thickness of the capacitor dielectric layer, a high-k dielectric is used. High-k materials include, but are not limited to, nitrides (e.g., SiN, AlN, TiN), metal oxides (mainly transition metal and lanthanide oxides, such as MgO, Al2O3, Ta2O5, TiO2, ZnO, ZrO2, HfO2, CeO2, Y2O3, La2O3), oxynitrides (e.g., SiON, HfSiON), and perovskite oxides (e.g., PbZrxTi1-xO3(PZT), BaxSr1-xTiO3(BST)). For compatibility with existing IC manufacturing processes, HfO2 is preferentially chosen as the dielectric for the insulating layer.
[0047] like Figure 2 As shown in (e), the top electrode metal layer of the capacitor is grown on the prepared wafer. Due to the deep via depth, a PECVD process is required to deposit the top electrode metal layer. Furthermore, to prevent the metal top electrode from becoming interconnected, it is necessary to... Figure 2 As shown in (f), the metal layer of the grown capacitor top electrode is etched until the metal layer in the vertical via is completely etched, leaving only the electrode metal in the groove.
[0048] like Figure 2 As shown in (g), a gate material functional layer is deposited in the via using methods such as magnetron sputtering. This functional layer needs to be made of a material with gate properties, such as OTS, MIT, CBTS and other gate devices with threshold conduction phenomena.
[0049] like Figure 2 As shown in (h), a bit line electrode layer is deposited in the through hole using magnetron sputtering. The electrode prepared needs to extend to the device surface.
[0050] Ultraviolet lithography is performed to etch grooves, exposing the topmost word line electrode metal. This process is then repeated the same number of times as the word line electrode layers, with each etching depth greater than the previous one, and the grooves positioned closer to the edge of the top electrode, until all bottom electrode metals are exposed sequentially. This process is repeated to fabricate a structure as shown in the image. Figure 1 The stepped word line electrode in the middle.
[0051] Ultraviolet lithography is performed to etch grooves, which are then filled with insulating material. The bottom of the grooves is at least the bottommost first dielectric layer. The grooves divide each word line electrode layer into several independent word lines, such as... Figure 1 As shown.
[0052] Ultraviolet lithography is performed to etch the bit line electrode structure in the same column. Only the photoresist is developed, and a bit line electrode metal layer is deposited using magnetron sputtering. Then, the spin-coated photoresist is stripped off; thus, a structure is fabricated as shown in the image. Figure 1 The column line electrode in the middle.
[0053] After the above steps, the fabrication of a three-layer 1S1C memory based on vertical electrodes can be completed.
[0054] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A three-dimensional 1S1C memory based on vertical electrodes, characterized in that, The three-dimensional 1S1C memory includes a peripheral electrode layer and a vertical gate functional layer: The peripheral electrode layer is formed on the substrate and consists of alternating stacks of a first dielectric layer and a first metal electrode layer from bottom to top, with the top layer being the first dielectric layer. The peripheral electrode layer has a number of vertically penetrating trenches, which are parallel to each other and the bottom of the trenches are located in the substrate. Each first metal electrode layer is divided into a number of independent strip electrodes by the trenches, and the strip electrodes are the word lines of the memory. The outer electrode layer is provided with a number of holes that penetrate vertically. The holes are arranged in an array according to a certain pattern, and the bottom of the holes extends at least to the bottommost first dielectric layer. Each hole is recessed inward at the point of contact with the first metal electrode layer in each layer. A second dielectric layer is uniformly covered on the inner wall of the hole, and the second dielectric layer is also recessed inward accordingly. A second metal electrode is formed at the recessed part of the second dielectric layer. Several second metal electrodes formed in each hole are independent of each other. A gate tube functional layer is formed on the surface formed by the second dielectric layer and the second metal electrode. A third metal electrode layer is formed on the surface of the gate tube functional layer. The bottom of the third metal electrode layer and the bottom of the gate tube functional layer are lower than the first metal electrode layer in the bottom layer in the vertical direction. The top of the third metal electrode layer extends to the surface of the first dielectric layer at the top layer to form a bit line electrode and is connected to the bit line. The area where the third metal electrode layer and the first metal electrode layer are directly opposite each other constitutes a memory cell.
2. The three-dimensional 1S1C memory as described in claim 1, characterized in that, The alternating stacked first dielectric layer and first metal electrode layer are periodically repeated in the vertical direction as needed, and the number of repetitions is the same as the number of storage cell layers required by the three-dimensional 1S1C memory.
3. The three-dimensional 1S1C memory as described in claim 1, characterized in that, All memory cells growing in the same vertical hole share the same third metal electrode as the bit line electrode, and all memory cells located on the same strip electrode share the same word line electrode.
4. The three-dimensional 1S1C memory as described in claim 1, characterized in that, The thickness of the first metal electrode layer and the size of the hole satisfy the following relationship: h w<1um 2 , where h is the thickness of the first metal electrode layer and w is the perimeter of the hole.
5. The three-dimensional 1S1C memory as described in claim 1, characterized in that, The holes in the outer electrode layer are arranged in an array according to a certain pattern, and the arrangement is either rectangular or parallelogram-shaped.
6. The three-dimensional 1S1C memory as described in claim 1, characterized in that, Each of the thin films constituting the memory cell is a ring-shaped region, forming a concentric sleeve structure. The innermost layer is a columnar third metal electrode, followed by a ring-shaped gate tube film, a second metal electrode film, and a second dielectric film. The second dielectric film is surrounded and wrapped by the first metal electrode layer.
7. A method for fabricating a three-dimensional 1S1C memory based on any one of claims 1-6, characterized in that, Includes the following steps: S1 forms a peripheral electrode layer on the substrate of the memory cell area, including alternating growth of a first dielectric layer and a first metal electrode layer, wherein the number of the first metal electrode layers is the same as the number of memory cell layers required by the three-dimensional 1S1C memory. S2 etching forms several vertical through holes, which are arranged in an array according to a certain pattern, and the bottom of the holes extends at least to the bottom first dielectric layer. S3 selectively etches away the first metal electrode layer from the hole, leaving multiple longitudinal annular grooves on the sidewall of the hole. The number of grooves in each hole is the same as the number of layers of the first metal electrode layer. S4 forms a second dielectric layer on the sidewalls and bottom of the hole, which serves as the dielectric layer of the capacitor. The second dielectric layer film will form a depression at the groove generated in step S3. S5 forms a second metal electrode in the recess formed in step S4, and each second metal electrode is independent of the others; S6 sequentially forms a gate tube functional layer and a third metal electrode layer in the hole. The third metal electrode layer extends to the surface of the top first dielectric layer and connects with the bit line. S7 performs multiple etchings at the edges to expose each first metal electrode layer, forming a multi-layer electrode step. S8 etching forms several vertically penetrating trenches that are parallel to each other and whose bottoms are located in the substrate. The trenches divide the outer electrode layer into several independent strip-shaped sections.
8. The preparation method according to claim 7, characterized in that, The material of the second dielectric layer is any one or a combination of SiO2 or a high-k material.
9. The preparation method according to claim 8, characterized in that, The high-k materials include: SiN, AlN, TiN, MgO, Al2O3, Ta2O5, TiO2, ZnO, ZrO2, HfO2, CeO2, Y2O3, La2O3, SiON, HfSiON, PbZrxTi1-xO3 (PZT) or BaxSr1-xTiO3 (BST).
10. The preparation method according to claim 7, characterized in that, The hole structure can be a square hole structure or a circular hole structure.