Secondary cross-coupling effects in memory devices with semi-circular drain side select gates and countermeasures

Abstract

A memory device and method of operation are provided. The memory device includes memory cells connected to word lines and arranged in strings. The memory cells are configured to hold threshold voltages corresponding to memory states. Each of the strings has a drain-side select gate transistor on a drain-side of the one of the strings, the one of the strings including a top drain-side select gate transistor connected to a bit line and coupled to the memory cells of the one of the strings. A control device is coupled to the word lines and the bit lines and configured to, during a memory operation, apply an unselected top voltage to unselected ones of the top drain-side select gate transistors. The control device is further configured to, during the memory operation, simultaneously apply a selected top voltage to selected ones of the top drain-side select gate transistors. The unselected top voltage is intentionally different, electrically, from the selected top voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to non-volatile memory devices and operations of non-volatile memory devices. BACKGROUND

[0002] This section provides background information relating to the technical field of the disclosure and as such is not necessarily prior art.

[0003] Semicircular drain side select gate ("SC-SGD") memory technology provides several advantages, including reduced die size. To produce SC-SGDs, etching techniques are used to cut memory holes, thereby imparting them with a semicircular shape and dividing the blocks or rows into several strings. Depending on the process used to form SC-SGDs, certain inefficiencies can arise. For example, cutting the memory holes will remove at least some portions of the SC-SGD, such as metal layers, that otherwise shield the channel and / or charge trapping layer from electric fields. As a result, the SC-SGDs can be affected by "adjacent" electric fields, causing parasitic transistors to leak along the SC-SGD transistors. In some cases, this causes the sense amplifier to falsely determine that the SC-SGD is turning on, which can impact certain sensing operations. Additionally, due to etching variations, some dies can be cut into the SGD layer while others can be cut into the layer that forms a dummy word line. As a result, known electric fields, such as those introduced by a weak erase bias on the dummy word line, distort (e.g., shift downward) the threshold voltage of the SC-SGD, thereby changing the overall threshold voltage of the memory structure. Accordingly, there is a need for improved non-volatile memory devices and methods of operation. SUMMARY

[0004] This section provides a general overview of the disclosure and is not a comprehensive disclosure of its full scope or all of its features and advantages.

[0005] It is an object of the present disclosure to provide memory devices and methods of operating the memory devices that address and overcome the above-mentioned disadvantages.

[0006] Accordingly, one aspect of the present disclosure is to provide an apparatus including memory cells connected to one of a plurality of word lines and arranged in strings. The memory cells are each configured to hold a threshold voltage. Each of the strings has a plurality of drain side select gate transistors on a drain side of the one of the strings, the one of the strings including one of a plurality of top drain side select gate transistors. The plurality of top drain side select gate transistors are connected to one of a plurality of bit lines and coupled to the memory cells of the one of the strings. A control apparatus is coupled to the plurality of word lines, the plurality of bit lines, and the plurality of drain side select gate transistors, and configured to apply an unselected top voltage to unselected ones of the plurality of top drain side select gate transistors during a memory operation. The control apparatus is further configured to simultaneously apply a selected top voltage to selected ones of the plurality of top drain side select gate transistors during the memory operation. The unselected top voltage is intentionally different in electrical from the selected top voltage.

[0007] According to another aspect of the present disclosure, a controller in communication with a memory apparatus including memory cells connected to one of a plurality of word lines and arranged in strings is also provided. The memory cells are each configured to hold a threshold voltage. Each of the strings has a plurality of drain side select gate transistors on a drain side of the one of the strings, the one of the strings including one of a plurality of top drain side select gate transistors. The plurality of top drain side select gate transistors are connected to one of a plurality of bit lines and coupled to the memory cells of the one of the strings. The controller is configured to instruct the memory apparatus to apply an unselected top voltage to unselected ones of the plurality of top drain side select gate transistors during a memory operation. The controller is further configured to simultaneously instruct the memory apparatus to apply a selected top voltage to selected ones of the plurality of top drain side select gate transistors during the memory operation, the unselected top voltage being intentionally different in electrical from the selected top voltage.

[0008] According to additional aspects of the present disclosure, a method of operating a memory device is provided. The memory device includes memory cells connected to one of a plurality of word lines and arranged in strings. The memory cells are each configured to hold a threshold voltage. Each of the strings has a plurality of drain side select gate transistors on a drain side of the one of the strings, the one of the strings including one of a plurality of top drain side select gate transistors. The plurality of top drain side select gate transistors are connected to one of a plurality of bit lines and coupled to the memory cells of the one of the strings. The method includes the step of applying an unselected top voltage to an unselected one of the plurality of top drain side select gate transistors during a memory operation. The method also includes the step of simultaneously applying a selected top voltage to a selected one of the plurality of top drain side select gate transistors during the memory operation, the unselected top voltage intentionally different in an electrical sense from the selected top voltage.

[0009] Additional areas of applicability will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0010] The drawings described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0011] Figure 1A is a block diagram of an exemplary memory device in accordance with aspects of the present disclosure;

[0012] Figure 1B is a block diagram of an exemplary control circuit including a program circuit, a count circuit, and a determination circuit in accordance with aspects of the present disclosure;

[0013] Figure 2 shows a schematic diagram of three types of memory architectures utilizing interleaved memory strings in accordance with aspects of the present disclosure;

[0014] Figure 3A shows a cross-sectional view of an exemplary floating gate memory cell in a NAND string in accordance with aspects of the present disclosure;

[0015] Figure 3B shows a cross-sectional view along a contact line shown in Figure 3A ;

[0016] Figure 4A and Figure 4BNon-volatile memory is shown in which charge-trapping memory cells store charge in a non-volatile manner using a non-conductive dielectric material in place of a conductive floating gate;

[0017] Figure 5 An exemplary block diagram of the sensing block of FIG. 1 is shown in accordance with aspects of the present disclosure;

[0018] Figure 6A A perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of FIG. 1 is shown in accordance with aspects of the present disclosure;

[0019] Figure 6B An exemplary cross-sectional view of a portion of one of the blocks of FIG. 1 is shown in accordance with aspects of the present disclosure; Figure 6A

[0020] Figure 6C An exemplary cross-sectional view of a portion of one of the blocks of FIG. 1 is shown in accordance with aspects of the present disclosure; Figure 6B A plot of memory hole diameters in the stack of FIG. 1 is shown in accordance with aspects of the present disclosure;

[0021] Figure 6D A close-up view of a region of the stack of FIG. 1 is shown in accordance with aspects of the present disclosure; Figure 6B A close-up view of a region of the stack of FIG. 1 is shown in accordance with aspects of the present disclosure;

[0022] Figure 7A A schematic plan view of a memory array having a plurality of memory holes is shown in accordance with aspects of the present disclosure;

[0023] Figure 7B A cross-sectional view of a memory array is shown in accordance with aspects of the present disclosure;

[0024] Figure 8A and Figure 8B An alternative memory structure without dummy holes is shown in accordance with aspects of the present disclosure;

[0025] Figure 9 An embodiment of a memory array having memory holes is shown in accordance with aspects of the present disclosure, in which the memory holes are cut to different sizes based on SHE cut operations;

[0026] Figure 10 A memory structure showing a number of memory holes cut by SHE is shown in accordance with aspects of the present disclosure;

[0027] Figure 11 A plot showing Vt distribution of a memory structure having memory holes is shown in accordance with aspects of the present disclosure;

[0028] Figure 12 A circuit diagram showing transistors for a selected gate and unselected gates is shown in accordance with aspects of the present disclosure; ​

[0029] Figure 13 Cross-sectional views of adjacent selected strings and unselected strings including drain side select gate SGD transistors associated with memory holes cut by SHE and resulting NSI and NCC effects are shown in accordance with aspects of the present disclosure;

[0030] Figure 14 Another cross-sectional view of adjacent selected strings and unselected strings including drain side select gate transistors associated with memory holes cut by SHE and a corresponding top view of a portion of a memory device are shown in accordance with aspects of the present disclosure;

[0031] Figure 15 Threshold voltage distributions of half-circle drain side select gate transistors and full-circle drain side select gate transistors are shown in accordance with aspects of the present disclosure;

[0032] Figure 16 Lower tail threshold voltages of threshold voltages of half-circle drain side select gate transistors and full-circle transistors are shown in accordance with aspects of the present disclosure;

[0033] Figure 17A Another cross-sectional view of adjacent selected strings and unselected strings including drain side select gate transistors associated with memory holes cut by SHE during a program operation and a corresponding top view of a portion of a memory device are shown in accordance with aspects of the present disclosure;

[0034] Figure 17B Corresponding perspective views of adjacent selected strings and unselected strings of Figure 17A including multiple drain side select gate transistors coupled to one of a plurality of bit lines during a program operation are shown in accordance with aspects of the present disclosure;

[0035] Figure 18A Another cross-sectional view of adjacent selected strings and unselected strings including drain side select gate transistors associated with memory holes cut by SHE during a read operation and a corresponding top view of a portion of a memory device are shown in accordance with aspects of the present disclosure;

[0036] Figure 18B Corresponding perspective views of adjacent selected strings and unselected strings of Figure 18A including drain side select gate transistors coupled to a bit line during a read operation are shown in accordance with aspects of the present disclosure;

[0037] Figure 19AAnother cross-sectional view of adjacent selected and unselected strings according to various aspects of the present disclosure and a corresponding top view of a portion of a memory device are shown, the adjacent selected and unselected strings including drain-side selected gate transistors associated with memory holes cut by SHE during programming operations, wherein the unselected top voltage is electrically isolated from the selected top voltage.

[0038] Figure 19B The various aspects shown in this disclosure are as follows Figure 19A A perspective view of adjacent selected and unselected strings, which include drain-side selected-gate transistors with different unselected top voltages and selected top voltages coupled to the bit line during programming operation;

[0039] Figure 20A Another cross-sectional view of adjacent selected strings and unselected strings according to various aspects of the present disclosure and a corresponding top view of a portion of a memory device are shown, the adjacent selected strings and unselected strings including drain-side selected gate transistors associated with memory holes cut by SHE during one of the read and verification operations, wherein the unselected top voltage is electrically separated from the selected top voltage.

[0040] Figure 20B The various aspects shown in this disclosure are as follows Figure 20A A perspective view of adjacent selected and unselected strings, which include drain-side selected-gate transistors with different unselected top voltages and selected top voltages coupled to the bit line during one of the read and verification operations.

[0041] Figure 21 The threshold voltage distribution of a top-drain-side selected gate transistor with relatively low and high threshold voltages, and the corresponding upper-tail threshold voltage, are shown according to various aspects of this disclosure.

[0042] Figure 22 and Figure 23 Exemplary groups of strings according to various aspects of this disclosure are shown, along with the corresponding NCC and NSI effects when these strings are selected; and

[0043] Figure 24 and Figure 25 The steps of a method for operating a memory device according to various aspects of this disclosure are shown.

[0044] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the accompanying drawings. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0045] In the following description, details are set forth to provide an understanding of the disclosure. In some instances, certain circuitry, structures, and techniques have not been described in detail or have been omitted so as not to obscure the disclosure.

[0046] In general, the present disclosure relates to non-volatile memory devices of the type that are well suited for many applications. The non-volatile memory devices and associated methods of operation of the present disclosure will be described in connection with one or more example embodiments. However, the specific example embodiments disclosed are merely for the purposes of clarity and to allow for a thorough and enabling disclosure of the present disclosure. Specifically, the example embodiments are provided so that this disclosure will be thorough and fully convey the scope of the disclosure to those skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods to provide a thorough understanding of embodiments of the present disclosure. Those skilled in the art will recognize that the example embodiments can be practiced without one or more of the specific details or with other methods, components, devices, etc. In some instances, well-known processes, well-known device structures, and well-known technologies are not described in detail in order to avoid obscuring the present disclosure. The present disclosure relates to non-volatile memory devices and methods of operation of the same. The non-volatile memory devices can be used in a variety of electronic devices, such as personal computers, digital televisions, digital recording devices, digital media players, video gaming devices, cellular telephones, wireless communication devices, and many other devices. The non-volatile memory devices can be used in a variety of applications, such as memory cards, solid state drives, and many other applications.

[0047] In some memory devices or apparatuses, memory cells are joined to one another, such as in NAND strings in a block or sub-block. Each NAND string includes a plurality of memory cells connected in series between one or more drain side select gate (SGD) transistors on a drain side of the NAND string connected to a bit line and one or more source side select gate (SGS) transistors on a source side of the NAND string connected to a source line. In addition, the memory cells can be arranged with a common control gate line (e.g., word line) that functions as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. The memory cells can be connected in other types of strings, and can also be connected in other ways.

[0048] In 3D memory structures, memory cells can be arranged in vertical strings in a stack, where the stack includes alternating conductive layers and dielectric layers. The conductive layers function as word lines connected to the memory cells. The memory cells can include data memory cells that are eligible to store user data, and dummy memory cells or non-data memory cells that are not eligible to store user data.

[0049] Prior to programming certain non-volatile memory devices, the memory cells are typically erased. For some devices, the erase operation removes electrons from the floating gates of the erased memory cells. Alternatively, the erase operation removes electrons from the charge trapping layer.

[0050] Each memory cell can be associated with a data state according to write data in a program command. Based on the data state of the memory cell, the memory cell will remain in an erased state or be programmed to a programmed data state. For example, in a three-bit-per-cell memory device, there are eight data states, including an erased state and programmed states.

[0051] During a program operation, memory cells are programmed according to a word line programming order. For example, programming can start from a word line on the source side of the block and proceed to a word line on the drain side of the block. In one approach, programming of each word line is completed before programming of the next word line. For example, a first word line WL0 is programmed using one or more program pulses until programming is complete. Next, a second word line WL1 is programmed using one or more program pulses until programming is complete, and so on. A program pulse can include a set of increasing program voltages that are applied to the word line in a corresponding program cycle or program-verify iteration. A verify operation or phase can be performed after each program voltage to determine whether a memory cell has completed programming. When programming of a memory cell is complete, the memory cell can be inhibited from further programming while programming of other memory cells continues in subsequent program cycles.

[0052] When forming various rows and strings for a memory structure, a cut operation (e.g., a shallow hole etch or SHE) can be used. The SHE cut can divide a block (in memory) into multiple strings within the block. While the SHE can form / define the strings, the SHE cut can further separate the strings, i.e., cut the edge memory hole in the string in half (or approximately two equal halves). In this regard, both the SGD and the channel are separated. However, as the cell is cut, the multi-channel is exposed to the adjacent SGD electric field. During a memory operation (i.e., a NAND operation), the channel region proximate to the adjacent SGD can easily turn on, which can result in a “SGD downshift.” Specifically, a half-circle SGD (SC-SGD) shows a lower threshold voltage Vt compared to a full-circle SGD (FC-SGD), resulting in a wider SGD threshold voltage Vt distribution. This effect is referred to as a “neighbor SGD interference effect” (NSI). In addition, there is also a neighbor cross-coupling (NCC) effect, where a secondary neighbor SGD T / dummy can cross-couple to the SGD layer. Such NSI and NCC effects can be effected to enhance or inhibit during a program operation, and can also cause leakage current and thus affect sensing operations (e.g., read or verify operations).

[0053] Aspects of the disclosure can be embodied in the form of apparatuses, systems, methods or computer program processes. As such, aspects of the present disclosure can be fully embodied in the form of hardware only, or software only, or can be embodied in the form of a combination of hardware and software, which generally can be referred to as a "circuit," "module," "apparatus," or "system." Additionally, aspects of the present disclosure can be embodied in the form of a computer program process, for example, embodied in one or more non-transitory computer-readable storage media of a computer-readable and / or computer-executable program of instructions operable to program an electronic device or that cause an electronic device to perform operations when executed on the electronic device.

[0054] Additionally, various terminology can be used herein to refer to particular system components. Different companies may refer to the same or similar components differently, and this document does not intend to distinguish between components that differ in name but not in function. To the extent a variety of functions are described in this disclosure as being performed by various functional units, such delineation is intended only to facilitate ease of description. For example, a "module" can be implemented as a hardware circuit comprising custom very-large-scale integration (VLSI) or gate arrays, or off-the-shelf semiconductors comprising logic chips, transistors, or other discrete components. In another example, a module can also be implemented in programmable hardware devices such as field programmable gate arrays (FPGAs), programmable array logic components, programmable logic devices, or the like. Additionally, a module can also be implemented at least partially as software executed by various types of processors. For example, a module can include an executable code segment that constitutes one or more physical or logical blocks of computer instructions that are transformed into an object, procedure, or function. Additionally, executable portions of such modules need not be physically located together, but can comprise different sections of code stored in different locations, and when executed together, constitute the identified module and achieve the stated purpose of the module. Executable code can include only a single instruction or many instructions, and can be spread out over several different code segments, among different programs, across several memory devices, or the like. In software or partially software module implementations, software portions can be stored on one or more computer-readable and / or computer-executable storage media including, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any suitable combination of the foregoing. Generally speaking, for purposes of this disclosure, computer-readable and / or computer-executable storage media can include any tangible and / or non-transitory media capable of storing and / or communicating programming code that is employable by an instruction execution system, apparatus, processor, or device.

[0055] Similarly, for purposes of the present disclosure, the term "component" can refer to any tangible, physical, and non-transitory device that is constructed to perform a function(s) (e.g., a device that is constructed to perform one or more of the techniques described herein). For example, a component can be in the form of a hardware logic circuit that is constructed using custom VLSI circuits, gate arrays, or other integrated circuits, or from a combination of pre-existing semiconductors including logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic devices. Further, a component can also be implemented in programmable hardware devices such as field programmable gate arrays (FPGAs), programmable array logic components, programmable logic devices, and the like. Additionally, components can be constructed from one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices that are in an electrical communication configuration with one or more other components via electrical conductors such as printed circuit boards (PCBs) and the like. Thus, modules as defined above can in certain embodiments be embodied as or implemented as components, and in some cases the terms module and component can be used interchangeably.

[0056] Where the term "circuit" is used in the present disclosure, it includes one or more electrical and / or electronic components that constitute an electrically conductive path that allows current to flow. A circuit can be in the form of a closed loop configuration or an open loop configuration. In a closed loop configuration, the circuit components can provide a return path for electrical current. In contrast, in an open loop configuration, the circuit components therein can be considered to form a circuit, although a return path for electrical current is not included. For example, an integrated circuit is referred to as a circuit whether or not it is grounded (as a return path for electrical current). In certain example embodiments, a circuit can include a group of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit can include custom VLSI circuits, gate arrays, logic circuits, and / or other forms of integrated circuits, and can include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit can include one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices that are in an electrical communication configuration with one or more other components via electrical conductors such as printed circuit boards (PCBs). A circuit can also be implemented as a synthesized circuit with respect to programmable hardware devices such as field programmable gate arrays (FPGAs), programmable array logic components, and / or programmable logic devices, and the like. In other example embodiments, a circuit can include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Thus, modules as defined above can in certain embodiments be embodied as or implemented as circuits.

[0057] It should be appreciated that the exemplary embodiments disclosed herein can include one or more microprocessors and specially- stored computer program instructions that control the one or more microprocessors to implement some, most, or all of the functionality disclosed herein in combination with certain non-processor circuits and other elements. Alternatively, some or all of the functionality can be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), or in field programmable gate arrays (FPGAs), where each function or some combination of functions can be implemented as custom logic. Combinations of these approaches can also be used. In addition, reference below to "a controller" should be construed to include individual circuit components, an application-specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a field programmable gate array (FPGA), and / or a processor with control software, or combinations thereof.

[0058] Further, as can be used herein, the terms "program" "software", "software application", and the like, refer to a sequence of instructions designed for execution on a computer implemented system. Thus, a "program", "software", "application", "computer program", or "software application" can include a subroutine, a function, a procedure, an object method, an object implementation, a

[0059] Additionally, as can be used herein, the terms "coupled", "coupling", or "coupling" are intended to mean either a direct connection or an indirect connection via another device (or component) and a connection. Thus, if a first device is coupled or coupled to a second device, the connection can be through a direct connection or through an indirect connection via other devices (or components) and connections.

[0060] With respect to the use of terms such as "embodiment", "one embodiment", "exemplary embodiment", "certain embodiments" or other similar terminology, such terminology is intended to indicate that the described feature is present in at least one embodiment of the present disclosure. Thus, the appearance of such phrases in various places throughout this specification is not necessarily intended to refer to the same embodiment of the present disclosure, unless otherwise indicated. Further, the terms "comprising", "having", "including", and their variations are used herein to mean "including but not limited to", and are thus to be construed as open-ended terminology not limiting the scope of the subject process, method, system, article, or apparatus. Additionally, recitation of "means" or "step" plus function recitations are intended to refer to the corresponding structure, material, or acts intended to accomplish the recited function.

[0061] The terms “a,” “an,” and “the” also refer to “one or more” unless otherwise explicitly stated. Furthermore, the phrase “at least one of’ A and B (as used herein and / or in the appended claims) means A or B, or both A and B, similar to the phrase “and / or,” unless otherwise explicitly stated. In the case where more than two items are listed, the phrase “at least one of’ shall be interpreted to include one of, any one of, a combination of any of, and all of the items listed, unless otherwise explicitly stated.

[0062] Furthermore, as used herein, the term “about” or “approximately” applies to all numeric values, unless otherwise explicitly stated. These terms generally refer to a range of values that one of skill in the art would consider equivalent to the recited value (e.g., having the same function or result). In certain instances, these terms can include values rounded to the nearest significant figure.

[0063] Furthermore, no enumeration of a listed item herein shall be deemed to imply that any or all of the listed items are mutually exclusive and / or collectively exhaustive unless expressly stated otherwise. Additionally, as used herein, the term “set” shall be construed to mean “one or more” in accordance with set theory, and in the case of “sets of sets” shall be construed to mean a plurality (multiple) of “one or more” and / or “multiple or more,” unless otherwise expressly indicated.

[0064] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. It is recognized that the preceding description has been presented only as an example and is not intended to limit the application in any way. Additional aspects, example embodiments, and features will become apparent to those skilled in the art upon examination of the following detailed description, which is provided herein for illustrative purposes only. Descriptions of elements in each of the figures can refer to the descriptions of the elements in the preceding figures. Like reference numbers can refer to like elements in the drawings including alternate example embodiments of like elements.

[0065] Figure 1Ais a block diagram of an example memory device. The memory device 100 can include one or more memory dies 108. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuits 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuits 128 include a plurality of sense blocks SB1, SB2,..., SBp (sense circuitry) and allow pages of memory cells to be read or programmed in parallel. A controller 122 is typically included in the same memory device 100 (e.g., removable memory card) as one or more memory dies 108. Commands and data are transferred between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via lines 118.

[0066] The memory structure 126 can be two-dimensional or three-dimensional. The memory structure 126 can include one or more arrays of memory cells including a three-dimensional array. The memory structure 126 can include a monolithic three-dimensional memory structure in which multiple levels of memory cells are formed above (rather than in) a single substrate, such as a wafer, without intervening substrates. The memory structure 126 can include any type of non-volatile memory that is integrally formed in one or more physical levels of memory cells having active regions disposed above a silicon substrate. The memory structure 126 can be in a non-volatile memory device having circuitry associated with operation of the memory cells whether the associated circuitry is above the substrate or within the substrate.

[0067] The control circuitry 110 cooperates with the read / write circuits 128 to perform memory operations on the memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip level control over internal cache operations, data flow, and timing.

[0068] A storage region 113 can be provided, for example, for programming parameters. The programming parameters can include program voltages, program voltage biases, location parameters indicative of locations of memory cells, contact line connector thickness parameters, verify voltages, etc. The location parameters can indicate locations of memory cells within an entire array of NAND strings, locations of memory cells within a particular group of NAND strings, locations of memory cells on a particular plane, etc. The contact line connector thickness parameters can indicate thicknesses of contact line connectors, substrates or materials making up the contact line connectors, etc.

[0069] On-chip address decoders 114 provide an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operations. The power control module can include drivers for the word lines, SGS transistors, and SGD transistors and source lines. In one approach, the sense blocks can include bit line drivers. SGS transistors are select gate transistors at the source end of the NAND string, and SGD transistors are select gate transistors at the drain end of the NAND string.

[0070] In some embodiments, some of the components can be combined. In various designs, one or more of the components other than memory structure 126 (alone or in combination) can be considered at least one control circuit that is configured to perform the actions described herein. For example, the control circuit can include any one or a combination of control circuit 110, state machine 112, decoders 114 / 132, power control module 116, sense blocks (SBi, SB2,..., SBp), read / write circuits 128, controller 122, etc.

[0071] The control circuit can include a program circuit configured to perform program and verify operations on a set of memory cells, where the set of memory cells includes memory cells allocated for representing one of a plurality of data states and memory cells allocated for representing another of the plurality of data states, the program and verify operations include a plurality of program and verify iterations, and at each program and verify iteration, the program circuit performs a program on one word line, after which the program circuit applies a verify signal to the one word line. The control circuit can also include a count circuit configured to obtain a count of memory cells that pass a verify test for the one data state. The control circuit can also include a determination circuit configured to determine, based on the count exceeding an amount of a threshold, a particular program and verify iteration of the plurality of program and verify iterations in which to perform a verify test on the another of the plurality of data states for the memory cells allocated for representing the another of the plurality of data states.

[0072] For example, Figure 1B is a block diagram of an example control circuit 150 that includes program circuit 151, count circuit 152, and determination circuit 153.

[0073] The off-chip controller 122 can include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct a number of read errors that arise when the upper tail of the Vth distribution becomes too high. However, in some cases there can be uncorrectable errors. The techniques provided herein reduce the likelihood of uncorrectable errors.

[0074] The storage devices 122a, 122b include code, such as a set of instructions, and the processor 122c is operable to execute the set of instructions to provide the functionality described herein. Alternatively, or in addition, the processor 122c can access code from a storage device 126a of the memory structure 126, such as a reserved area of memory cells in one or more word lines. For example, the controller 122 can use the code to access the memory structure 126, such as for program, read, and erase operations. The code can include boot code and control code (e.g., a set of instructions). Boot code is software that initializes the controller 122 during a boot or startup process and enables the controller 122 to access the memory structure 126. The controller 122 can use the code to control one or more memory structures 126. Upon power up, the processor 122c fetches the boot code from the ROM 122a or the storage device 126a for execution and the boot code initializes the system components and loads the control code into the RAM 122b. Once the control code is loaded into the RAM 122b, it is executed by the processor 122c. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0075] Generally, the control code can include instructions to perform the functionality described herein, including the steps of the flowcharts discussed further below, and to provide voltage waveforms, including those discussed further below.

[0076] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smartphone, a tablet, a digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drives, solid state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host can also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices in communication with the one or more processors.

[0077] Other types of non-volatile memory can be used in addition to NAND flash memory.

[0078] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, nonvolatile memory devices, such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetic random access memory ("MRAM") devices, and other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, a flash memory device can be configured in either a NAND or a NOR configuration.

[0079] The memory devices can be formed from passive and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as resistive-switching or phase-change materials, and optional steering elements, such as diodes or transistors. Further, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements that include charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0080] Multiple memory elements can be configured such that they are connected in series or such that each element can be individually accessed. By way of non-limiting example, a flash memory device in a NAND configuration (NAND memory) typically contains memory elements connected in series. A NAND string is an example of a set of series-connected transistors including memory cells and SG transistors.

[0081] A NAND memory array can be configured such that the array is composed of multiple strings of memory, where a string is composed of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be individually accessed, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional memory structures or three-dimensional memory structures.

[0082] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an x-y directional plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate can be a wafer on or in which layers of the memory elements are formed, or it can be a carrier substrate that is attached to the memory elements after they are formed. As non-limiting examples, the substrate can comprise a semiconductor, such as silicon.

[0083] The memory elements can be arranged in a single memory device level in an ordered array, such as in a plurality of rows and / or columns. However, the memory elements can be arranged in irregular or non-orthogonal configurations. The memory elements can each have two or more electrodes or contact lines, such as bit lines and word lines.

[0084] A three-dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, forming a three-dimensional structure (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular and the x and y directions are substantially parallel to a major surface of the substrate).

[0085] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to a major surface of the substrate, i.e., along the y direction), each column having a plurality of memory cells. The columns can be arranged in a two-dimensional configuration, e.g., in an x-y plane, resulting in a three-dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0086] By way of non-limiting example, in a three-dimensional array of NAND strings, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., x-y) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other three-dimensional configurations are contemplated, in which some NAND strings contain memory elements in a single memory level, while other strings contain memory elements that span multiple memory levels. Three-dimensional memory arrays can also be designed in NOR configurations, as well as ReRAM configurations.

[0087] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, a monolithic three-dimensional memory array can also have one or more memory levels at least partially within the single substrate. As a non-limiting example, the substrate can comprise a semiconductor, such as silicon. In a monolithic three-dimensional array, each memory device level that makes up the array is typically formed on a layer of a lower memory device level of the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array can be shared or have intervening layers between the memory device levels.

[0088] Then, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multiple memory levels. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates can be thinned or removed from the memory device levels prior to stacking, but because the memory device levels are initially formed over separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Further, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0089] Figure 2 Schematics of three types of memory architectures utilizing interleaved memory strings are shown. For example, reference number 201 shows a schematic of a first example memory architecture, reference number 203 shows a schematic of a second example memory architecture, and reference number 205 shows a schematic of a third example memory architecture. In some embodiments, as shown, the memory architectures can include an array of interleaved NAND strings.

[0090] Figure 2 Blocks 200, 210 of memory cells in an example two-dimensional configuration of the memory array 126 of FIG. 1 are shown. The memory array 126 can include many such blocks 200, 210 of memory. Each example block 200, 210 includes a plurality of NAND strings and corresponding bit lines, e.g., BL0, BL1,... shared between blocks. Each NAND string is connected at one end to a drain-side select gate (SGD) and the control gates of that drain select gate are connected via a common SGD line. The NAND strings are connected at their other end to a source-side select gate (SGS) which in turn is connected to a common source line 220. Sixteen word lines, e.g., WL0-WL15, extend between the SGD and the SGS. In some cases, dummy word lines that do not contain user data can also be used in the memory array adjacent to the select gate transistors. Such dummy word lines can shield edge data word lines from certain edge effects.

[0091] One type of non-volatile memory that can be provided in a memory array is a floating gate memory, such as Figure 3A and Figure 3B floating gate memory of the type shown. However, other types of non-volatile memory can also be used. As discussed in further detail below, in another example shown in Figure 4A and Figure 4B charge-trapping memory cell stores charge in a non-volatile manner using a non-conductive dielectric material instead of a conductive floating gate. A three-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semiconductive substrate over the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a finite region. This stored charge then changes the threshold voltage of the portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. A split-gate configuration can provide a similar cell, in which a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0092] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, with an ONO dielectric layer extending over the channel between the source and drain diffusions. Charges for one data bit are located in the dielectric layer adjacent to the drain, and charges for the other data bit are located in the dielectric layer adjacent to the source. Multi-state data storage is obtained by reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0093] Figure 3A Cross-sectional views of exemplary floating gate memory cells 300, 310, 320 in a NAND string are shown. In this figure, the bit line or NAND string direction goes into the page, and the word line direction is from left to right. For example, word line 324 extends across a NAND string that includes respective channel regions 306, 316, and 326. Memory cell 300 includes control gate 302, floating gate 304, tunnel oxide layer 305, and channel region 306. Memory cell 310 includes control gate 312, floating gate 314, tunnel oxide layer 315, and channel region 316. Memory cell 320 includes control gate 322, floating gate 321, tunnel oxide layer 325, and channel region 326. Each of memory cells 300, 310, and 320 is in a different respective NAND string. A polysilicon interpoly dielectric (IPD) layer 328 is also shown. Control gates 302, 312, 322 are part of a word line. Figure 3B A cross-sectional view along contact line connector 329 is provided in

[0094] The control gates 302, 312, 322 are wrapped around the floating gates 304, 314, 321, increasing the surface contact area between the control gates 302, 312, 322 and the floating gates 304, 314, 321. This results in higher IPD capacitance, resulting in higher coupling ratios, which makes programming and erasing easier. However, as NAND memory devices are scaled down, the spacing between adjacent cells 300, 310, and 320 becomes smaller, so there is little room for the control gates 302, 312, 322 and the IPD layer 328 between two adjacent floating gates 302, 312, 322.

[0095] As an alternative, as shown in FIGS. 4, 5, and 6, planar or flat memory cells 400, 410, 420 have been developed in which the control gates 402, 412, 422 are flat or planar; that is, the control gates are not wrapped around the floating gates, and the only contact of the control gates to the charge storage layer 428 is from above. In this case, there is no advantage to having a high floating gate. Instead, the floating gate is made thinner. In addition, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This approach can avoid the ballistic electron transport problem, in which electrons can travel through the floating gate after tunneling through the tunnel oxide during programming. Figure 4A and Figure 4B As an alternative, as shown in FIGS. 4, 5, and 6, planar or flat memory cells 400, 410, 420 have been developed in which the control gates 402, 412, 422 are flat or planar; that is, the control gates are not wrapped around the floating gates, and the only contact of the control gates to the charge storage layer 428 is from above. In this case, there is no advantage to having a high floating gate. Instead, the floating gate is made thinner. In addition, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This approach can avoid the ballistic electron transport problem, in which electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0096] Figure 4A Cross-sectional views of exemplary charge-trapping memory cells 400, 410, 420 in a NAND string are shown. The view is in the word line direction of the memory cells 400, 410, 420 including planar control gates and charge-trapping regions, as a two-dimensional example of the memory cells 400, 410, 420 in the memory cell array 126 of FIG. 1. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses insulators such as SiN films to store electrons, as compared to floating gate MOSFET technology that uses conductors such as doped polysilicon to store electrons. For example, a word line 424 extends across a NAND string, which includes respective channel regions 406, 416, 426. Portions of the word line provide control gates 402, 412, 422. IPD layers 428, charge-trapping layers 404, 414, 421, polysilicon layers 405, 415, 425, and tunnel layers 409, 407, 408 are below the word line. Each charge-trapping layer 404, 414, 421 extends continuously in the respective NAND string. The planar configuration of the control gates can be made thinner than the floating gate. In addition, the memory cells can be placed closer together.

[0097] Figure 4B A cross-sectional view of a portion of a NAND string along a contact line connector 429 is shown. Figure 4AA cross-sectional view of the structure of Figure 4A is shown. The NAND string 430 includes SGS transistor 431, exemplary memory cells (400, 433, 435,...), and SGD transistor 436. The vias in the IPD layer 428 in the SGS transistor 431 and the SGD transistor 436 allow the control gate layer 402 and the floating gate layer to be in communication. For example, the control gate layer 402 and the floating gate layer can be polysilicon, and the tunnel oxide layer can be silicon oxide. The IPD layer 428 can be a stack of nitride (N) and oxide (O), such as in an N-O-N-O-N configuration.

[0098] The NAND string can be formed on a substrate that includes a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, N-type source / drain diffusion regions sd2, N-type source / drain diffusion regions sd3, N-type source / drain diffusion regions sd4, N-type source / drain diffusion regions sd5, N-type source / drain diffusion regions sd6, and N-type source / drain diffusion regions sd7 are formed in the p-type well. A channel voltage Vch can be applied directly to the channel region of the substrate.

[0099] Figure 5 An exemplary block diagram of the sense block SB1 of Figure 1 is shown. In one approach, the sense block includes a plurality of sense circuits. Each sense circuit is associated with a data latch. For example, exemplary sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different respective sense blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sense circuits to be divided and processed by respective processors in each sense block. For example, a sense circuit controller 560 in SB1 can communicate with the set of sense circuits and latches. The sense circuit controller 560 can include a pre-charge circuit 561 that provides a voltage to each sense circuit for setting a pre-charge voltage. In one possible approach, the voltage can be provided to each sense circuit independently, e.g., via a data bus and a local bus. In another possible approach, a common voltage can be provided to each sense circuit simultaneously. The sense circuit controller 560 can also include a pre-charge circuit 561, a memory 562, and a processor 563. The memory 562 can store code that can be executed by the processor to perform the functions described herein. These functions can include reading the latches 550b, 551b, 552b, 553b associated with the sense circuits 550a, 551a, 552a, 553a, setting the bit values in the latches, and providing a voltage for setting the pre-charge level in the sense nodes of the sense circuits 550a, 551a, 552a, 553a. Further exemplary details of the sense circuit controller 560 and the sense circuits 550a, 551a, 552a, 553a are provided below.

[0100] In some implementations, a memory cell can include a flag register that includes a set of latches that store flag bits. In some implementations, the number of flag registers can correspond to the number of data states. In some implementations, one or more flag registers can be used to control the type of verification technique used in verifying a memory cell. In some implementations, the output of the flag bits can modify the associated logic of a device, such as address decode circuitry, so that a specified block of cells is selected. Bulk operations (e.g., erase operations, etc.) can be performed using the flags set in the flag registers, or a combination of flag registers and address registers, as in implicit addressing, or alternatively performed by directly addressing with only the address registers.

[0101] Figure 6A A perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126 of FIG. 1. On a substrate are exemplary blocks BLKO, BLKI, BLK2, BLK3 of memory cells (storage elements), and a peripheral region 604 with circuitry for use by the blocks BLKO, BLKI, BLK2, BLK3. For example, the circuitry can include voltage drivers 605 that can be connected to control gate layers of the blocks BLKO, BLKI, BLK2, BLK3. In one approach, control gate layers at a common height in the blocks BLKO, BLKI, BLK2, BLK3 are commonly driven. The substrate 601 can also carry circuitry under the blocks BLKO, BLKI, BLK2, BLK3, along with one or more lower metal layers that are patterned in conductive paths to carry signals of the circuitry. The blocks BLKO, BLKI, BLK2, BLK3 are formed in a middle region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each of the blocks BLKO, BLKI, BLK2, BLK3 includes a stack region of memory cells, with alternating levels of the stack representing word lines. In one possible approach, each of the blocks BLKO, BLKI, BLK2, BLK3 has an opposite layered side from which vertical contacts extend upward to the upper metal layers to form connections with the conductive paths. Although four blocks BLKO, BLKI, BLK2, BLK3 are shown as an example, two or more blocks extending in the x-direction and / or the y-direction can be used.

[0102] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0103] Figure 6B It shows Figure 6A An exemplary cross-sectional view of a portion of one of blocks BLK0, BLK1, BLK2, and BLK3. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WLL0 to WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL19. Furthermore, a region of the stack 610 including NAND strings NS1 and NS2 is shown. Each NAND string contains memory vias 618 and 619 filled with material forming memory cells adjacent to the word lines. Region 622 of the stack 610 is shown in… Figure 6D This is shown in more detail below, and discussed further in detail below.

[0104] Stack 610 includes a substrate 611, an insulating film 612 located on the substrate 611, and a portion of a source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack 610. Contact line connectors (e.g., slots, such as metal-filled slots) 617, 620 may be provided periodically across the stack 610 as interconnects extending through the stack 610, such as to connect source lines to specific contact lines above the stack 610. Contact line connectors 617, 620 may be used during word line formation and subsequently metal-filled. A portion of a bit line BL0 is also shown. A conductive via 621 connects the drain terminal 615 to BL0.

[0105] Figure 6C It shows Figure 6B A graph showing the diameter of memory apertures in a stack. The vertical axis is... Figure 6B The stack alignment is shown, and the width (wMH) of memory holes 618 and 619, such as the diameter, is shown. Figure 6AThe word line layers WLL0-WLL10 are repeated as an example and are at respective heights zo-zio in the stack. In such memory devices, the memory holes etched through the stack have a very high aspect ratio. For example, a depth to diameter ratio of about 25 to 30 is common. The memory holes can have a circular cross section. Due to the etching process, the width of the memory hole can vary along the length of the hole. Typically, the diameter of the memory hole tapers from its top to its bottom. That is, the memory hole is tapered, narrowing at the bottom of the stack. In some cases, there is a slight narrowing at the top of the hole near the select gate, such that the diameter of the memory hole widens slightly before tapering from its top to its bottom.

[0106] Due to the non-uniformity of the memory hole width, the programming speed, including the programming slope and erase speed of the memory cell, can vary based on the location of the memory cell along the memory hole (e.g., based on the height of the memory cell in the stack). For smaller diameter memory holes, the electric field across the tunnel oxide is relatively stronger, making the programming and erase speed relatively higher. One approach is to define groups of adjacent word lines that are similar in memory hole diameter (e.g., within a defined diameter range), and apply an optimized verify scheme for each word line in the group. Different groups can have different optimized verify schemes.

[0107] Figure 6D A close-up view of a region 622 of the stack 610 is shown. Figure 6B The word line layers WLL0-WLL10 are repeated as an example and are at respective heights zo-zio in the stack. In such memory devices, the memory holes etched through the stack have a very high aspect ratio. For example, a depth to diameter ratio of about 25 to 30 is common. The memory holes can have a circular cross section. Due to the etching process, the width of the memory hole can vary along the length of the hole. Typically, the diameter of the memory hole tapers from its top to its bottom. That is, the memory hole is tapered, narrowing at the bottom of the stack. In some cases, there is a slight narrowing at the top of the hole near the select gate, such that the diameter of the memory hole widens slightly before tapering from its top to its bottom.

[0108] When a data memory cell MC is programmed, electrons are stored in a portion of the charge trapping layer 663 associated with the memory cell MC. These electrons are attracted from the channel 665 into the charge trapping layer 663 and through the tunnel layer 664. The Vth of the memory cell MC increases in proportion to the amount of charge stored. During an erase operation, the electrons return to the channel 665.

[0109] Each of the memory holes 630 can be filled with a plurality of annular layers including a blocking oxide layer, a charge trapping layer 663, a tunnel layer 664, and a channel layer 665. The core region of each of the memory holes 630 is filled with a bulk material, and the plurality of annular layers is located between the core region and the word line in each of the memory holes 630.

[0110] The NAND string can be considered to have a floating body channel 665 because the length of the channel 665 is not formed on the substrate. Further, the NAND string is provided by a plurality of word line layers stacked on top of one another and separated from one another by dielectric layers.

[0111] Figure 7A A schematic plan view of a memory array 700 is shown having a plurality of memory holes 722, which can be chains of vertical memory cells as described herein, and a plurality of dummy holes 705 that do not require a full memory structure. A shallow trench etch or shallow etch feature (SHE) 710 extends through a plurality of word lines (e.g., five) but not all the way through the chip to electrically isolate adjacent strings from one another. The SHE extends directly through a set of aligned dummy holes 705, thereby preventing those dummy holes 705 from storing data or otherwise being functional memory cells.

[0112] Reference is now made to Figure 8A and 8B There are no dummy holes. Unlike the memory structure 700 of Figure 7A and 7B The SHE 810 is located in the gap between two adjacent rows of memory cells 825 and overlaps the memory holes 825, thereby forming a working chain having a trench etched into one side of at least the SGD switch at the top of the working memory chain, shown here as a memory hole 825. This configuration greatly improves yield and memory density because all of the memory holes 822, 825 are functional, i.e., fewer memory holes are wasted.

[0113] Unlike the full circular memory holes 822, the memory holes 825 partially cut by the SHE 810 and the SGD switch have a semi-circular shape, which can be a semicircle or can be larger or smaller than a semicircle. In some cases, the memory holes 825 and SGD switch can be smaller than a semicircle on one side of the SHE 810 and larger than a semicircle on the other side of the SHE 810.

[0114] The memory holes 822, 825 are connected with a plurality of bit lines 830 (labeled Bit 0-7 in Figure 8A FIG. 8). For ease of illustration, only eight bit lines 830 are shown. The bit lines 830 extend over the memory holes and are connected to select the memory holes via the connection points. The memory holes in each string region are also connected at one end to the SGD switch and at the other end to the SGS switch. The SHE trench 810 can be etched into a portion of the SGD switch.

[0115] Referring now to FIG. 9, Figure 9 Due to variations and defects in the manufacturing operations, the SHE can be non-centrally positioned between adjacent rows of memory holes. When this occurs, the semi-circular SGD on one side of the SHE trench can be larger in size than the semi-circular SGD on the other side of the SHE trench. The memory holes including the larger size SGD are referred to hereinafter as “under offset SGD” and the memory holes including the smaller size SGD are referred to hereinafter as “over offset memory holes.” As shown, each string has one row of under offset semi-circular SGD, two rows of full circle SGD, and one row of over offset semi-circular SGD. With respect to string 1, row 0 includes over offset semi-circular SGD 925b; rows 1 and 2 include full circle SGD 922; and row 3 includes under offset semi-circular SGD 925a.

[0116] Figure 10A memory structure 1000 showing several memory holes cut by SHE 1010 is shown in accordance with some described embodiments. Memory structure 1000 includes several FC-SGD memory holes 1022 (representing several additional FC-SGDs) and several SC-SGD memory holes 1025a and 1025b (representing several additional SC-SGDs), where SC-SGD memory holes 1025a and 1025b are cut by SHE 1010. Additionally, the memory holes of memory structure 1000 are surrounded by a metal layer 1032, such as a tungsten metal layer. During certain operations (e.g., read operations), a bias voltage is placed on two regions (in addition to being divided by SHE 1010). For example, during a read operation, a bias voltage is applied to region 1030a of memory holes such that the string of memory connected to the memory holes in region 1030a can be read. This region 1030a can be referred to as the selected SGD. However, at the same time, a bias voltage is applied to region 1030b of memory holes that are not selected for reading. This region 1030b can be referred to as the unselected SGD.

[0117] SHE 1010 forms an electrical isolation separating regions 1030a and 1030b from each other. However, as shown in the magnified view, SHE 1010 cuts and removes some portions of the SC-SGD, such as memory hole 1025b. For example, memory hole 1025b includes a channel 1034 (serving as a passageway for electrons), a charge trapping layer 1036 (for storing electrons and determining Vt), and a dielectric layer 1038 such as aluminum oxide (for blocking external electric fields). Additionally, an oxide layer 1040 extends into memory hole 1025b and separates channel 1034 from charge trapping layer 1036, and also separates charge trapping layer 1036 from dielectric layer 1038. These aforementioned features (channel 1034, charge trapping layer 1036, and dielectric layer 1038) are present in both FC-SGDs and SC-SGDs.

[0118] In a full-circle memory hole, the respective channel, charge-trapping layer, and metal layer each resemble a ring. However, due to the SHE 1010, some portions of the channel 1034, charge-trapping layer 1036, and dielectric layer 1038 are partially removed. While the memory 1025b with partially removed features can still work, certain issues arise. For example, due to the partial removal of the dielectric layer 1038, both the channel 1034 and the charge-trapping layer 1036 are exposed to an electric field 1042 (represented by the longer dashed arrow) due to the bias voltage placed on the region 1030b (unselected SGD) during a read operation. As a result, the end regions 1044a and 1044b (or tips) of the channel 1034 can be substantially turned on during a read operation, causing the end regions 1044a and 1044b to become conductive. The plot (not labeled) of the transistor represents the gate of the end regions 1044a and 1044b that can be turned on. This, in turn, can effectively lower the Vt of the memory hole 1025b required to turn on the channel 1034. This illustrates one issue with NSI. Also, it is noted that the memory hole 1025b generally represents other SC-SGD memory holes in the memory structure 1000. However, each memory hole can be cut to a different extent by the SHE 1010. Figure 10

[0119] Figure 11 A plot 1100 showing the Vt distribution of a memory structure with memory holes is shown in accordance with some described embodiments. The count (program-erase cycles) is shown versus Vt. The plot 1110a represents the Vt distribution of all SGD memory holes. In addition, the plot 1110b represents the Vt distribution of all FC-SGD memory holes, while the plot 1110c represents the Vt distribution of all SC-SGD memory holes. In this regard, the plots 1110b and 1110b represent components of the plot 1110a. The plot 1110c shows that the Vt distribution will "shift down" or lower the overall Vt distribution. Furthermore, the impact of SC-SGD makes the plot 1110a (the overall plot) wider, making the Vt distribution more difficult to predict. Several modifications shown and described below are used to overcome these challenges with the use of SC-SGD.

[0120] Figure 12 A circuit diagram 1200 showing the transistors for a selected gate and an unselected gate is shown. As shown, the transistor 1250a represents a selected SC-SGD memory hole, such as the memory hole 1025b (as shown in FIG. 10B). In particular, the transistor 1250a represents the end regions 1044a and 1044b (as shown in FIG. 10B). The transistor 1250a is designed to turn on based on a predetermined select gate voltage V Figure 10 Figure 10 SEL ​​​To connect. Additionally, transistor 1250b indicates an unselected SC-SGD memory port, such as memory port 1025a (e.g., Figure 10 (As shown). Additionally, transistor 1250c (parasitic transistor) runs in parallel with transistor 1250a. Ideally, when V... SEL When the bias voltage is sufficiently high on transistor 1250a, the circuit carries current. However, when a bias voltage is applied to transistor 1250b (e.g., during a read operation), an electric field 1242, known as NSI, can turn on transistor 1250c. When this occurs, leakage current flows through the source, causing the sense amplifier 1260 to determine that transistor 1250a is conducting when transistor 1250a is not turned on, while transistor 1250c, acting as a parasitic transistor, is conducting.

[0121] The formula for determining whether electric field 1242 is sufficient to turn on transistor 1250c is as follows:

[0122] VOD = α * V attacker - VSELSRC formula (1)

[0123] Where V OD It is the overdrive voltage, α is the coupling coefficient (based on the width of SHE, and will be described further below), V 攻击者 The "attack" voltage or interference voltage caused by NSI, V SELSRC This is the source line voltage. V 攻击者 It is also based on the voltage derived from the bias voltage applied to the unselected gate. It can be seen that V OD Similar to traditional transistor formulas, such as gate-source voltage (“V”). GS Furthermore, it can be seen that V OD Depends on V 攻击者 And it is proportional to it (provided α is greater than 0). Therefore, when V OD High enough (corresponding to V) 攻击者 When the voltage is high enough, transistor 1250c will be turned on.

[0124] To fully reduce the V of the turn-on transistor OD It can be achieved by manipulating V 攻击者 To sufficiently reduce the electric field 1242. For example, placing a negative bias (such as -2V) on the unselected gate can sufficiently reduce the voltage (in some cases 0V) driven through the electric field on transistor 1250c. Therefore, transistor 1250c will not be unintentionally turned on, and only current is allowed to flow through transistor 1250a, provided that V... SEL High enough. To provide a negative voltage, additional modifications, such as a tri-well transistor, can be used.

[0125] As described above and return to reference Figure 10Due to the bias voltage placed on region 1030b (unselected SGD) during a read operation (e.g., due to partial removal of dielectric layer 1038), in a memory hole or string including a half-circle SGD (SC-SGD), both the channel 1034 and charge trapping layer 1036 are exposed to an electric field 1042 (indicated by the longer dashed arrow in Figure 10 ). Referring to Figure 12 , the electric field 1042 contributes to the NSI or NSI effect described. In addition to the SC-SGD being disturbed by the adjacent SGD, there is also an adjacent cross-coupling (NCC) effect 1046 (indicated by the shorter dashed arrow in Figure 10 ), where the unselected secondary adjacent SGDT / dummy can cross-couple to the SGD layer (i.e., the selected SGD). Such adjacent cross-coupling also causes the SGD downshift problem shown in Figure 11 . Due to the lower threshold voltage Vt of the SC-SGD, the NSI and NCC can together affect the boost / suppression during a program operation. The NSI and NCC can also cause leakage current and thus affect the sense operation. Figure 13 shows a cross-sectional view of adjacent selected and unselected strings including SGD transistors associated with memory holes cut by SHE 1310 and the resulting NSI (V 初级攻击者 ) and NCC (V 次级攻击者 ) effects.

[0126] Figure 14 shows another cross-sectional view of adjacent selected and unselected strings including SGD transistors associated with memory holes cut by SHE 1310 and a corresponding top view of a portion of the memory device. To demonstrate the existence of the secondary coupling or NCC effect, the unselected SGD bias is fixed, but the DD0 bias is changed from 4.2V to 8.6V. Figure 15 shows threshold voltage Vt distributions of half-circle SGD transistors and full-circle SGD transistors. Figure 16 shows the lower tail threshold voltage Vt of the threshold voltage Vt of a half-circle SGD transistor (right-most graph of Figure 16 ) and a full-circle SGD transistor (left-most graph of Figure 16 ). As shown, the threshold voltage Vt of the SGD transistor starts to shift down when a higher dummy WL bias is applied in the half-circle SGD. The sensitivity is much higher than the full-circle SGD, as evidenced by the different slopes shown in Figure 16 . This demonstrates that the adjacent cross-coupling (NCC) does exist. This diagonal coupling can cause a considerable SGD downshift.

[0127] Figure 17AAnother cross-sectional view of adjacent selected and unselected strings during a program operation and corresponding top view of a portion of a memory device are shown, including SGD transistors associated with memory holes cut by SHE 1310. As shown, each of the strings has a plurality of drain-side select gate transistors (SGD and SGDT transistors) on a drain-side of one of the strings. The plurality of drain-side select gate transistors includes one of a plurality of top drain-side select gate SGDT transistors. Figure 17B A corresponding perspective view of adjacent selected and unselected strings including a plurality of drain-side select gate transistors (SGD and SGDT transistors) coupled to one of a plurality of bit lines BL during a program operation is shown. Figure 17A A corresponding perspective view of adjacent selected and unselected strings including a plurality of drain-side select gate transistors (SGD and SGDT transistors) coupled to one of a plurality of bit lines BL during a program operation is shown. 次级攻击者 A selected one of the plurality of top drain-side select gate SGDT transistors and an unselected one of the plurality of top drain-side select gate SGDT transistors are electrically shorted during a program operation (sharing the same bias for all strings). Similarly, a selected one of the plurality of dummy word lines DWL and an unselected one of the plurality of dummy word lines DWL are electrically shorted during a program operation (sharing the same bias for all strings). In more detail, when an adjacent transistor (a selected one of the plurality of top drain-side select gate SGDT transistors) and / or a dummy word line of the plurality of dummy word lines DWL is biased high, an electric field can cross-couple to the SGD layer (layer N+1 to N diagonal coupling and / or layer N-1 to N diagonal coupling), causing a leakage current in a selected one of the plurality of drain-side select gate SGD transistors (equivalent to SGD downshift). This will cause a significant NCC in the OPS (pitch SGD) technique. This NCC effect or interference effect is weaker than the NSI effect (coupling within the same physical layer).

[0128] Figure 18A Another cross-sectional view of adjacent selected and unselected strings during a read operation and corresponding top view of a portion of a memory device are shown, including SGD transistors associated with memory holes cut by SHE 1310. Figure 18BIt shows Figure 18A A perspective view of adjacent selected and unselected strings, which include SGD transistors coupled to bit line BL during read operations. As in programming operations, V on the unselected string... 次级攻击者 During read operations, coupling to the selected string SGD results in increased leakage current. Therefore, although one selected top-drain-side-select-gate transistor and one unselected top-drain-side-select-gate transistor in the multiple top-drain-side-select-gate SGDT transistors are physically separated, they are electrically shorted during programming (sharing the same bias for all strings). Similarly, although one selected dummy word line and one unselected dummy word line in the multiple dummy word lines DWL are physically separated, they are electrically shorted during read operations (sharing the same bias for all strings). More specifically, when adjacent transistors (one of the multiple top-drain-side-select-gate SGDT transistors) and / or one of the multiple dummy word lines (DWLs) are biased high, the electric field can cross-couple to the SGD layer (layer N+1 to N diagonal coupling and / or layer N-1 to N diagonal coupling), resulting in leakage current in the selected drain-side-select-gate SGDT transistor (equivalent to SGD down-off). This will lead to significant NCC in OPS technology. This NCC effect, or interference effect, is weaker than the NSI effect (coupled within the same physical layer).

[0129] Therefore, the memory devices described herein (e.g., Figure 1A The memory device 100 includes connections to a plurality of word lines (e.g., Figure 6B Data word line layer (word line) WLL0 to WLL10 or Figure 6D A word line memory cell (e.g., data memory cell MC and WLL10) in WLL10 Figure 6D Virtual memory cells 682, 683). The memory cells are arranged in one or more strings (e.g., Figure 6Band configured to hold a threshold voltage Vt or Vth corresponding to one of a plurality of memory states. Again, each of these strings has a plurality of drain side select gate transistors (SGD and SGDT transistors) located on a drain side of the one of these strings, the one of these strings including one of a plurality of top drain side select gate SGDT transistors. The plurality of top drain side select gate SGDT transistors are connected to one of a plurality of bit lines and coupled to memory cells of one of the strings. The apparatus also includes a control circuit or a device coupled to the plurality of word lines, the plurality of bit lines, and the plurality of drain side select gate transistors (e.g., one or any combination of the control circuit 110, the decoders 114 / 132, the power control module 116, the sense blocks (SBb, SB2,..., SBp), the read / write circuits 128, Figure 1A the controller 122, Figure 1B the control circuit 150, and / or Figure 5 the sense circuit controller 560, etc. of the memory device 100). The control device is configured to apply an unselected top voltage to unselected ones of the plurality of top drain side select gate SGDT transistors during a memory operation. The control device is also configured to simultaneously apply a selected top voltage to selected ones of the plurality of top drain side select gate SGDT transistors during the memory operation. The unselected top voltage is electrically separate (i.e., intentionally different electrically) from the selected top voltage. According to one aspect, the unselected top voltage is less than the selected top voltage. In particular, the unselected top voltage can be approximately zero volts or a negative voltage.

[0130] As described above and with reference back to Figure 6D , 17Aand 18A, for example, the plurality of word lines and the plurality of dielectric layers extend horizontally and are stacked in an alternating fashion with one another, and the strings extend vertically through the stack. The plurality of drain side gate transistors (SGD and SGDT transistors) includes one of the plurality of other drain side gate SGD transistors connected in series between the one of the plurality of top drain side gate SGDT transistors and the memory cells of each of the strings. The control device is further configured to apply a selected other voltage to the selected other drain side gate transistor of the plurality of other drain side gate SGD transistors during the memory operation. According to one aspect, the unselected top voltage is less than the selected other voltage. In other words, the unselected SGDT bias is lower than the selected SGD bias during the memory operation. Subsequently, the control device is configured to minimize a neighboring cross-coupling (NCC) effect between the unselected top drain side gate transistor of the plurality of top drain side gate SGDT transistors and the selected top drain side gate transistor of the plurality of top drain side gate SGDT transistors.

[0131] According to one aspect, the memory operation is a program operation. Thus, during the program operation, the control device is further configured to apply at least one program pulse in a program voltage to the selected word line of the plurality of word lines while applying a pass voltage to the unselected word line of the plurality of word lines. Figure 19A Another cross-sectional view of adjacent selected and unselected strings including SGD transistors associated with a memory hole cut by the SHE 1310 during a program operation, where the unselected top voltage is electrically separated (i.e., intentionally different electrically) from the selected top voltage, and a corresponding top view of a portion of the memory device are shown. Figure 19B A perspective view of adjacent selected and unselected strings of Figure 19A A perspective view of adjacent selected and unselected strings of 次级攻击者 As the NCC effect will couple to the selected string SGD, resulting in more leakage current, the electrically separated or intentionally different (i.e., intentionally different electrically) unselected SGDT bias (i.e., unselected top voltage) and selected SGDT bias (selected top voltage) reduces the NCC effect in the diagonal direction during the program operation.

[0132] Alternatively or in addition, the memory operation is one of a read operation and a verify operation. Thus, during the one of the read operation and the verify operation, the control device is further configured to apply one of a read voltage and a verify voltage to the selected word line of the plurality of word lines while applying the pass voltage to the unselected word lines of the plurality of word lines. Figure 20A Another cross-sectional view of adjacent selected strings and unselected strings including SGD transistors associated with memory holes cut by the SHE 1310 during one of a read operation and a verify operation and a corresponding top view of a portion of the memory device are shown, where the unselected top voltage is electrically separated (i.e., intentionally different electrically) compared to the selected top voltage. Figure 20B A perspective view of adjacent selected strings and unselected strings of Figure 20A including SGD transistors having different unselected top voltages and selected top voltages coupled to the bit line BL during one of a read operation and a verify operation are shown. While V 次级攻击者 The electrically separated or intentionally different (i.e., intentionally different electrically) unselected SGDT bias (i.e., unselected top voltage) and selected SGDT bias (selected top voltage) reduces the NCC effect during one of a read operation and a verify operation despite the NCC effect coupling to the selected string SGD.

[0133] According to another aspect, the control device is further configured to adaptively adjust the selected top voltage based on a transistor threshold voltage of the plurality of top drain side select gate SGD transistors. In more detail, the control device is further configured to detect a threshold voltage V 检测 initialized to a predetermined detection threshold voltage V 检测 in response to receiving a memory operation command. The control device is further configured to count a top drain side select gate quantity N 检测 of those top drain side select gate transistors of the plurality of top drain side select gate SGD transistors having a transistor threshold voltage above the detection threshold voltage V 检测 By counting the top drain side select gate quantity N 检测 of those top drain side select gate transistors of the plurality of top drain side select gate SGD transistors having a transistor threshold voltage above the detection threshold voltage V 检测 , the control device detects the tail threshold voltage Vt on the SGD. Figure 21 A threshold voltage Vt distribution of SGD transistors having relatively lower and higher threshold voltages Vt and corresponding tail threshold voltages Vt are shown. The control device determines a top drain side select gate quantity N检测 Whether it is less than the gate quantity detection threshold selected on the top drain side. The control device additionally detects the threshold voltage V by incrementing the detection threshold voltage by Δ. 检测 And the returned count has a voltage V higher than the detection threshold voltage. 检测 The threshold voltage of the transistor, the top drain side selected gate of the SGDT transistor, and the top drain side selected gate amount N. 检测 In response to the selection of gate amount N on the top drain side 检测 The selected gate quantity detection threshold voltage is not less than the top drain side selection threshold. The control device is also configured to set the selected top voltage to be equal to the detection threshold voltage V. 检测 An adaptive, unselected top voltage VSGDT is applied in response to a predetermined fixed overdrive voltage (e.g., 2a.u.) to select the gate amount N on the top drain side. 检测 The threshold value is less than the gate quantity detection threshold selected on the top drain side. Figure 21 The diagram also illustrates an exemplary adaptive unselected top voltage for an SGDT transistor with relatively low and high threshold voltages Vt. The control device then continues memory operation using the adaptive selected top voltage VSGDT. Therefore, an adaptive method is used to reduce the bias of the selected SGDT, where the selected SGDT bias (i.e., the selected top voltage) adapts to the threshold voltage Vt of the SGDT transistor. This minimizes the adjacent cross-coupling (NCC) effect in the diagonal direction between the unselected SGDT and the selected SGD, and better cuts off unselected strings. Such a strategy can also significantly reduce the voltage difference between the SGDT and SGD layers, thereby reducing concerns about SGDT injection interference.

[0134] These strings can be grouped into strings that include a number of strings. The memory device also includes multiple drivers, each coupled to one or more strings in the string group. Figure 22 and Figure 23 Exemplary groups of strings are shown, along with the corresponding NCC and NSI effects when these strings are selected. Figure 23 As shown, with Figure 22 In contrast, because unselected strings are electrically different or disconnected (i.e., SGDT disconnection), NCC and NSI effects can be reduced. Figure 23 Furthermore, the number of strings can be greater than the number of drivers. Therefore, according to one aspect, the control device is further configured to select at least one unselected top voltage and a selected top voltage based on which of the multiple drivers coupled to each of one or more strings in the string group.

[0135] Figure 24 and Figure 25The steps of a method for operating a memory device are illustrated. As described above, a memory device (e.g., Figure 1A The memory device 100 includes connections to a plurality of word lines (e.g., Figure 6B Data word line layer (word line) WLL0 to WLL10 or Figure 6D A word line memory cell (e.g., data memory cell MC and WLL10) in WLL10 Figure 6D Virtual memory cells 682, 683). The memory cells are arranged in one or more strings (e.g., Figure 6B The NAND strings NS1 and NS2 are configured to maintain a threshold voltage Vt or Vth corresponding to one of a plurality of memory states. Each of these strings has a plurality of drain-side selected-gate transistors (SGD and SGDT transistors) located on the drain side of that particular string, and that particular string includes one of a plurality of top-drain-side selected-gate SGDT transistors. The plurality of top-drain-side selected-gate SGDT transistors are connected to one of a plurality of bit lines and coupled to a memory cell of one of the strings. (Refer to [reference first]) Figure 24 The method includes step 1400: during memory operation, applying an unselected top voltage to one of the plurality of top-drain-side-select-gate SGDT transistors. The method also includes step 1402: during memory operation, simultaneously applying a selected top voltage to the selected top-drain-side-select-gate SGDT transistors, wherein the unselected top voltage is intentionally different from the selected top voltage. Also, according to one aspect, the unselected top voltage is less than the selected top voltage. For example, the unselected top voltage may be approximately zero volts or a negative voltage.

[0136] As discussed, the plurality of word lines and the plurality of dielectric layers extend horizontally and overlie one another in an alternating fashion, and the strings extend vertically through the stack. The plurality of drain side select gate transistors includes one of the plurality of other drain side select gate (SGD) transistors connected in series between the one of the plurality of top drain side select gate (SGDT) transistors and the memory cells of each of the strings. The method further includes the step of applying a selected other voltage to the selected other drain side select gate (SGD) transistors of the plurality of other drain side select gate (SGD) transistors during the memory operation, the unselected top voltage being less than the selected other voltage. As a result, adjacent cross-coupling effects between unselected ones of the plurality of top drain side select gate (SGDT) transistors and selected ones of the plurality of top drain side select gate (SGDT) transistors are minimized.

[0137] Reference is now made to Figure 25 , the method further includes the step 1404 of adaptively adjusting the selected top voltage based on transistor threshold voltages of the plurality of top drain side select gate (SGDT) transistors. More specifically, the method further includes the step 1406 of receiving a memory operation command (e.g., a program command, or one of a read command or a verify command). Next, 1408 the detection threshold voltage V 检测 is initialized to a predetermined detection threshold voltage (e.g., 2 a.u.) in response to receiving the memory operation command. The method continues with the step 1410 of counting a number N 检测 of top drain side select gates of those of the plurality of top drain side select gate (SGDT) transistors having transistor threshold voltages above the detection threshold voltage V 检测 . The method further includes the step 1412 of determining whether the number N 检测 of top drain side select gates is less than a top drain side select gate number detection threshold. The method additionally includes the step 1414 of incrementing the detection threshold voltage V 检测 by a delta detection threshold voltage, and returning to counting the number N 检测 of top drain side select gates of those of the plurality of top drain side select gate (SGDT) transistors having transistor threshold voltages above the detection threshold voltage V 检测 in response to the number N 检测 of top drain side select gates not being less than the top drain side select gate number detection threshold. The method further includes the step 1416 of setting the selected top voltage to be equal to the detection threshold voltage V 检测 plus an adaptive unselected top voltage of a predetermined fixed overdrive voltage in response to the number N检测 Less than top drain side select gate amount detection threshold. Next, 1418 continues memory operations using the adaptive selected top voltage VSGDT. Thus, the tail threshold voltage Vt on SGDT is detected prior to regular memory operations, and the selected SGDT bias is set adaptively (e.g., +2 a.u. tail voltage threshold on SGDT). This guarantees sufficient selected SGDT overdrive and minimal NCC effect between selected SGDT and unselected SGD. The method can be easily extended to adjust the bias applied to dummy word lines.

[0138] As discussed and in accordance with one aspect, the memory operation is a program operation. Thus, the method further includes the step of, during the program operation, applying at least one program pulse in a program voltage to selected word lines in the plurality of word lines while applying a pass voltage to unselected word lines in the plurality of word lines. Alternatively or in addition, the memory operation is one of a read operation and a verify operation, and the method further includes the step of, during the one of a read operation and a verify operation, applying one of a read voltage and a verify voltage to selected word lines in the plurality of word lines while applying a pass voltage to unselected word lines in the plurality of word lines.

[0139] Also, the strings can be grouped into string groups that include a string amount of strings. The memory device can also include a plurality of drivers that are each coupled to one or more strings of a string group, and the string amount of strings can be greater than a driver amount of the plurality of drivers. Thus, the method further includes the step of selecting the at least one unselected top voltage and the selected top voltage based on which driver of the plurality of drivers is coupled to each of the one or more strings of the string group.

[0140] Advantages of the memory devices and methods disclosed herein include reducing NCC effects during data word line operations (e.g., program operations or read / verify operations). Thus, the half-circle SGD technique becomes more practical due to the memory devices and methods disclosed herein using an unselected top voltage that is electrically separate (i.e., intentionally different electrically) compared to the selected top voltage.

[0141] Obviously, many variations and modifications of the described and illustrated implementations can be effected without departing from the scope of the application. The foregoing description has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Various elements or features of a specific implementation can be substituted for elements or features of another implementation on the same application and vice versa, depending on the variation and modification of specific implementation. The same can hold true for the description of specific implementations where not everything stated in the description may be required to implement the implementations. Such variations and modifications are considered to be within the scope of the disclosure. The implementation(s) should not be limited, except as by the claims.

Claims

1. A memory device comprising: memory cells connected to one of a plurality of word lines and arranged in strings and configured to hold threshold voltages; each of the strings having a plurality of drain-side select gate transistors on a drain-side of the one of the strings, and including one of a plurality of top drain-side select gate transistors connected to one of a plurality of bit lines and coupled to the memory cells of the one of the strings; and a control device coupled to the plurality of word lines, the plurality of bit lines, and the plurality of drain-side select gate transistors, and configured to: apply an unselected top voltage to unselected ones of the plurality of top drain-side select gate transistors during a memory operation, and apply a selected top voltage to selected ones of the plurality of top drain-side select gate transistors concurrently during the memory operation, the unselected top voltage being electrically different from the selected top voltage; wherein the control device is further configured to adaptively adjust the selected top voltage based on transistor threshold voltages of the plurality of top drain-side select gate transistors; and wherein the control device is further configured to: initialize a detection threshold voltage to a predetermined detection threshold voltage in response to receiving a memory operation command; count a top drain-side select gate quantity of those of the plurality of top drain-side select gate transistors having the transistor threshold voltages higher than the detection threshold voltage; determine whether the top drain-side select gate quantity is less than a top drain-side select gate quantity detection threshold; increment the detection threshold voltage by a delta detection threshold voltage and return to count the top drain-side select gate quantity of those of the plurality of top drain-side select gate transistors having the transistor threshold voltages higher than the detection threshold voltage in response to the top drain-side select gate quantity not being less than a top drain-side select gate quantity detection threshold; set the selected top voltage to an adaptive selected top voltage equal to the detection threshold voltage plus a predetermined fixed overdrive voltage in response to the top drain-side select gate quantity being less than a top drain-side select gate quantity detection threshold; and continue the memory operation using the adaptive selected top voltage.

2. The memory device of claim 1, wherein the unselected top voltage is less than the selected top voltage. ​ ​ 3. The memory device of claim 1, wherein the plurality of word lines and plurality of dielectric layers extend horizontally in a stack and overlie one another in an alternating fashion and the strings extend vertically through the stack, the plurality of drain side select gate transistors include one of a plurality of other drain side select gate transistors connected in series between the one of the plurality of top drain side select gate transistors and the memory cells of each of the strings, and the control device is further configured to, during the memory operation, apply a selected other voltage to a selected one of the plurality of other drain side select gate transistors, the unselected top voltage being less than the selected other voltage.

4. The memory device of claim 1, wherein the memory operation is a program operation and the control device is further configured to, during the program operation, apply at least one program pulse of a program voltage to selected ones of the plurality of word lines while applying a pass voltage to unselected ones of the plurality of word lines.

5. The memory device of claim 1, wherein the memory operation is one of a read operation and a verify operation and the control device is further configured to, during the one of the read operation and the verify operation, apply one of a read voltage and a verify voltage to selected ones of the plurality of word lines while applying a pass voltage to unselected ones of the plurality of word lines.

6. The memory device of claim 1, wherein the strings are grouped into string groups comprising a string quantity of the strings, the memory device further comprising a plurality of drivers each coupled to one or more of the strings of the string groups, the string quantity of the strings being greater than a driver quantity of the plurality of drivers, and the control device is further configured to select at least one of the unselected top voltage and the selected top voltage based on which one of the plurality of drivers is coupled to each of the one or more of the strings of the string groups.

7. A controller in communication with a memory device, the memory device comprising memory cells connected to one of a plurality of word lines and arranged into strings and configured to hold threshold voltages, each of the strings having a plurality of drain side select gate transistors located on a drain side of the one of the strings, and one of a plurality of top drain side select gate transistors connected to one of a plurality of bit lines and coupled to the memory cells of the one of the strings, the controller configured to: during a memory operation, instructing the memory device to apply an unselected top voltage to unselected top drain-side select gate transistors of the plurality of top drain-side select gate transistors; and concurrently instruct the memory device to apply a selected top voltage to a selected one of the plurality of top drain side select gate transistors, the unselected top voltage being electrically different from the selected top voltage, during the memory operation. wherein the controller is further configured to adaptively adjust the selected top voltage based on transistor threshold voltages of the plurality of top drain side select gate transistors; and wherein the controller is further configured to: initialize a detection threshold voltage to a predetermined detection threshold voltage in response to receiving a memory operation command; instruct the memory device to count a top drain side select gate quantity of those of the plurality of top drain side select gate transistors having a transistor threshold voltage higher than the detection threshold voltage; determine whether the top drain side select gate quantity is less than a top drain side select gate quantity detection threshold; instruct the memory device to increment the detection threshold voltage by a delta detection threshold voltage and return to counting the top drain side select gate quantity of those of the plurality of top drain side select gate transistors having a transistor threshold voltage higher than the detection threshold voltage in response to the top drain side select gate quantity not being less than a top drain side select gate quantity detection threshold; instruct the memory device to set the selected top voltage to an adaptive selected top voltage equal to the detection threshold voltage plus a predetermined fixed overdrive voltage in response to the top drain side select gate quantity being less than a top drain side select gate quantity detection threshold; and instruct the memory device to continue the memory operation using the adaptive selected top voltage.

8. The controller of claim 7, wherein the plurality of word lines and plurality of dielectric layers extend horizontally in a stack and overlie one another in an alternating fashion and the strings extend vertically through the stack, the plurality of drain side select gate transistors include one of a plurality of other drain side select gate transistors connected in series between the one of the plurality of top drain side select gate transistors and the memory cells of each of the strings, and the controller is further configured to instruct the memory device to apply a selected other voltage to a selected one of the plurality of other drain side select gate transistors during the memory operation, the unselected top voltage being less than the selected other voltage.

9. A method of operating a memory device, the memory device including memory cells connected to one of a plurality of word lines and arranged into strings and configured to hold threshold voltages, each of the strings having a plurality of drain side select gate transistors on a drain side of the one of the strings, and one of a plurality of top drain side select gate transistors connected to one of a plurality of bit lines and coupled to the memory cells of the one of the strings, the method comprising the steps of: applying an unselected top voltage to unselected ones of the plurality of top drain side select gate transistors during a memory operation; ​ applying a selected top voltage to selected ones of the plurality of top drain side select gate transistors concurrently during the memory operation, the unselected top voltage being electrically different from the selected top voltage; adjusting the selected top voltage adaptively based on transistor threshold voltages of the plurality of top drain side select gate transistors; initializing a detection threshold voltage to a predetermined detection threshold voltage in response to receiving a memory operation command; counting a top drain side select gate quantity of those of the plurality of top drain side select gate transistors having the transistor threshold voltages higher than the detection threshold voltage; determining whether the top drain side select gate quantity is less than a top drain side select gate quantity detection threshold; incrementing the detection threshold voltage by a delta detection threshold voltage and returning to counting the top drain side select gate quantity of those of the plurality of top drain side select gate transistors having the transistor threshold voltages higher than the detection threshold voltage in response to the top drain side select gate quantity not being less than a top drain side select gate quantity detection threshold; setting the selected top voltage to an adaptive selected top voltage equal to the detection threshold voltage plus a predetermined fixed overdrive voltage in response to the top drain side select gate quantity being less than a top drain side select gate quantity detection threshold; and continuing the memory operation using the adaptive selected top voltage.

10. The method of claim 9, wherein the unselected top voltage is less than the selected top voltage.

11. The method of claim 9, wherein the plurality of word lines and plurality of dielectric layers extend horizontally in a stack overlying one another in an alternating fashion and the strings extend vertically through the stack, the plurality of drain side select gate transistors including one of a plurality of other drain side select gate transistors connected in series between the one of the plurality of top drain side select gate transistors and the memory cells of each of the strings, the method further comprising the step of applying a selected other voltage to selected ones of the plurality of other drain side select gate transistors concurrently during the memory operation, the unselected top voltage being less than the selected other voltage.

12. The method of claim 9, wherein the memory operation is a program operation, and the method further comprises the step of applying at least one program pulse of a program voltage to selected ones of the plurality of word lines concurrently with applying a pass voltage to unselected ones of the plurality of word lines during the program operation. ​ 13. The method of claim 9, wherein the memory operation is one of a read operation and a verify operation, and the method further comprises the step of, during the one of the read operation and the verify operation, applying one of a read voltage and a verify voltage to selected word lines of the plurality of word lines while applying a pass voltage to unselected word lines of the plurality of word lines.

14. The method of claim 9, wherein the strings are grouped into string groups comprising a string quantity of the strings, the memory device further comprises a plurality of drivers each coupled to one or more of the strings of the string groups, the string quantity of the strings is greater than a driver quantity of the plurality of drivers, and the method further comprises the step of selecting at least one of the unselected top voltage and the selected top voltage based on which of the plurality of drivers is coupled to each of the one or more of the strings of the string groups.

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