Pixel circuit and display panel

Abstract

A pixel circuit (PIX) and a display panel, comprising: a first reset module (01), a second reset module (02), a driving transistor (T0), a first light emitting control module (03), a write compensation module (04) and a light emitting device (OLED); wherein: the write compensation module (04) is used to write a data signal into the light emitting device (OLED) through the driving transistor (T0) and to compensate for a threshold voltage (Vth) of the driving transistor (T0); the first reset module (01) is used to, under the control of a first reset control terminal (RET1), reset a first reset signal terminal (i1) The invention relates to a method for providing a gate of a driving transistor (T0) with a signal provided to the gate of the driving transistor (T0); a second reset module (02) is used for providing a signal of a second reset signal terminal (i2) to the anode of a light emitting device (OLED) under the control of a second reset control terminal (RET2); a first light emitting control module (03) is used for connecting the drain of the driving transistor (T0) to the anode of the light emitting device (OLED) under the control of a first light emitting control terminal (EM); a cathode of the light emitting device (OLED) is connected to a first power supply voltage terminal (VSS); and a potential of the first reset signal terminal (i1) is greater than a potential of the second reset signal terminal (i2).

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) is one of the hot topics in the field of flat panel display research. Compared with liquid crystal display, OLED has the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed. At present, OLED has begun to replace traditional liquid crystal display (LCD) in the field of flat panel display such as mobile phones, PDAs, digital cameras, etc. Among them, pixel circuit design is the core technology content of OLED display and has important research significance.

[0003] Unlike LCD, which uses a stable voltage to control brightness, OLED is current-driven and requires a stable current to control light emission. A general pixel circuit usually consists of three parts: a driving transistor, a switching transistor, and a storage capacitor. When OLED emits light, the storage capacitor cannot store the potential of the gate of the driving transistor for a long time due to the long light emission time of OLED, and the leakage of the gate of the driving transistor will cause display abnormality. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a pixel circuit and a display panel, and the specific scheme is as follows:

[0005] A pixel circuit provided in an embodiment of the present application includes: a first reset module, a second reset module, a driving transistor, a first light emitting control module, a write compensation module and a light emitting device; wherein:

[0006] The write compensation module is used to write the data signal into the light emitting device through the driving transistor and compensate the threshold voltage of the driving transistor;

[0007] The first reset module is used for providing the signal of the first reset signal terminal to the gate of the driving transistor under the control of the first reset control terminal;

[0008] The second reset module is used for providing the signal of the second reset signal terminal to the anode of the light emitting device under the control of the second reset control terminal;

[0009] The first light emitting control module is used to connect the drain of the driving transistor to the anode of the light emitting device under the control of the first light emitting control terminal;

[0010] The cathode of the light emitting device is connected to the first power supply voltage terminal;

[0011] The potential of the first reset signal terminal is greater than the potential of the second reset signal terminal.

[0012] Optionally, in the pixel circuit provided in an embodiment of the present application, the potential of the first power supply voltage terminal is the same as the potential of the second reset signal terminal.

[0013] Optionally, in the pixel circuit provided in the embodiment of the present application, the first reset module includes a first switch transistor, a gate of the first switch transistor is connected to the first reset control terminal, a first electrode of the first switch transistor is connected to the first reset signal terminal, and a second electrode of the first switch transistor is connected to the gate of the driving transistor;

[0014] The second reset module comprises a second switch transistor, a gate of the second switch transistor is connected to the second reset control terminal, a first electrode of the second switch transistor is connected to the second reset signal terminal, and a second electrode of the second switch transistor is connected to the anode of the light emitting device;

[0015] The first light-emitting control module includes a third switch transistor, a gate of the third switch transistor is connected to the first light-emitting control terminal, a first electrode of the third switch transistor is connected to the drain of the driving transistor, and a second electrode of the third switch transistor is connected to the anode of the light-emitting device.

[0016] Optionally, in the pixel circuit provided in the embodiment of the present application, the write compensation module includes: a fourth switch transistor, a fifth switch transistor, a sixth switch transistor and a first capacitor; wherein:

[0017] The gate of the fourth switch transistor is connected to the scan signal terminal, the first electrode of the fourth switch transistor is connected to the gate of the drive transistor, and the second electrode of the fourth switch transistor is connected to the drain of the drive transistor;

[0018] The gate of the fifth switch transistor is connected to the scan signal terminal, the first electrode of the fifth switch transistor is connected to the data signal terminal, and the second electrode of the fifth switch transistor is connected to the source of the drive transistor;

[0019] The gate of the sixth switch transistor is connected to the first light emitting control terminal, the first electrode of the sixth switch transistor is connected to the gate of the driving transistor, and the second electrode of the sixth switch transistor is connected to the second power supply voltage terminal;

[0020] The first capacitor is connected between the second power supply voltage terminal and the gate of the driving transistor.

[0021] Optionally, in the pixel circuit provided in the embodiment of the present application, the write compensation module includes: the write compensation module includes: a fourth switch transistor, a fifth switch transistor, a sixth switch transistor and a first capacitor; wherein:

[0022] The gate of the fourth switch transistor is connected to the scan signal terminal, the first electrode of the fourth switch transistor is connected to the gate of the drive transistor, and the second electrode of the fourth switch transistor is connected to the source of the drive transistor;

[0023] The gate of the fifth switch transistor is connected to the scan signal terminal, the first electrode of the fifth switch transistor is connected to the data signal terminal, and the second electrode of the fifth switch transistor is connected to the drain of the drive transistor;

[0024] The gate of the sixth switch transistor is connected to the first light emitting control terminal, the first electrode of the sixth switch transistor is connected to the gate of the driving transistor, and the second electrode of the sixth switch transistor is connected to the second power supply voltage terminal;

[0025] The first capacitor is connected between the second power supply voltage terminal and the gate of the driving transistor.

[0026] Optionally, in the pixel circuit provided in the embodiment of the present application, the write compensation module includes: the write compensation module includes: a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, a seventh switch transistor and a first capacitor; wherein:

[0027] The gate of the fourth switch transistor is connected to the first scan signal terminal, the first electrode of the fourth switch transistor is connected to the gate of the drive transistor, and the second electrode of the fourth switch transistor is connected to the drain of the drive transistor;

[0028] The gate of the fifth switch transistor is connected to the second scan signal terminal, the first electrode of the fifth switch transistor is connected to the data signal terminal, and the second electrode of the fifth switch transistor is connected to the first electrode of the first capacitor;

[0029] The second electrode of the first capacitor is connected to the gate of the driving transistor;

[0030] The gate of the sixth switch transistor is connected to the first light emitting control terminal, the first electrode of the sixth switch transistor is connected to the reference signal terminal, and the second electrode of the sixth switch transistor is connected to the first electrode of the first capacitor;

[0031] The gate of the seventh switch transistor is connected to the second reset control terminal, the first electrode of the seventh switch transistor is connected to the reference signal terminal, and the second electrode of the seventh switch transistor is connected to the first electrode of the first capacitor.

[0032] Correspondingly, an embodiment of the present application further provides a display panel, which includes a display area and a frame area, and the display area includes a plurality of pixel circuits of any one of the above types provided by the embodiment of the present application arranged in a matrix.

[0033] Optionally, in the display panel provided in the embodiment of the present application, the display area further includes a plurality of first reset signal lines and a plurality of second reset signal lines;

[0034] Each of the first reset signal lines is correspondingly connected to a first reset signal terminal of a row or a column of pixel circuits;

[0035] Each of the second reset signal lines is correspondingly connected to the second reset signal terminals of a row or a column of the pixel circuits.

[0036] Optionally, in the display panel provided in the embodiment of the present application, the frame area includes a driving chip, a first reset signal bus connected to the driving chip, a second reset signal bus and a first power supply voltage bus;

[0037] The plurality of first reset signal lines are all connected to the first reset signal bus, the plurality of second reset signal lines are all connected to the second reset signal bus, and the first power supply voltage bus is connected to the first power supply voltage terminal of the pixel circuit.

[0038] Optionally, in the display panel provided in the embodiment of the present application, the frame area includes a driving chip, a first reset signal bus and a first power supply voltage bus connected to the driving chip;

[0039] The plurality of first reset signal lines are all connected to the first reset signal bus, and the plurality of second reset signal lines and the first power supply voltage terminal of the pixel circuit are all connected to the first power supply voltage bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application;

[0041] Figure 2 A schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application;

[0042] Figure 3 A schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application;

[0043] Figure 4 A schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application;

[0044] Figure 5A timing diagram of a pixel circuit provided in an embodiment of the present application;

[0045] Figure 6 Another timing diagram of the pixel circuit provided in the embodiment of the present application;

[0046] Figure 7 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application;

[0047] Figure 8 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0048] Fig. 9 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0049] Fig.10 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0050] Fig.11 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0051] Fig.12 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0052] Fig.13 A schematic diagram of the structure of another display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described below in conjunction with the drawings and examples. However, the example embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present application more comprehensive and complete, and to fully convey the concepts of the example embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in this application are all explained using the drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0054] It should be noted that specific details are described in the following description to facilitate a full understanding of the present application. However, the present application can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific implementation methods disclosed below. The subsequent description of the specification is a preferred implementation method for implementing the present application, but the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application. The scope of protection of the present application shall be determined by the definition of the attached claims.

[0055] The pixel circuit and display panel provided in the embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0056] An embodiment of the present application provides a pixel circuit, such as Figure 1 As shown, it includes: a first reset module 01, a second reset module 02, a driving transistor T0, a first light-emitting control module 03, a write compensation module 04 and a light-emitting device OLED; wherein: the write compensation module 04 is used to write the data signal to the light-emitting device OLED through the driving transistor T0, and compensate for the threshold voltage of the driving transistor T0; the first reset module 01 is used to provide the signal of the first reset signal terminal i1 to the gate of the driving transistor T0 under the control of the first reset control terminal RET1; the second reset module 02 is used to provide the signal of the second reset signal terminal i2 to the anode of the light-emitting device OLED under the control of the second reset control terminal RET2; the first light-emitting control module 03 is used to connect the drain of the driving transistor T0 to the anode of the light-emitting device OLED under the control of the first light-emitting control terminal EM; the cathode of the light-emitting device OLED is connected to the first power supply voltage terminal VSS; the potential of the first reset signal terminal i1 is greater than the potential of the second reset signal terminal i2.

[0057] In the pixel circuit provided by the embodiment of the present application, the first reset module provides the signal of the first reset signal terminal to the gate of the driving transistor under the control of the first reset control terminal, and uses the signal of the first reset signal terminal to reset the gate of the driving transistor; the second reset module provides the signal of the second reset signal terminal to the anode of the light-emitting device under the control of the second reset control terminal, and uses the signal of the second reset signal terminal to reset the anode of the light-emitting device; increasing the potential of the first reset signal terminal can reduce the leakage current at the gate of the driving transistor, and reducing the potential of the first reset signal terminal can reduce the leakage current flowing through the light-emitting device. Therefore, in the present application, the potential of the first reset signal terminal is greater than the potential of the second reset signal terminal, which can reduce the leakage current of the pixel circuit, prevent the screen from flickering, and ensure the display quality.

[0058] Optionally, in the pixel circuit provided in the embodiment of the present application, the potential of the first power supply voltage terminal is the same as the potential of the second reset signal terminal i2. This can further reduce the leakage current flowing through the light emitting device OLED and ensure the display image quality.

[0059] It should be noted that the pixel circuit provided in the embodiment of the present application is applicable to any pixel circuit that needs to reset the anode of the driving transistor and the light-emitting device, such as Figure 7 The pixel circuit shown in the figure includes a first reset module 01, a second reset module 02, a driving transistor T0, a writing module 05 and a light-emitting device OLED; the writing module 05 is used to write the data signal to the light-emitting device OLED through the driving transistor T0, but due to the process and device aging, the threshold voltage of the driving transistor T0 of the pixel circuit may be uneven. Therefore, the pixel circuit of the present application can be as follows Figure 1 As shown, the writing compensation module 04 is used to write the data signal into the light-emitting device through the driving transistor, and the threshold voltage of the driving transistor is compensated to avoid the threshold voltage of the driving transistor of the pixel circuit from shifting.

[0060] Optionally, in the pixel circuit provided in the embodiment of the present application, if Figure 1 As shown, the first reset module 01 includes a first switch transistor T1, the gate of the first switch transistor T1 is connected to the first reset control terminal RET1, the first electrode of the first switch transistor T1 is connected to the first reset signal terminal i1, and the second electrode of the first switch transistor T1 is connected to the gate of the driving transistor T0; the second reset module 02 includes a second switch transistor T2, the gate of the second switch transistor T2 is connected to the second reset control terminal RET2, the first electrode of the second switch transistor T2 is connected to the second reset signal terminal i2, and the second electrode of the second switch transistor T2 is connected to the anode of the light-emitting device OLED; the first light-emitting control module 03 includes a third switch transistor T3, the gate of the third switch transistor T3 is connected to the first light-emitting control terminal EM, the first electrode of the third switch transistor T3 is connected to the drain of the driving transistor T0, and the second electrode of the third switch transistor T3 is connected to the anode of the light-emitting device OLED.

[0061] In the specific implementation, the present application does not limit the specific implementation of the write compensation module, and the pixel circuit provided in the embodiment of the present application is suitable for any pixel circuit having a first reset module and a second reset module. The present application is described in detail below in conjunction with specific embodiments. It should be noted that the present embodiment is for better explanation of the present application, but does not limit the present application.

[0062] In one embodiment, in the pixel circuit provided in the embodiment of the present application, if Figure 2As shown, the write compensation module 04 includes: a fourth switch transistor T4, a fifth switch transistor T5, a sixth switch transistor T6 and a first capacitor C1; wherein: the gate of the fourth switch transistor T4 is connected to the scan signal terminal G1, the first electrode of the fourth switch transistor T4 is connected to the gate of the driving transistor T0, and the second electrode of the fourth switch transistor T4 is connected to the drain of the driving transistor T0; the gate of the fifth switch transistor T5 is connected to the scan signal terminal G1, the first electrode of the fifth switch transistor T5 is connected to the data signal terminal D1, and the second electrode of the fifth switch transistor T5 is connected to the source of the driving transistor T0; the gate of the sixth switch transistor T6 is connected to the first light-emitting control terminal EM, the first electrode of the sixth switch transistor T6 is connected to the gate of the driving transistor T0, and the second electrode of the sixth switch transistor T6 is connected to the second power supply voltage terminal VDD; the first capacitor C1 is connected between the second power supply voltage terminal VDD and the gate of the driving transistor T0.

[0063] Specifically, the timing diagram corresponding to the above pixel circuit is as follows: Figure 5 As shown, in the t1 stage, the first switch transistor T1 and the second switch transistor T2 are turned on, the potential of the N1 node is Vi1, and the potential of the anode of the light-emitting device OLED is VSS. In this stage, since the potential of the first power supply voltage terminal VSS is the same as the potential of the second reset signal terminal i2, the leakage current on the light-emitting device OLED can be reduced as much as possible. In the t2 stage, the fourth switch transistor T4, the fifth switch transistor T5 and the driving transistor T0 are turned on, the potential of the N2 node is Vdata, and Vdata is written to the N1 node through the driving transistor T0 and the fourth switch transistor T4 until the potential of the N1 node becomes Vdata+Vth, and the driving transistor T0 is turned off, where Vth is the threshold voltage of the driving transistor T0. In the t3 stage, the third switch transistor T3 and the sixth switch transistor T6 are turned on, the potential of the N2 node is VSS, and the potential of the N1 node is still Vdata+Vth. The driving transistor T0 works in a saturated state. According to the saturated state current characteristics, it can be known that the working current I flowing through the driving transistor T0 and used to drive the light-emitting device OLED to emit light is oled Satisfy the formula: I oled =K(V gs –Vth) 2 =K[Vdata+Vth-V DD –Vth] 2 =K(Vdata-V DD ) 2 , where K is a structural parameter. This value is relatively stable in the same structure and can be regarded as a constant. In this stage, since the potential of the first reset signal terminal i1 is relatively high, the leakage current of the N1 node can be reduced.

[0064] In another embodiment, in the pixel circuit provided in the embodiment of the present application, if Figure 3 As shown, the write compensation module 04 includes: the write compensation module 04 includes: a fourth switch transistor T4, a fifth switch transistor T5, a sixth switch transistor T6 and a first capacitor C1; wherein: the gate of the fourth switch transistor T4 is connected to the scan signal terminal G1, the first electrode of the fourth switch transistor T4 is connected to the gate of the driving transistor T0, and the second electrode of the fourth switch transistor T4 is connected to the source of the driving transistor T0; the gate of the fifth switch transistor T5 is connected to the scan signal terminal G1, the first electrode of the fifth switch transistor T5 is connected to the data signal terminal D1, and the second electrode of the fifth switch transistor T5 is connected to the drain of the driving transistor T0; the gate of the sixth switch transistor T6 is connected to the first light-emitting control terminal EM, the first electrode of the sixth switch transistor T6 is connected to the gate of the driving transistor T0, and the second electrode of the sixth switch transistor T6 is connected to the second power supply voltage terminal VDD; the first capacitor C1 is connected between the second power supply voltage terminal VDD and the gate of the driving transistor T0.

[0065] Specifically, the timing diagram corresponding to the above pixel circuit is as follows: Figure 5 As shown, in the t1 stage, the first switch transistor T1 and the second switch transistor T2 are turned on, the potential of the N1 node is Vi1, and the potential of the anode of the light-emitting device OLED is VSS. In this stage, since the potential of the first power supply voltage terminal VSS is the same as the potential of the second reset signal terminal i2, the leakage current on the light-emitting device OLED can be reduced as much as possible. In the t2 stage, the fourth switch transistor T4, the fifth switch transistor T5 and the driving transistor T0 are turned on, the potential of the N2 node is Vdata, and Vdata is written to the N1 node through the driving transistor T0 and the fourth switch transistor T4 until the potential of the N1 node becomes Vdata+Vth, and the driving transistor T0 is turned off, where Vth is the threshold voltage of the driving transistor T0. In the t3 stage, the third switch transistor T3 and the sixth switch transistor T6 are turned on, the potential of the N3 node is VDD, and the potential of the N1 node is still Vdata+Vth. The driving transistor T0 works in a saturated state. According to the saturated state current characteristics, it can be known that the working current I flowing through the driving transistor T0 and used to drive the light-emitting device OLED to emit light is oled Satisfy the formula: I oled =K(V gs –Vth) 2 =K[Vdata+Vth-V DD –Vth] 2 =K(Vdata-V DD ) 2, where K is a structural parameter. This value is relatively stable in the same structure and can be regarded as a constant. In this stage, since the potential of the first reset signal terminal i1 is relatively high, the leakage current of the N1 node can be reduced.

[0066] In yet another embodiment, in the pixel circuit provided in the embodiment of the present application, if Figure 4 As shown, the write compensation module 04 includes: the write compensation module 04 includes: a fourth switch transistor T4, a fifth switch transistor T5, a sixth switch transistor T6, a seventh switch transistor T7 and a first capacitor C1; wherein: the gate of the fourth switch transistor T4 is connected to the first scan signal terminal G1, the first electrode of the fourth switch transistor T4 is connected to the gate of the driving transistor T0, and the second electrode of the fourth switch transistor T4 is connected to the drain of the driving transistor T0; the gate of the fifth switch transistor T5 is connected to the second scan signal terminal G2, the first electrode of the fifth switch transistor T5 is connected to the data signal terminal D1, and the The second electrode of the fifth switch transistor T5 is connected to the first electrode of the first capacitor C1; the second electrode of the first capacitor C1 is connected to the gate of the driving transistor T0; the gate of the sixth switch transistor T6 is connected to the first light-emitting control terminal EM, the first electrode of the sixth switch transistor T6 is connected to the reference signal terminal REF, and the second electrode of the sixth switch transistor T6 is connected to the first electrode of the first capacitor C1; the gate of the seventh switch transistor T7 is connected to the second reset control terminal RET2, the first electrode of the seventh switch transistor T7 is connected to the reference signal terminal REF, and the second electrode of the seventh switch transistor T7 is connected to the first electrode of the first capacitor C1.

[0067] Specifically, the timing diagram corresponding to the above pixel circuit is as follows: Figure 6As shown, in the t1 stage, the first switch transistor T1, the second switch transistor T2 and the seventh switch transistor T7 are turned on, the potential of the N1 node is VREF, the potential of the N2 node is Vi1, and the potential of the anode of the light-emitting device OLED is VSS. In this stage, since the potential of the first power supply voltage terminal VSS is the same as the potential of the second reset signal terminal i2, the leakage current on the light-emitting device OLED can be reduced as much as possible. In the t2 stage, the fourth switch transistor T4 and the driving transistor T0 are turned on, and VDD is written to the N2 node through the driving transistor T0 and the fourth switch transistor T4 until the potential of the N2 node becomes VDD+Vth, and the driving transistor T0 is turned off, where Vth is the threshold voltage of the driving transistor T0. In the t3 stage, the fifth switch transistor T5 is turned on, the potential of the N1 node is Vdata, and the potential of the N2 node becomes VDD+Vth+Vdata-VREF. In the t4 stage, the third switch transistor T3 and the sixth switch transistor T6 are turned on, the potential of the N1 node becomes VREF, the potential of the N2 node becomes VDD+Vth+Vdata-VREF, and the driving transistor T0 works in a saturated state. According to the saturated current characteristics, the working current I flowing through the driving transistor T0 and used to drive the light-emitting device OLED to emit light is oled Satisfy the formula: I oled =K(V gs –Vth) 2 =K[VDD+Vth+Vdata-VREF-V DD –Vth] 2 =K(Vdata-VREF) 2 , where K is a structural parameter. This value is relatively stable in the same structure and can be regarded as a constant. In this stage, since the potential of the first reset signal terminal i1 is relatively high, the leakage current of the N1 node can be reduced.

[0068] In at least one embodiment of the present disclosure, the voltage range of the first reset signal terminal i1 can be -9V to -2V; the voltage range of the second reset signal terminal i2 can be -10V to -2.1V, for example, the voltage of i1 is -8V, -7V, -6V, -5V, -4V, -3V, etc.; the voltage of the second reset signal terminal i2 is -9, -8V, -7V, -6V, -5V, -4V, -3V, etc.

[0069] In at least one embodiment of the present disclosure, the voltage range of the first power supply voltage terminal bus VSS is -10V to -2.1V, and can be -4V to -2.1V in specific implementation. For example, when the voltage of the second reset signal terminal i2 is between -4V and -2.1V, it can be connected to the same potential as the first power supply voltage terminal bus VSS. In this way, the signal of the second reset signal terminal i2 can be provided by the first power supply voltage terminal bus VSS (cathode potential line VSS) arranged around the display area, and the layout space can be optimized at this time.

[0070] In at least one embodiment of the present disclosure, the voltage of the first reset signal terminal i1 may be 0.5 to 3 times higher than the voltage of the second reset signal terminal i2, so that the leakage current may be reduced.

[0071] In at least one embodiment of the present disclosure, the voltage of the second reset signal terminal i2 may be lower than VSS, such as an absolute value of 0.5 to 2 times of VSS, which can reduce the occurrence of leakage current.

[0072] It should be noted that the driving transistor and the switching transistor mentioned in the above embodiments of the present application can be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited here.

[0073] Optionally, in the above pixel circuit provided in the embodiment of the present application, the transistor may be a P-type transistor or an N-type transistor, which is not limited here.

[0074] Based on the same inventive concept, the embodiment of the present application further provides a display panel, such as Figure 8 and Fig. 9 As shown, the display panel includes a display area AA and a frame area BB, and the display area AA includes a plurality of pixel circuits PIX arranged in a matrix, and the pixel circuit PIX is any of the above-mentioned pixel circuits PIX provided in the embodiment of the present application. Since the principle of solving the problem of the display panel is similar to that of the above-mentioned pixel circuit, the implementation of the liquid display panel can refer to the implementation of the above-mentioned pixel circuit, and the repeated parts will not be repeated.

[0075] Optionally, in the display panel provided in the embodiment of the present application, Figure 8 and Fig. 9 As shown, the display area AA further includes a plurality of first reset signal lines L1 and a plurality of second reset signal lines L2;

[0076] Each first reset signal line L1 is correspondingly connected to a first reset signal terminal i1 of a row or a column of pixel circuits;

[0077] Each second reset signal line L2 is correspondingly connected to a second reset signal terminal i2 of a row or a column of pixel circuits.

[0078] Optionally, in the display panel provided in the embodiment of the present application, Figure 8 As shown, the frame area BB includes a driver chip IC, a first reset signal bus Li1 connected to the driver chip IC, a second reset signal bus Li2, and a first power supply voltage bus VSS; multiple first reset signal lines L1 are connected to the first reset signal bus Li1, multiple second reset signal lines L2 are connected to the second reset signal bus Li2, and the first power supply voltage bus LVSS is connected to the first power supply voltage terminal (not shown in the figure) of the pixel circuit PIX. Compared with the existing display panel, this has less design difficulty and less modification.

[0079] Optionally, the first reset signal bus Li1 and / or the first power supply voltage bus LVSS may be arranged around the AA area, so that the signals in the effective display area AA are uniform.

[0080] Alternatively, optionally, in the display panel provided in the embodiment of the present application, as Fig. 9 As shown, the frame area BB includes a driver chip IC, a first reset signal bus Li1 connected to the driver chip IC, and a first power supply voltage bus LVSS; multiple first reset signal lines L1 are connected to the first reset signal bus Li1, and multiple second reset signal lines L2 and a first power supply voltage terminal of the pixel circuit PIX (not shown in the figure) are connected to the first power supply voltage bus LVSS. This can reduce the number of wirings in the frame area, which is conducive to narrow frame design.

[0081] In a specific implementation, the light emitting devices of each pixel circuit in the display panel share a cathode layer, and the cathode layer is connected to the first power supply voltage bus, thereby realizing the connection between the first power supply voltage bus and the first power supply voltage terminal of each pixel circuit.

[0082] In a specific implementation, in the display panel provided in the embodiment of the present application, if Fig.10 and Fig.11 As shown, when the frame area B is not provided with the second reset signal bus line Li2, that is, the frame area BB is only provided with the first reset signal bus line Li1 and the first power supply voltage bus line LVSS, as shown in FIG. Fig.10 As shown, each second reset signal line L2 can be connected to the first power supply voltage bus LVSS respectively, or can be connected to the first power supply voltage bus LVSS as shown in FIG. Fig.11 As shown, a plurality of second reset signal lines L2 are connected to one wiring line and then connected to the first power voltage bus LVSS.

[0083] In a specific implementation, in the display panel provided in the embodiment of the present application, if Fig.10 and Fig.11 As shown, the frame area BB is generally further provided with a gate drive circuit GOA, which is used to control the gate of each switch transistor in each pixel circuit in the display area AA. The first power supply voltage bus LVSS is provided on the side of the gate drive circuit GOA away from the display area AA, such as Fig.10 As shown, the second reset signal line L2 in the display area AA can be connected to the first power supply voltage bus LVSS through a jumper design, or as shown in FIG. Fig.11 As shown, a plurality of second reset signal lines L2 may be connected to one line and then connected to the first power voltage bus LVSS through a winding manner, bypassing the gate driving circuit GOA.

[0084] In a specific implementation, in the display panel of the present application, if Fig.12 and Fig.13 As shown, it generally includes a base substrate 10, an active layer (Poly layer) 11 located on the base substrate 10, a first gate layer (Gate1) 12, a second gate layer (Gate2) 13, a first source and drain layer (SD1) 14, a second source and drain layer (SD2) 15, an anode layer (Anode) 16, a pixel defining layer (PDL) 17, a light emitting layer (not shown in the figure) and a cathode layer (Cathode) 18. Among them, the gate of the switching transistor in the pixel circuit is generally arranged in the first gate layer 12, a storage electrode is arranged in the second gate layer 13, and the storage electrode and the gate of the driving transistor constitute the first capacitor in the pixel circuit, the source and drain electrodes of the switching transistor are generally arranged in the first source and drain layer 14, the second power supply voltage line (not shown in the figure) connected to the second power supply voltage terminal is generally arranged in the second source and drain layer 15, and the first power supply voltage bus LVSS located in the frame area BB is generally arranged in the cathode layer 18.

[0085] In specific implementation, Fig.12 As shown, the second reset signal line L2 can be connected to the first power supply voltage bus LVSS through the anode layer 16. Alternatively, as shown in FIG. Fig.13 As shown, the second reset signal line L2 is connected to the first power voltage bus LVSS through a via hole penetrating the anode layer 16 and the pixel defining layer 17 .

[0086] This application only illustrates the pixel circuit and display panel provided by this application through the above-mentioned embodiments, and is not limited thereto. In the pixel circuit and display panel provided by the embodiments of this application, the first reset module provides the signal of the first reset signal terminal to the gate of the driving transistor under the control of the first reset control terminal, and uses the signal of the first reset signal terminal to reset the gate of the driving transistor; the second reset module provides the signal of the second reset signal terminal to the anode of the light-emitting device under the control of the second reset control terminal, and uses the signal of the second reset signal terminal to reset the anode of the light-emitting device; increasing the potential of the first reset signal terminal can reduce the leakage current at the gate of the driving transistor, and reducing the potential of the first reset signal terminal can reduce the leakage current flowing through the light-emitting device. Therefore, in this application, the potential of the first reset signal terminal is greater than the potential of the second reset signal terminal, which can reduce the leakage current of the pixel circuit, prevent the screen from flickering, and ensure the display quality.

[0087] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A pixel circuit, comprising: A first reset module, a second reset module, a driving transistor, a first light emitting control module, a write compensation module and a light emitting device; wherein: The write compensation module is used to write the data signal into the light emitting device through the driving transistor and compensate the threshold voltage of the driving transistor; The first reset module is used for providing the signal of the first reset signal terminal to the gate of the driving transistor under the control of the first reset control terminal; The second reset module is used for providing the signal of the second reset signal terminal to the anode of the light emitting device under the control of the second reset control terminal; The first light emitting control module is used to connect the drain of the driving transistor to the anode of the light emitting device under the control of the first light emitting control terminal; The cathode of the light emitting device is connected to the first power supply voltage terminal; The potential of the first reset signal terminal is greater than the potential of the second reset signal terminal; The write compensation module includes: the write compensation module includes: a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, a seventh switch transistor and a first capacitor; wherein: The gate of the fourth switch transistor is connected to the first scan signal terminal, the first electrode of the fourth switch transistor is connected to the gate of the drive transistor, and the second electrode of the fourth switch transistor is connected to the drain of the drive transistor; The gate of the fifth switch transistor is connected to the second scan signal terminal, the first electrode of the fifth switch transistor is connected to the data signal terminal, and the second electrode of the fifth switch transistor is connected to the first electrode of the first capacitor; The second electrode of the first capacitor is connected to the gate of the driving transistor; The gate of the seventh switch transistor is connected to the second reset control terminal, the first electrode of the seventh switch transistor is connected to the reference signal terminal, and the second electrode of the seventh switch transistor is connected to the first electrode of the first capacitor.

2. The pixel circuit according to claim 1, wherein: The potential of the first power supply voltage terminal is the same as the potential of the second reset signal terminal.

3. The pixel circuit according to claim 1 or 2, wherein: The first reset module includes a first switch transistor, a gate of the first switch transistor is connected to the first reset control terminal, a first electrode of the first switch transistor is connected to the first reset signal terminal, and a second electrode of the first switch transistor is connected to the gate of the driving transistor; The second reset module comprises a second switch transistor, a gate of the second switch transistor is connected to the second reset control terminal, a first electrode of the second switch transistor is connected to the second reset signal terminal, and a second electrode of the second switch transistor is connected to the anode of the light emitting device; The first light-emitting control module includes a third switch transistor, a gate of the third switch transistor is connected to the first light-emitting control terminal, a first electrode of the third switch transistor is connected to the drain of the driving transistor, and a second electrode of the third switch transistor is connected to the anode of the light-emitting device.

4. A display panel, comprising a display area and a frame area, wherein the display area comprises a plurality of pixel circuits according to any one of claims 1 to 3 arranged in a matrix.

5. The display panel according to claim 4, wherein: The display area further includes a plurality of first reset signal lines and a plurality of second reset signal lines; Each of the first reset signal lines is correspondingly connected to a first reset signal terminal of a row or a column of pixel circuits; Each of the second reset signal lines is correspondingly connected to the second reset signal terminals of a row or a column of the pixel circuits.

6. The display panel according to claim 5, wherein: The frame area includes a driving chip, a first reset signal bus connected to the driving chip, a second reset signal bus and a first power supply voltage bus; The plurality of first reset signal lines are all connected to the first reset signal bus, the plurality of second reset signal lines are all connected to the second reset signal bus, and the first power supply voltage bus is connected to the first power supply voltage terminal of the pixel circuit.

7. The display panel according to claim 5, wherein: The frame area includes a driving chip, a first reset signal bus and a first power supply voltage bus connected to the driving chip; The plurality of first reset signal lines are all connected to the first reset signal bus, and the plurality of second reset signal lines and the first power supply voltage terminal of the pixel circuit are all connected to the first power supply voltage bus.

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