Display device and method for manufacturing the same

Abstract

A display device (10) having a pixel circuit (PC) is provided. A driving transistor (T4) and a capacitor element (Cp) having a first structure including a crystalline silicon semiconductor layer (SC) are formed in the pixel circuit. The capacitor element includes a first capacitor electrode (17a) electrically connected to a first gate electrode (15a) of the driving transistor, a second capacitor electrode (19a) opposite to the first capacitor electrode, and a dielectric film (18a) arranged between the first capacitor electrode and the second capacitor electrode. The dielectric film (18a) is formed in a layer different from a first interlayer insulating film (16) and a second interlayer insulating film (20).

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] Patent Document 1 discloses a display device including a transistor made of polysilicon, a transistor made of a semiconductor oxide, and a capacitor connected to the transistor made of polysilicon, which are formed on the same substrate.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. WO2015 / 031037 Summary of the Invention

[0006] Technical problems to be solved by the present invention

[0007] In the display device of Patent Document 1, an insulating film covering the gate of a transistor made of polysilicon is used as a dielectric film of a capacitor element, and therefore there is a problem in that it is difficult to optimize the capacitance.

[0008] Technical solutions to technical problems

[0009] A display device according to one embodiment of the present disclosure includes a pixel circuit and a light-emitting element, wherein the pixel circuit is formed with a transistor of a first structure and a transistor of a second structure, wherein the transistor of the first structure includes a crystalline silicon semiconductor layer and a first gate, and the transistor of the second structure includes an oxide semiconductor film and a second gate, and comprises: a first interlayer insulating film covering the first gate; and a second interlayer insulating film covering the second gate, wherein the pixel circuit is formed with a driving transistor serving as the transistor of the first structure and a capacitor element, wherein the capacitor element includes: a first capacitor electrode electrically connected to the first gate of the driving transistor; a second capacitor electrode opposite to the first capacitor electrode; and a dielectric film arranged between the first capacitor electrode and the second capacitor electrode, wherein the dielectric film is formed in a layer different from the first interlayer insulating film and the second interlayer insulating film.

[0010] Beneficial effects

[0011] According to one embodiment of the present invention, the dielectric film of the capacitor element is formed in a layer different from the first interlayer insulating film and the second interlayer insulating film, thereby achieving an effect of facilitating optimization of capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 (a) is a schematic plan view showing the configuration of the display device of this embodiment.

[0013] Figure 1 (b) is a cross-sectional view showing the structure of the display device.

[0014] Figure 2 It is a cross-sectional view showing the structure of the display device according to this embodiment.

[0015] Figure 3 : is a circuit diagram showing an example of a pixel circuit.

[0016] Figure 4 It is a plan view showing a configuration example of a thin film transistor substrate including a pixel circuit.

[0017] Figure 5 (a) is Figure 4 Aa cross-sectional view, Figure 5 (b) is Figure 4 Bb cross-sectional view, Figure 5 (c) is Figure 4 Cc cross-sectional view.

[0018] Figure 6 This is a flowchart showing a method for manufacturing the display device of this embodiment.

[0019] Figure 7 Yes Figure 6 Flowchart of a method for forming a thin film transistor substrate.

[0020] Figure 8 It is a cross-sectional view showing a method for forming a thin film transistor substrate according to this embodiment.

[0021] Figure 9 It is a cross-sectional view showing a method for forming a thin film transistor substrate according to this embodiment.

[0022] Figure 10 It is a cross-sectional view showing a method for forming a thin film transistor substrate according to this embodiment.

[0023] Figure 11 It is a cross-sectional view showing a method for forming a thin film transistor substrate according to this embodiment.

[0024] Figure 12 It is a cross-sectional view showing a method for forming a thin film transistor substrate according to this embodiment.

[0025] Figure 13 It is a cross-sectional view showing a method for forming a thin film transistor substrate according to this embodiment.

[0026] Figure 14 It is a cross-sectional view showing a method for forming a thin film transistor substrate according to this embodiment.

[0027] Figure 15It is a cross-sectional view showing the structure of a thin film transistor substrate of a comparative example. DETAILED DESCRIPTION

[0028] Figure 1 (a) is a schematic plan view showing the configuration of the display device of this embodiment. Figure 1 (b) is a cross-sectional view showing the structure of the display device. Figure 2 It is a cross-sectional view showing the structure of the display device according to this embodiment.

[0029] like Figure 1 As shown, the display device 10 includes a thin film transistor substrate 7, a top emission (emission toward the upper layer side) type light emitting element layer 5, and a sealing layer 6. A light emitting element ED and a pixel circuit PC for the light emitting element are formed for each sub-pixel SP.

[0030] The thin-film transistor substrate 7 includes a substrate 2, a primer film 3, and a thin-film transistor layer 4 forming the pixel circuit PC. The substrate 2 is a glass substrate or a flexible base material primarily composed of a resin such as polyimide. For example, the substrate 2 may be composed of two layers of polyimide film and an inorganic film sandwiched between them. The primer film (barrier layer) 3 is an inorganic insulating layer that prevents the intrusion of foreign matter such as water and oxygen, and can be composed of, for example, silicon nitride or silicon oxide.

[0031] The pixel circuit PC includes a plurality of transistors TA of a first structure each including a crystalline silicon semiconductor layer SC and first gate electrodes 15a and 15A, a plurality of transistors TB of a second structure each including an oxide semiconductor film SZ and a second gate electrode 19b, and a capacitor Cp connected to a drive transistor (T4), which is one of the transistors TA of the first structure. The transistors TA of the first structure and the transistors TB of the second structure are top-gate transistors, with their control terminals (first gate electrodes 15a and 15A, second gate electrode 19b) formed above the channel.

[0032] like Figure 2As shown, the thin film transistor layer 4 includes: a crystalline silicon semiconductor layer SC formed on the primer film 3; a first gate insulating film 14 covering the crystalline silicon semiconductor layer SC; a first gate electrode 15A, 15a (first metal layer 15) formed on a layer higher than the first gate insulating film 14; a first interlayer insulating film 16 covering the first metal layer 15; a first capacitor electrode 17a and relay electrodes 17B, 17b (intermediate metal layer 17) formed on a layer higher than the first interlayer insulating film 16; an oxide semiconductor film SZ formed on a layer higher than the intermediate metal layer 17; a dielectric film 18a and a second gate insulating film 18b (intermediate insulating layer 18) formed on a layer higher than the oxide semiconductor film SZ; a second capacitor electrode 19a and a second gate electrode 19b (second metal layer 19) formed on a layer higher than the intermediate insulating layer 18; a second interlayer insulating film 20 covering the second metal layer 19; an upper wiring UW ( Figure 1 (b) The third metal layer 21 ), a planarization film PF is formed on an upper layer than the third metal layer 21 .

[0033] The first gate insulating film 14 is arranged between the crystalline silicon semiconductor layer SC and the first gate electrodes 15 a and 15A, and the second gate insulating film 18 b is arranged between the oxide semiconductor film SZ and the second gate electrode 19 b .

[0034] The portion of the crystalline silicon semiconductor layer SC that overlaps with the first gate electrodes 15a and 15A functions as a semiconductor (channel), while the portion that does not overlap becomes a conductor through impurity doping, etc. The portion of the oxide semiconductor film SZ that overlaps with the second gate electrode 19b functions as a semiconductor (channel), while the portion that does not overlap becomes a conductor through a reduction treatment, etc.

[0035] The crystalline silicon semiconductor layer SC is composed of, for example, low-temperature formed polycrystalline silicon (LTPS). The oxide semiconductor film SZ contains, for example, at least one element selected from indium (In), gallium (Ga), tin (Sn), hafnium (Hf), zirconium (Zr), and zinc (Zn), and oxygen. Specifically, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (InGaZnO), an oxide semiconductor containing indium (In), tin (Sn), zinc (Zn), and oxygen (InSnZnO), an oxide semiconductor containing indium (In), zirconium (Zr), zinc (Zn), and oxygen (InZrZnO), an oxide semiconductor containing indium (In), hafnium (Hf), zinc (Zn), and oxygen (InHfZnO), and the like can be used.

[0036] The first metal layer 15 , the intermediate metal layer 17 , the second metal layer 19 , and the third metal layer 21 are composed of, for example, a metal single layer film or a metal multilayer film containing at least one of aluminum, tungsten, molybdenum, tantalum, chromium, titanium, and copper.

[0037] The first gate insulating film 14 can be composed of, for example, a silicon oxide (SiOx) film. The first interlayer insulating film 16 covering the first gates 15A and 15a can be composed of, for example, a stacked film of silicon oxide (SiOx) and silicon nitride (SiNx). The dielectric film 18a and the second gate insulating film 18b (intermediate insulating layer) can be composed of, for example, a silicon oxide (SiOx) film. The second interlayer insulating film 20 covering the second gate 19b can be composed of a single layer of silicon oxide (SiOx) or a stacked film of silicon oxide (SiOx) and silicon nitride (SiNx). The planarization film PF can be composed of, for example, a coatable organic material such as polyimide or acrylic resin.

[0038] Figure 1 The light-emitting element layer 5 of (b) includes a lower electrode 22, an insulating edge cover film 23 covering the edge of the lower electrode 22, an EL (electroluminescent) layer 24 on top of the edge cover film 23, and an upper electrode 25 on top of the EL layer 24. The edge cover film 23 is formed by applying an organic material such as polyimide or acrylic resin and then patterning it using photolithography.

[0039] The light emitting element layer 5 includes a plurality of light emitting elements ED emitting different colors. Each light emitting element includes an island-shaped lower electrode 22, an EL layer 24 (including a light emitting layer EK), and an upper electrode 25. The upper electrode 25 is a solid common electrode shared by the plurality of light emitting elements ED.

[0040] The light-emitting element ED may be, for example, an OLED (Organic Light-Emitting Diode) including an organic layer as a light-emitting layer, or a QLED (Quantum Dot Light-Emitting Diode) including a quantum dot layer as a light-emitting layer.

[0041] The EL layer 24 is formed, for example, by stacking a hole injection layer, a hole transport layer, a light-emitting layer EK, an electron transport layer, and an electron injection layer in this order from the bottom. The light-emitting layer is formed into an island shape at the opening (for each sub-pixel) of the edge cover film 23 by vapor deposition, inkjet printing, or photolithography. The other layers are formed into island shapes or across the entire surface (common layers). Alternatively, a configuration may be employed in which at least one of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer is not formed.

[0042] The lower electrode 22 (anode) is a light-reflecting electrode composed of, for example, a stack of ITO (Indium Tin Oxide) and Ag (silver) or an alloy containing Ag. The upper electrode 25 (cathode) is composed of, for example, a light-transmitting metal thin film such as a magnesium-silver alloy.

[0043] When the light-emitting element ED is an OLED, the drive current between the lower electrode 22 and the upper electrode 25 causes holes and electrons to recombine within the light-emitting layer EK, and the resulting excitons emit light as they migrate to the ground state. When the light-emitting element ED is a QLED, the drive current between the lower electrode 22 and the upper electrode 25 causes holes and electrons to recombine within the light-emitting layer EK, and the resulting excitons emit light as they migrate from the conduction band energy level of the quantum dot to the valence band energy level.

[0044] Figure 1 In (b), the sealing layer 6 covering the light emitting element layer 5 is a layer that prevents foreign matter such as water and oxygen from penetrating into the light emitting element layer 5, and can be composed of, for example, two inorganic sealing films 26 and 28 and an organic film 27 formed therebetween.

[0045] Figure 3 : is a circuit diagram showing an example of a pixel circuit. Figure 3 The pixel circuit PC includes a capacitor element Cp, a reset transistor T1 whose control terminal is connected to the scanning signal line Gn-1 of the previous stage (n-1 stage), a threshold control transistor T2 whose control terminal is connected to the scanning signal line Gn of the current stage (n stage), a write control transistor T3 whose control terminal is connected to the scanning signal line Gn of the current stage (n stage), a driving transistor T4 for controlling the current of the light-emitting element ED, a power supply transistor T5 whose control terminal is connected to the light-emitting control line EM (n stage), a light-emitting control transistor T6 whose control terminal is connected to the light-emitting control line EM (n stage), and an initialization transistor T7 whose control terminal is connected to the scanning signal line Gn of the current stage (n stage).

[0046] The write control transistor T3, the drive transistor T4, the power supply transistor T5 and the light emission control transistor T6 are transistors of the first structure (TA) and have a crystalline silicon semiconductor layer SC (see Figure 2 ). The reset transistor T1, the threshold control transistor T2, and the initialization transistor T7 are transistors of the second structure (TB), and have an oxide semiconductor film SZ (see Figure 2 ).

[0047] The control terminal of the driving transistor T4 is connected to the anode of the light emitting element ED via the capacitor Cp, and is connected to the power supply line PL via the reset transistor T1. The high voltage power supply ELVDD is supplied to the power supply line PL.

[0048] The source region of the drive transistor T4 is connected to the data signal line DL via the write control transistor T3, and is connected to the anode (lower electrode 22) of the light-emitting element ED via the emission control transistor T6. The drain region of the drive transistor T4 is connected to the control terminal of the drive transistor T4 via the threshold control transistor T2, and is connected to the power supply line PL via the power supply transistor T5.

[0049] The node of the light emitting element ED is connected to the initialization signal line IL via the initialization transistor T7. The initialization signal line IL and the cathode (upper electrode 25) of the light emitting element ED are supplied with, for example, the same low voltage side power supply (ELVSS).

[0050] Figure 4 It is a plan view showing a configuration example of a thin film transistor substrate including a pixel circuit. Figure 5 (a) is Figure 4 Aa cross-sectional view, Figure 5 (b) is Figure 4 Bb cross-sectional view, Figure 5 (c) is Figure 4 Cc cross-sectional view.

[0051] The pixel circuit PC is configured with paired scanning signal lines Gn and gn, emission control lines EM, data signal lines DL, initialization signal lines IL, and a high-voltage power supply line PL. The scanning signal lines Gn and gn each have a two-layer structure, with lower wiring contained in the first metal layer 15 and upper wiring contained in the second metal layer 19. The emission control lines EM are contained in the first metal layer 15, while the data signal lines DL, initialization signal lines IL, and power supply lines PL are contained in the third metal layer 21.

[0052] The write control transistor T3, the power supply transistor T5, and the light emission control transistor T6 are transistors of the first structure (TA), and have a first gate 15A (see FIG. 1 ) functioning as a control terminal. Figure 2 The first gate electrode 15A is a portion of the lower wiring of the scanning signal line gn or a portion of the light emission control line EM.

[0053] The reset transistor T1, the threshold control transistor T2, and the initialization transistor T7 are transistors of the second structure (TB), and have a second gate 19b (see Figure 2 The second gate electrode 19b is a portion of the upper wiring of the scanning signal line Gn-1, a portion of the upper wiring of the scanning signal line gn, or a portion of the upper wiring of the scanning signal line Gn.

[0054] like Figure 2 and Figure 5As shown, the driving transistor T4 is a transistor of the first structure (TA), and the capacitor element Cp includes a first capacitor electrode 17a electrically connected to the first gate 15a of the driving transistor T4, a second capacitor electrode 19a opposite to the first capacitor electrode 17a, and a dielectric film 18a arranged between the first capacitor electrode 17a and the second capacitor electrode 19a. The dielectric film 18a is formed in a layer different from the first interlayer insulating film 16 and the second interlayer insulating film 20 (the intermediate insulating layer 18 including the second gate insulating film 18b).

[0055] Therefore, for example, the dielectric film 18a can be formed thinner than the first interlayer insulating film 16 and the second interlayer insulating film 20 using silicon oxide, making it easier to optimize the capacitance of the capacitor Cp. Furthermore, the first interlayer insulating film 16 can be made of a material (e.g., silicon nitride) that is a good source of hydrogen for the crystalline silicon semiconductor layer SC, and the second interlayer insulating film 20 can be made of a material (e.g., silicon oxide) that is suitable for the oxide semiconductor film SZ.

[0056] The dielectric film 18a and the second gate insulating film 18b are in the same layer and are formed of the same material. The first capacitor electrode 17a is included in the intermediate metal layer 17, and the second capacitor electrode 19a is included in the second metal layer 19. Therefore, the above effect can be achieved without increasing the manufacturing process.

[0057] The second gate insulating film 18 b is formed in an island shape so as to match the second gate electrode 19 b , and the dielectric film 18 a is formed in an island shape so as to match the second capacitor electrode 19 a .

[0058] The first gate 15a of the driving transistor T4 and the first capacitor electrode 17a are connected via a contact hole H1x formed in the first interlayer insulating film 16. Since the capacitor Cp overlaps the channel CH of the driving transistor T4 in a plan view, the pixel circuit PC can be made small.

[0059] like Figures 2 to 5 As shown, the oxide semiconductor film SZ includes two conductor portions ZB and Zb on either side of the channel. The intermediate metal layer 17 includes a relay electrode 17B in contact with the conductor portion ZB and a relay electrode 17b in contact with the conductor portion Zb. For example, the relay electrode 17b is connected to the upper-layer wiring UW (third metal layer 21) via a contact hole H3 formed in the second interlayer insulating film 20, and the relay electrode 17B is connected to the power supply line PL (third metal layer 21) via a contact hole formed in the second interlayer insulating film 20.

[0060] The first capacitor electrode 17a is connected to the power supply line PL via the reset transistor T1 as the transistor (TB) of the second structure, and the second capacitor electrode 19a is connected to the initialization signal line IL via the initialization transistor T7 as the transistor (TB) of the second structure.

[0061] The crystalline silicon semiconductor layer SC of the drive transistor T4 is arranged on both sides of the channel and includes a conductive source region SA and a drain region DA. The source region SA is connected to the data signal line DL via the write transistor T3, a transistor of the first structure (TA), and is also connected to the anode of the light-emitting element ED via the emission control transistor T6, a transistor of the first structure (TA). The drain region DA is connected to the power supply line PL via the power supply transistor T5, a transistor of the first structure (TA), and is also connected to the first gate 15a of the drive transistor T4 via the threshold control transistor T2, a transistor of the second structure (TB).

[0062] In addition, if Figure 4 and Figure 5 As shown, the second capacitor electrode 19a is connected to the upper wiring UW via a contact hole H1y formed in the second interlayer insulating film 20 (in Figure 4 , the contact holes H1x and H1y are collectively referred to as H1. The first gate 15a of the driving transistor T4 is connected to the upper layer wiring UW via a contact hole H2 formed in the first interlayer insulating film 16 and the second interlayer insulating film 20.

[0063] The relay electrode 17b, which contacts one end (conductor portion) of the oxide semiconductor film SZ of the threshold control transistor T2, is connected to the upper-layer wiring UW via a contact hole H3 formed in the second interlayer insulating film 20. The relay electrode 17B, which contacts the other end (conductor portion), is connected to the drain region DA of the crystalline silicon semiconductor layer SC of the drive transistor T4 via a contact hole H4 formed in the first interlayer insulating film 16 and the first gate insulating film 14. The source region SA of the crystalline silicon semiconductor layer SC of the transistor T4 is connected to the data signal line DL via the write control transistor T3 and a contact hole H5 formed in the second interlayer insulating film 20, the first interlayer insulating film 16, and the first gate insulating film 14.

[0064] The drain region DA of the crystalline silicon semiconductor layer SC of the power supply transistor T5 is connected to the power line PL via a contact hole H6 formed in the second interlayer insulating film 20 , the first interlayer insulating film 16 , and the first gate insulating film 14 .

[0065] Figure 6 FIG. 1 is a flowchart showing a method for manufacturing a display device according to this embodiment. Figure 1 as well as Figure 6 As shown, in step S101, the thin film transistor substrate 7 is formed. In step S102, the lower electrode 22 is formed. In step S103, the EL layer 24 is formed. In step S104, the upper electrode 25 is formed. In step S105, the sealing layer 6 is formed.

[0066] Figure 7 Yes Figure 6 Flowchart of a method for forming a thin film transistor substrate. Figures 8 to 14 is a cross-sectional view showing a method for forming a thin film transistor substrate, Figures 8 to 14 (a) to (c) in Figure 5 (a) to (c) correspond to.

[0067] like Figure 7 and Figure 8 As shown, in step S1, a substrate 2 is formed. In step S2, a primer film 3 is formed. In step S3, amorphous silicon (amorphous silicon) is formed. In step S4, the amorphous silicon is dehydrogenated by heat treatment. In step S5, laser annealing using ELA (Excimer Laser Annealing) is performed to convert the amorphous silicon into crystalline silicon (polycrystalline silicon), thereby forming a crystalline silicon semiconductor layer SC. In step S6, the crystalline silicon semiconductor layer SC is patterned by photolithography.

[0068] like Figure 7 and Figure 9 As shown, in step S7, a first gate insulating film 14 (e.g., silicon oxide) is formed using CVD. In step S8, a first metal layer 15 (molybdenum or a molybdenum-based alloy such as MoW) is formed using sputtering. In step S9, the first metal layer 15 is patterned using photolithography (forming the lower wiring of the scanning signal line, the light emission control line EM, the first gate 15a, etc.). In step S10, the crystalline silicon semiconductor layer SC is doped with impurities (conductivity treatment).

[0069] like Figure 7 and Figure 10 As shown, in step S11, a first interlayer insulating film 16 (e.g., a stacked film of silicon oxide and silicon nitride) is formed using CVD. In step S12, hydrogenation annealing (a heat treatment for the purpose of supplying hydrogen to the crystalline silicon semiconductor layer SC) is performed. This reduces the effects of defects in the crystalline silicon semiconductor layer SC. In step S13, the first interlayer insulating film 16 is patterned (forming contact holes H4, H1x, etc.) using photolithography. In step S14, an intermediate metal layer 17 (molybdenum or a molybdenum-based alloy such as MoW) is formed.

[0070] like Figure 7 as well as Figure 11As shown, in step S15, the intermediate metal layer 17 is patterned using photolithography (forming the first capacitor electrode 17a, relay electrodes 17B, 17b, etc.). In step S16, the oxide semiconductor film SZ is formed using sputtering. In step S17, the oxide semiconductor film SZ is patterned. Here, a method is used to etch only the oxide semiconductor film SZ without etching the intermediate metal layer 17 (for example, wet etching using oxalic acid or hydrofluoric acid).

[0071] like Figure 7 and Figure 12 As shown, in step S18, the area not covered by the second gate electrode 19b and the second gate insulating film 18b is subjected to hydrogen plasma treatment (forming the conductor portion of the oxide semiconductor film SZ). In step S19, the intermediate insulating layer 18 (for example, silicon oxide) is formed using CVD. In step S20, the second metal layer 19 (for example, a stacked film of titanium / aluminum / titanium) is formed using sputtering.

[0072] like Figure 7 as well as Figure 13 As shown, in step S21, the second metal layer 19 and the intermediate insulating layer 18 are patterned by photolithography (forming the dielectric film 18a, the second gate insulating film 18b, the second capacitor electrode 19a, the second gate 19b, etc.). In step S21, the patterning of the second metal layer 19 and the patterning of the intermediate insulating layer 18 are performed continuously using the same mask.

[0073] like Figure 7 and Figure 14 As shown, in step S22, a second interlayer insulating film 20 (e.g., a single layer of silicon oxide or a stacked film of silicon nitride and silicon oxide) is formed using CVD. In step S23, the first interlayer insulating film 16, the second interlayer insulating film 20, and the first gate insulating film 14 are patterned using photolithography (forming contact holes H1y, H2, H3, H5, and H6). In step S24, a third metal layer 21 (e.g., a stacked film of titanium / aluminum / titanium) is formed using sputtering. In step S25, the third metal layer 21 is patterned using photolithography (forming upper layer wiring UW, data signal lines DL, initialization signal lines IL, and power supply lines PL).

[0074] Figure 15 1 is a cross-sectional view showing the structure of a thin film transistor substrate of a comparative example. Figure 15 As shown, when the inorganic insulating film 116 covering the gate GE is used as a dielectric film of a capacitor connected to the driving transistor, the inorganic insulating film 116 needs to have both the function of a hydrogenation supply source for the polysilicon semiconductor layer and the function of a dielectric film, and it is difficult to achieve both.

[0075] The above embodiments are for illustration and description purposes only and are not intended to be limiting. Based on these illustrations and descriptions, it will be apparent to those skilled in the art that various modifications can be made.

[0076] 〔Summarize〕

[0077] [Form 1]

[0078] A display device includes a pixel circuit and a light-emitting element, wherein the pixel circuit includes a transistor with a first structure and a transistor with a second structure, the transistor with the first structure including a crystalline silicon semiconductor layer and a first gate, and the transistor with the second structure including an oxide semiconductor film and a second gate, and comprises: a first interlayer insulating film covering the first gate; and a second interlayer insulating film covering the second gate.

[0079] In the pixel circuit, a driving transistor and a capacitor are formed as transistors of the first structure.

[0080] The capacitor element includes: a first capacitor electrode electrically connected to the first gate of the driving transistor; a second capacitor electrode facing the first capacitor electrode; and a dielectric film disposed between the first capacitor electrode and the second capacitor electrode.

[0081] The dielectric film is formed in a layer different from the first interlayer insulating film and the second interlayer insulating film.

[0082] [Form 2]

[0083] The display device according to embodiment 1 includes a first gate insulating film and a second gate insulating film, wherein the first gate insulating film is arranged between the crystalline silicon semiconductor layer and the first gate, and the second gate insulating film is arranged between the oxide semiconductor film and the second gate.

[0084] The dielectric film is formed in the same layer as the second gate insulating film and is made of the same material.

[0085] [Form 3]

[0086] In the display device according to aspect 1 or 2, the capacitor element overlaps with a channel of the driving transistor in a plan view.

[0087] [Form 4]

[0088] According to the display device according to aspect 2, the dielectric film and the second gate insulating film are each formed in an island shape.

[0089] [Form 5]

[0090] According to the display device of any one of aspects 1 to 4, the oxide semiconductor film is formed on an upper layer than the crystalline silicon semiconductor layer.

[0091] The transistor of the first structure and the transistor of the second structure are top-gate transistors.

[0092] [Form 6]

[0093] The display device according to aspect 5 includes:

[0094] a first metal layer including the first gate;

[0095] a second metal layer including the second gate;

[0096] a third metal layer located above the second interlayer insulating film; and

[0097] an intermediate metal layer disposed above the first interlayer insulating film and below the oxide semiconductor film,

[0098] The first capacitor electrode is included in the intermediate metal layer.

[0099] [Form 7]

[0100] According to the display device according to aspect 6, the second capacitor electrode is included in the second metal layer.

[0101] [Form 8]

[0102] According to the display device according to aspect 6, the first gate electrode of the driving transistor and the first capacitor electrode are connected via a contact hole formed in the first interlayer insulating film.

[0103] [Form 9]

[0104] According to the display device of aspect 6, the oxide semiconductor film includes a conductive conductor portion.

[0105] A relay electrode is provided, which is in contact with the conductor portion,

[0106] The relay electrode is included in the intermediate metal layer.

[0107] [Form 10]

[0108] In the display device according to any one of aspects 1 to 9, the dielectric film is made of silicon oxide.

[0109] [Form 11]

[0110] The display device according to any one of aspects 1 to 10, wherein the first interlayer insulating film includes silicon nitride.

[0111] The second interlayer insulating film includes silicon oxide.

[0112] [Form 12]

[0113] According to the display device in any one of aspects 1 to 11, the first capacitor electrode is connected to a power supply line via a reset transistor as the transistor of the second structure.

[0114] [Form 13]

[0115] According to the display device in any one of aspects 1 to 12, the second capacitor electrode is connected to the initialization signal line via an initialization transistor as a transistor of the second structure.

[0116] [Form 14]

[0117] According to the display device of any one of aspects 1 to 12, the crystalline silicon semiconductor layer of the driving transistor includes a source region and a drain region arranged on both sides of a channel.

[0118] [Form 15]

[0119] According to the display device according to the fourteenth aspect, one of the source region and the drain region is connected to a data signal line via a write transistor which is a transistor having the first structure.

[0120] [Form 16]

[0121] According to the display device of aspect 14, one of the source region and the drain region is connected to the anode of the light-emitting element via a light-emission control transistor which is a transistor of the first structure.

[0122] [Form 17]

[0123] According to the display device of aspect 14, the other of the source region and the drain region is connected to a power supply line via a power supply transistor which is the transistor having the first structure.

[0124] [Form 18]

[0125] According to the display device of aspect 14, the other of the source region and the drain region is connected to the first gate of the driving transistor via a threshold control transistor as a transistor of the second structure.

[0126] [Form 19]

[0127] According to the display device in any one of aspects 1 to 18, the light-emitting element is an organic light-emitting diode or a quantum dot light-emitting diode.

[0128] [Form 20]

[0129] A method for manufacturing a display device, the display device including a pixel circuit and a light-emitting element, the pixel circuit being formed with a transistor having a first structure, a transistor having a second structure, and a capacitor, the transistor having the first structure including a crystalline silicon semiconductor layer, a first gate insulating film, and a first gate, and the transistor having the second structure including an oxide semiconductor film, a second gate insulating film, and a second gate; the method for manufacturing the display device comprising: forming a crystalline silicon semiconductor layer;

[0130] forming a first gate insulating film on an upper layer than the crystalline silicon semiconductor layer;

[0131] forming a first metal layer above the first gate insulating film;

[0132] forming a first interlayer insulating film on a layer above the first metal layer;

[0133] forming an intermediate metal layer on a layer above the first interlayer insulating film;

[0134] forming an oxide semiconductor film on an upper layer than the intermediate metal layer;

[0135] forming an intermediate insulating layer above the oxide semiconductor film;

[0136] A step of forming a second metal layer on a layer above the intermediate insulating layer; and

[0137] forming a second interlayer insulating film on a layer above the second metal layer;

[0138] By patterning the intermediate metal layer, a first capacitor electrode of the capacitor element is formed.

[0139] The second gate and the second capacitor electrode of the capacitor element are formed by patterning the second metal layer.

[0140] The second gate insulating film and the dielectric film of the capacitor are formed by patterning the intermediate insulating layer.

[0141] [Form 21]

[0142] According to the method for manufacturing a display device according to aspect 20, patterning of the second metal layer and patterning of the intermediate insulating layer are performed continuously using the same mask.

[0143] Description of Reference Numerals

[0144] 2: Substrate

[0145] 4: Thin film transistor layer

[0146] 5: Light-emitting element layer

[0147] 6: Sealing layer

[0148] 7: Thin film transistor substrate

[0149] 10: Display device

[0150] 14: First gate insulating film

[0151] 15: First metal layer

[0152] 15a, 15A: First gate

[0153] 16: First interlayer insulating film

[0154] 17: Middle metal layer

[0155] 17a: First capacitor electrode

[0156] 17b, 17B: Relay electrodes

[0157] 18: Middle insulation layer

[0158] 18a: Dielectric film

[0159] 18b: Second gate insulating film

[0160] 19: Second metal layer

[0161] 19a: Second capacitor electrode

[0162] 19b: Second gate

[0163] 20: Second interlayer insulating film

[0164] 21: The third metal layer

[0165] ED: Light Emitting Element

[0166] SC: Crystalline silicon semiconductor layer

[0167] SZ: oxide semiconductor film

[0168] Cp: Capacitor element

Claims

1. A display device comprising a pixel circuit and a light-emitting element, wherein the pixel circuit comprises a transistor having a first structure and a transistor having a second structure, wherein the transistor having the first structure comprises a crystalline silicon semiconductor layer and a first gate electrode, and the transistor having the second structure comprises an oxide semiconductor film and a second gate electrode, wherein: have: a first interlayer insulating film covering the first gate; a second interlayer insulating film covering the second gate; a first gate insulating film disposed between the crystalline silicon semiconductor layer and the first gate; as well as a second gate insulating film disposed between the oxide semiconductor film and the second gate, In the pixel circuit, a driving transistor and a capacitor are formed as transistors of the first structure. The capacitor element includes: a first capacitor electrode electrically connected to the first gate of the driving transistor; a second capacitor electrode facing the first capacitor electrode; and a dielectric film disposed between the first capacitor electrode and the second capacitor electrode. The dielectric film is formed in a layer different from the first interlayer insulating film and the second interlayer insulating film, The dielectric film and the second gate insulating film are in the same layer and are formed of the same material. The dielectric film and the second gate insulating film are each formed in an island shape.

2. The display device according to claim 1, wherein The capacitor element overlaps with a channel of the driving transistor in a plan view.

3. The display device according to claim 1, wherein The oxide semiconductor film is formed on an upper layer than the crystalline silicon semiconductor layer, The transistor of the first structure and the transistor of the second structure are top-gate transistors.

4. The display device according to claim 3, wherein include: a first metal layer including the first gate; a second metal layer including the second gate; a third metal layer located above the second interlayer insulating film; as well as an intermediate metal layer disposed above the first interlayer insulating film and below the oxide semiconductor film, The first capacitor electrode is included in the intermediate metal layer.

5. The display device according to claim 4, wherein: The second capacitor electrode is included in the second metal layer.

6. The display device according to claim 4, wherein: The first gate of the driving transistor and the first capacitor electrode are connected via a contact hole formed in the first interlayer insulating film.

7. The display device according to claim 4, wherein: The oxide semiconductor film includes a conductive conductor portion. A relay electrode is provided, which is in contact with the conductor portion, The relay electrode is included in the intermediate metal layer.

8. The display device according to claim 1, wherein The dielectric film is made of silicon oxide.

9. The display device according to claim 1, wherein The first interlayer insulating film includes silicon nitride, The second interlayer insulating film includes silicon oxide.

10. The display device according to claim 1, wherein The first capacitor electrode is connected to a power supply line via a reset transistor serving as a transistor of the second structure.

11. The display device according to claim 1, wherein The second capacitor electrode is connected to an initialization signal line via an initialization transistor serving as a transistor of the second structure.

12. The display device according to claim 1, wherein The crystalline silicon semiconductor layer of the driving transistor includes a source region and a drain region arranged on both sides of a channel.

13. The display device according to claim 12, wherein: One of the source region and the drain region is connected to a data signal line via a write transistor serving as a transistor of the first structure.

14. The display device according to claim 12, wherein: One of the source region and the drain region is connected to the anode of the light-emitting element via a light-emission control transistor, which is a transistor of the first structure.

15. The display device according to claim 12, wherein: The other of the source region and the drain region is connected to a power supply line via a power supply transistor serving as the transistor of the first structure.

16. The display device according to claim 12, wherein: The other of the source region and the drain region is connected to the first gate of the driving transistor via a threshold control transistor as a transistor of the second structure.

17. The display device according to any one of claims 1 to 16, wherein: The light emitting element is an organic light emitting diode or a quantum dot light emitting diode.

18. A method for manufacturing a display device, the display device comprising a pixel circuit and a light-emitting element, the pixel circuit being formed with a transistor having a first structure, a transistor having a second structure, and a capacitor, the transistor having the first structure comprising a crystalline silicon semiconductor layer, a first gate insulating film, and a first gate, and the transistor having the second structure comprising an oxide semiconductor film, a second gate insulating film, and a second gate, the method comprising: a step of forming a crystalline silicon semiconductor layer; forming a first gate insulating film on an upper layer than the crystalline silicon semiconductor layer; forming a first metal layer above the first gate insulating film; forming a first interlayer insulating film on a layer above the first metal layer; forming an intermediate metal layer on a layer above the first interlayer insulating film; forming an oxide semiconductor film on an upper layer than the intermediate metal layer; forming an intermediate insulating layer above the oxide semiconductor film; forming a second metal layer on a layer above the intermediate insulating layer; as well as forming a second interlayer insulating film on a layer above the second metal layer; By patterning the intermediate metal layer, a first capacitor electrode of the capacitor element is formed. The second gate and the second capacitor electrode of the capacitor element are formed by patterning the second metal layer. The second gate insulating film and the dielectric film of the capacitor are formed by patterning the intermediate insulating layer.

19. The method for manufacturing a display device according to claim 18, wherein: The second metal layer and the intermediate insulating layer are patterned sequentially using the same mask.

20. A display device comprising a pixel circuit and a light-emitting element, wherein the pixel circuit comprises a transistor having a first structure and a transistor having a second structure, wherein the transistor having the first structure comprises a crystalline silicon semiconductor layer and a first gate electrode, and the transistor having the second structure comprises an oxide semiconductor film and a second gate electrode, wherein: have: a first interlayer insulating film covering the first gate; a second interlayer insulating film covering the second gate; a first gate insulating film disposed between the crystalline silicon semiconductor layer and the first gate; as well as a second gate insulating film disposed between the oxide semiconductor film and the second gate, In the pixel circuit, a driving transistor and a capacitor are formed as transistors of the first structure. The capacitor element includes: a first capacitor electrode electrically connected to the first gate of the driving transistor; a second capacitor electrode facing the first capacitor electrode; and a dielectric film disposed between the first capacitor electrode and the second capacitor electrode. The dielectric film is formed in a layer different from the first interlayer insulating film and the second interlayer insulating film, The dielectric film and the second gate insulating film are in the same layer and are formed of the same material. The oxide semiconductor film is formed on an upper layer than the crystalline silicon semiconductor layer, The transistor of the first structure and the transistor of the second structure are top-gate transistors, The display device further includes: a first metal layer including the first gate; a second metal layer including the second gate; a third metal layer located above the second interlayer insulating film; and an intermediate metal layer disposed above the first interlayer insulating film and below the oxide semiconductor film, The first capacitor electrode is included in the intermediate metal layer.

21. The display device according to claim 20, wherein: The capacitor element overlaps with a channel of the driving transistor in a plan view.

22. The display device according to claim 20, wherein: The second capacitor electrode is included in the second metal layer.

23. The display device according to claim 20, wherein The first gate of the driving transistor and the first capacitor electrode are connected via a contact hole formed in the first interlayer insulating film.

24. The display device according to claim 20, wherein The oxide semiconductor film includes a conductive conductor portion. A relay electrode is provided, which is in contact with the conductor portion, The relay electrode is included in the intermediate metal layer.

25. The display device according to claim 20, wherein The dielectric film is made of silicon oxide.

26. The display device according to claim 20, wherein The first interlayer insulating film includes silicon nitride, The second interlayer insulating film includes silicon oxide.

27. The display device according to claim 20, wherein: The first capacitor electrode is connected to a power supply line via a reset transistor serving as a transistor of the second structure.

28. The display device according to claim 20, wherein The second capacitor electrode is connected to an initialization signal line via an initialization transistor serving as a transistor of the second structure.

29. The display device according to claim 20, wherein The crystalline silicon semiconductor layer of the driving transistor includes a source region and a drain region arranged on both sides of a channel.

30. The display device according to claim 29, wherein One of the source region and the drain region is connected to a data signal line via a write transistor serving as a transistor of the first structure.

31. The display device according to claim 29, wherein One of the source region and the drain region is connected to the anode of the light-emitting element via a light-emission control transistor, which is a transistor of the first structure.

32. The display device according to claim 29, wherein The other of the source region and the drain region is connected to a power supply line via a power supply transistor serving as the transistor of the first structure.

33. The display device according to claim 29, wherein The other of the source region and the drain region is connected to the first gate of the driving transistor via a threshold control transistor as a transistor of the second structure.

34. The display device according to any one of claims 20 to 33, wherein: The light emitting element is an organic light emitting diode or a quantum dot light emitting diode.

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