An integrated circuit

Abstract

The application provides an integrated circuit, comprising: a first metal oxide semiconductor field effect transistor (FET), wherein a first effective gate and a second effective gate are arranged in the first FET, and a first redundant gate is arranged between the first effective gate and the second effective gate; the first effective gate, the second effective gate and the first redundant gate surround a first channel; the first effective gate and the second effective gate are connected to a gate end of the first FET; the first channel on both sides of the first effective gate and the first channel on both sides of the second effective gate are respectively connected to a source end and a drain end of the first FET; and the first redundant gate is connected to a redundant potential or is suspended. Through the structure of the redundant gate arranged between the two effective gates, the current density of the GAA tube can be reduced, and the heat dissipation performance of the GAA tube is further improved.

Description

Technical Field

[0001] This application relates to an integrated circuit, and more particularly to an integrated circuit that improves the heat dissipation performance of a gate all around field effect transistor (GAA) process. Background Technology

[0002] Integrated circuits, also known as chips, are the core driving force behind modern technological progress. As integrated circuits evolved from planar field-effect transistor (FET) technology to gas-air-based (GAA) technology, the transistor, as its basic unit, changed from a planar structure to a three-dimensional structure, resulting in smaller transistor sizes and a smaller integrated circuit area. With the increase in integration density, higher heat density also arises, making heat dissipation, a persistent problem in the chip industry, even more prominent under GAA technology. Summary of the Invention

[0003] This application provides an integrated circuit based on a gate-all-around (GAA) field-effect transistor (FET) structure to improve the heat dissipation performance of the chip device.

[0004] In a first aspect, this application proposes an integrated circuit including a first gate-all-around field-effect transistor (GAA). The first GAA has a first effective gate, a second effective gate, and a first redundant gate. The first redundant gate is disposed between the first effective gate and the second effective gate. The first effective gate, the second effective gate, and the first redundant gate surround a first channel. The first effective gate and the second effective gate are connected to the gate terminals of the first GAA. The two sides of the first channel surrounded by the first effective gate and the second effective gate are respectively connected to the source terminal and the drain terminal of the first GAA. The first redundant gate is connected to a redundant potential or is left floating.

[0005] By adopting the above technical solution, the current density of the GAA can be reduced by setting a redundant gate between two effective gates, thereby improving the heat dissipation performance of the GAA.

[0006] In one possible implementation, in combination with any of the above possible implementations, a second channel is further included, which is arranged side by side with the first channel in a direction perpendicular to the substrate of the first GAA; the first effective gate, the second effective gate and the first redundant gate surround the second channel; the two sides of the second channel surrounded by the first effective gate and the second effective gate are respectively connected to the source end and the drain end of the first GAA.

[0007] By adopting the above technical solution, the performance of GAA is further improved by introducing a second channel arranged in parallel, and the heat dissipation benefits brought by the introduction of redundant gate structure are also further improved.

[0008] In combination with any of the above possible implementations, one possible implementation further includes a second redundant gate, which is located between the first effective gate and the first redundant gate; the second redundant gate is connected to the redundant potential or is left floating.

[0009] By adopting the above technical solution, a second redundant gate is further provided between the two effective gates on the basis of the first redundant gate, which can further reduce the current density of the unit FET and further improve the heat dissipation performance of the GAA.

[0010] In one possible implementation, combining any of the above possible implementations, the first GAA is of type N, and the redundant potential is coupled to the ground terminal of the integrated circuit.

[0011] By adopting the above technical solution, some of the heat generated by the GAA can be discharged to the outside of the integrated circuit through the ground connection line of the redundant gate of the NMOS transistor based on the GAA structure, which can further improve the heat dissipation performance of the GAA.

[0012] In combination with any of the above possible implementations, one possible implementation further includes a first protection ring; the first protection ring is disposed on one or more sides of the first GAA of the N type; the first protection ring is a P type protection ring.

[0013] By adopting the above technical solution, due to the introduction of the guard ring, the substrate of the N-type transistor based on the GAA structure can be connected to the ground terminal of the integrated circuit through the P-type guard ring, and it can be set on one side or multiple sides according to the actual chip area layout. In this way, based on any of the above possible redundant gate structures, the heat dissipation performance of the N-type transistor based on the P-type guard ring structure can be further improved.

[0014] In combination with any of the above possible implementations, one possible implementation further includes a second protection ring, wherein the first protection ring is disposed between the second protection ring and the N-type first GAA; the second protection ring is an N-type protection ring.

[0015] By adopting the above technical solution, the heat dissipation performance of N-tubes based on GAA technology can be further improved due to the introduction of the second protection ring.

[0016] In one possible implementation, combining any of the above possible implementations, the first GAA is P-type, and the redundant potential terminal is coupled to the power supply terminal of the integrated circuit.

[0017] By adopting the above technical solution, some of the heat generated by the redundant gate based on P-type GAA is conducted to the outside of the integrated circuit through the connection line of the integrated circuit power supply terminal, which can further improve the heat dissipation performance.

[0018] In combination with any of the above possible implementations, one possible implementation further includes a first protection ring; the first protection ring is disposed on one or more sides of the first GAA of the P type; the first protection ring is an N type protection ring.

[0019] By adopting the above technical solution, due to the introduction of the guard ring, the substrate of the P-type GAA can be connected to the power supply terminal of the integrated circuit through the N-type guard ring, and can be set on one side or multiple sides according to the actual chip area layout. In this way, based on any of the above possible redundant gate structures, the heat dissipation performance of the P-type GAA based on the N-type guard ring structure can be further improved.

[0020] In one possible implementation, in combination with any of the above possible implementations, a second protection ring is also included, wherein the first protection ring is disposed between the second protection ring and the PMOS transistor; the second protection ring is a P-type protection ring.

[0021] By adopting the above technical solution, the heat dissipation performance of the P-type GAA can be further improved due to the introduction of the second protection ring.

[0022] In combination with any of the above possible implementations, in one possible implementation, the first protective ring is provided with one or more openings.

[0023] By adopting the above technical solution, the protection ring can be introduced more flexibly, and whether it is open or closed, it can improve the heat dissipation performance of the first GAA.

[0024] In one possible implementation, combining any of the above possible implementations, the first GAA is located in the hot spot area of ​​the integrated circuit.

[0025] By adopting the above technical solution, the transistors located in the hot spot area can also adopt a redundant gate GAA transistor structure, which helps to further improve the thermal efficiency of the hot spot area, thereby further improving the heat dissipation performance of the integrated circuit.

[0026] Secondly, this application also provides a power amplifier, wherein a first amplifying tube is provided; the first amplifying tube is used to amplify the signal received by the power amplifier; the first amplifying tube includes a first GAA in any of the above possible implementations.

[0027] Using the above technical solution, the amplifier tube is the tube in the PA that carries high heat dissipation. Therefore, the GAA tube with redundant gate in the above embodiment can be used first to improve the heat dissipation performance of the PA. Since the tube that mainly causes heat dissipation is identified, it will not bring the cost of excessively increasing the area of ​​the PA.

[0028] In combination with any of the above possible implementations, in one possible implementation, PA may also include an isolation tube for better isolation between the input and output terminals, wherein the isolation tube includes the first GAA in any of the above possible implementations.

[0029] By adopting the above technical solution, the heat dissipation performance of the PA can be further improved.

[0030] In one possible implementation, combining any of the above possible methods, the first amplifying transistor is an N-type transistor. The effective gate of the first amplifying transistor is coupled to the signal input terminal (IN) of the PA (amplifier) ​​to receive the signal to be amplified. The redundant gate of the first amplifying transistor is coupled to the ground terminal (GND) of the integrated circuit where the amplifier is located. The source stage of the first amplifying transistor is used to couple to the ground terminal of the PA.

[0031] By adopting the above technical solution, the heat dissipation performance of the PA can be guaranteed, while also ensuring the effective amplification of the signal by the PA.

[0032] Thirdly, this application also provides a power module, wherein a power transistor is provided in the power module, and the power transistor includes the first GAA in any of the above possible implementations.

[0033] Using the above technical solution, the power transistor is the transistor in the power module that carries high heat dissipation. Therefore, the GAA transistor with redundant gate, as described in the above possible implementation, can be used first to improve the heat dissipation performance of the power module. Since the transistor that mainly causes heat dissipation is identified, it will not cause excessive sacrifice of the area of ​​the power module.

[0034] In one possible implementation, combining any of the above possible implementations, the power transistor is coupled between the input and output of the LDO in the voltage module, and the effective gate of the power transistor is coupled to the output of the error amplifier. One input of the error amplifier is the feedback terminal of the output voltage, and the other input is the input terminal of the reference voltage.

[0035] By adopting the above technical solution and introducing a GAA transistor with redundant gates as described in the above possible implementations, the heat dissipation performance of the LDO itself is improved.

[0036] In one possible implementation, combining any of the above possible implementations, the power module includes a DC-DC converter, and the power transistor includes a first switching transistor and a second switching transistor connected in series. The effective gates (G) of the first switching transistor and the second switching transistor are used to receive control signals for turning the corresponding DC-DC converter on and off.

[0037] By adopting the above technical solution and introducing a GAA transistor with redundant gates in the above possible implementations, the heat dissipation performance of the DC-DC converter itself can be improved.

[0038] Fourthly, this application also provides a terminal, including an integrated circuit of the first aspect or any possible implementation of the first aspect, or a power amplifier of the second aspect, or a power module of the third aspect. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the structure of a GAA provided in an embodiment of this application;

[0040] Figure 2 This is a schematic diagram of another GAA structure provided in an embodiment of this application;

[0041] Figure 3 A schematic diagram of a redundant gate GAA provided in an embodiment of this application;

[0042] Figure 4 A schematic diagram of another redundant gate GAA provided in an embodiment of this application;

[0043] Figure 5 A schematic diagram of another redundant gate GAA provided in an embodiment of this application;

[0044] Figure 6 A schematic diagram of a power amplifier circuit employing a redundant gate GAA provided for an embodiment of this application;

[0045] Figure 7 A schematic diagram of various single-ended power amplifier circuits using redundant gates in GAA provided for embodiments of this application;

[0046] Figure 8 A schematic diagram of various differential dual-terminal power amplifier circuits using redundant gates in GAA provided for embodiments of this application;

[0047] Figure 9 This is a schematic diagram of a GAA power module with redundant gates provided in an embodiment of this application.

[0048] It should be understood that the dimensions and shapes of the block diagrams in the above schematic diagrams are for reference only and should not constitute an exclusive interpretation of the embodiments of this application. The relative positions and inclusion relationships between the block diagrams presented in the structural schematic diagrams are only schematic representations of the structural relationships between the block diagrams, and are not intended to limit the physical connection methods of the embodiments of this application. Detailed Implementation

[0049] The technical solutions provided in this application will be further described below with reference to the accompanying drawings and embodiments. It should be understood that the system structures and business scenarios provided in the embodiments of this application are mainly for explaining some possible implementations of the technical solutions of this application and should not be construed as a unique limitation on the technical solutions of this application. Those skilled in the art will recognize that, with the evolution of the system and the emergence of newer business scenarios, the technical solutions provided in this application will still be applicable to the same or similar technical problems.

[0050] It should be understood that the technical solutions provided in the embodiments of this application include methods and related apparatus for transmitting reference detection signals. These technical solutions solve problems in the same or similar ways. In the following description of specific embodiments, some repetitions may not be repeated, but it should be considered that these specific embodiments have mutual references and can be combined with each other.

[0051] Integrated circuits have evolved from Planar FETs to GAA (Gate-Apartment) processes starting with advanced process nodes. The transistors, the fundamental components of these devices, have transformed from planar structures to 3D structures. Planar FETs have planar channels on a silicon substrate, with doped sides forming the source and drain, respectively. A gate is then placed over the planar source and drain, as well as the central channel region. In contrast to Planar FET transistors, GAA transistors have the gate surrounding the channel, creating a three-dimensional structure. The gate forms the source and drain of the GAA on either side of the channel.

[0052] Figure 1 This is a schematic diagram of the structure of a GAA provided in an embodiment of this application. Figure 1 As shown, GAA currently includes two main implementation methods, one of which is as follows: Figure 1 As shown in (a), it is called a nanowire; another type is... Figure 1As shown in (b), this is called a nanoplate. Nanowire-type GAAs use a linear channel structure with small width and height in the horizontal direction, resulting in a small channel size. Due to the small channel size, nanowire-type GAAs are not well-suited for high-power applications, and their commercial applications are currently unclear. Nanoplate-type GAAs, on the other hand, use a plate-type channel. Because the nanoplate can have a larger size in the horizontal direction, they have a larger channel width compared to nanowire-type GAAs, making them suitable for higher-power applications. They have already been successfully commercialized at the 3nm process node. Optionally, both nanowire-type and nanoplate-type GAAs can achieve multiple parallel channel stacks in the direction perpendicular to the substrate, which can further improve the performance of the GAA.

[0053] Compared to Planar FETs, the channel of a GAA is surrounded and controlled by the gate from all four sides. Due to its larger contact area, the gate of a GAA allows for better control of the channel turn-off compared to a Planar FET in advanced processes. In the turn-off state, the leakage current between the source and drain of a GAA is very small. Therefore, compared to Planar FETs, GAAs can achieve better turn-on and turn-off characteristics and better performance in advanced processes, making them a preferred choice for advanced process nodes.

[0054] However, because GAA (Gate-Area Interchange) completely surrounds the channel to further enhance gate control over the channel, making the channel a buried layer without direct contact with the substrate, the heat generated during transistor operation is difficult to dissipate through the silicon substrate, resulting in the channel temperature potentially being much higher than the substrate temperature. More advanced processes, with their smaller transistor sizes and chip areas, inherently have even higher heat density, further exacerbating the heat dissipation issues of GAA.

[0055] Furthermore, such as Figure 1 As shown, in the direction perpendicular to the substrate, as indicated by arrows (11) and (12), GAA can generally stack multiple channels, which will further worsen the heat dissipation problem of GAA.

[0056] Figure 2 This is a schematic diagram of another GAA structure provided in an embodiment of this application. When the size of a single GAA-based transistor is relatively large, a structure in which multiple parallel gates work together in the same channel is generally used. For example... Figure 2As shown, taking the Nanoplate GAA type as an example, multiple gates surround the same nanoplate, a structure that can fully utilize the space of the GAA. However, when using this structure, adjacent gates are affected by the channels in the plate, leading to serious heat dissipation problems. Furthermore, when multiple parallel plate channels are arranged in the vertical direction, this heat dissipation problem is further aggravated. Specifically, as... Figure 2 As shown, taking adjacent gates G1, G2, and G3 as an example, the parallel first channel C1 and second channel C2 between these three adjacent gates generate current in C1 and C2 when the gates are turned on, leading to heat generation and thus heat dissipation problems. Moreover, as the number of gates and channels increases, the heat dissipation environment becomes increasingly severe; the higher the temperature of the GAA gate relative to the silicon substrate, the more serious the heat dissipation problem becomes. High temperatures not only degrade the circuit characteristics, but prolonged operation in high-temperature mode also significantly shortens the device's lifespan and affects chip reliability. Therefore, a method to improve GAA heat dissipation is urgently needed.

[0057] Figure 3 This is a schematic diagram of a redundant gate GAA provided in an embodiment of this application. Figure 3 As shown, in this GAA, taking a nanoplate-type GAA as an example, effective gates and redundant gates are arranged around the perimeter of the planar channel. For example... Figure 3 As shown in the example, the GAA structure includes multiple active gates arranged in an alternating pattern, and source and drain electrodes located between the active gates. Specifically, as... Figure 3 The first effective gate (G1) and the second effective gate (G2) shown are connected to the gate terminal of the GAA for connecting the gate voltage. The nanoplatelet regions on both sides of the first effective gate G1 are the first source (S1) and the first drain (D2), respectively, and the nanoplatelet regions on both sides of the second effective gate G2 are the first source (S1) and the first drain (D2), respectively. S1 and S2 are connected to the source terminal of the GAA for connecting the source voltage. D2 and D1 are connected to the drain terminal of the GAA for connecting the drain voltage.

[0058] A first redundant gate (DG1) is also provided between the first effective gate (G1) and the second effective gate (G2), and DG1 is left floating. Therefore, when the gate of the GAA is connected to the turn-on voltage, the GAA is turned on, and when the corresponding drain voltage and source voltage are applied to the drain and source terminals of the GAA respectively, conduction current will flow through the channels between S1 and D1 and between S2 and D2; when the gate of the GAA is connected to the turn-off voltage, no conduction current will flow through the channels between S1 and D1 and between S2 and D2. Since DG1 is left floating, no conduction current will flow through the channel between S2 and D1. Because the gates G1 and G2 connected to the gate terminals can control the turn-on and turn-off of the GAA, they are called "effective gates"; while the floating gate DG1 cannot control the turn-on and turn-off, so it is called a "redundant gate". Due to the introduction of the redundant gate structure between the effective gates, the current flowing per unit area of ​​the GAA is reduced. Therefore, based on the structure of alternating effective and redundant gates, the heat dissipation performance of GAA can be improved.

[0059] Furthermore, there can be two or more channels in the direction perpendicular to the substrate, such as... Figure 3 As shown, the first channel C1 and the second channel C2 located on both sides of the effective gate can be connected to the source and drain terminals of the GAA, so that a higher transistor density of the GAA can be achieved when the transistor is turned on.

[0060] Furthermore, based on the above GAA structure, in addition to the first redundant gate, a second redundant gate or more redundant gates can be further included between the first effective gate and the second effective gate. This can further reduce the current density per unit GAA and further improve heat dissipation performance. Optionally, a second redundant gate can be inserted between the first effective gate and the first redundant gate, or a second redundant gate can be inserted between the second effective gate and the first redundant gate.

[0061] Generally, to ensure fabrication feasibility, the gates of the same GAA transistor are arranged in parallel at equal intervals. Therefore, introducing the aforementioned redundant gates into the GAA does not change the existing characteristic of equal-interval arrangement. Figure 3 For example, the distance between DG1 and G1 is equal to the distance between DG1 and G2. Of course, the so-called "equidistant parallelism" is a relative concept, referring to equidistant parallelism within the allowable deviation range of existing process accuracy.

[0062] Figure 4This is a schematic diagram of another GAA with a redundant gate provided in an embodiment of this application. Based on the above embodiment, the redundant gate can be coupled to a redundant potential. The redundant potential is used to keep the redundant gate off, preventing the channels on both sides of the redundant gate from conducting.

[0063] Specifically, when the GAA is an N-type transistor, the redundancy potential is connected to the ground terminal (GND) of the integrated circuit containing the GAA; when the GAA is a P-type transistor, the redundancy potential is connected to the power supply terminal (VDD) of the integrated circuit containing the GAA. The integrated circuit is coupled to the power supply potential and ground potential outside the integrated circuit through the ground terminal and the power supply terminal.

[0064] Compared to a floating redundant gate, a redundant gate connected to a redundant potential can avoid the uncertainty caused by a floating gate, which could lead to accidental gate activation. Furthermore, because it is connected to the integrated circuit's GND or VDD, the redundant gate can dissipate some of the heat generated by the GAA to the outside of the integrated circuit via the GND and VDD connection lines, further improving heat dissipation performance.

[0065] Figure 5 This is a schematic diagram of another redundant gate GAA provided in an embodiment of this application. Based on the above embodiment, one or more sides of the GAA may be provided with guard rings. The guard rings may be closed or have multiple notches, and the GAA may have one or more guard rings around its perimeter.

[0066] Specifically, such as Figure 5 As shown, the first protective ring is arranged around the GAA. The first protective ring can be closed or have multiple openings, or it can be arranged only on one side of the GAA.

[0067] Furthermore, based on the first protection ring, the integrated circuit can also be provided with a second protection ring, with the first protection ring disposed between the second protection ring and the GAA. Similar to the first protection ring, the second protection ring can be disposed around the GAA, or it can be disposed only on one side of the first protection ring. The second protection ring can be closed or it can have multiple openings.

[0068] The specific type of guard ring varies depending on the GAA (Gas Alignment Array). Specifically, when the GAA is a P-type pipe, the first guard ring is an N-type guard ring, and the second guard ring is a P-type guard ring. When the GAA is an N-type pipe, optionally, for example, in a deep well, the first guard ring is a P-type guard ring, the second guard ring is an N-type guard ring, and a third guard ring, also a P-type guard ring, can be added in addition to the second guard ring.

[0069] With the introduction of the guard ring, the substrate of the GAA can be connected to the ground or VDD terminal of the integrated circuit through the guard ring. It can be set on one side or multiple sides, open or closed, according to the actual chip area layout. In this way, the heat dissipation performance of the GAA based on the guard ring structure can be further improved on the basis of the redundant gate.

[0070] It should be noted that although the GAA based on the redundant gate in the embodiments of this application can achieve better heat dissipation performance, the redundant gate structure will also incur additional area costs. Therefore, identifying circuit modules with high heat dissipation requirements and specifically identifying the specific transistors in those circuit modules, and then adopting a redundant gate-based structure, is also an issue that needs to be considered in chip design.

[0071] When a chip is operating, certain localized areas generate more heat than other areas; these areas are called hotspots. Some or all transistors located in a hotspot can employ a redundant gate array (GAA) structure as described in the above embodiments, which helps reduce the heat generated by the hotspot. A hotspot can be a specific analog functional module, such as a power amplifier or power supply module, or a digital processing module, such as a CPU, GPU, or memory module.

[0072] Figure 6 This document provides a schematic diagram of a power amplifier circuit employing a redundant-gate GAA (Gate Alternate Architecture) according to an embodiment of this application. The power amplifier (PA) is a crucial functional circuit in wireless communication systems, used to amplify the power of transmitted signals. The PA is a circuit with very high requirements for chip heat dissipation. Due to the complexity of the PA system, the overall layout area is relatively large. Therefore, using the structure described in the above embodiment for all transistors in the PA may result in excessive area. By identifying the core transistors in the PA and employing the redundant-gate GAA structure described in the above embodiment, heat dissipation performance can be improved while also optimizing the area.

[0073] Specifically, such as Figure 6 As shown, the PA includes an amplifying transistor and a load. One end of the amplifying transistor is coupled to the input terminal of the PA to receive and amplify the input signal, and the other end is coupled to the output terminal of the PA. The load coupled to the output terminal is used to provide impedance matching for the output signal. The amplifying transistor is the transistor in the PA that carries the highest heat dissipation. Therefore, a GAA transistor with redundant gates, as shown in the above embodiment, can be used to improve the heat dissipation performance of the PA. Since the transistor that mainly causes heat dissipation has been identified, the PA area will not be sacrificed excessively.

[0074] Furthermore, the PA may also include an isolation transistor to achieve better isolation between the input and output terminals. Since the isolation transistor also carries a large current, it can also adopt a redundant gate structure, thereby further improving the heat dissipation performance of the PA.

[0075] Figure 7 This document provides schematic diagrams of various single-ended power amplifier circuits employing redundant gate GAAs, as illustrated in embodiments of this application. Specifically, Figure 7 (a) is a PA with a common-source amplifier architecture. The amplifier transistor 71a is an N-type transistor. The effective gate of the N-type transistor is coupled to the signal input terminal (IN) of the PA to receive the signal to be amplified. The redundant gate of the N-type transistor is coupled to the ground terminal (GND) of the integrated circuit containing the N-type transistor. The source of the N-type transistor is used to couple to the ground terminal of the PA, as shown in the figure. Optionally, there can be a matching device or other types of FET transistors between the N-type transistor and the ground terminal. The drain of the N-type transistor is used to couple to the output terminal (OUT) to output the amplified signal. The output terminal is also coupled to a load inductor for matching.

[0076] Furthermore, an isolation transistor can also be included between the amplifying transistor and the load in a common-source amplifier. For example... Figure 7 As shown in (b), amplifier transistor 71b and isolation transistor 72b form a cascode amplification structure. Amplifier 71b is an N-type transistor, and 72b is also an N-type transistor. The effective gate of 71b is used to receive the input signal (IN) of PA, and the effective gate of 72b is used to receive the bias voltage (VB). The redundant gates of 71b and 72b can be coupled to ground (GND) respectively.

[0077] Besides the common-source amplifier architecture, power amplifier circuits can also be based on a common-gate architecture. For example... Figure 7 As shown in (c), the amplifier transistor 71c is an N-type transistor. The effective gate of 71c is used to receive the bias voltage (VB), and the redundant gate of 71c is used to ground (GND). The source of 71c is used to couple to the input terminal (IN) to receive the signal to be amplified; the drain of 71c is used to couple to the load terminal (OUT) to output the amplified signal. An inductor is coupled between the source of 71c and ground, and the drain of 71c is also coupled to the power supply terminal through an inductor.

[0078] Furthermore, the common-gate amplifier may further include an isolation transistor, such as... Figure 7 As shown in (d), an N-type transistor 72d is further included between the amplifier transistor 71d and the load terminal. The effective gate of 72d is used to receive a suitable bias voltage (VB2: voltage bias), and the redundant gate of 72d is also coupled to the ground terminal.

[0079] Optional, Figure 7 The redundant gates of all or part of the amplifier and isolation transistors shown can also be left floating.

[0080] Figure 8 This is a schematic diagram of various differential dual-ended power amplifier circuits using redundant gates in GAA configurations provided in embodiments of this application. Figure 7 (a) Based on a single end, such as Figure 8 As shown in (a), the differential signal received at the PA input terminal (IN) is coupled to the effective gates of two amplifier transistors, 81a and 82a, through the input transformer coil T1. Simultaneously, the redundant gates of these two transistors are coupled to ground. The differential signals output from the drains of these two transistors are coupled to the PA output terminal (OUT) through the output transformer coil T2. The sources of these two transistors can be directly grounded or grounded through a matching device.

[0081] Similarly, an isolation transistor can be further included between the differential amplifier transistor and the output signal, such as... Figure 8 As shown in (b). In Figure 8 Based on (a), Figure 8 In (b), the differential amplifier tubes 81b and 82b are coupled to the output transformer coil T2 through two isolation tubes 83b and 84b, respectively.

[0082] Besides the differential common-source amplifier architecture, differential two-ended power amplifiers can also adopt a differential common-gate amplifier architecture, such as... Figure 8 As shown in (c) and 8(d). In as Figure 7 Based on the single-ended architecture shown in (a) and 7(b), the differential signal received at the differential input terminal (IN) and coupled to the input transformer T1 is coupled to the source stages of the two amplifiers 81c and 82c, respectively. The drains of the two amplifier transistors are used to output the differential signal, which is coupled to the output terminal through the output transformer T2. The effective gates of amplifier transistors 81c and 82c are used to couple the bias voltage (VB1) to establish the DC operating point, and the redundant gates of the two amplifier transistors are coupled to the ground terminal.

[0083] Furthermore, based on 8(c), such as Figure 8 As shown in (d), the two amplifier transistors 81d and 82d can also be further coupled to the output with isolation transistors 83d and 84d. The connection method of the effective gate and redundant gate of the isolation transistors is the same as... Figure 7 The isolation tube shown in (d) is the same.

[0084] Optional, Figure 8 The redundant gates of all or part of the amplifier and isolation transistors shown can be left floating or grounded.

[0085] Figure 9This is a schematic diagram of a GAA power module with redundant gates provided in an embodiment of this application. Based on the above embodiments, the power module is also an important circuit module in chip design where heat dissipation needs to be considered. Similar to power amplifiers, for power modules, given chip area constraints, improving heat dissipation should prioritize power transistors. Introducing the redundant gate GAA structure described in the above embodiments into the power transistors can improve the heat dissipation performance of the power module while simultaneously optimizing area.

[0086] like Figure 9 (a) The low dropout linear regulator (LDO) shown is a typical power supply module. As shown, because the power transistor in the LDO carries a large output current and generates a lot of heat, the power transistor 91a can be a redundant gate GAA transistor to improve the thermal efficiency of the LDO. The power transistor 91a is coupled between the input and output of the LDO. The effective gate of 91a is coupled to the output of the error amplifier. One input of the error amplifier is the feedback terminal of the output voltage, and the other input is the input terminal of the reference voltage. The redundant gate of the power transistor 91a can be left floating or connected to a redundant potential.

[0087] Figure 9 (b) shows a DC-DC converter (DCDC). The power transistors of the DCDC are the first and second switching transistors shown in the figure. Since these two transistors carry a large output current in the DCDC, they generate a significant amount of heat. These two transistors can employ a GAA structure based on redundant gates to improve the thermal efficiency of the DCDC. The effective gates (G) of the first and second switching transistors are used to receive the control signals for turning the corresponding switches on and off, while the redundant gates can be left floating or connected to a redundant potential.

[0088] Specifically, DC-DC converters can be closed-loop architectures, such as buck, boost, or buck-boost, or open-loop architectures, such as charge pumps.

[0089] The chips in the above embodiments of this application can be used in various terminals. Terminals can be mobile phones, tablet computers, laptop computers, wearable devices (such as smartwatches, smart bracelets, smart helmets, and smart glasses), and other devices with wireless access capabilities, such as smart cars, mobile wireless routers, various Internet of Things (IoT) devices, including various smart home devices (such as smart meters and smart appliances) and smart city devices (such as security or monitoring equipment, and smart road traffic facilities), etc.

[0090] The terms "first," "second," and "third," etc., used in the embodiments and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to indicate non-exclusive inclusion, for example, including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units literally listed, but may include other steps or units not literally listed or inherent to these processes, methods, products, or apparatuses.

[0091] It should be understood that in this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0092] It should be understood that, in this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The term "coupling" mentioned in this application is used to express the interconnection or interaction between different components, which may include direct connection or indirect connection through other components.

[0093] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An integrated circuit, characterized in that, include: A first gate-all-around field-effect transistor (GAA) includes a plurality of active gates arranged in an alternating manner and sources and drains located between the active gates; the plurality of active gates are connected to the gate terminals of the first gate-all-around field-effect transistor (GAA), the plurality of sources are connected to the source terminals of the first gate-all-around field-effect transistor (GAA), and the plurality of drains are connected to the drain terminals of the first gate-all-around field-effect transistor (GAA). The first gate-all-around field-effect transistor (GAA) is provided with a first effective gate, a second effective gate, and a first redundant gate, wherein the first redundant gate is disposed between the first effective gate and the second effective gate; The first effective gate, the second effective gate, and the first redundant gate surround the first channel. The first effective gate and the second effective gate are connected to the gate terminals of the first gate all-around field-effect transistor (GAA); The first channel, which is surrounded by the first effective gate and the second effective gate, is respectively connected to the source terminal and the drain terminal of the first gate-around-the-all-area field-effect transistor (GAA). The first redundant gate is connected to a redundant potential or left floating.

2. The integrated circuit according to claim 1, characterized in that, Also includes: The second channel is arranged side by side with the first channel in a substrate direction perpendicular to the first gate all-around field-effect transistor (GAA). The first effective gate, the second effective gate, and the first redundant gate surround the second channel. The two sides of the second channel surrounding the first effective gate and the second effective gate are respectively connected to the source and drain terminals of the first gate-around-the-all-area field-effect transistor (GAA).

3. The integrated circuit according to claim 1, characterized in that, Also includes: A second redundant gate is located between the first effective gate and the first redundant gate; The second redundant gate is connected to the redundant potential or left floating.

4. The integrated circuit according to claim 1, characterized in that: The first gate-all-around field-effect transistor (GAA) is of type N, and the redundant potential is coupled to the ground terminal of the integrated circuit.

5. The integrated circuit according to claim 4, characterized in that: It also includes the first protective ring; The first protection ring is disposed on one or more sides of the first gate all-around field-effect transistor GAA of the N type; The first protective ring is a P-type protective ring.

6. The integrated circuit according to claim 1, characterized in that: The first gate-all-around field-effect transistor (GAA) is P-type, and the redundant potential terminal is coupled to the power supply terminal of the integrated circuit.

7. The integrated circuit according to claim 6, characterized in that: It also includes the first protective ring; The first protection ring is disposed on one or more sides of the first gate all-around field-effect transistor GAA of the P type; The first protection ring is an N-type protection ring.

8. The integrated circuit according to claim 5 or 7, characterized in that: The first protective ring has one or more openings.

9. The integrated circuit according to any one of claims 1 to 7, characterized in that: The first gate-all-around field-effect transistor (GAA) is disposed in the hot spot region of the integrated circuit.

10. The integrated circuit according to any one of claims 1 to 7, characterized in that: The first channel is a nanoplate or nanowire.

11. A power amplifier, characterized in that: Including the first amplifying tube; The first amplifying tube is used to amplify the signal received by the power amplifier; The first amplifying transistor includes a first gate-all-around field-effect transistor (GAA) as described in any one of claims 1-10.

12. A power supply module, characterized in that: Includes a power transistor, said power transistor comprising a first gate-all-around field-effect transistor (GAA) as described in any one of claims 1-10.

13. A terminal, characterized in that: This includes the integrated circuit as described in any one of claims 1-10, the power amplifier as described in claim 11, or the power module as described in claim 12.

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