A semiconductor structure, an electronic device and a method for manufacturing a semiconductor structure

Abstract

This application provides a semiconductor structure, an electronic device, and a method for fabricating a semiconductor structure, relating to the field of heat dissipation technology for electronic products. The semiconductor structure includes a semiconductor device, a bonding layer, a substrate, conductive vias, and a metal layer. The semiconductor device is disposed on the upper surface of the substrate via the bonding layer, and the metal layer is disposed on the lower surface of the substrate. The substrate includes a substrate base, a groove formed in the substrate, and a diamond contained in the groove. The conductive vias penetrate the substrate, the bonding layer, and at least a portion of the semiconductor device, and are electrically connected to the metal layer. The grooves bypass the conductive vias.

Description

Technical Field

[0001] This application relates to the field of heat dissipation technology for electronic products, and in particular to a semiconductor structure, an electronic device, and a method for preparing the semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor technology, the number of transistors on chips is constantly increasing. High-density transistor integration and increased circuit speed mean that the power per unit of chip is also constantly increasing. This increase in power per unit inevitably leads to the generation of more heat in the chip, which can easily cause the temperature of electronic devices to become too high. When the temperature of electronic devices is too high, their performance and lifespan will decrease rapidly.

[0003] One existing heat dissipation method is through diamond materials, such as in the semiconductor structure of high electron mobility transistors (HEMTs), where diamond is often used for heat dissipation.

[0004] Figure 1 The diagram shows a schematic of a prior art HEMT semiconductor structure, which includes an HEMT 1, a diamond substrate 2, a metal ground layer 3, and a heat sink 4. The HEMT 1 is placed on the diamond substrate 2, and the heat it generates is transferred through the diamond substrate 2 to the metal ground layer 3, and then dissipated through the heat sink 4.

[0005] The HEMT1 comprises three layers: an aluminum gallium nitride (AlGaN) layer 101, a gallium nitride (GaN) layer 102, and a substrate layer 103. An active electrode T1, a gate electrode T2, and a drain electrode T3 are formed on the AlGaN layer 101. The substrate layer 103 can be a Si substrate or a SiC substrate, etc. Since the source of the HEMT1 needs to be grounded, a via needs to be created in the entire semiconductor structure, running from the upper surface of the HEMT1 (also known as the active surface), through the diamond substrate 2, and down to the metal ground layer 3.

[0006] In preparation Figure 1 When referring to the semiconductor structure shown, refer to Figure 2 In step 2a, HEMT1 is connected to the diamond substrate 2 via bonding layer 5; see reference. Figure 2 In step 2b, a via 6 extending to the source electrode of the HEMT1 is fabricated on the HEMT1, the bonding layer 5, and the diamond substrate 2; refer to Figure 2 In 2c, conductive material is deposited within the through-hole 6 to form a conductive path.

[0007] In other words, during the fabrication of this semiconductor structure, holes need to be drilled in the diamond substrate O2. However, drilling holes in the diamond substrate is very inefficient and does not meet the requirements for large-scale mass production. Summary of the Invention

[0008] The embodiments of this application provide a semiconductor structure, an electronic device, and a method for fabricating a semiconductor structure, with the main objective of providing a semiconductor structure that can improve aperture efficiency.

[0009] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0010] In a first aspect, this application provides a semiconductor structure including a semiconductor device, a bonding layer, a substrate, a conductive via, and a metal layer, wherein the semiconductor device is disposed on the upper surface of the substrate via the bonding layer, the metal layer is disposed on the lower surface of the substrate, the substrate includes a substrate, a groove formed in the substrate, and a diamond contained in the groove, the conductive via penetrating at least a portion of the substrate, the bonding layer, and the semiconductor device, and is electrically connected to the metal layer, and the groove bypasses the conductive via.

[0011] The semiconductor structure provided in this application includes a substrate with grooves, in which diamond is housed, and the grooves bypass conductive vias. It can be understood that by creating grooves on the substrate, protrusions are reserved for conductive vias, and holes are then created on these protrusions. Compared to creating holes on the diamond itself, this significantly reduces the difficulty of creating holes, improves efficiency, and enables large-scale mass production.

[0012] In the first possible implementation, the substrate is a Si substrate or a SiC substrate. Firstly, creating holes in the Si substrate or SiC substrate is relatively easy; secondly, the Si substrate or SiC substrate also has high thermal conductivity, resulting in good heat dissipation.

[0013] In one possible implementation of the first aspect, the diamond on the bottom surface of the groove is exposed to the outside of the substrate. Since diamond has a thermal conductivity of up to 2000 W / mK at room temperature, while Si or SiC has a thermal conductivity of around 150 W / mK, it is clear that the thermal conductivity of diamond is much greater than that of Si or SiC. Therefore, by reducing the thickness of the substrate to expose the diamond, the heat dissipation efficiency will be significantly improved.

[0014] In one possible implementation of the first aspect, the diamond includes a first diamond layer and a second diamond layer; the first diamond layer is formed on the bottom surface and sidewall surface of the groove, and the second diamond layer is formed on the first diamond layer; wherein the average volume of the grains in the first diamond layer is smaller than the average volume of the grains in the second diamond layer.

[0015] In one possible implementation of the first aspect, the first diamond layer on the bottom surface of the groove is exposed to the outside of the substrate. Exposing the first diamond layer reduces thermal resistance and improves heat dissipation efficiency compared to hiding it within the substrate.

[0016] In one possible implementation of the first aspect, the second diamond layer on the bottom surface of the groove is exposed to the outside of the substrate. Because the average volume of the diamond grains in the second diamond layer is greater than that in the first diamond layer, the thermal conductivity of the second diamond layer is greater than that of the first diamond layer. Exposing the second diamond layer, compared to hiding it within the first diamond layer, further reduces thermal resistance and improves heat dissipation efficiency.

[0017] In one possible implementation of the first aspect, there are multiple conductive vias, which are spaced apart, and the substrate has a boss, in which the multiple conductive vias are disposed.

[0018] In other words, when there are multiple conductive vias, a boss is formed on the substrate to house the multiple conductive vias within the boss. That is, the outer periphery of the conductive vias is the substrate. Compared with setting diamond (including the first diamond layer and the second diamond layer) around the conductive vias, this effectively reduces the process difficulty of preparing high-density conductive vias and can improve the strength of the entire semiconductor structure.

[0019] In one possible implementation of the first aspect, the semiconductor device is an active device including a grounding structure, the metal layer is a grounding layer, and the conductive via extends through the semiconductor device and is electrically connected to the grounding structure.

[0020] In one possible implementation of the first aspect, the semiconductor device is a HEMT.

[0021] In one possible implementation of the first aspect, the semiconductor device is a chip, the metal layer is a second redistribution layer, a conductive via penetrates the passive layer of the chip and is electrically connected to a first redistribution layer located on the active layer of the chip, an insulating layer is provided between the second redistribution layer and the substrate, and an insulating layer is provided between the conductive via and the chip, the bonding layer and the substrate. By providing the insulating layer, the stability of signal transmission between the first redistribution layer and the second redistribution layer is ensured.

[0022] In one possible implementation of the first aspect, the semiconductor device has an intermediate metal layer on the surface opposite to the bonding layer, and a conductive via is electrically connected to the intermediate metal layer.

[0023] In a possible implementation of the first aspect, the portion of the conductive via located within the semiconductor device is a first conductive via, and the portion of the conductive via located within the substrate and the bonding layer is a second conductive via. The cross-sectional areas of both the first and second conductive vias are smaller than the surface area of ​​the intermediate metal layer, and / or the axial directions of the first and second conductive vias are not on the same straight line.

[0024] In one possible implementation of the first aspect, vias are formed on the substrate, bonding layer, and semiconductor device, and a conductive layer is formed on the inner wall of the via. The via with the conductive layer and a hollow structure forms a conductive via.

[0025] In other words, a conductive layer is formed on the inner wall of the via to achieve a conductive via. That is, the conductive via is a hollow structure. When the semiconductor device is working, it will dissipate a lot of heat, which will be conducted to the conductive via and cause it to expand. By designing the conductive via as a hollow structure, the expanding conductive via will not generate large thermal stress on the semiconductor device, thus avoiding the impact on the performance of the semiconductor device.

[0026] In one possible implementation of the first aspect, vias are formed on the substrate, bonding layer, and semiconductor, and the vias are filled with conductive material, forming a conductive via with a solid structure.

[0027] In one possible implementation of the first aspect, the bonding layer includes a polycrystalline silicon carbide layer, an amorphous silicon carbide layer, or a combination of polycrystalline and amorphous silicon carbide layers stacked together. Polycrystalline and amorphous silicon carbide have high thermal conductivity and are easy to process and manufacture.

[0028] Secondly, embodiments of this application also provide a method for fabricating a semiconductor structure, the method comprising:

[0029] Grooves are formed on the surface of the substrate to create bosses;

[0030] Diamond is placed in the groove to obtain a substrate containing a substrate and diamond;

[0031] Semiconductor devices are disposed on the upper surface of a substrate via a bonding layer;

[0032] Through-holes are formed on at least a portion of the boss, bonding layer, and semiconductor device, and the through-holes are metallized to form conductive through-holes.

[0033] A metal layer is disposed on the lower surface of the substrate so that the conductive vias are electrically connected to the metal layer.

[0034] The semiconductor structure fabrication method provided in this application involves creating holes on the bumps of a substrate. Compared to the prior art method of creating holes in diamond, this reduces the difficulty of creating holes and improves the efficiency of hole creation. Furthermore, when cutting the semiconductor structure, cutting can be performed on the substrate, which also improves cutting efficiency compared to cutting in diamond.

[0035] In a possible implementation of the second aspect, after placing the diamond within the groove, the method further includes removing the substrate on the bottom surface of the groove to expose the diamond on the bottom surface of the groove to the outside of the substrate. Removing the substrate on the bottom surface of the groove further improves heat dissipation efficiency.

[0036] In a possible implementation of the second aspect, placing the diamond within the groove includes:

[0037] Nanocrystalline diamond seed layers are fabricated on the bottom and sidewall surfaces of the groove;

[0038] A nanocrystalline diamond nucleation layer is fabricated on a nanocrystalline diamond seed layer, and nanocrystals grow to form a micron-crystalline diamond layer.

[0039] The first diamond layer is formed by diamond layers with an average grain volume of nanometers, and the second diamond layer is formed by diamond layers with an average grain volume of micrometers.

[0040] The nanocrystalline diamond seed layer first prepared in the groove will allow the nanocrystalline diamond nucleation layer to be deposited evenly in the groove, and will be beneficial to the growth of diamond grains.

[0041] In the second possible implementation, when making the nanocrystalline diamond seed layer, the nanocrystalline diamond seed layer can be made by spraying gel-like diamond particles, or by performing ultrasonic treatment in a solution of nanocrystalline diamond particles.

[0042] In the second possible implementation, chemical vapor deposition is used to fabricate the nanocrystalline diamond nucleation layer.

[0043] In a possible implementation of the second aspect, after placing the diamond in the groove, the method further includes: removing the substrate on the bottom surface of the groove so that the first diamond layer on the bottom surface of the groove is exposed to the outside of the substrate. In the semiconductor structure prepared in this way, the first diamond layer is exposed, which further improves the heat dissipation effect of the semiconductor structure compared to covering the first diamond layer inside the substrate.

[0044] In a possible implementation of the second aspect, after setting the diamond in the groove, the method further includes: removing the substrate on the bottom surface of the groove so that the second diamond layer on the bottom surface of the groove is exposed to the outside of the substrate.

[0045] In the semiconductor structure prepared in this way, the second diamond layer is exposed, which further improves the heat dissipation effect compared to encapsulating the first diamond layer with the second diamond layer.

[0046] In a possible implementation of the second aspect, after creating the through hole, the method further includes: forming a conductive layer on the inner wall surface of the through hole, so that the hollow through hole with the conductive layer forms a conductive through hole; or, filling the through hole with a conductive material, so that the solid through hole filled with the conductive material forms a conductive through hole.

[0047] In a possible implementation of the second aspect, after forming a via on at least a portion of the boss, bonding layer, and semiconductor device, the method further includes: forming an insulating layer on the inner wall surface of the via, forming an insulating layer on the lower surface of the substrate, and then metallizing the via with the insulating layer.

[0048] Thirdly, this application also provides an electronic device, including a printed circuit board and a semiconductor structure made in any implementation of the first aspect or any implementation of the second aspect, wherein the printed circuit board is electrically connected to the semiconductor structure.

[0049] The electronic device provided in this application includes the semiconductor structure provided in the first aspect embodiment or the semiconductor structure obtained in the second aspect. Therefore, the electronic device provided in this application and the semiconductor structure of the above technical solution can solve the same technical problem and achieve the same expected effect. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the structure of a HEMT in the prior art;

[0051] Figure 2 This is a schematic diagram of the structure corresponding to each step in the preparation method of HEMT in the prior art.

[0052] Figure 3 This is a schematic diagram of the semiconductor structure in an embodiment of this application;

[0053] Figure 4a This is a schematic diagram of a semiconductor structure including a HEMT according to an embodiment of this application;

[0054] Figure 4b This is a schematic diagram of a semiconductor structure including a chip, according to an embodiment of this application.

[0055] Figure 5 This is a schematic diagram of the semiconductor structure in an embodiment of this application;

[0056] Figure 6 This is a schematic diagram of the semiconductor structure in an embodiment of this application;

[0057] Figure 7 This is a schematic diagram of the substrate structure of the semiconductor structure in an embodiment of this application;

[0058] Figure 8 This is a schematic diagram of the semiconductor structure in an embodiment of this application;

[0059] Figure 9 This is a schematic diagram of the semiconductor structure in an embodiment of this application;

[0060] Figure 10 This is a schematic diagram of the semiconductor structure in an embodiment of this application;

[0061] Figure 11 This is a schematic diagram of a semiconductor structure with multiple conductive vias according to an embodiment of this application;

[0062] Figure 12 This is a schematic diagram of a semiconductor structure with multiple conductive vias according to an embodiment of this application;

[0063] Figure 13 for Figure 12 A schematic diagram of the substrate structure;

[0064] Figure 14 This is a schematic diagram of the semiconductor structure in an embodiment of this application;

[0065] Figure 15 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure fabrication method of the embodiments of this application after completion;

[0066] Figure 16 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure fabrication method of the embodiments of this application after completion;

[0067] Figure 17 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure fabrication method of the embodiments of this application after completion;

[0068] Figure 18 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure fabrication method of the embodiments of this application after completion;

[0069] Figure 19 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure fabrication method of the embodiments of this application after completion;

[0070] Figure 20 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure fabrication method of the embodiments of this application after completion;

[0071] Figure 21 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure fabrication method of the embodiments of this application.

[0072] Figure label:

[0073] 1-HEMT; 101-AlGaN layer; 102-GaN layer; 103-Substrate layer; 2-Diamond substrate; 3-Metal ground layer; 4-Heat sink; 5-Bonding layer; 6-Through hole; 7-Semiconductor device; 8-Substrate; 81-Substrate; 811-Groove; 812-Boss; 82-Diamond; 82A-First diamond layer; 82B-Second diamond layer; 821-Nanocrystalline diamond seed layer; 822-Nanocrystalline diamond nucleation layer; 9-Metal layer; 10-Conductive via; 101-First conductive via; 102-Second conductive via; 111-Active layer; 112-Passive layer; 113-First redistribution layer; 12-Insulating layer; 13-Intermediate metal layer; 14-Mask layer; A1-Bottom surface of groove; A2-Side wall surface of groove. Detailed Implementation

[0074] Electronic devices contain printed circuit boards (PCBs) and semiconductor structures electrically connected to them. With the increasing density of transistor integration and circuit speeds, the power per unit area of ​​semiconductor structures is constantly increasing, leading to a continuous increase in the heat dissipated.

[0075] In alternative implementations, the electronic device may be a mobile phone, tablet computer, or the like.

[0076] Figure 3 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application. The semiconductor structure includes a semiconductor device 7, a bonding layer 5, a substrate 8, and a metal layer 9.

[0077] The semiconductor device 7 is formed on the upper surface of the substrate 8 via the bonding layer 5. The metal layer 9 is formed on the lower surface of the substrate 8.

[0078] In this embodiment of the application, the semiconductor device 7 may be as follows: Figure 1 The HEMT1 shown includes three main parts: an AlGaN layer 101, a GaN layer 102, and a substrate layer 103. In alternative embodiments, the semiconductor device 7 can also be other types of semiconductor devices, or it can be a chip equipped with an HEMT or other types of semiconductor devices.

[0079] The substrate 8 includes a substrate 81 and a diamond 82 embedded in the substrate 81. In an alternative embodiment, a groove 811 with an opening facing the bonding layer 5 is formed in the substrate 81, the diamond 82 is disposed in the groove 811, and the surface of the diamond 82 is in contact with the bonding layer 5.

[0080] In this embodiment, the semiconductor device 7 may have a grounding structure. For example, taking a HEMT as an example, the source of the HEMT needs to be grounded, and the metal layer 9 serves as a grounding layer, meaning the source of the HEMT needs to be connected to the metal layer 9. In an alternative embodiment, the semiconductor device is a chip that needs to be stacked and electrically connected to another chip. The metal layer 9 serves as a redistribution layer, meaning the chip needs to be connected to the metal layer 9, and the metal layer 9 is then electrically connected to another chip. Therefore, the semiconductor structure in this embodiment also includes a conductive via 10 that penetrates the substrate 8, the bonding layer 5, and at least a portion of the semiconductor device 7.

[0081] exist Figure 4a In one embodiment, a source T1 of the HEMT that needs to be grounded is formed on the surface of the semiconductor device, therefore the conductive via 10 penetrates the semiconductor device 7 directly to the source T1 of the HEMT. Figure 4b In one embodiment, the semiconductor device is a chip, including an active layer 111 and a passive layer 112. The active layer 111 integrates a semiconductor device, and a conductive via 10 passes through the passive layer 112 and is electrically connected to a semiconductor device in the active layer 111.

[0082] like Figure 3 As shown, the groove 811 in the substrate 8 bypasses the conductive via 10, or in other words, a boss is reserved for the conductive via 10 when the groove 811 is formed. No groove or diamond is formed at the location where the conductive via 4 needs to pass through, thus avoiding the problem of drilling holes in diamond, reducing the manufacturing difficulty of the entire semiconductor structure, and improving the hole-opening efficiency.

[0083] The material of substrate 81 can be varied. For example, a Si substrate can be used. As another example, a SiC substrate can be used.

[0084] When using a Si substrate, its high thermal conductivity ensures that it does not affect heat dissipation from semiconductor devices. Furthermore, Si substrates are inexpensive, reducing the overall manufacturing cost of the semiconductor structure. Similarly, when using a SiC substrate, its high thermal conductivity also ensures that it does not affect heat dissipation from semiconductor devices. Additionally, SiC substrates are heat-resistant, and it is easy to create openings in them.

[0085] Figure 4aThe diagram shows a detailed schematic of a semiconductor structure including a HEMT (Heated Metal-Oxide-Mechanical System). This semiconductor structure includes a stacked AlGaN layer 101, a GaN layer 102, and a substrate layer 103. A source electrode T1, a gate electrode T2, and a drain electrode T3 are formed on the AlGaN layer 101. A substrate 8, including a substrate 81 and a diamond electrode 82, is connected to the substrate layer 103 via a bonding layer 5. This semiconductor structure includes two substrate structures: a substrate layer 103 and a substrate 81. The substrate layer 103 is used to form the GaN layer 102 and the AlGaN layer 101, and the substrate 81 is used to support the diamond electrode 82.

[0086] exist Figure 4a In this structure, the substrate layer 103 is not required, and the GaN layer 102 can be directly connected to the substrate 8 through the bonding layer 5.

[0087] Figure 4b The diagram shows a detailed schematic of a semiconductor structure including a chip. This semiconductor structure includes an active layer 111 and a passive layer 112 stacked together. A substrate 8, including a substrate 81 and a diamond 82, is connected to the passive layer 112 via a bonding layer 5. The semiconductor structure includes two substrates: a passive layer 112 and a substrate 81. The passive layer 112 is used to form the active layer 111, and the substrate 81 is used to support the diamond 82.

[0088] Figure 4b In the structure shown, the passive layer 112 is bonded to the substrate via the bonding layer 5. In an alternative embodiment, the passive layer 112 can be located above the active layer 111, with the active layer 111 bonded to the substrate via the bonding layer 5. In this case, the conductive via can directly penetrate to the active layer.

[0089] exist Figure 4b In the structure shown, since the chip is made of Si or SiC material, if the chip directly contacts the conductive via, it will cause semiconductor devices on the chip that do not need to be electrically connected to the conductive via to become electrically connected to the via. To avoid this phenomenon, such as... Figure 5 As shown, an insulating layer 12 is formed on the sidewall surface of the conductive via that contacts the chip.

[0090] In the embodiments of this application, the bonding layer material is generally one of Si, SiC, SiO2, and SiN. SiC can be polycrystalline silicon carbide or amorphous silicon carbide. Firstly, polycrystalline silicon carbide and amorphous silicon carbide have higher thermal conductivity; secondly, polycrystalline silicon carbide and amorphous silicon carbide are also easier to process and manufacture. In optional embodiments, a polycrystalline silicon carbide layer forms the bonding layer, or an amorphous silicon carbide layer forms the bonding layer, or a stacked polycrystalline silicon carbide layer and amorphous silicon carbide layer form the bonding layer.

[0091] To avoid electrical connection between the bonding layer and the conductive via, such as Figure 5 As shown, an insulating layer 12 is also formed between the conductive via 10 and the bonding layer 5.

[0092] exist Figure 5 In the structure shown, when the conductive via comes into contact with the substrate 81, an insulating layer 12 is also formed between the conductive via 10 and the substrate 81 to prevent the Si substrate or SiC substrate from being electrically connected to the conductive via.

[0093] exist Figure 5 In the structure shown, when the metal layer located on the lower surface of the substrate comes into contact with the substrate, an insulating layer 12 is also formed between the metal layer 9 and the substrate 81 in order to prevent the Si substrate or SiC substrate from being electrically connected to the metal layer.

[0094] Figure 6 The diagram shown is a schematic of a semiconductor structure in another embodiment. Before bonding to the substrate 8, the semiconductor device 7 already has conductive vias (referred to as the first conductive via 101 for convenience in the following description), and the lower surface of the semiconductor device 7 has an intermediate metal layer 13 electrically connected to the first conductive via 101. Thus, only conductive vias (referred to as the second conductive via 102 for convenience in the following description) need to be formed on the substrate 8 and the bonding layer 5, and electrically connected to the intermediate metal layer 13. Typically, the surface area of ​​the intermediate metal layer 13 in contact with the semiconductor device 7 is much larger than the cross-sectional area of ​​the first conductive via. Therefore, when forming the second conductive via, even if the axial direction of the second conductive via is not collinear with the axial direction of the first conductive via, or if the cross-sectional area of ​​the second conductive via is different from that of the first conductive via, electrical connection between the first and second conductive vias can still be achieved. Therefore, the processing difficulty of the second conductive via is reduced.

[0095] Figure 7 The diagram shown is a schematic representation of a substrate in a semiconductor structure according to yet another embodiment. Figure 7 In this embodiment, the substrate includes a substrate 81, a groove 811 formed on the substrate 81, and a diamond 82 formed in the groove 811. The diamond 82 includes a first diamond layer 82A and a second diamond layer 82B. The first diamond layer 82A is formed on the bottom surface of the groove 8111. Figure 7 A1 surface and sidewall surface (in the middle) Figure 7 On the A2 plane of the first diamond layer 82A, the second diamond layer 82B is formed on the first diamond layer 82A. In this embodiment, the average volume of the diamond grains in the first diamond layer 82A is smaller than the average volume of the diamond grains in the second diamond layer 82B.

[0096] In the diamond preparation process, such as Figure 7 As shown, a nanocrystalline diamond seed layer 821 is first prepared on the bottom surface A1 and sidewall surface A2 of the groove 811. Then, a nanocrystalline diamond nucleation layer 822 is deposited on the nanocrystalline diamond seed layer 821. During the deposition of the nanocrystalline diamond nucleation layer 822, diamond grains gradually grow to form a micron-sized diamond layer. Specifically, a diamond layer with an average grain volume of nanometers forms the first diamond layer 82A, and a diamond layer with an average grain volume of micrometers forms the second diamond layer 82B.

[0097] In this process, a nanocrystalline diamond seed layer 821 is first prepared on the bottom surface A1 and the side wall surface A2 of the groove 811. This allows the nanocrystalline diamond nucleation layer 822 to be uniformly deposited in the groove 811 and provides favorable conditions for the subsequent growth of grains, so that the grains in the final diamond are uniformly distributed and the heat dissipation efficiency of the diamond is improved.

[0098] In this embodiment, the diamond 82 is supported in the substrate 81. The specific support method can be as follows: Figure 3 As shown, a groove 811 with an opening facing the bonding layer 5 is provided in the substrate 81. The bonding layer 5 and the groove 811 form a receiving space for holding the diamond 82. To ensure heat dissipation, the upper surface of the diamond 82 is attached to the surface of the bonding layer 5 to absorb heat from it. Similarly, the other surfaces of the diamond are attached to the inner wall of the groove 811 in the substrate 81 to absorb heat from the substrate from multiple directions. In an alternative embodiment, the thickness of the substrate below the groove can be reduced, thereby shortening the distance from the diamond to the metal layer. This can be achieved as follows... Figure 8 As shown, the substrate below the groove 811 is completely removed, meaning that the diamond on the bottom surface of the groove 811 is exposed to the outside of the substrate. Compared to hiding the diamond inside the substrate, the heat dissipation efficiency is greatly improved.

[0099] When the diamond comprises a first diamond layer and a second diamond layer, in alternative embodiments, such as Figure 8 As shown, the first diamond layer 82A on the bottom surface of the groove 811 is exposed to the outside of the substrate 81. In another alternative embodiment, such as Figure 9 As shown, the second diamond layer 82B on the bottom surface of the groove 811 is exposed to the outside of the substrate 81.

[0100] Figure 8 compared to Figure 9In this embodiment, the technical effect achieved is as follows: Since the average volume of the grains of the second diamond layer 82B is greater than the average volume of the grains of the first diamond layer 82A, the thermal conductivity of the second diamond layer 82B is greater than that of the first diamond layer 82A. Removing the first diamond layer 82A and exposing the second diamond layer 82B will further reduce the thermal resistance and further improve the heat dissipation efficiency.

[0101] In an embodiment of this application, diamond is formed within a groove, and the shape of the groove can be as follows: Figure 9 and Figure 10 As shown, in Figure 9 In the middle, the direction from the bottom to the top of the groove ( Figure 9 (in the P direction), the cross-sectional area of ​​groove 811 remains unchanged. Figure 10 In the middle, the direction from the bottom to the top of the groove ( Figure 10 (in the P direction), the cross-sectional area of ​​groove 811 gradually increases.

[0102] During the fabrication of the first and second diamond layers, the diamond grains undergo a growth phase. As the grains grow, their volume gradually increases, occupying more and more space. Therefore, the grooves are designed to... Figure 10 The structure of the grooves promotes uniform grain growth within the grooves, ensuring effective heat dissipation for the final diamond. Furthermore, a larger groove opening provides a larger contact area between the diamond and the bonding layer, correspondingly improving heat conduction efficiency.

[0103] In the semiconductor structure provided in this application embodiment, there may be only one conductive via or there may be multiple conductive vias. For example, if the semiconductor device is a HEMT and the source electrode is large, multiple conductive vias need to be provided to electrically connect to the source electrode; as another example, if the semiconductor device is a chip and the chip carries multiple semiconductor devices with different functions, multiple conductive vias need to be provided to electrically connect to the corresponding semiconductor devices.

[0104] Figure 11 and Figure 12 Schematic diagrams of semiconductor structures with multiple conductive vias are shown. The semiconductor device with this structure is a HEMT (Heated Electron Mediator). Because the HEMT has a strip-like structure, the multiple conductive vias are also arranged along the same straight line. Figure 13 for Figure 12 The diagram shows the structure of the substrate.

[0105] exist Figure 11 In this design, the periphery of each conductive via 10 is made of diamond 82. This can be understood as follows: when a groove is formed on the substrate 81, the protrusion reserved for the conductive via can only form one conductive via. Figure 12In this structure, the periphery of each conductive via 10 is a substrate structure, such as... Figure 13 As shown, when a groove is formed on the substrate 81, a strip-shaped boss 812 is formed according to the arrangement trajectory of multiple conductive vias. In this way, all the conductive vias are located within the boss 812. If the multiple conductive vias are arranged according to other trajectories, the shape of the formed boss may also be other shapes. In short, the formed boss 812 only needs to be able to accommodate multiple conductive vias. However, the volume of the boss cannot be too large. If the volume of the boss is large, the volume occupied by the diamond will be smaller, which will also affect the heat dissipation effect of the semiconductor structure.

[0106] When there are multiple conductive vias, especially when the spacing between two adjacent conductive vias is close (e.g.) Figure 11 (As shown, L is the spacing between two adjacent conductive vias). This application preferentially adopts the following... Figure 12 The structure shown is because: if the spacing between two adjacent conductive vias is close, and a... Figure 11 In the structure shown, the distance between two adjacent bosses reserved for conductive vias is very close, resulting in a very small groove between the two adjacent bosses. This makes it difficult to deposit diamond evenly and sufficiently within the small groove, leading to reduced strength and heat dissipation of the final diamond. However, if a structure like... Figure 12 and Figure 13 When the structure is designed in this way, not only can the above-mentioned phenomena be avoided, but the manufacturing process will also be simplified.

[0107] Figure 9 and Figure 14 These are two different types of conductive vias. Figure 9 In this process, through-holes are formed on the substrate, bonding layer, and semiconductor device. A conductive layer is formed on the inner wall of the through-hole, and the hollow through-hole with the conductive layer forms a conductive through-hole 10. Figure 14 In the process, through holes are formed on the substrate, bonding layer and semiconductor device, and the through holes are filled with conductive material. The through holes with solid structure filled with conductive material form conductive through holes 10.

[0108] When a semiconductor device is operating, some of the heat it dissipates is conducted to the conductive vias. Figure 14 In semiconductor devices, when a via is a solid structure, it absorbs heat and expands, generating thermal stress F. This thermal stress F can cause deformation of the semiconductor device, affecting its performance. However, when the via is constructed using... Figure 9 With the structure shown, even if the heat from the semiconductor device is conducted to the conductive via, the conductive via has a certain thermal expansion space, which greatly reduces the thermal stress F generated on the semiconductor device.

[0109] This application also provides a method for fabricating a semiconductor structure, referring to... Figure 15 The method for manufacturing this semiconductor structure includes:

[0110] like Figure 15 In 15a and 15b, grooves 811 are formed on the surface of substrate 81 to form bosses 812.

[0111] There can be one or more bosses 812. The number of bosses 812 depends on the number of conductive vias.

[0112] In addition, if there are multiple conductive vias and the distance between any two adjacent conductive vias is very close, a boss with a large area can be formed to accommodate all the conductive vias.

[0113] like Figure 15 In sections 15c to 15e, diamond 82 is disposed in groove 811 to obtain substrate 8 containing substrate 81 and diamond 82.

[0114] In an alternative implementation, the preparation of diamond includes:

[0115] like Figure 15 In section 15c, a nanocrystalline diamond seed layer 821 is fabricated on the bottom and sidewall surfaces of groove 811.

[0116] like Figure 15 In step 15d, a nanocrystalline diamond nucleation layer 822 is fabricated on the nanocrystalline diamond seed layer 821. During the fabrication process, the nanocrystalline diamond nucleation layer 822 grows grains to form a micron-sized diamond layer. The average volume of the grains is at the nanometer level, forming the first diamond layer 82A. The average volume of the grains is at the micrometer level, forming the second diamond layer 82B.

[0117] When fabricating the nanocrystalline diamond seed layer 821, it can be prepared by spraying gel-like diamond seed particles. Alternatively, the substrate 81 can be placed in a nanocrystalline diamond particle solution and subjected to ultrasonic treatment to obtain the nanocrystalline diamond seed layer 821.

[0118] The nanocrystalline diamond nucleation layer 822 can be prepared using chemical vapor deposition.

[0119] like Figure 15 As shown in 15d, after the diamond is produced, it will cover the boss. Figure 15 In section 15e, the diamond needs to be ground and polished to expose the surface of the boss and make the diamond flush or nearly flush with the surface of the boss.

[0120] like Figure 15 In 15f, a bonding layer 5 is formed on the upper surface of the substrate.

[0121] The bonding layer can be a Si layer, a SiC layer, a SiO2 layer, a SiN layer, a polycrystalline silicon carbide layer, an amorphous silicon carbide layer, or a polycrystalline silicon carbide layer and an amorphous silicon carbide layer stacked together.

[0122] In forming the stacked polycrystalline silicon carbide layer and the amorphous silicon carbide layer, a polycrystalline silicon carbide layer can be formed on the upper surface of the substrate first, and then the surface of the polycrystalline silicon carbide layer can be activated to form the amorphous silicon carbide layer.

[0123] like Figure 15 In the 15g, the semiconductor device 7 is disposed on the upper surface of the substrate 8 through the bonding layer 5.

[0124] For example, when the semiconductor device is a HEMT, the source and the bump are positioned correspondingly.

[0125] like Figure 15 In 15h and 15i, through-hole 6 is formed on at least a portion of the boss, bonding layer and semiconductor device, and the through-hole 6 is metallized to form conductive through-hole 10.

[0126] like Figure 15 In 15i, a metal layer 9 is disposed on the lower surface of the substrate, and a conductive via 10 is electrically connected to the metal layer 9.

[0127] In the embodiments of this application, when metallizing vias using a deposition method, a metal layer is also deposited on the lower surface of the substrate. If the semiconductor device includes a structure that needs to be grounded, it is not necessary to use additional process methods to prepare a metal layer, and the deposited metal layer can be directly used as the final metal layer. If the semiconductor device is a chip, the metal layer on the lower surface of the substrate needs to be removed, and a redistribution layer needs to be prepared and electrically connected to the conductive via.

[0128] In the above-mentioned preparation method, the groove is opened on the substrate to place diamond in the groove, and the boss is to reserve space for conductive vias. The vias are usually etched on the bosses using plasma etching process. Compared with the existing method of etching vias on diamond, the chemical reaction efficiency between plasma gas and bosses (such as silicon material or silicon carbide material) is higher and the etching speed is faster. Therefore, this application will significantly improve the opening efficiency.

[0129] like Figure 16 This is also a method for preparing semiconductor structures, and this preparation method is similar to... Figure 15 The preparation methods are different: such as Figure 15 In sections 15h and 15i, after opening through-hole 6, a conductive layer is prepared on the inner wall surface of through-hole 6 to form a hollow conductive through-hole 10. For example... Figure 16After opening the through hole 6 in 16h and 16i, conductive material is filled into the through hole 6 to form a solid conductive through hole 10.

[0130] Furthermore, in the fabrication of semiconductor structures, instead of fabricating only one semiconductor structure at a time, multiple semiconductor devices are integrated onto a single substrate, as shown in the reference. Figure 15 The 15i, and Figure 16 The 16i has a cutting process, where Q1 and Q2 are cutting lines. As can be seen from the figure, in the embodiments of this application, cutting is performed on the substrate, which will improve the cutting efficiency and ultimately improve the fabrication efficiency of multiple semiconductor structures.

[0131] like Figure 17 This is also a method for preparing a semiconductor structure, and the manufacturing method of this semiconductor structure is similar to... Figure 15 The difference between the preparation methods shown is: Figure 17 In step 17h, after bonding the substrate to the semiconductor device via the bonding layer, the substrate on the bottom surface of the groove is removed to expose the first diamond layer on the bottom surface of the groove to the outside of the substrate. The rest of the fabrication process is the same. Of course, the substrate on the bottom surface of the groove can also be removed before bonding the substrate to the semiconductor device. The substrate can be removed by grinding or etching.

[0132] like Figure 18 It is also a method for preparing semiconductor structures, and Figure 17 The difference between the preparation methods shown is: Figure 18 In step 18h, after bonding the substrate to the semiconductor device via the bonding layer, the substrate on the bottom surface of the groove is removed to expose the second diamond layer on the bottom surface of the groove to the outside of the substrate. The rest of the fabrication process is the same. Of course, the substrate on the bottom surface of the groove can also be removed before bonding the substrate to the semiconductor device.

[0133] like Figure 19 This is also a method for preparing semiconductor structures, and the semiconductor structures prepared by this method are... Figure 15 The semiconductor structures prepared by the methods shown are the same. Regarding the preparation methods, Figure 19 and Figure 15 The difference is: in Figure 19 In steps 19h and 19i, a mask layer 14 is provided on the lower surface of the substrate 81 before the via is formed. The purpose of the mask layer 14 is to prevent unwanted parts of the substrate from being etched during the etching of the via. Before metallizing the via, the mask layer on the substrate needs to be removed before proceeding with subsequent steps.

[0134] The mask layer can be a metal layer or an insulating layer.

[0135] In Adoption Figure 16 and Figure 17 In the fabrication method shown, it is not necessary to set a mask layer before opening the through hole, because the substrate on the bottom surface of the groove is removed before opening the through hole, and the diamond is exposed. Diamond has strong chemical inertness and is difficult to be etched away, so there is no need to set a mask layer.

[0136] like Figure 20 This is also a method for fabricating semiconductor structures. In this method, the semiconductor device is a chip, and the metal layer is a redistribution layer. Therefore, as... Figure 20 In step 20j, after the through hole is fabricated, an insulating layer 12 is provided on the inner wall surface of the through hole and on the lower surface of the substrate. In step 20k, the through hole with the insulating layer is metallized to obtain a conductive through hole. In step 20l, a redistribution layer is provided on the insulating layer of the substrate and electrically connected to the conductive through hole.

[0137] Figure 20 In the fabrication method shown, a mask layer can also be formed on the lower surface of the substrate before creating the through-hole. The function of the mask layer is to prevent unwanted portions of the substrate from being etched during the etching of the through-hole. Figure 19 The difference is that the mask layer is an insulating layer and is not removed, so as to serve as an insulating layer on the lower surface of the substrate.

[0138] like Figure 21 This is a method for fabricating a semiconductor structure. Before the semiconductor device 7 is bonded to the substrate via the bonding layer 5, such as... Figure 21 In section 21a, a first conductive via 101 has been formed on the semiconductor device 7, and an intermediate metal layer 13 is disposed on the lower surface of the semiconductor device 7, the intermediate metal layer 13 being electrically connected to the first conductive via. In this way, as... Figure 21 In section 21b, after bonding the semiconductor device with the first conductive via to the substrate, as shown... Figure 21 In 21c, it is only necessary to make holes in the substrate and bonding layer. When making the holes, it is not required whether the axis of the second conductive via is consistent with that of the first conductive via, or whether the cross-sectional area of ​​the second conductive via is consistent with that of the first conductive via. It is only necessary that the second conductive via is in contact with the intermediate metal layer, which can reduce the difficulty of making holes.

[0139] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0140] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor devices; Bonding layer; Substrate; as well as Metal layer; The semiconductor device is disposed on the upper surface of the substrate via the bonding layer, and the metal layer is disposed on the lower surface of the substrate. The substrate includes a base plate, a groove formed in the base plate, and a diamond contained in the groove. The semiconductor structure further includes conductive vias that penetrate the substrate, the bonding layer, and at least a portion of the semiconductor device, and are electrically connected to the metal layer. The groove surrounds the conductive via.

2. The semiconductor structure according to claim 1, characterized in that, The diamond on the bottom surface of the groove is exposed to the outside of the substrate.

3. The semiconductor structure according to claim 1 or 2, characterized in that, The diamond includes: First diamond layer and second diamond layer; The first diamond layer is formed on the bottom surface and sidewall surface of the groove, and the second diamond layer is formed on the first diamond layer; The average volume of the grains in the first diamond layer is smaller than the average volume of the grains in the second diamond layer.

4. The semiconductor structure according to claim 3, characterized in that, The first diamond layer on the bottom surface of the groove is exposed to the outside of the substrate.

5. The semiconductor structure according to claim 3, characterized in that, The second diamond layer on the bottom surface of the groove is exposed to the outside of the substrate.

6. The semiconductor structure according to claim 1 or 2, characterized in that, The conductive vias are multiple, and a boss is formed on the substrate, with the multiple conductive vias disposed within the boss.

7. The semiconductor structure according to claim 3, characterized in that, The conductive vias are multiple, and a boss is formed on the substrate, with the multiple conductive vias disposed within the boss.

8. The semiconductor structure according to claim 1 or 2, characterized in that, The semiconductor device is an active device including a grounding structure, the metal layer is a grounding layer, and the conductive via is electrically connected to the grounding structure.

9. The semiconductor structure according to claim 1 or 2, characterized in that, The semiconductor device is a chip, which includes an active layer and a passive layer stacked on top of each other. A first redistribution layer is disposed on the active layer, and the metal layer is a second redistribution layer. The conductive via is electrically connected to the first redistribution layer. An insulating layer is provided between the second redistribution layer and the substrate. An insulating layer is provided between the conductive via and the chip, the bonding layer, and the substrate.

10. The semiconductor structure according to claim 1 or 2, characterized in that, The semiconductor device has an intermediate metal layer on the surface opposite to the bonding layer, and the conductive via is electrically connected to the intermediate metal layer.

11. The semiconductor structure according to claim 10, characterized in that, The portion of the conductive via located within the semiconductor device is a first conductive via, and the portion of the conductive via located within the substrate and the bonding layer is a second conductive via. The cross-sectional area of ​​at least one of the first and second conductive vias is smaller than the surface area of ​​the intermediate metal layer, and / or the axial direction of the first and second conductive vias is not on the same straight line.

12. The semiconductor structure according to claim 1 or 2, characterized in that, The bonding layer includes a polycrystalline silicon carbide layer, or an amorphous silicon carbide layer, or a polycrystalline silicon carbide layer and an amorphous silicon carbide layer stacked together.

13. A method for fabricating a semiconductor structure, characterized in that, include: Grooves are formed on the surface of the substrate to create bosses; A diamond is placed in the groove to obtain a substrate containing the substrate and the diamond; Semiconductor devices are disposed on the upper surface of the substrate via a bonding layer; Through-holes are formed on at least a portion of the boss, the bonding layer, and the semiconductor device, and the through-holes are metallized to form conductive through-holes; A metal layer is disposed on the lower surface of the substrate so that the conductive via is electrically connected to the metal layer.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, After placing the diamond in the groove, the method further includes: Remove the substrate from the bottom surface of the groove so that the diamond on the bottom surface of the groove is exposed to the outside of the substrate.

15. The method for fabricating a semiconductor structure according to claim 13 or 14, characterized in that, Setting the diamond within the groove includes: Nanocrystalline diamond seed layers are formed on the bottom and sidewall surfaces of the groove; A nanocrystalline diamond nucleation layer is fabricated on the nanocrystalline diamond seed layer, and nanocrystals grow to form a micron-crystalline diamond layer. The first diamond layer is formed by diamond layers with an average grain volume of nanometers, and the second diamond layer is formed by diamond layers with an average grain volume of micrometers.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, After placing the diamond in the groove, the method further includes: Remove the substrate from the bottom surface of the groove to expose the first diamond layer on the bottom surface of the groove to the outside of the substrate; or, Remove the substrate from the bottom surface of the groove so that the second diamond layer on the bottom surface of the groove is exposed to the outside of the substrate.

17. The method for preparing a semiconductor structure according to claim 13 or 14, characterized in that, After forming through-holes in at least a portion of the boss, the bonding layer, and the semiconductor device, the method further includes: An insulating layer is provided on the inner wall surface of the through hole and on the lower surface of the substrate, and then the through hole with the insulating layer is metallized.

18. An electronic device, characterized in that, Including printed circuit boards; The semiconductor structure is prepared by any one of claims 1 to 12 or by any one of claims 13 to 17; the printed circuit board is electrically connected to the semiconductor structure.

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