Fin field effect transistor, esd protection circuit, filter circuit, and electronic device
By utilizing redundant polysilicon as resistors in FinFET and FET, the problem of increased chip cost caused by large resistor area is solved, enabling smaller and lower cost chip designs, and providing stable charge release and control in ESD protection and filtering circuits.
Patent Information
- Application Number
- CN202080103261.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-08-31
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2040-08-31
AI Technical Summary
With advancements in semiconductor technology, chip size has increased, leading to a rise in the area occupied by resistors and consequently, higher chip design costs. In particular, functional circuits such as ESD protection and filters occupy a large area, further increasing chip manufacturing costs.
In FinFET and FET, redundant polysilicon is used as a resistor. The resistor is formed by connecting redundant polysilicon in series to reduce the area occupied by the resistor, meet the high resistance requirement, and isolate the effective gate from the redundant polysilicon by floating redundant gate to avoid leakage current.
This reduces the chip area occupied by resistors, lowers chip manufacturing costs, improves chip integration, and enables more stable charge release and circuit control in ESD protection and filtering circuits.
Smart Images
Figure CN115917744B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the chip technical field, and in particular to a fin field effect transistor, an ESD protection circuit, a filter circuit and an electronic device. BACKGROUND
[0002] With the continuous evolution of semiconductor technology and the continuous expansion of chip scale, the area occupied by resistors in the chip is getting larger and larger. Especially for some functional circuits with high demand for resistors, such as ESD, filter, etc., the chip area occupied by resistors is extremely large. For the whole chip, many similar functional circuits are generally needed, and the area is very large, especially with deep nanometer technology, the chip manufacturing cost is getting more and more expensive, which makes the chip design cost huge. SUMMARY
[0003] Embodiments of the present application provide a fin field effect transistor, an ESD protection circuit, a filter circuit and an electronic device, which are used to optimize the problem of large chip area caused by resistors in the chip.
[0004] In a first aspect, an embodiment of the present application provides a fin field effect transistor (FinFET), comprising: one or more fins arranged side by side, a plurality of effective gates, and a first redundant polysilicon; the one or more fins extend along a first direction, the plurality of effective gates and the first redundant polysilicon extend along a second direction and cover the surface of the one or more fins arranged in columns; the first redundant polysilicon is located on one side of the plurality of effective gates, and the fins on both sides of each effective gate in the plurality of effective gates are the source end and the drain end of the FinFET, respectively; the plurality of effective gates are coupled to the gate end of the FinFET; and the first redundant polysilicon is coupled between the gate end of the FinFET and a resistor potential end.
[0005] The FinFET described above uses redundant polysilicon on the field effect transistor, uses the redundant polysilicon as a resistor, can reduce the occupied area of the resistor or avoid the additional occupied area of the resistor in the chip, makes the chip more miniaturized, improves the chip integration, and reduces the preparation cost of the chip.
[0006] In a possible implementation, a first end of the first redundant polysilicon is coupled to the gate end of the FinFET, and a second end of the first redundant polysilicon is coupled to the resistor potential end.
[0007] In a possible implementation, the FinFET can further include: a second redundant polysilicon extending along the second direction and covering surfaces of the one or more column-arranged fins, the second redundant polysilicon being located on the other side of the plurality of effective gates, a first end of the first redundant polysilicon being coupled to a gate terminal of the FinFET, a second end of the first redundant polysilicon being coupled to a first end of the second redundant polysilicon, and a second end of the second redundant polysilicon being coupled to the resistance potential terminal.
[0008] The FinFET described above uses the series connection of the plurality of redundant polysilicons on both sides as a resistor, which can increase the resistance value of the resistor and meet the requirement of a circuit in which the FinFET is applied for a high resistance value, and when the FinFET is applied to an ESD protection circuit, the plurality of fins can be more stably controlled to be turned on uniformly.
[0009] Optionally, in a possible implementation, the FinFET can further include: a first redundant gate and a second redundant gate, both of which extend along the second direction and cover surfaces of the one or more column-arranged fins; the first redundant gate is located between the first redundant polysilicon and the plurality of effective gates; the second redundant gate is located between the second redundant polysilicon and the plurality of effective gates; and both the first redundant gate and the second redundant gate are suspended.
[0010] The FinFET described above introduces the suspended redundant gates before the effective gates and the redundant polysilicons to isolate the effective gates and the redundant polysilicons, thereby avoiding the leakage current of the effective gates and the redundant polysilicons before application and improving the performance of the FinFET.
[0011] Optionally, the first redundant polysilicon, the second redundant polysilicon, the first redundant gate, the second redundant gate, and the effective gate are made of the same material. For example, all of them are metal.
[0012] In a possible implementation, the FinFET can further include: a third redundant polysilicon extending along the second direction and covering surfaces of the one or more column-arranged fins, the third redundant polysilicon and the first redundant polysilicon being located on the same side of the plurality of effective gates, a first end of the first redundant polysilicon being coupled to a gate terminal of the FinFET, a second end of the first redundant polysilicon being coupled to a first end of the third redundant polysilicon, and a second end of the third redundant polysilicon being coupled to the resistance potential terminal.
[0013] The FinFET uses a plurality of redundant polysilicon in series on one side as a resistor, which can increase the resistance value of the resistor to meet the requirement of high resistance value of the FinFET in the application circuit, and when the FinFET is applied to an ESD protection circuit, the plurality of fins can be more stably controlled to be opened uniformly.
[0014] Optionally, the first redundant polysilicon, the third redundant polysilicon, and the effective gate are made of the same material.
[0015] In a possible implementation, the FinFET is an N-type fin field effect transistor, the drain terminal is coupled to a signal line, and the resistance potential terminal and the source terminal of the FinFET are both coupled to a ground terminal of the FinFET to release the charge on the signal line to the ground terminal.
[0016] In a possible implementation, the FinFET is a P-type fin field effect transistor, the drain terminal is coupled to a signal line, and the resistance potential terminal and the source terminal of the FinFET are both coupled to a power terminal of the FinFET to release the charge on the signal line to the power terminal.
[0017] In a second aspect, the embodiments of the present application further provide a planar field effect transistor (FET tube), comprising: a plurality of effective gates, a first redundant polysilicon, and a third redundant polysilicon.
[0018] The plurality of effective gates and the first redundant polysilicon are arranged side by side, and the first redundant polysilicon is located on one side of the plurality of effective gates.
[0019] The plurality of effective gates are coupled to a gate terminal of the FET tube, and the active regions on both sides of each effective gate in the plurality of effective gates are respectively coupled to a source terminal and a drain terminal of the FET tube.
[0020] The first redundant polysilicon is coupled between the gate terminal and a resistance potential terminal of the FET tube.
[0021] The FET tube fully utilizes the redundant polysilicon, uses the redundant polysilicon as a resistor, can reduce the occupied area of the resistor or avoid the additional occupied area of the chip by the resistor, makes the chip more miniaturized, improves the chip integration, and reduces the preparation cost of the chip.
[0022] In a possible implementation, a first end of the first redundant polysilicon is coupled to a gate terminal of the FET tube, and a second end of the first redundant polysilicon is coupled to the resistance potential terminal.
[0023] In a possible implementation, the FET tube can further include: a second redundant polysilicon, the plurality of effective gates, the first redundant polysilicon, and the second redundant polysilicon are arranged side by side and spaced apart, the second redundant polysilicon is located on the other side of the plurality of effective gates, a first end of the first redundant polysilicon is coupled to a gate end of the FET tube, a second end of the first redundant polysilicon is coupled to a first end of the second redundant polysilicon, and a second end of the second redundant polysilicon is coupled to the resistance potential end.
[0024] The FET tube described above uses the series connection of the plurality of redundant polysilicons on both sides as a resistor, which can increase the resistance value of the resistor and meet the requirement of high resistance value of the FET tube in the circuit applied by the FET tube.
[0025] In a possible implementation, the FET tube can further include: a first redundant gate and a second redundant gate, the first redundant gate, the second redundant gate, the plurality of effective gates, the first redundant polysilicon, and the third redundant polysilicon are arranged side by side and spaced apart; the first redundant gate is located between the first redundant polysilicon and the plurality of effective gates; the second redundant gate is located between the second redundant polysilicon and the plurality of effective gates; and the first redundant gate and the second redundant gate are both suspended.
[0026] The FET tube described above introduces the suspended redundant gate between the effective gate and the redundant polysilicon, so as to isolate the effective gate and the redundant polysilicon, avoid the leakage current of the effective gate and the redundant polysilicon before the application, and improve the performance of the FET tube.
[0027] Optionally, the first redundant polysilicon, the second redundant polysilicon, the first redundant gate, the second redundant gate, and the effective gate are made of the same material. For example, all are metal.
[0028] In a possible implementation, the FET tube can further include: a third redundant polysilicon, the plurality of effective gates, the first redundant polysilicon, and the third redundant polysilicon are arranged side by side and spaced apart, the third redundant polysilicon and the first redundant polysilicon are located on the same side of the plurality of effective gates, a first end of the first redundant polysilicon is coupled to a gate end of the FET tube, a second end of the first redundant polysilicon is coupled to a first end of the third redundant polysilicon, and a second end of the third redundant polysilicon is coupled to the resistance potential end.
[0029] The FET tube described above uses the series connection of the plurality of redundant polysilicons on one side as a resistor, which can increase the resistance value of the resistor and meet the requirement of high resistance value of the FET in the circuit applied by the FET.
[0030] Optionally, the first redundant polysilicon, the third redundant polysilicon, and the effective gate are made of the same material.
[0031] In a possible implementation, the FET is an N-type metal oxide semiconductor field effect transistor, the drain terminal is coupled to a signal line, and the resistance potential terminal and the source terminal of the FET are both coupled to a ground terminal of the FET.
[0032] In a possible implementation, the FET is a P-type metal oxide semiconductor field effect transistor, the drain terminal is coupled to a signal line, and the resistance potential terminal and the source terminal of the FET are both coupled to a power terminal of the FET.
[0033] In a third aspect, an ESD protection circuit is also provided in the embodiments of the present application, and the ESD protection circuit includes any one of the FinFETs in the first aspect or any one of the FETs in the second aspect.
[0034] The ESD protection circuit is coupled to a first functional circuit and a second functional circuit.
[0035] The first functional circuit is coupled to the second functional circuit through a signal line, and the FinFET is coupled to the signal line.
[0036] Optionally, the first functional circuit is a digital logic circuit, and the second functional circuit is an analog logic circuit.
[0037] Optionally, the first functional circuit and the second functional circuit are located in different chips, respectively.
[0038] In a possible implementation, the drain terminal of the FinFET is coupled to a signal line, and the source terminal and the resistance potential terminal are coupled to a ground terminal, so as to release the charge on the signal line to the ground terminal.
[0039] In a possible implementation, the drain terminal of the FinFET is coupled to a signal line, and the source terminal and the resistance potential terminal are coupled to a power terminal, so as to release the charge on the signal line to the power terminal.
[0040] In a fourth aspect, a filter circuit is also provided in the embodiments of the present application, and the filter circuit includes any one of the FinFETs in the first aspect or any one of the FETs in the second aspect.
[0041] Optionally, the FinFET or the FET is an NMOS, the drain terminal is connected to an input signal, a common terminal of the gate terminal and a first terminal of a first redundant polysilicon is connected to an output signal, and the source terminal and the resistance potential terminal are coupled to a ground terminal.
[0042] Optionally, the filter circuit further includes a capacitor, one terminal of the capacitor is coupled to the common terminal, and the other terminal of the capacitor is coupled to the ground terminal.
[0043] In a fifth aspect, the embodiments of the present application further provide an electronic device, comprising a circuit board, and any one of the FinFETs of the first aspect, or any one of the FETs of the second aspect, or any one of the ESD protection circuits of the third aspect, or any one of the filter circuits of the fourth aspect.
[0044] Optionally, the circuit board can comprise at least one of a processor, a memory, a communication module, an input module, an output module, a sensor, etc. BRIEF DESCRIPTION OF DRAWINGS
[0045] The drawings needed to be used in the description of the embodiments or prior art will be briefly introduced as follows.
[0046] Figure 1 is a structure schematic diagram of a FinFET provided by the embodiments of the present application;
[0047] Figure 2 is a structure schematic diagram of another FinFET provided by the embodiments of the present application;
[0048] Figure 3 is a structure schematic diagram of still another FinFET provided by the embodiments of the present application;
[0049] Figure 4 is a structure schematic diagram of still another FinFET provided by the embodiments of the present application;
[0050] Figure 5 is a structure schematic diagram of a planar FET provided by the embodiments of the present application;
[0051] Figure 6 is a structure schematic diagram of another planar FET provided by the embodiments of the present application;
[0052] Figure 7 is a cross-sectional schematic diagram of a GGNMOS provided by the embodiments of the present application;
[0053] Figure 8A is a circuit schematic diagram of an ESD protection circuit provided by the embodiments of the present application;
[0054] Figure 8B is a circuit schematic diagram of another ESD protection circuit provided by the embodiments of the present application;
[0055] Figure 8C is a circuit schematic diagram of still another ESD protection circuit provided by the embodiments of the present application;
[0056] Figure 9 is a circuit schematic diagram of a filter circuit provided by the embodiments of the present application. DETAILED DESCRIPTION
[0057] The technical solutions in the embodiments of the present application will be clearly and completely described in connection with the drawings in the embodiments of the present application.
[0058] In the present application, the serial numbers of components, such as "first", "second", etc., are only used to distinguish the described objects, and do not have any sequence or technical meaning. In the present application, "connection" and "coupling" include direct and indirect connection (coupling) unless otherwise specified. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.
[0059] In the present application, "coupling" can mean direct connection; it can also be indirect connection, that is, through other elements or metal connection.
[0060] First, the abbreviations and technical terms involved in the present application are explained.
[0061] (1) Metal oxide semiconductor field effect transistor (MOSFET), also known as MOS tube, is a kind of field effect transistor (FET tube). It can include planar MOSFET and three-dimensional MOSFET, and the three-dimensional MOSFET includes Fin Field-Effect Transistor (FinFET). Among them, the early MOSFET is mainly of planar structure. The channel of FinFET is composed of a high and thin fin protruding from the insulating substrate, and the source and drain electrodes are respectively at both ends thereof, and the gate closely contacts the sidewall and top thereof for assisting current control. This fin-shaped structure increases the surface of the gate surrounding the channel, strengthens the control of the gate on the channel, and effectively alleviates the short channel effect in the planar MOSFET, greatly improves the circuit control and reduces the leakage current.
[0062] (2) MOSFET can be divided into NMOSFET and PMOSFET, wherein the MOSFET composed of P-type substrate and two high-concentration N diffusion regions is called P-channel MOSFET, namely NMOSFET; and the MOSFET composed of N-type substrate and two high-concentration P diffusion regions is called P-channel MOSFET, namely PMOSFET.
[0063] (3) Electro static discharge (ESD) protection circuit is a discharge path for integrated circuits or electronic devices to avoid static electricity from damaging integrated circuits or electronic devices. ESD protection circuit is usually added at the input end of a chip or functional circuit.
[0064] (4) Gate grounded NMOS (GGNMOS) is an ESD protection circuit. Generally, the drain of GGNMOS is connected to a signal line (PAD), and the gate end is connected to a ground end, so that the charge on the signal line can be discharged to the ground end.
[0065] (5) Gate grounded PMOS (GGPMOS) is an ESD protection circuit. Generally, the drain of GGPMOS is connected to a signal line (PAD), and the gate end is connected to a power supply end, so that the charge on the signal line can be discharged to the power supply end.
[0066] (6) Charged device model (CDM) is a mode / model of ESD.
[0067] (7) Dummy poly and dummy gate are redundant parts of some FET tubes needed in the process of processing, which are located on both sides of the FET tube and can improve the performance of the intermediate functional device. Among them, the dummy poly is outside the active area of the FET tube, and the dummy gate is on the active area and is floating, which is used to isolate the active area and the dummy poly. In the embodiments of the present application, the dummy poly in the FET tube is used as a resistor.
[0068] Figure 1A structure diagram of a FinFET is provided in the embodiments of the present application. The FinFET can include, but is not limited to, one or more fins 11 arranged in parallel, a plurality of effective gates 12, one or more redundant polysilicon 13, one or more redundant gates 14, etc. Wherein, the one or more fins 12 are arranged on a semiconductor substrate 10, and each extends along a first direction; the plurality of effective gates 12, the one or more redundant polysilicon 13, and the one or more redundant gates 14 each extend along a second direction and cover the surface of the one or more fins 11 arranged in parallel; the one or more redundant polysilicon 13 can be located on one side or both sides of the plurality of effective gates 12. The redundant gate 14 is located between the effective gate 12 and the redundant polysilicon 13, and is used to isolate the effective gate 12 and the redundant polysilicon 14, and is suspended (i.e. not connected to an external circuit). It should be understood that the redundant gate 14 is not a necessary structure of the FinFET. For example, when the length of the FinFET is greater than a predetermined value, the FinFET can not include the redundant gate 14. Here, the length of the FinFET refers to the length of the FinFET along the second direction.
[0069] It should also be understood that the first direction is perpendicular or close to perpendicular to the second direction. Wherein, close to perpendicular can be understood as the included angle between the first direction and the second direction is in the range of 60°-120°, and each embodiment of the present application is illustrated by taking the first direction perpendicular to the second direction as an example.
[0070] In some embodiments, the materials of the effective gate 12, the redundant polysilicon 13, and the redundant gate 14 can be the same, and each can be metal. Alternatively, they can also be prepared by the same process. Alternatively, the plurality of effective gates 12, the one or more redundant polysilicon 13, and the one or more redundant gates 14 can be arranged at equal intervals. They have the same length and width, wherein the length is the edge length in the second direction, and the width is the edge length in the first direction.
[0071] The plurality of effective gates 12 collectively constitute the gate terminal of the FinFET; or each of the plurality of effective gates is coupled to the gate terminal of the FinFET, and at this time, the gate terminal is a common terminal coupled to the plurality of effective gates.
[0072] Wherein, the fins on both sides of each effective gate in the plurality of effective gates 12 are the active regions of the FinFET, and are respectively the source and the drain, and the fin covered by the effective gate is the channel of the FinFET. The fins on both sides of each effective gate collectively form the source terminal and the drain terminal of the FinFET; or the fins on both sides of each effective gate are respectively coupled to the source terminal and the drain terminal of the FinFET, and at this time, the source terminal is a common terminal coupled to each source, and the drain terminal is a common terminal coupled to each drain.
[0073] The fins on both sides of the redundant gate are also the active regions of the FinFET, but they are suspended.
[0074] It should be noted that the region where the above-mentioned multiple effective gates, one or more redundant gates, and active regions are located is called the active region.
[0075] In this embodiment, the fins on both sides of the redundant polysilicon and the covered fins are all non-active regions, meaning they have not undergone N-type or P-type ion implantation and have not formed source, channel, or drain structures. The regions they occupy are called non-active regions, which are the areas on the semiconductor substrate 10 excluding the active regions. It should be noted that the redundant polysilicon is a conductive material. Redundant polysilicon is an inherent redundant structure in FinFETs. In this application embodiment, one or more redundant polysilicon layers form a resistor connecting the gate terminal and the resistor potential terminal, reducing the chip area and fabrication cost.
[0076] In this embodiment, the resistance value of the FinFET is increased by the resistor formed by the redundant polysilicon 13 or by the series connection of multiple redundant polysilicon 12s on one or both sides of the effective gate 12, so as to uniformly turn on multiple fins.
[0077] In some embodiments, a resistor connecting the gate terminal and the resistor potential terminal can be formed using a redundant polysilicon. For example, Figure 2 The diagram shows the structure of a FinFET. This FinFET includes a first redundant polysilicon P1, a second redundant polysilicon P2, a third redundant polysilicon P3, and a fourth redundant polysilicon P4. The first redundant polysilicon P1 and the third redundant polysilicon P3 are located on one side of the first effective gate G1, the second effective gate G2, and the third effective gate G3, while the second redundant polysilicon P2 and the fourth redundant polysilicon P4 are located on the other side. The first terminal of the first redundant polysilicon P1 is coupled to the gate terminal of the FinFET. The source terminals S1 and S2 of the FinFET are jointly connected to the source terminal, and the drain terminals D1 and D2 of the FinFET are jointly connected to the drain terminal.
[0078] like Figure 2 As shown, the second terminal of the first redundant polysilicon P1 is coupled to the potential terminal of the resistor. It should be understood that the first and second terminals of the first redundant polysilicon P1 are the two ends of the first redundant polysilicon P1 in the second direction.
[0079] In some embodiments, a resistor connecting the gate terminal and the resistive potential terminal can be formed by connecting multiple redundant polysilicon cells in series on both sides of the effective gate. For example, as... Figure 3The structure diagram of the FinFET is shown in the figure. The FinFET includes a second redundant polysilicon P2 in the redundant polysilicon. The second redundant polysilicon P2 also extends along the second direction and covers the surface of the one or more column-arranged fins. The second redundant polysilicon P2 is located on the other side of the plurality of effective gates (G1, G2, G3), that is, the side of the plurality of effective gates away from the first redundant polysilicon P1. The second end of the first redundant polysilicon P1 is coupled to the first end of the second redundant polysilicon P1, and the second end of the second redundant polysilicon P2 is coupled to the resistance potential end. It should be understood that the first end and the second end of the second redundant polysilicon P2 are the two ends of the second redundant polysilicon P2 in the second direction. This embodiment uses the series connection of the two redundant polysilicon on both sides of the effective gate as a resistor, which can increase the resistance value of the resistor to fully utilize the redundant polysilicon and more evenly turn on the FinFET.
[0080] In some embodiments, the resistor connecting the gate end and the resistance potential end can be formed by the series connection of a plurality of redundant polysilicon on one side of the effective gate. For example, as shown in the structure diagram of the FinFET in the figure, the FinFET includes a third redundant polysilicon P3 in the redundant polysilicon. The third redundant polysilicon P3 also extends along the second direction and covers the surface of the one or more column-arranged fins. The third redundant polysilicon P3 is located on the same side of the effective gate (G1, G2, G3) as the first redundant polysilicon P1. The second end of the first redundant polysilicon P1 is coupled to the first end of the third redundant polysilicon P3, and the second end of the third redundant polysilicon P3 is coupled to the resistance potential end. It should be understood that the first end and the second end of the third redundant polysilicon P3 are the two ends of the third redundant polysilicon P3 in the second direction. This embodiment uses the series connection of the two redundant polysilicon on one side of the effective gate as a resistor, which can increase the resistance value of the resistor to fully utilize the redundant polysilicon and more evenly turn on the FinFET. Figure 4 Optionally, the above-mentioned
[0081] Figures 2-4 Any of the FinFETs shown can include a first redundant gate DG1 and a second redundant gate DG2. The first redundant gate DG1 is located between the first redundant polysilicon P1 and the plurality of effective gates (G1, G2, G3). The second redundant gate DG2 is located between the second redundant polysilicon P2 and the plurality of effective gates (G1, G2, G3). The first redundant gate DG1 and the second redundant gate DG2 are both suspended.
[0082] It should be noted that the above-mentioned Figure 3 , Figure 4 The above-mentioned resistor formed by the series connection of two redundant polysilicon on both sides or one side of the effective gate is only used as an example. In other embodiments of the present application, the resistor connecting the gate end and the resistance potential end can also be formed by the series connection of more effective gates on both sides or one side of the effective gate.
[0083] In some embodiments, the FinFET is an N-type fin field-effect transistor, with its drain terminal coupled to the signal line, and its resistive potential terminal and source terminal both coupled to the FinFET's ground terminal.
[0084] In some embodiments, the FinFET is a P-type fin field-effect transistor, with its drain terminal coupled to the signal line, and its resistive potential terminal and source terminal both coupled to the power supply terminal of the FinFET.
[0085] It should be noted that the effective gate, redundant gate, and redundant polysilicon cover the fins but are not in direct contact with them. A gate insulating layer (not shown in the figure) separates them from the fins. This gate insulating layer is made of insulating materials such as silicon dioxide or silicon nitride and is used to isolate them from the fins. It should also be noted that FinFETs may include other necessary or non-essential structures, and this is not limited.
[0086] like Figure 5 The diagram shows a schematic representation of a planar FET according to an embodiment of this application. The FET may include an epitaxial layer 50, multiple active gates 51, one or more redundant polysilicon cells 52, and one or more redundant gates 53. The multiple active gates 51, the one or more redundant polysilicon cells 52, and the one or more redundant gates 53 are disposed on the surface of the epitaxial layer 50, and are arranged in parallel with spacing between them. The one or more redundant polysilicon cells 52 may be located on one or both sides of the multiple active gates 51; the redundant gates 53 are located between the active gates 51 and the redundant polysilicon cells 52, serving to isolate the active gates 51 and the redundant polysilicon cells 52, and are all floating (i.e., not connected to external circuitry). It should be understood that the redundant gates 53 are not a necessary structure for the FET; in some embodiments, the FET may not include redundant gates 53.
[0087] In this case, multiple effective gates 51 together constitute the gate terminal of the FET; or, multiple effective gates 51 are all coupled to the gate terminal of the FET, in which case the gate terminal is the common terminal coupled to the multiple effective gates 51.
[0088] The epitaxial layer 50 includes an active region, a source, a channel, and a drain. The epitaxial layers 50 on either side of each effective gate 51 are the source and drain of the FET, respectively. All sources together constitute the source terminal of the FET; or, all sources are coupled to the source terminal of the FET, in which case the source terminal is the common terminal connecting all sources. The channel is the region in the epitaxial layer opposite the effective gate, located between the source and drain. Each source and drain constitutes the active region of the FET. The region containing the multiple effective gates 51, one or more redundant gates 53, and the active region is called the active region. It should be understood that for an N MOSFET, the epitaxial layer 50 includes a P-well, and the region of the P-well includes N-type doped source and drain; for a P MOSFET, the epitaxial layer 50 includes an N-well, and the region of the N-well includes P-type doped source and drain.
[0089] The non-active region refers to the area in the FET other than the active region. The redundant polysilicon 52 and the epitaxial layers 50 on both sides of the redundant polysilicon 52 both belong to the non-active region. In some embodiments, the epitaxial layer 50 may include one or more trenches formed in a shallow trench isolation (STI) process. The trenches may be filled with dielectric materials such as silicon dioxide and silicon nitride. Some of these trenches may be used to isolate the source of two adjacent active gates or to isolate the drain of two adjacent active gates. It should be noted that the redundant polysilicon 52 is a conductive material. The redundant polysilicon 52 is an inherent redundant structure in the FET. In this embodiment, one or more redundant polysilicon 52 form a resistor connecting the gate terminal and the resistor potential terminal, reducing the chip area.
[0090] In some embodiments, a resistor connecting the gate terminal and the resistive potential terminal can be formed by connecting one or more redundant polysilicon cells on both sides of the effective gate in series. For example, as... Figure 6 The schematic diagram of the FET shown illustrates the structure of a FET comprising a first redundant polysilicon P21, a second redundant polysilicon P22, a third redundant polysilicon P23, and a fourth redundant polysilicon P24. The first redundant polysilicon P21 and the third redundant polysilicon P23 are located on one side of the first effective gate G21, the second effective gate G22, and the third effective gate G23, while the second redundant polysilicon P22 and the fourth redundant polysilicon P24 are located on the other side. The source terminals S21 and S22 of the FET are jointly connected to the source terminal, and the drain terminals D21 and D22 of the FET are jointly connected to the drain terminal.
[0091] In some embodiments, the resistance connecting the gate terminal and the resistance potential terminal can be formed by one redundant polysilicon. For example, a first redundant polysilicon P21 is used, which is located at one side of the plurality of effective gates 51. The first end of the first redundant polysilicon P21 is coupled to the gate terminal of the FET, and the second end of the first redundant polysilicon P21 is coupled to the resistance potential terminal. It should be understood that the first end and the second end of the first redundant polysilicon P21 are two ends of the first redundant polysilicon P21 in the extension direction thereof.
[0092] In some embodiments, the resistance connecting the gate terminal and the resistance potential terminal can be formed by a plurality of redundant polysilicons. For example Figure 6 In the illustrated FET, the redundant polysilicons included therein include the first redundant polysilicon P21 and the third redundant polysilicon P23. The first redundant polysilicon P21 and the third redundant polysilicon P23 are located at the same side of the plurality of effective gates (G21, G22, G23). The second end of the first redundant polysilicon P21 is coupled to the first end of the third redundant polysilicon P23, and the second end of the third redundant polysilicon P23 is coupled to the resistance potential terminal. It should be understood that the first end and the second end of the third redundant polysilicon P23 are two ends of the third redundant polysilicon P23 in the extension direction thereof. This embodiment uses the series connection of the two redundant polysilicons on both sides of the effective gate as the resistance, which can increase the resistance value of the resistance, so as to make full use of the redundant polysilicon and more evenly turn on the FET.
[0093] In other embodiments of the present application, the series connection of the first redundant polysilicon P21 and the second redundant polysilicon P22 can also be used as the resistance connecting the gate terminal and the resistance potential terminal, or the series connection of one or more other redundant polysilicons can be used as the resistance, which can be connected by the conductor part.
[0094] In some embodiments, the FET is an NMOSFET, the drain terminal of which is coupled to the signal line, and the resistance potential terminal and the source terminal of which are both coupled to the ground terminal of the FET.
[0095] In some embodiments, the FinFET is a PMOSFET, the drain terminal of which is coupled to the signal line, and the resistance potential terminal and the source terminal of which are both coupled to the power terminal of the FET.
[0096] It should be noted that the effective gate, the redundant gate, and the redundant polysilicon are covered on the epitaxial layer, and are not in direct contact with the channel on the epitaxial layer. There is also a gate insulating layer (not shown in the figure) between the gate and the channel, which is an insulating material such as silicon dioxide or silicon nitride, and is used to isolate the gate from the channel. It should also be noted that the FET can also include other necessary structures or unnecessary structures, which are not limited.
[0097] The above Figures 1-4 The FinFET orFigures 5-6 The FETs shown are all taken as an example including 4 redundant polysilicon, 3 active gates, 2 redundant gates, in other embodiments of the present application, the FinFET or FET can also include more or less redundant polysilicon, active gates or redundant gates, the FinFET or FET can also include more or less redundant polysilicon or series of redundant polysilicon as a resistor, one end of the resistor is connected to the gate end of the FET where it is located, which is not limited here.
[0098] Optionally, Figures 1-6 The active gate, redundant gate, and redundant polysilicon shown can be prepared by the same process flow, have the same material, the same size, and are arranged at equal intervals.
[0099] It should be noted that the coupling between the above-mentioned elements can be direct connection or indirect connection, such as through the conductor part and via hole connection shown in Figures 2-4 、 Figure 6 . The conductor part is a conductor, which can be a metal material; the via hole is used to connect structures of different layers.
[0100] To solve the ESD problem in IC and electronic equipment, especially the CDMESD problem, the GGNMOS or GGPMOS mode is generally not used, but the upper and lower diode mode. This is because when the power-on sequence of two functional circuits coupled by the signal line is not the same, the upper and lower diode mode may cause leakage.
[0101] The following introduces the principle of electrostatic discharge involved in the embodiments of the present application in combination with a cross-sectional view of a GGNMOS shown in Figure 7 . As shown in Figure 7 , the GGNMOS includes a P-type substrate, an N-type heavily doped source (S) and drain (D), and a P-type doped substrate end (B). When electrostatic discharge is performed through the GGNMOS, the D end is coupled to the signal line.
[0102] When the D end connected to the signal line accumulates a large amount of negative charge, the PN junction between the D end and the P substrate is turned on, and the negative charge is discharged to GND through the B end.
[0103] When the D end connected to the signal line accumulates a large amount of positive charge, the PN junction between the D end and the P substrate is broken down, resulting in a leakage current; under the action of the leakage current, due to the existence of the substrate parasitic resistance R, the parasitic diode between the P substrate and the S end is turned on, at this time, the parasitic transistor T is turned on, a large amount of charge flows from the D end to the S end through the parasitic transistor, and then is discharged to GND.
[0104] The following introduces the FinFET shown in Figures 1-4 of the above-mentioned embodiments provided by the present application, Figure 5 orFigure 6 The FinFET, FET tube can be applied to ESD protection circuit, filter circuit, etc.
[0105] Please refer to Figure 8A , Figure 8B , Figure 8A , Figure 8B is the circuit schematic diagram of two ESD protection circuits provided by the embodiment of the application. The ESD protection circuit is coupled to the first functional circuit and the second functional circuit, wherein the first functional circuit is coupled to the second functional circuit through a signal line, and the ESD protection circuit comprises a FET tube, which can be any one of the above-mentioned Figures 1-4 FinFET, Figure 5 or Figure 6 FET tube. The gate end G of the FET tube is connected to one end of a resistor R, and the other end of the resistor R is the resistance potential end, and the drain end D of the FET tube is connected to the signal line, and the charge on the signal line can be released. Wherein, the resistor R is the resistor formed by the redundant polysilicon in the above-mentioned Figures 1-4 FinFET or Figures 5-6 FET tube.
[0106] In a specific implementation, the FET tube in the ESD protection circuit is an N-type FET tube, such as an N-type FinFET, NMOSFET, etc. As Figure 8A shown, the resistance potential end and the source end S of the N-type FET tube are both coupled to the ground end GND to release the charge on the signal line to the ground end GND.
[0107] In another specific implementation, the FET tube in the ESD protection circuit is a P-type FET tube, such as a P-type FinFET, PMOSFET, etc. As Figure 8B shown, the resistance potential end and the source end S of the P-type FET tube are both coupled to the power supply end VDD2 of the second functional circuit to release the charge on the signal line to the power supply end VDD2.
[0108] Wherein, the above-mentioned first functional circuit is a circuit for realizing a first function, and the second functional circuit is a circuit for realizing a second function, and the first function is usually not equal to the second function. In some embodiments, the first functional circuit can be a digital control circuit, which can control the second functional circuit, such as an analog-to-digital converter (ADC) converting an analog signal into a digital signal.
[0109] In some embodiments, the power supply voltage VDD1 of the first functional circuit in the above-mentioned Figure 8A or Figure 8B is not equal to the power supply voltage VDD2 of the second functional circuit.
[0110] In some embodiments, the first functional circuit in the above Figure 8A or Figure 8B may be a digital logic circuit, and the second functional circuit may be an analog logic circuit.
[0111] In some embodiments, the first functional circuit and the second functional circuit in the above Figure 8A or Figure 8B may be located in different chips.
[0112] As shown in Figure 8C , another circuit schematic diagram of an ESD protection circuit combined with an application scenario is provided in embodiments of the present application. When an input / output interface (I / O interface) is connected with a functional circuit, the I / O interface includes a plurality of pins, each pin is connected with a signal line, and part or all of the plurality of signal lines are coupled with the ESD protection circuit. The connection relationship between the ESD protection circuit and the corresponding signal line is the same as that of the ESD protection circuit shown in the above Figure 8A or Figure 8B , which will not be described here again.
[0113] Embodiments of the present application further provide an ESD protection device, which can include a FET tube, which can be any one of the FET tubes in the above Figures 1-4 , the FinFET shown in Figure 5 or Figure 6 .
[0114] Embodiments of the present application further provide a filter circuit, which can include a FET tube, which can be any one of the FET tubes in the above Figures 1-4 , the FinFET shown in Figure 5 or Figure 6 .
[0115] As shown in Figure 9 , a circuit schematic diagram of an RC filter circuit, which can include the above FET tube and a capacitor C. The capacitor C is not a necessary element of the filter circuit, and in other embodiments of the present application, the capacitor C can be included in the FET tube as a parasitic capacitor of the FET tube.
[0116] In the above, the drain end D of the FET tube is connected with an input signal IN, the gate end G of the FET tube is connected with one end of a resistor R, the other end of the resistor R is a resistor potential end, and the resistor R is the FinFET shown in the above Figures 1-4 or Figures 5-6The resistance formed by the redundant polysilicon in the FET shown. One end of the capacitor C is connected to the common end of the resistance R and the gate end G, and the other end is connected to the ground end GND. The FET can be an N-type FET, such as an N-type FinFET, NMOSFET, etc., whose resistance potential end and source end S are both coupled to the ground end GND, and the above-mentioned RC filter circuit can realize filtering processing on the input signal IN to obtain the filtered output signal OUT.
[0117] Embodiments of the present application also provide an electronic device, which can be a mobile phone, a notebook computer, a tablet computer, a smart watch, a smart bracelet, a VR / AR device, etc. The electronic device can include a circuit board and a circuit as shown in any one of Figures 1-4 FinFET or Figures 5-6 FET shown; or the electronic device can include a circuit board and a circuit as shown in any one of Figures 8A-8C or Figure 9 any one of the above. It can be understood that the above-mentioned FinFET or FET can be located on the circuit board, or can be independent of the circuit board and coupled to the circuit board.
[0118] It should be understood that the circuit board can be the mainboard of the above-mentioned electronic device, which can include but is not limited to a processor, a memory, a radio frequency module, a power management module, an input module, an output module, a communication interface, one or more sensors, etc. Among them:
[0119] The processor can include one or more processing units, for example: the processor can include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processing units can be independent devices, or can be integrated in one or more processors.
[0120] The power management module is used to connect the battery and the processor, and is used to power the processor, the memory, the radio frequency module, the power management module, the input module, the output module, the communication interface, one or more sensors, etc.
[0121] The radio frequency module is used to realize the transceiving of signals, so as to realize the wireless communication with other devices. The input module can include a touch panel, a microphone, etc., and the output module can include a display screen, a loudspeaker, etc., so as to realize the man-machine interaction between the electronic device and the user.
[0122] The input module can include but is not limited to a touch panel, a keyboard, etc., and the output module can include a display screen, etc., which can be used to realize the man-machine interaction between the electronic device and the user.
[0123] The sensor can include one or more combinations of an acceleration sensor, a pressure sensor, a magnetic force sensor, a fingerprint sensor, an image sensor (camera, etc.), an ambient light sensor, etc.
[0124] The technical terms used in the embodiments of the present application are only used for describing the specific embodiments and are not intended to limit the present application. In this paper, the singular form "a", "an" and "the" are used to include the plural form, unless the context clearly indicates otherwise. Further, the "comprising" and / or "including" used in the specification means that the features, integers, steps, operations, elements and / or components exist, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements and / or components.
[0125] The equivalents of the corresponding structures, materials, actions and all devices or steps and functional elements (if any) in the appended claims are intended to include any structure, material or action that is used in combination with other explicitly required elements to perform the function. The description of the present application is given for the purpose of examples and description, but is not intended to be exhaustive or to limit the invention to the disclosed form.
Claims
1. A fin field effect transistor (FinFET) comprising: comprising: one or more fins arranged in parallel, a plurality of effective gates, a first redundant polysilicon; the one or more fins each extend along a first direction, the plurality of effective gates, the first redundant polysilicon each extend along a second direction and cover surfaces of the one or more fins arranged in parallel; the first redundant polysilicon is located at one side of the plurality of effective gates, fins at two sides of each of the plurality of effective gates are coupled to a source terminal and a drain terminal of the fin field effect transistor respectively; the plurality of effective gates are coupled to a gate terminal of the fin field effect transistor; the first redundant polysilicon is coupled between the gate terminal of the fin field effect transistor and a resistive potential terminal.
2. The fin field effect transistor of claim 1, wherein: a first end of the first redundant polysilicon is coupled to the gate terminal of the fin field effect transistor, and a second end of the first redundant polysilicon is coupled to the resistive potential terminal.
3. The fin field effect transistor of claim 1, wherein, further comprising: a second redundant polysilicon; the second redundant polysilicon extends along the second direction and covers surfaces of the one or more fins arranged in parallel, the second redundant polysilicon is located at another side of the plurality of effective gates; a first end of the first redundant polysilicon is coupled to the gate terminal of the fin field effect transistor, a second end of the first redundant polysilicon is coupled to a first end of the second redundant polysilicon, and a second end of the second redundant polysilicon is coupled to the resistive potential terminal.
4. The fin field effect transistor of any of claims 1-3, wherein, further comprising: a first redundant gate and a second redundant gate; the first redundant gate and the second redundant gate each extend along the second direction and cover surfaces of the one or more fins arranged in parallel; the first redundant gate is located between the first redundant polysilicon and the plurality of effective gates; the second redundant gate is located between the second redundant polysilicon and the plurality of effective gates; the first redundant gate and the second redundant gate are both suspended.
5. The fin field effect transistor of claim 4, wherein: materials of the first redundant polysilicon, the second redundant polysilicon, the first redundant gate, the second redundant gate and the effective gate are the same.
6. The fin field effect transistor of claim 1, wherein, further comprising: a third redundant polysilicon; the third redundant polysilicon extends along the second direction and covers surfaces of the one or more fins arranged in parallel, the third redundant polysilicon is located at the same side of the plurality of effective gates as the first redundant polysilicon; a first end of the first redundant polysilicon is coupled to the gate terminal of the fin field effect transistor, a second end of the first redundant polysilicon is coupled to a first end of the third redundant polysilicon, and a second end of the third redundant polysilicon is coupled to the resistive potential terminal.
7. The fin field effect transistor of any one of claims 1-3, 5, 6, wherein: the fin field effect transistor is an N-type fin field effect transistor, the drain terminal is coupled to a signal line, and the resistive potential terminal and the source terminal are both coupled to a ground terminal of the fin field effect transistor.
8. The fin field effect transistor of any one of claims 1-3, 5, 6, wherein: The fin field effect transistor is a P-type fin field effect transistor, the drain terminal is connected to a signal line, and the resistance potential terminal and the source terminal of the fin field effect transistor are both connected to the power terminal of the fin field effect transistor.
9. An electrostatic discharge (ESD) protection circuit, characterized by, Comprising: The fin field effect transistor of any one of claims 1-8; The electrostatic discharge protection circuit is coupled to a first functional circuit and a second functional circuit. The first functional circuit is coupled to the second functional circuit through a signal line, and the fin field effect transistor is coupled to the signal line.
10. The electrostatic discharge protection circuit of claim 9, wherein The first functional circuit is a digital logic circuit, and the second functional circuit is an analog logic circuit.
11. The electrostatic discharge protection circuit of claim 10, wherein The first functional circuit and the second functional circuit are located in different chips, respectively.
12. A filter circuit, characterized by Comprising: The fin field effect transistor of any one of claims 1-8.
13. An electronic device, comprising: Comprising: A circuit board; The fin field effect transistor of any one of claims 1-8, the electrostatic discharge protection circuit of any one of claims 9-11, or the filter circuit of claim 12.
Citation Information
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