Microelectronic devices including stepped structures and related memory devices, electronic systems, and methods

Abstract

This application relates to microelectronic devices including stepped structures and related memory devices, electronic systems, and methods. A microelectronic device includes a stack structure including alternating conductive structures and insulative structures arranged in tiers, the tiers individually including one of the conductive structures and one of the insulative structures; first support pillar structures extending through the stack structure within a first region of the microelectronic device, the first support pillar structures electrically isolated from a source structure underlying the stack structure; second support pillar structures extending through the stack structure within a second region of the microelectronic device, the second support pillar structures including a conductive material in electrical communication with the source structure; and a bridge structure extending between at least some adjacent ones of the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

Description

[0001] Cross-citation of related applications

[0002] This application is a national phase entry of international patent application PCT / US2021 / 035748, filed June 3, 2021, which designates the People's Republic of China and was published in English on December 30, 2021 as international patent publication WO 2021 / 262415 A1. The application claims the benefit of U.S. Patent Application No. 16 / 908,287, filed June 22, 2020, and now U.S. Patent No. 11,417,673, published August 16, 2022, under Article VIII of the Patent Cooperation Treaty for “Microelectronic Devices Including Stair Step Structures, and Related Memory Devices, Electronic Systems, and Methods”. Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to microelectronic devices and related memory devices, electronic systems, and methods comprising a stepped structure. Background Technology

[0004] A persistent goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize vertical memory array (also known as “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array comprises vertical memory strings extending through openings in one or more stacks (e.g., stacked structures) containing conductive structures and dielectric material layers. Each vertical memory string may contain at least one selection device coupled in series with a series combination of vertically stacked memory cells. Compared to structures with conventional planar (e.g., two-dimensional) transistor arrangements, this configuration allows for a greater number of switching devices (e.g., transistors) to be located in cells (i.e., the length and width of the active surface consumed) of the die region by constructing the array upwards (e.g., vertically) on the die.

[0005] A vertical memory array architecture generally comprises electrical connections between conductive structures of layers in a stack (e.g., a stacked structure) of memory devices and access lines (e.g., word lines), allowing memory cells in the vertical memory array to be uniquely selected for write, read, or erase operations. One method of forming such electrical connections involves forming a so-called "staircase" (or "step") structure at the edges (e.g., horizontal ends) of the layers in the stack of memory devices. The staircase structure includes individual "steps" defining contact areas of conductive structures, on which conductive contact structures can be positioned to provide electrical access to the conductive structures.

[0006] As memory density increases, the number of layers of conductive structures and dielectric materials, as well as associated memory cells, increases for each vertical memory string. Support pillar structures can extend through the stack structure to support it during various processing actions, such as during so-called "gate replacement" or "post-gate" processes. Support pillar structures can be filled with various materials (e.g., tungsten) that exhibit relatively greater tensile stress compared to other materials or structures in the stack structure. Therefore, by way of example only, the tensile stress in a support pillar structure including tungsten can lead to so-called "block bending," where the stack structure exhibits asymmetry, resulting in, for example, layer shrinkage, over-etching or incomplete etching of various regions of the stack structure, contact misalignment (e.g., between access lines and memory cell strings), and electrical short circuits between various conductive features of the stack structure. Summary of the Invention

[0007] In some embodiments, a microelectronic device includes: a stacked structure comprising alternating conductive and insulating structures arranged in layers, each layer individually including one of the conductive structures and one of the insulating structures; a first support pillar structure extending through the stacked structure in a first region of the microelectronic device, the first support pillar structure being electrically isolated from a source structure underlying the stacked structure; a second support pillar structure extending through the stacked structure in a second region of the microelectronic device, the second support pillar structure including a conductive material electrically in communication with the source structure; and a bridging structure extending between at least some adjacent first support pillar structures.

[0008] In other embodiments, a memory device includes: a stacked structure comprising layers, each layer including at least one conductive structure and at least one insulating structure vertically adjacent to the at least one conductive structure; a stepped structure having steps including at least some of the horizontal ends of the layers; a source structure resting on the stacked structure; a first support pillar structure extending vertically through the stepped structure to the source structure, at least one of the first support pillar structures being coupled to at least another of the first support pillar structures via a bridging structure within the source structure; and a second support pillar structure including a conductive material extending vertically through the stacked structure and in electrical communication with the source structure.

[0009] In another embodiment, a method of forming a microelectronic device structure includes: forming a conductive support pillar structure through a first region of a stacked structure comprising multiple alternating insulating structures and other insulating structures arranged in layers, the conductive support pillar structure contacting a bridging structure underlying a source structure of the stacked structure; forming a conductive support pillar structure through a second region of the stacked structure and in contact with the source structure; forming an opening through the stacked structure and in contact with the bridging structure in the first region and a landing pad in the second region; removing conductive material from the bridging structure and the conductive support pillar structure in the first region through the opening to form a support structure comprising a dielectric lining material, at least one support structure in the first region communicating with at least one other support structure through a recess; replacing the insulating structure with a conductive structure through the opening; and filling the opening in the first region and the second region with a dielectric material and another material, and filling the recess in the first region with the other material.

[0010] In another embodiment, an electronic system includes an input device, an output device, a processor device operatively coupled to the input and output devices, and a memory device operatively coupled to the processor device and including at least one microelectronic device structure. The at least one microelectronic device structure includes: a memory cell string extending through a stacked structure comprising alternating layers of insulating and conductive structures; a first support pillar structure located within a first region of the stacked structure, extending vertically through the stacked structure to a source structure underlying the stacked structure and electrically isolated from the source structure; and a second support pillar structure located within a second region of the stacked structure, extending vertically through the stacked structure and electrically connected to the source structure. Attached Figure Description

[0011] Figure 1 This is a simplified cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure;

[0012] Figure 2According to embodiments of this disclosure Figure 1 A simplified perspective view of the microelectronic device structure shown in the image;

[0013] Figures 3A to 3T This is a simplified cross-sectional view illustrating a method for forming a microelectronic device structure according to an embodiment of the present disclosure. Figure 3A , Figure 3B , Figure 3D , Figure 3E , Figure 3G to Figure 3R , Figure 3T ) and plan view ( Figure 3C , Figure 3F , Figure 3S );

[0014] Figure 4 This is a block diagram of an electronic system according to embodiments of the present disclosure; and

[0015] Figure 5 It is a processor-based system according to embodiments of the present disclosure. Detailed Implementation

[0016] The illustrations contained herein are not intended to be actual views of any particular system, microelectronic structure, microelectronic device, or its integrated circuit, but are merely idealized representations used to describe the embodiments described herein. Elements and features shared between the figures may retain the same numerical designations, but for ease of the following description, the reference numerals begin with the number of the figure on which the element is introduced or most fully described.

[0017] The following description provides specific details, such as material types, material thicknesses, and processing conditions, to provide a thorough description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the descriptions provided herein do not constitute a complete process flow for manufacturing microelectronic devices (e.g., semiconductor devices, memory devices, such as NAND flash memory devices), devices, or electronic systems, or include complete microelectronic devices, devices, or electronic systems comprising self-aligned contact structures having a relatively large lateral dimension (e.g., area, cross-sectional area) relative to the vertical memory strings or pillars associated with the contact structure. The structures described below do not form complete microelectronic devices, devices, or electronic systems. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form complete microelectronic devices, devices, or electronic systems from structures can be performed using conventional techniques.

[0018] The materials described herein can be formed using conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials can be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by those skilled in the art. Unless the context otherwise indicates, material removal can be achieved by any suitable technique including but not limited to etching, planarization (e.g., chemical-mechanical planarization), or other known methods.

[0019] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” refer to the principal plane of a substrate (e.g., substrate material, substrate structure, substrate configuration, etc.) on which one or more structures and / or features are formed and are not necessarily defined by the Earth’s gravitational field. A “lateral” or “horizontal” direction is a direction generally parallel to the principal plane of the substrate, while a “longitudinal” or “vertical” direction is a direction generally perpendicular to the principal plane of the substrate. The principal plane of the substrate is defined by the surface of the substrate, which has a relatively large area compared to the other surfaces of the substrate.

[0020] As used herein, the term "generally" in reference to a given parameter, characteristic, or condition means and includes the degree to which a given parameter, characteristic, or condition is satisfied with a deviation (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the particular parameter, characteristic, or condition that is generally satisfied, the parameter, characteristic, or condition may be satisfied with at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0021] As used herein, the term "about" or "approximately" when referring to a value for a particular parameter includes that value, and those skilled in the art will understand that deviations from that value are within acceptable tolerances for the particular parameter. For example, "about" or "approximately" when referring to a reference value may include additional values ​​that are in the range of 90.0% to 110.0% of the value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0022] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” and “right” may be used for descriptive purposes to illustrate the relationship of one element or feature to another as depicted in the diagrams. Unless otherwise stated, spatial relative terms are intended to cover different orientations of material in addition to those depicted in the diagrams. For example, if the material in the diagram is inverted, an element described as “below,” “under,” “below,” or “bottom” of another element or feature will be oriented “above” or “top” of said other element or feature. Thus, the term “below” may cover both above and below orientations depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.), and the spatial relative descriptors used herein will be interpreted accordingly.

[0023] As used herein, features described as “adjacent” to each other (e.g., region, material, structure, device) mean and include features of the disclosed identity (or multiple identities) that are most closely (e.g., closest to) positioned with each other. Additional features (e.g., additional region, additional material, additional structure, additional device) of the disclosed identity (or multiple identities) that do not match “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identity other than the identity associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other mean and include features of the disclosed identity (or multiple identities) that are most closely (e.g., closest to) positioned with each other vertically. Furthermore, features described as “horizontally adjacent” to each other mean and include features of the disclosed identity (or multiple identities) that are most closely (e.g., closest to) positioned with each other horizontally.

[0024] As used herein, the term "memory device" means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, and by way of example only, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also microelectronic devices that include application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), combinational logic and memory, and graphics processing units (GPUs) incorporating memory.

[0025] According to embodiments described herein, a microelectronic device includes a stacked structure comprising alternating conductive and insulating structures arranged in layers, each layer including both conductive and insulating structures. A string of memory cells may extend through the stacked structure. A first support pillar structure extends vertically through the stacked structure in a first region, and a second support pillar structure extends vertically through the stacked structure in a second region. The first support pillar structure may be connected to a bridging structure underlying a source structure within the stacked structure and is electrically isolated from the source structure by a dielectric liner material. The bridging structure may couple at least one first support pillar structure to at least another support pillar structure. The bridging structure may include a dielectric material and, in some embodiments, include at least another material (e.g., polysilicon). A trench structure may be horizontally located between at least one first support pillar structure and at least another support pillar structure. The second support pillar structure may include a conductive material electrically connected to the source structure and to the underlying circuitry (e.g., conductive wiring structures, CMOS structures). Therefore, the second support pillar structure may include a different material composition than the first support pillar structure. Because the first support pillar structure does not include the conductive material of the second support pillar structure, the first support pillar structure may not exhibit misaligned tensile stresses that cause bending of the stacked structure and / or various features of the stacked structure or microelectronic device. In some embodiments, the first support pillar structure is located in a stepped region of the microelectronic device, and the second support pillar structure is located outside the stepped region, for example, in a region between adjacent stepped regions.

[0026] Figure 1 This is a simplified cross-sectional perspective view of a microelectronic device (e.g., a semiconductor device, a memory device (e.g., a vertical memory device), such as a 3D NAND flash memory device) according to embodiments of the present disclosure. The microelectronic device 100 includes a microelectronic device structure 130 comprising a stacked structure 125 and a stepped structure 120, the stepped structure defining contact areas for connecting access lines 106 to a conductive layer 105 (e.g., a conductive layer, conductive plate, etc.). The microelectronic device 100 may include vertical strings 101 of memory cells 103 coupled in series with each other. The vertical string 101 may extend vertically (e.g., in the Z direction) and be orthogonal to the conductive line and conductive layer 105, such as data line 102, source layer 104, conductive layer 105, access line 106, first select gate 108 (e.g., upper select gate, drain select gate (SGD)), select line 109, and second select gate 110 (e.g., lower select gate, source select gate (SGS)).

[0027] Vertical conductive contacts 111 can electrically couple components to each other, as shown. For example, select line 109 can be electrically coupled to first select gate 108, and access line 106 can be electrically coupled to conductive layer 105. The microelectronic device 100 may also include a control unit 112 positioned below the memory array, which may include at least one of a string driver circuitry, a transmission gate, a circuitry for select gates, a circuitry for selecting conductive lines (e.g., data line 102, access line 106, etc.), a circuitry for amplifying signals, and a circuitry for sensing signals. Control unit 112 may be electrically coupled to, for example, data line 102, source layer 104, access line 106, first select gate 108, and second select gate 110. In some embodiments, control unit 112 includes complementary metal-oxide-semiconductor (CMOS) circuitry. In such embodiments, control unit 112 may be characterized as having an “array-controlled CMOS” (“CuA”) configuration.

[0028] The first selection gate 108 may extend horizontally in a first direction (e.g., the X direction) and may be coupled to a corresponding first group of vertical strings 101 of the memory cell 103 at a first end (e.g., the upper end). The second selection gate 110 may be formed in a generally flat configuration and may be coupled to the vertical string 101 at a second opposite end (e.g., the lower end) of the vertical string 101 of the memory cell 103.

[0029] Data lines 102 (e.g., bit lines) may extend horizontally in a second direction (e.g., in the Y direction) at an angle (e.g., perpendicular) to a first direction in which the first select gate 108 extends. Data lines 102 may be coupled to a corresponding second group of vertical strings 101 at a first end (e.g., upper end). The first group of vertical strings 101 coupled to the corresponding first select gate 108 may share a specific vertical string 101 with the second group of vertical strings 101 coupled to the corresponding data lines 102. Therefore, a specific vertical string 101 may be selected at the intersection of a specific first select gate 108 and a specific data line 102.

[0030] Conductive layers 105 (e.g., word lines) may extend in a corresponding horizontal plane. The conductive layers 105 may be stacked vertically such that each conductive layer 105 is coupled to all vertical strings 101 of memory cells 103, and the vertical strings 101 of memory cells 103 extend vertically through the stack of conductive layers 105. The conductive layers 105 may be coupled to or may form control gates of the memory cells 103. Each conductive layer 105 may be coupled to one memory cell 103 in a specific vertical string 101 of the memory cells 103.

[0031] The first select gate 108 and the second select gate 110 can be used to select a specific vertical string 101 of memory cells 103 between a specific data line 102 and the source layer 104. Thus, a specific memory cell 103 can be selected and electrically coupled to the data line 102 by operating (e.g., by selecting) the appropriate first select gate 108, second select gate 110 and conductive layer 105 coupled to the specific memory cell 103.

[0032] The stepped structure 120 can be configured to provide an electrical connection between the access line 106 and the conductive layer 105 via vertical conductive contacts 111. In other words, a specific level of the conductive layer 105 can be selected via the access line 106 electrically connected to a corresponding vertical conductive contact 111 electrically connected to the same specific conductive layer 105.

[0033] Support pillar structures 136 may extend vertically (e.g., in the Z direction) through the stepped structure 120 to reach the source layer 104. As will be described herein, support pillar structures 136 may serve as support structures for forming the conductive layer 105 of the stepped structure 120 using a so-called “replacement gate” or “post-gate” processing action. At least some of the support pillar structures 136 may include horizontally extending bridging structures therebetween, which may facilitate the formation of support pillar structures 136 coupled to each other via the bridging structures. At least some of the other support pillar structures may not be coupled to the bridging structures and may contain a different material composition than the support pillar structures coupled to each other via the bridging structures, which extend horizontally between the support pillar structures. In some embodiments, the support pillar structures 136 coupled via the bridging structures are positioned within the stacked structure 125.

[0034] Figure 2 This is a simplified perspective view of a microelectronic device structure 200 according to an embodiment of the present disclosure. The microelectronic device structure 200 may be used, for example, as a prior reference. Figure 1 The microelectronic device structure 130 in the described microelectronic device 100. For example... Figure 2 As shown, the microelectronic device structure 200 may include one or more stepped structures 210 (e.g., stepped structure 120). Figure 1 The steps 211 of the stepped structure 210 of the microelectronic device structure 200 can serve as a component for the stacked structure 205 (see, for example, see...). Figure 1 The microelectronic device 100 described in the microelectronic device structure 130 of the stacked structure 125) consists of different layers of conductive material (e.g., conductive layer 105). Figure 1 The contact area of ​​the conductive structure (e.g., conductive layer 105) and the horizontal end of the insulating structure located between adjacent conductive structures may be positioned at the conductive structure (e.g., conductive layer 105).

[0035] The stepped structure 210 may include, for example, a first stepped structure 201a, a second stepped structure 202a, a third stepped structure 203a, and a fourth stepped structure 204a, which are located at different heights (e.g., vertically) within the stacked structure 205. Additionally, the stepped structure 210 may further include another first stepped structure 201b opposite to the first stepped structure 201a and at the same height, another second stepped structure 202b opposite to the second stepped structure 202b and at the same height, another third stepped structure 203b opposite to the third stepped structure 203b and at the same height, and another fourth stepped structure 204b opposite to the fourth stepped structure 204b and at the same height. Each of the first stepped structure 201a, the second stepped structure 202a, the third stepped structure 203a, and the fourth stepped structure 204a can individually exhibit a generally negative slope; and each of the other first stepped structure 201b, the other second stepped structure 202b, the other third stepped structure 203b, and the other fourth stepped structure 204b can individually exhibit a generally positive slope. For example... Figure 2 As shown, a first stepped structure 201a and another first stepped structure 201b can form a first stadium structure 201, wherein a valley 225 exists between the first stepped structure 201a and the other first stepped structure 201b; a second stepped structure 202a and another second stepped structure 202b can form a second stadium structure 202, wherein a valley 225 exists between the second stepped structure 202a and the other second stepped structure 202b; a third stepped structure 203a and another third stepped structure 203b can form a third stadium structure 203, wherein a valley 225 exists between the third stepped structure 203a and the other third stepped structure 203b; and a fourth stepped structure 204a and another fourth stepped structure 204b can form a fourth stadium structure 204, wherein a valley 225 exists between the fourth stepped structure 204a and the other fourth stepped structure 204b.

[0036] As described above, conductive contacts (e.g., vertical conductive contact 111) Figure 1 The conductive portion of each layer (e.g., each step 211) of the stacked structure 205 of the microelectronic device structure 200 can be formed.

[0037] The area between adjacent stadium structures (e.g., first stadium structure 201, second stadium structure 202, third stadium structure 203, and fourth stadium structure 204) may include a raised area 240, which may also be referred to as a so-called stair-like or stepped “top area.” As will be described herein, a supporting column structure (e.g., supporting column structure 136) Figure 1The support pillar structure can be located within the raised region 240, and other support pillar structures can be located within the stepped structure (e.g., a first stepped structure 201a, another first stepped structure 201b, a second stepped structure 202a, another second stepped structure 202b, a third stepped structure 203a, another third stepped structure 203b, a fourth stepped structure 204a, and another fourth stepped structure 204b). In some embodiments, the support pillar structure in the stepped structure can be coupled to at least one other support pillar structure via a bridging structure. The support pillar structure within the raised region 240 may not be coupled to at least one other support pillar structure. In some embodiments, the support pillar structure is located in the raised region 240 (and is not coupled to the bridging structure) and is electrically coupled to a microelectronic device (e.g., a control unit 112). Figure 1 The underlying source structure and underlying circuit system.

[0038] As will be understood by those skilled in the art, although the microelectronic device structure 130 ( Figure 1 ) and microelectronic device structure 200 ( Figure 2 The microelectronic device structures 130 and 200 have been described as having a specific structure, but this disclosure is not limited thereto, and the microelectronic device structures 130 and 200 may have different geometric configurations and orientations.

[0039] Figures 3A to 3S This is a partial cross-sectional view illustrating a method of forming a microelectronic device structure 300 according to an embodiment of the present disclosure. The microelectronic device structure 300 may include, for example, previously referenced... Figure 1 and Figure 2 The microelectronic device structures 130 and 200 are described. Those skilled in the art will understand that... Figures 3A to 3S Only a portion of the microelectronic device structure 300 is depicted. Therefore, other regions of the microelectronic device structure 300 can be modified as needed. Figures 3A to 3S The processes illustrated are similar to or different from those in the previous reference (e.g., to form a previous reference). Figure 1 and Figure 2 The microelectronic device 100 or microelectronic device structure 130, 200 described herein.

[0040] Figure 3A and Figure 3B This is a simplified cross-sectional view of the microelectronic device structure 300. Figure 3C This is a simplified plan view of the microelectronic device structure 300. Figure 3A Through Figure 3C The cross-sectional view of the microelectronic device structure 300 is taken by section line AA, and Figure 3B Through Figure 3C The cross-sectional view of the microelectronic device structure 300 is taken by the section line BB.

[0041] refer to Figure 3A and Figure 3B The microelectronic device structure 300 may include a stacked structure 301 comprising a vertically alternating (e.g., in the Z direction) sequence of insulating structures 302 and other insulating structures 304 arranged in layers 306. The insulating structures 302 of the stacked structure 301 may also be referred to herein as “insulating material,” and the other insulating structures 304 of the stacked structure 301 may also be referred to herein as “other insulating material.” Each of the layers 306 of the stacked structure 301 may include at least one (1) of the insulating structures 302 vertically adjacent to at least one of the other insulating structures 304. The stacked structure 301 may include a desired number of layers 306. For example, the stack structure 301 may include a conductive stack structure 301 and an insulating structure 302 comprising ten (10) layers 306, twenty-five (25) layers 306, fifty (50) layers 306, one hundred (100) layers 306, one hundred and fifty (150) layers 306, or two hundred (200) layers 306.

[0042] The multi-layered insulating structure 302 may be formed of and comprise at least one dielectric material, such as oxide materials (e.g., silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borosilicate glass, fluorosilicate glass, titanium dioxide (TiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), tantalum oxide (TaO2), magnesium oxide (MgO), and aluminum oxide (Al2O3)). In some embodiments, the insulating structure 302 is formed of and comprises silicon dioxide.

[0043] Other insulating structures 304 in the multilayer may be formed of and comprise insulating materials different from insulating structure 302 and exhibiting etch selectivity with respect to it. In some embodiments, other insulating structures 302 are formed of and comprise materials such as nitride materials (e.g., silicon nitride (Si3N4)) or oxide nitride materials (e.g., silicon oxynitride). In some embodiments, other insulating structures 304 comprise silicon nitride.

[0044] A stacked structure 301 may be formed above a source structure 310 (e.g., a source plate). The source structure 310 may include, for example, a first source material 312 above (e.g., on top of) a second source material 314. The first source material 312 may be formed of and include a semiconductor material doped with either a P-type conductive material (e.g., polysilicon doped with at least one P-type dopant (e.g., boron ions)) or an N-type conductive material (e.g., polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorus ions, antimony ions)). In some embodiments, the first source material 312 comprises polysilicon. The second source material 314 may include, for example, tungsten, such as tungsten silicide (WSi). x ).

[0045] although Figure 3A and Figure 3B The present disclosure is not limited thereto, though it has been described and illustrated as including a stacked structure 301 with a particular configuration. In some embodiments, the stacked structure 301 includes a first stacked structure directly above (e.g., on top of) the source structure 310 on the source electrode and a second stacked structure above the first stacked structure. The second stacked structure may be separable from the first stacked structure by at least one dielectric material. In some such embodiments, the stacked structure 301 may be referred to as a double stacked structure.

[0046] Bridging structure 316 ( Figure 3A ) and landing pad 318 ( Figure 3B The bridging structure 316 may be located within the source structure 310. As will be described herein, each of the bridging structures 316 may be used to facilitate landing of a trench (e.g., a replacement gate trench) between at least two pillar structures (e.g., support pillar structure 328) and at least two pillar structures, and a landing pad 318 may be used to facilitate trench landing. The bridging structure 316 may have a larger dimension than the landing pad 318 (e.g., a larger horizontal dimension (in the X direction)). Joint Reference Figures 3A to 3C The bridging structure 316 may be positioned in a first region 320 of the microelectronic device structure 300, and the landing pad 318 may be positioned in a second region 322 of the microelectronic device structure 300. In some embodiments, the first region 320 includes a stepped structure (e.g., stepped structure 120). Figure 1 ), stepped structure 210 ( Figure 2 The second region 322 includes the region outside the stepped structure (e.g., the raised region 240). Figure 2 )).

[0047] Dielectric material 326 may be overlaid on stacked structure 301 and may be formed of and contain electrical insulating material, such as SiO2. xPhosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate-phosphosilicate glass (BPSG), fluorosilicate glass (FSG), AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x At least one dielectric nitride material (e.g., SiN) y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO2). x C z N y One or more of amorphous carbon. In some embodiments, dielectric material 326 comprises silicon dioxide.

[0048] refer to Figure 3C The bridging structure 316 and the landing pad 318 may be coupled to each other as a line 324 extending in, for example, the Y direction. The bridging structure 316, the landing pad 318, and the line 324 may be formed of and contain a conductive material. In some embodiments, the bridging structure 316, the landing pad 318, and the line 324 comprise the same material composition. In some embodiments, the bridging structure 316, the landing pad 318, and the line 324 comprise tungsten.

[0049] refer to Figure 3D to Figure 3F The support column structure 328 can be formed through the dielectric material 326 and the stacked structure 301. Figure 3D Drawing through Figure 3F The cross-section of the microelectronic device structure 300 is taken by the cross-section line DD, and Figure 3E Drawing through Figure 3F The cross-section of the microelectronic device structure 300 is taken by the cross-section line EE. Figure 3F Through Figure 3D The cross-section line DD and Figure 3E A planar cross-sectional view of the microelectronic device structure, taken by section line EE. (Reference) Figure 3D and Figure 3E The support pillar structure 328 may include a lining material (dielectric lining material) 330 and a conductive material 332 horizontally adjacent to the lining material 330. Since the support pillar structure 328 includes the conductive material 332, the support pillar structure 328 may be referred to herein as a "conductive support pillar structure".

[0050] refer to Figure 3D and Figure 3FThe support column structure 328 in the first region 320 may contact the bridging structure 316 (e.g., land on the bridging structure, land within the bridging structure, terminate on the bridging structure, or terminate within the bridging structure). In some embodiments, the bridging structure 316 may extend horizontally between horizontally adjacent support column structures 328. In other words, the bridging structure 316 may couple two support column structures 328 to each other. However, this disclosure is not limited thereto, and in other embodiments, the bridging structure 316 may couple more than two (e.g., three, four, five, or six) support column structures 328 in the first region 320 to each other.

[0051] See Figure 3E and Figure 3F The support pillar structure 328 in the second region 322 may contact, for example, the source structure 310 of the second source material 314 (e.g., landing on, landing within, terminating on, or terminating within the source structure). In some such embodiments, the support pillar structure 328 in the second region 322 may extend through the first source material 312 and may be electrically connected to the source structure 310 (e.g., the second source material 314). The support pillar structure 328 in the second region 322 may be positioned between adjacent (e.g., horizontally adjacent) landing pads 318 and may not contact the landing pads 318. Thus, in some embodiments, the support pillar structure 328 in the first region 320 may contact the bridging structure 316, while the support pillar structure 328 in the second region 322 contacts the source structure 310 (e.g., the second source material 314).

[0052] The lining material 330 may be formed of and comprise a dielectric material, such as one or more of the materials described above with reference to dielectric material 326. In some embodiments, the lining material 330 comprises an oxide material, such as silicon dioxide. The conductive material 332 may be formed of and comprise, for example, tungsten. In some embodiments, the conductive material 332 comprises the same material composition as the bridging structure 316 and the landing pad 318.

[0053] The support pillar structure 328 can be formed, for example, by forming an opening through the dielectric material 326 and the stacked structure 301. By means of a non-limiting example, the opening can be formed by dry etching (e.g., reactive ion etching (RIE)). In some embodiments, the opening is formed by sequentially exposing the insulating structure 302 and other insulating structures 304 of the stacked structure 301 to various etchants. For example, insulating structure 302 can be removed by exposure to one or more hydrofluorocarbon gases, such as one or more of octafluorocyclobutane (C4F8), hexafluoro-1,3-butane (C4F6), carbon tetrafluoride (CF4), difluoromethane (CH2F2), fluoromethane (CH3F), and trifluoromethane (CHF3), as well as one or more of sulfur hexafluoride (SF6) and nitrogen trifluoride (NF3); and other insulating structures 304 can be removed by exposure to one or more of tetrafluoropropylene (C3H2F4), fluoropropane (C3H5F), hydrogen (H2), fluorine (F2), carbon tetrafluoride (CF4), fluoromethane (CH3F), or another material. However, this disclosure is not limited thereto, and openings can be formed by other methods and / or with different etching gases.

[0054] After the opening is formed, a portion of the other insulating structure 304 may be removed to form a recess, which is then filled with a dielectric liner material 330 to form a laterally extending portion 331 of the dielectric liner material 330. In some embodiments, the other insulating structures 304 may be exposed to one or more etchants to selectively remove a portion of each of the other insulating structures 304 without substantially removing the insulating structure 302. By means of non-limiting examples, the other insulating structures 304 may be exposed to one or more of phosphoric acid, hydrochloric acid, sulfuric acid, hydrofluoric acid, nitric acid, ammonium fluoride, or another material. The liner material 330 may be formed after removing a portion of each of the other insulating structures 304.

[0055] After the support pillar structure 328 is formed, a dielectric material 334 may be formed over the microelectronic device structure 300. The dielectric material 334 may also be referred to as a "mask material" or "capping material." The dielectric material 334 may include one or more of the materials described above with reference to dielectric material 326. In some embodiments, the dielectric material 334 comprises silicon dioxide. In some embodiments, the dielectric material 334 comprises the same material composition as dielectric material 326.

[0056] Figure 3G The illustration shows the relationship with Figure 3D The same cross-sectional view, and Figure 3H The illustration shows the relationship with Figure 3E Same cross-sectional view. Reference Figure 3G and Figure 3HAn opening 336 (which may also be referred to herein as a “replacement gate trench opening”) may pass through the stack structure 301 and be formed between adjacent (e.g., horizontally adjacent) support pillar structures in the support pillar structure 328.

[0057] Opening 336 may extend through dielectric material 334, dielectric material 326, and stacked structure 301. In a first region 320, opening 336 may extend to bridging structure 316 (e.g., landing on, landing within, terminating on, or terminating within the bridging structure), and in a second region 322, opening 336 may extend to landing pad 318 (e.g., landing on, landing within, or terminating on, or terminating within the landing pad). Opening 336 may be formed as described above with reference to the opening for forming support column structure 328.

[0058] Figure 3I The illustration shows the relationship with Figure 3G A cross-sectional view of the same microelectronic device structure 300, and Figure 3J The illustration shows the relationship with Figure 3H A cross-sectional view of the same microelectronic device structure 300. (Reference) Figure 3I and Figure 3J The bridging structure 316 can be removed (e.g., excavated) through the opening 336. Figure 3G ), landing pad 318 ( Figure 3H ) and line 324 ( Figure 3F To form a recess 317 at a location corresponding to the bridging structure 316 and a recess 319 at a location corresponding to the landing pad 318. In some embodiments, the conductive material 332 of the support pillar structure 328 in the first region 320 may be removed without removing the conductive material 332 of the support pillar structure 328 in the second region 322. For example, since the conductive material 332 of the support pillar structure 328 in the first region 320 is electrically connected to the bridging structure 316 (e.g., since the bridging structure 316 spans horizontally adjacent support pillar structures 328 and physically contacts the conductive material 332 of such support pillar structures 328), the conductive material 332 of the support pillar structure 328 may be removed while the bridging structure 316 in the first region 320 is being removed. Since the conductive materials 332 of the support pillar structures 328 in the second region 322 are isolated from each other and do not include intermediate bridging structures 316, the conductive materials 332 of the support pillar structures 328 in the second region 322 do not need to be removed during the removal of the conductive materials 332 of the support pillar structures 328 in the first region 320. Therefore, the conductive materials 332 of the support pillar structures 328 in the second region 322 do not need to be exposed during the removal of the landing pad 318 in the second region 322.

[0059] The lining material 330 can remain in the position corresponding to the support pillar structure 328 in the first region 320 after the conductive material 332 is removed. Removing the conductive material 332 from the support pillar structure 328 in the first region 320 can form a support structure 329 including the lining material 330 (e.g., lining material 330 only).

[0060] This can be achieved, for example, by bridging structure 316 ( Figure 3G ), landing pad 318 ( Figure 3H ) and line 324 ( Figure 3F The bridging structure 316, landing pad 318, and line 324 are exposed to a wet etchant through opening 336 to remove them. The wet etchant may contain, for example, hydrofluoric acid, nitric acid, ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), a mixture of ammonium hydroxide and hydrogen peroxide, a mixture of nitric acid and hydrochloric acid (also known as aqua regia), hydrochloric acid, or another material.

[0061] Figure 3K The illustration shows the relationship with Figure 3I A cross-sectional view of the same microelectronic device structure 300, and Figure 3L The illustration shows the relationship with Figure 3J A cross-sectional view of the same microelectronic device structure 300. (Reference) Figure 3K and Figure 3L Other insulating structures 304 can be removed from the stacked structure 301. Figure 3I , Figure 3J In the first area 320 ( Figure 3F The lining material 330 of the support structure 329 can support the insulation structure 302 from collapsing during and after the removal of other insulation structures 304. Additionally, the lateral extension 331 of the lining material 330 can further support the insulation structure 302 from collapsing after the removal of other insulation structures 304. (See reference) Figure 3L Second area 322 ( Figure 3F The support column structure 328 in the structure may include lining material 330 and conductive material 332, which can support the insulation structure 302 from collapsing during and after the removal of other insulation structures 304.

[0062] Other insulating structures 304 can be removed by exposing them to the etching composition through opening 336. The etching composition may contain one or more of phosphoric acid, hydrochloric acid, sulfuric acid, hydrofluoric acid, nitric acid, ammonium fluoride, or another material. In some embodiments, the etching composition includes phosphoric acid. In some embodiments, the other insulating structure 304 includes silicon nitride.

[0063] Figure 3M The illustration shows the relationship with Figure 3K A cross-sectional view of the same microelectronic device structure 300, and Figure 3NThe illustration shows the relationship with Figure 3L A cross-sectional view of the same microelectronic device structure 300. (Reference) Figure 3M and Figure 3N Conductive structure 338 (e.g., word line, word line board) can be used with other insulating structure 304 ( Figure 3K , Figure 3L The positions corresponding to the locations of the insulating structures 302 are formed between adjacent (e.g., vertically adjacent) insulating structures 302 to form a stacked structure 340, the stacked structure comprising alternating layers 342 of insulating structures 302 and conductive structures 338. In some embodiments, at least one lower conductive structure 338 may serve as at least one lower selection gate (e.g., at least one source-side selection gate (SGS)) of the microelectronic device structure 300. Additionally, in some embodiments, the upper conductive structure 338 may serve as an upper selection gate (e.g., a drain-side selection gate (SGS)) of the microelectronic device structure 300.

[0064] The conductive structure 338 may be formed of and comprise a conductive material, such as at least one conductive material, such as tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys, metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), comprising titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO). x ), Ruthenium oxide (RuO) x Materials, alloys thereof, conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.), polycrystalline silicon, other materials exhibiting electrical conductivity, or combinations thereof. In some embodiments, conductive structure 338 includes tungsten.

[0065] In some embodiments, the conductive structure 338 may include one or more lining materials (e.g., conductive lining materials) surrounding the conductive structure 338, such as between the conductive structure 338 and the insulating structure 302. The lining material may include, for example, a seed material, and the conductive structure 338 may be formed from said seed material. The lining material may be formed from and include, for example, metals (e.g., titanium, tantalum), metal nitrides (e.g., tungsten nitride, titanium nitride, tantalum nitride), alumina, or another material. In some embodiments, the lining material includes titanium nitride. In some embodiments, the lining material further includes alumina. In some embodiments, the conductive structure 338 includes alumina immediately adjacent to the insulating structure 302, titanium nitride immediately adjacent to the alumina, and tungsten immediately adjacent to the titanium nitride. For clarity and ease of understanding, one or more lining materials are not mentioned. Figure 3M and Figure 3N As illustrated, but it should be understood that the lining material may be placed around the conductive structure 338.

[0066] Continue to refer to Figure 3M and Figure 3N During the formation of the conductive structure 338, conductive material 344 may be formed within the opening 336. The conductive material 344 may be formed simultaneously with the formation of the conductive structure 338. The conductive material 344 may include the same material composition as the conductive structure 338. For example, in some embodiments, the conductive material 344 includes alumina, titanium nitride, and tungsten. Additionally, the conductive material 344 may be formed within the recesses 317 and 319. Therefore, in the first region 320, the conductive material 344 may extend through the recess 317 from the first support structure 329 to the second support structure 329, and may further extend within the opening 336. Therefore, referring to... Figure 3M The conductive material 344 may be formed within the support structure 329 (e.g., on the sidewall). In the second region, the conductive material 344 may be formed only within the opening 336.

[0067] Figure 3O and Figure 3P The diagram shows the area from the first region 320 ( Figure 3F The sidewalls of the support structure 329 in the ) and the recesses 317 and 319 ( Figure 3M , Figure 3N ) and removing conductive material 344 from the sidewalls of the openings 336 in the first region 320 and the second region 322. Figure 3M , Figure 3N The microelectronic device structure 300 follows. Figure 3O The illustration shows the relationship with Figure 3M The same cross section is shown in the figure, and Figure 3P The illustration shows the relationship with Figure 3N The same cross-section is shown in the figure.

[0068] Removing the conductive material 344 allows for physical and electrical isolation of the conductive structures 338 from each other. In some embodiments, the conductive material 344 is removed by exposing it through the opening 336 to one or more wet etchants. Figure 3M , Figure 3N The wet etchant may contain one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, aqua regia, or hydrogen peroxide. However, this disclosure is not limited thereto, and other etchants may be used to remove conductive material 344.

[0069] refer to Figure 3Q to Figure 3S The groove structure 346 can be in the first region 320 and the second region 322 in relation to the opening 336 ( Figure 3O , Figure 3P The support column structure 348 is formed at the corresponding position in the first region 320 (e.g., only in the first region 320) and is positioned in relation to the support structure 329. Figure 3O It forms at the corresponding location. Figure 3S yes Figure 3Q and Figure 3R Top plan view of the microelectronic device structure 300. Figure 3Q Through Figure 3S The cross-sectional view of the microelectronic device structure 300 is taken by the cross-sectional line QQ, and Figure 3R Through Figure 3S The cross-sectional view of the microelectronic device structure 300 is taken by section line RR. For clarity and ease of understanding of the diagram and related descriptions, dashed lines are used. Figure 3S The diagram depicts some of the vertically lower components (e.g., features, structures, devices) of the microelectronic device structure 300, which are subordinate to the relatively vertically higher components, in order to provide a clearer understanding of aspects of the vertically lower components (e.g., location, geometric configuration).

[0070] The groove structure 346 may include a lining material 350 and another material 352 laterally adjacent to the lining material 350. The support column structure 348 may include a lining material 330 and another material 352 horizontally adjacent to the lining material 330. In some embodiments, the lining material 350 and the lining material 330 are continuous. In other words, the lining material 330 of the support column structure 348 in the first region 320 is continuous with the lining material 350 of the support column structure 348 in the first region 320.

[0071] The height of the groove structure 346 (in the vertical direction (e.g., in the Z direction)) may be greater than the height of the support column structure 348 but less than the height of the support column structure 328. For example, the groove structure 346 may extend through the dielectric material 334, while the support column structure 348 does not extend through the dielectric material 334. In the first region 320, the groove structure 346 may be coupled to the support column structure 348. In some such embodiments, another material 352 may be continuous between the groove structure 346 and the support column structure 348. In some embodiments, a bridging structure 354 comprising a lining material 350 and another material 352 may couple the groove structure 346 to an adjacent support column structure 348 in the first region 320. In some embodiments, two adjacent support column structures 348 in the first region 320 are coupled to each other via the bridging structure 354, with the groove 346 extending between the adjacent support column structures 348.

[0072] The support pillar structure 328 in the second region 322 is electrically connected to the source structure 310 via a conductive material 332. By comparison, the support pillar structure 348 in the first region 320 is electrically isolated from the source structure 310 via lining materials 330 and 350. The support pillar structure 328 may (e.g., in the Z direction) have a greater vertical height than the support pillar structure 348. For example, the support pillar structure 328 may extend further into the source structure 310 than the support pillar structure 348 in the first region 320.

[0073] Lining material 350 may comprise one or more of the materials described above with reference to lining material 330. In some embodiments, lining material 350 comprises silicon dioxide. In some embodiments, lining material 350 comprises the same material composition as lining material 330.

[0074] Another material 352 may include one or more materials exhibiting tensile stress lower than that of tungsten. In some embodiments, the other material 352 includes polycrystalline silicon.

[0075] refer to Figure 3S After forming the groove structure 346 and the support pillar structure 348, the conductive contact pillar 305 may be formed to extend vertically through at least a portion of the microelectronic device structure 300 within the first region 320. The conductive contact pillar 305 may be electrically connected to individual conductive structures 338 of the stacked structure 301.

[0076] As referenced above Figures 3A to 3S As discussed, the first region 320 may include a stepped structure. Figure 3T This is a simplified cross-sectional view of a microelectronic device structure 300 including a stepped structure 380 according to an embodiment of the present disclosure. The microelectronic device structure 300 may include steps 311 at the horizontal ends of layers 342 of insulating structure 302 and conductive structure 338. Support pillar structure 348 may extend through a dielectric material 382 overlying the steps 311 of the stepped structure 380 and through the stacked structure 340. The dielectric material 382 may include one or more of the materials described above with reference to dielectric material 326. In some embodiments, the dielectric material 382 includes silicon dioxide. It should be understood that... Figure 3T The second region of the microelectronic device structure 300 can be substantially similar to the reference above. Figure 3R and Figure 3S The second region 322 is described and illustrated.

[0077] Compared to conventional microelectronic devices formed from support pillars including tungsten or other high tensile stress materials, forming a support pillar structure 348 in the first region 320 to include a lining material 330 and another material 352 can facilitate a reduction in pillar bending and block bending of the microelectronic device structure 300. Furthermore, since the support pillar structure 328 in the second region 322 contains conductive material 332 instead of the other material 352, the support pillar structure 328 can be electrically coupled to one or more regions, for example, within or below the source structure 310, such as electrically coupled to a control unit (e.g., control unit 112) that can be characterized as having an "array-controlled CMOS" ("CuA") configuration. Figure 1 For example, the support pillar structure 328 may be electrically coupled to a conductive interconnect structure, which in turn may be electrically coupled to a conductive wiring structure. The conductive wiring structure may then be electrically coupled to additional structures and / or devices (e.g., back-end line (BEOL) devices; control logic devices, such as CMOS devices or string driver circuit systems) vertically subordinate to the microelectronic device structure 300.

[0078] Therefore, the support pillar structure 348 in the first region 320 can be formed to include a different material composition (e.g., another material 352) than the support pillar structure 328 in the second region 322 (e.g., conductive material 332), without the need for separate mask materials and separate processes to form the support pillar structure 348 in the first region 320 and the support pillar structure 328 in the second region 322. Specifically, the support pillar structure 348 and the support pillar structure 328 can be formed simultaneously, as described above. Furthermore, forming the support pillar structure 348 by forming the support pillar structure 328 and grounding it onto the bridging structure 316 improves the reliability of the microelectronic device structure 300 and substantially prevents over-etching of the source structure 310 within the first region 320 and unwanted etching of the underlying circuitry and wiring material. Forming the support pillar structure 348 to include a material with relatively lower tensile stress than the conductive material 332 facilitates improved fabrication of the microelectronic device structure 300. By comparison, conventional microelectronic device structures incorporating high-tensile-stress materials in their support pillar structures may exhibit layer shrinkage and block bending. However, during the fabrication of microelectronic device structures, layer shrinkage and block bending can lead to non-planar surfaces. During subsequent processing actions (e.g., during the formation of contacts between access lines and memory strings extending through the stacked structure), unwanted materials (e.g., polysilicon) may be deposited on these non-planar surfaces. Such unwanted deposition of materials can cause electrical short circuits between conductive features or other malfunctions in the microelectronic device structure.

[0079] In some embodiments, forming the support pillar structure 348 with a different material 352 can facilitate improved electrical characteristics of the microelectronic device structure 300. By comparison, conventional microelectronic device structures containing tungsten in the support pillars may undesirably capacitively couple to the word lines (e.g., conductive structures) of the microelectronic device and cause capacitive breakdown of the microelectronic device structure. Therefore, forming the support pillar structure 348 with a different material 352 can facilitate an increase in the permissible voltage window for operation of the microelectronic device structure 300.

[0080] In some embodiments, bridging structure 316 ( Figure 3A This can facilitate improved processing of the microelectronic device structure 300. In some embodiments, the bridging structure 316 may be positioned in a stepped structure (e.g., stepped structure 120). Figure 1 ), stepped structure 210 ( Figure 2 ), stepped structure 380 ( Figure 3T In this context, it can be filled with oxide materials (e.g., dielectric material 382). Figure 3T The oxide filler material is etched at a rate comparable to that of the stacked structure 301 during the formation of the support pillar structure 328. Figure 3D , Figure 3E The material in region 322 is etched at a faster rate. Therefore, compared to the second region 322 ( Figure 3F A supporting column structure 328 is formed in the first region 320, which may contain a stepped structure. Figure 3F ) forms a supporting column structure 328 ( Figure 3D Over-etching may easily occur. During the formation of the support pillar structure 328 in the first region 320, the bridging structure 316 can act as an etch termination layer.

[0081] Therefore, in at least some embodiments, a microelectronic device includes: a stacked structure comprising alternating conductive and insulating structures arranged in layers, each layer individually including one of the conductive structures and one of the insulating structures; a first support pillar structure extending through the stacked structure in a first region of the microelectronic device, the first support pillar structure being electrically isolated from a source structure underlying the stacked structure; a second support pillar structure extending through the stacked structure in a second region of the microelectronic device, the second support pillar structure including a conductive material electrically connected to the source structure; and a bridging structure extending between at least some adjacent first support pillar structures.

[0082] Therefore, in at least some embodiments, a memory device includes: a stacked structure comprising layers, each layer including at least one conductive structure and at least one insulating structure vertically adjacent to the at least one conductive structure; a stepped structure having steps including at least some of the horizontal ends of the layers; a source structure resting on the stacked structure; a first support pillar structure extending vertically through the stepped structure to the source structure, at least one of the first support pillar structures being coupled to at least another of the first support pillar structures via a bridging structure within the source structure; and a second support pillar structure including a conductive material extending vertically through the stacked structure and in electrical communication with the source structure.

[0083] Therefore, in some embodiments, a method of forming a microelectronic device structure includes: forming a conductive support pillar structure through a first region of a stacked structure comprising multiple alternating insulating structures and other insulating structures arranged in layers, the conductive support pillar structure contacting a bridging structure underlying a source structure of the stacked structure; forming a conductive support pillar structure through a second region of the stacked structure and in contact with the source structure; forming an opening through the stacked structure and in contact with the bridging structure in the first region and a landing pad in the second region; removing conductive material from the bridging structure, the landing pad, and the conductive support pillar structure in the first region through the opening to form a support structure comprising a dielectric lining material, at least one support structure in the first region communicating with at least one other support structure through a recess; replacing the insulating structure with a conductive structure through the opening; and filling the opening in the first region and the second region with a dielectric material and another material, and filling the recess in the first region with the other material.

[0084] Microelectronic devices including support pillar structures 328 and 348, comprising microelectronic devices (e.g., microelectronic device 100) and microelectronic device structures (e.g., microelectronic device structures 130, 200, 300), can be used in embodiments of the electronic systems disclosed herein. For example, Figure 4This is a block diagram of an electronic system 403 according to an embodiment of the present disclosure. The electronic system 403 may include, for example, a computer or computer hardware component, a server or other network-connected hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., an iPad® or Surface® tablet computer), an e-book, a navigation device, etc. The electronic system 403 includes at least one memory device 505. The memory device 405 may include, for example, a microelectronic device structure previously described herein (e.g., microelectronic device structures 130, 200, 300) including support pillar structures 328 and 348, or previously referenced... Figure 1 , Figure 2 as well as Figures 3A to 3T Embodiments of the described microelectronic device (e.g., microelectronic device 100).

[0085] Electronic system 403 may further include at least one electronic signal processor device 407 (generally referred to as a “microprocessor”). Electronic signal processor device 407 may optionally include microelectronic devices or microelectronic device structures previously described herein (e.g., previously referenced...). Figure 1 , Figure 2 as well as Figures 3A to 3T The embodiments described are of the microelectronic device 100 or one or more of the microelectronic device structures 130, 200, 300. The electronic system 403 may further include one or more input devices 409 for inputting information into the electronic system 403 by a user, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 403 may further include one or more output devices 411 for outputting information (e.g., visual or audio output) to the user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 409 and output device 411 may include a single touchscreen device that can be used both to input information into the electronic system 403 and to output visual information to the user. The input device 409 and output device 411 may be electrically connected to one or more of the memory device 405 and the electronic signal processor device 407.

[0086] refer to Figure 5The present invention describes a processor-based system 500. The processor-based system 500 may include various microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 100 or microelectronic device structures 130, 200, 300). The processor-based system 500 may be any of a variety of types, such as a computer, pager, cellular phone, personal assistant, control circuitry, or other electronic device. The processor-based system 500 may include one or more processors 502, such as microprocessors, to control system functions and request processing within the processor-based system 500. The processor 502 and other sub-components of the processor-based system 500 may include microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 100 or microelectronic device structures 130, 200, 300).

[0087] The processor-based system 500 may include a power supply 504 operatively connected to the processor 502. For example, if the processor-based system 500 is a portable system, the power supply 504 may include one or more of a fuel cell, an energy purification device, a permanent battery, a replaceable battery, and a rechargeable battery. For example, the power supply 504 may also include an AC adapter; thus, the processor-based system 500 can be plugged into a wall outlet. For example, the power supply 504 may also include a DC adapter, allowing the processor-based system 500 to be plugged into a vehicle cigarette lighter or a vehicle power port.

[0088] Various other devices may be coupled to processor 502 depending on the functions performed by processor-based system 500. For example, user interface 506 may be coupled to processor 502. User interface 506 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. Display 508 may also be coupled to processor 502. Display 508 may include LCD displays, SED displays, CRT displays, DLP displays, plasma displays, OLED displays, LED displays, 3D projections, audio displays, or combinations thereof. Furthermore, RF subsystem / baseband processor 510 may also be coupled to processor 502. RF subsystem / baseband processor 510 may include antennas coupled to RF receivers and RF transmitters (not shown). Communication port 512 or more may also be coupled to processor 502. For example, communication port 512 may be adapted to couple to one or more peripheral devices 514, such as modems, printers, computers, scanners or cameras, or to a network, such as a local area network, a remote local area network, an intranet or the Internet.

[0089] Processor 502 can control processor-based system 500 by implementing software programs stored in memory. For example, the software programs may include operating systems, database software, graphics software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 502 to store and facilitate the execution of various programs. For example, processor 502 may be coupled to system memory, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. System memory 516 may include volatile memory, non-volatile memory, or combinations thereof. System memory 516 is typically large enough to dynamically store loaded applications and data. In some embodiments, system memory 516 may include semiconductor devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 100 and microelectronic device structures 130, 200, 300), or combinations thereof.

[0090] Processor 502 may also be coupled to non-volatile memory 518, which does not imply that system memory 516 is necessarily volatile. Non-volatile memory 518 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with system memory. The size of non-volatile memory 518 is typically chosen to be sufficient to store only the necessary operating system, applications, and fixed data. Additionally, non-volatile memory 518 may include, for example, large-capacity memory such as disk drive memory, such as a hybrid drive containing resistive memory, or other types of non-volatile solid-state memory. Non-volatile memory 518 may include microelectronic devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 100 and microelectronic device structures 130, 200, 300), or combinations thereof.

[0091] Therefore, in at least some embodiments, an electronic system includes an input device, an output device, a processor device operatively coupled to the input and output devices, and a memory device operatively coupled to the processor device and including at least one microelectronic device structure. The at least one microelectronic device structure includes: a memory cell string extending through a stacked structure comprising alternating layers of insulating and conductive structures; a first support pillar structure located within a first region of the stacked structure, extending vertically through the stacked structure to a source structure underlying the stacked structure and electrically isolated from the source structure; and a second support pillar structure located within a second region of the stacked structure, extending vertically through the stacked structure and electrically connected to the source structure.

[0092] Additional non-limiting example embodiments of this disclosure are described below.

[0093] Example 1: A microelectronic device comprising: a stacked structure including alternating conductive and insulating structures arranged in layers, each layer individually including one of the conductive structures and one of the insulating structures; a first support pillar structure extending through the stacked structure in a first region of the microelectronic device, the first support pillar structure being electrically isolated from a source structure underlying the stacked structure; a second support pillar structure extending through the stacked structure in a second region of the microelectronic device, the second support pillar structure including a conductive material electrically connected to the source structure; and a bridging structure extending between at least some adjacent first support pillar structures.

[0094] Example 2: The microelectronic device according to Example 1, wherein at least one of the bridging structures physically connects one of the first support pillar structures to the other of the first support pillar structures.

[0095] Example 3: The microelectronic device according to Example 2 further includes a replacement gate trench located between the two in the first support pillar structure and in contact with the at least one bridging structure.

[0096] Example 4: The microelectronic device according to Example 3, wherein the replacement gate trench and the first support pillar structure both comprise the same material composition.

[0097] Example 5: A microelectronic device according to any one of Examples 1 to 4, wherein the bridging structure is electrically isolated from the source structure by a lining material.

[0098] Example 6: A microelectronic device according to any one of Examples 1 to 5, wherein the bridging structure comprises polysilicon.

[0099] Example 7: A microelectronic device according to any one of Examples 1 to 6, wherein the bridging structure includes a dielectric liner material in contact with the source structure.

[0100] Example 8: A microelectronic device according to any one of Examples 1 to 7, wherein at least some of the first support pillar structures are located in a stepped region.

[0101] Example 9: A microelectronic device according to any one of Examples 1 to 8, wherein the first support pillar structure comprises the same material composition as the bridging structure.

[0102] Example 10: A microelectronic device according to any one of Examples 1 to 9, wherein the conductive material includes tungsten.

[0103] Example 11: A memory device comprising: a stacked structure including layers, each layer including at least one conductive structure and at least one insulating structure vertically adjacent to the at least one conductive structure; a stepped structure having steps including at least some of the horizontal ends of the layers; a source structure resting on the stacked structure; a first support pillar structure extending vertically through the stepped structure to the source structure, at least one of the first support pillar structures being coupled to at least another of the first support pillar structures via a bridging structure within the source structure; and a second support pillar structure including a conductive material extending vertically through the stacked structure and in electrical communication with the source structure.

[0104] Example 12: The memory device according to Example 11, wherein the second support column structure is located outside the horizontal boundary of the stepped structure.

[0105] Example 13: The memory device according to Example 11 or Example 12, wherein the first support pillar structure is electrically isolated from the source structure.

[0106] Example 14: A memory device according to any one of Examples 11 to 13, further comprising a slot structure located between the at least one of the first support pillar structures and the at least other of the first support pillar structure.

[0107] Example 15: The memory device according to Example 14, wherein the slot structure physically contacts the bridging structure.

[0108] Example 16: A memory device according to any one of Examples 11 to 15, wherein the second support column structure extends a greater distance in the vertical direction than the first support column structure.

[0109] Example 17: A memory device according to any one of Examples 11 to 16, wherein the first support pillar structure comprises a dielectric material.

[0110] Example 18: The memory device according to Example 17, wherein the first support pillar structure comprises polycrystalline silicon horizontally adjacent to the dielectric material.

[0111] Example 19: A method of forming a microelectronic device structure, the method comprising: forming a conductive support pillar structure through a first region of a stacked structure comprising multiple alternating insulating structures and other insulating structures arranged in layers, the conductive support pillar structure contacting a bridging structure underlying a source structure of the stacked structure; forming a conductive support pillar structure through a second region of the stacked structure and contacting the source structure; forming an opening through the stacked structure and contacting the bridging structure in the first region and a landing pad in the second region; removing conductive material from the bridging structure and the conductive support pillar structure in the first region through the opening to form a support structure comprising a dielectric lining material, at least one support structure in the first region communicating with at least one other support structure through a recess; replacing the insulating structure with a conductive structure through the opening; and filling the opening in the first region and the second region with a dielectric material and another material, and filling the recess in the first region with the other material.

[0112] Example 20: According to the method of Example 19, wherein forming a conductive support pillar structure through a second region of the stacked structure and in contact with the source structure includes forming the conductive support pillar structure in the second region with a greater vertical height than the conductive support pillar structure in the first region.

[0113] Example 21: The method according to Example 19 or Example 20 further includes forming the bridging structure to include tungsten.

[0114] Example 22: The method according to any of Examples 19 to 21, wherein filling the openings in the first region and the second region with a dielectric material and another material includes filling the openings with a dielectric material and polysilicon.

[0115] Example 23: The method according to any of Examples 19 to 22, wherein filling the openings in the first region and the second region with a dielectric material and another material, and filling the recesses of the support structure and the recesses in the first region with the other material, includes forming the support structure in the first region to be electrically isolated from the source structure.

[0116] Example 24: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure including: a memory cell string extending through a stacked structure comprising alternating layers of insulating and conductive structures; a first support pillar structure located in a first region of the stacked structure, extending vertically through the stacked structure to a source structure underlying the stacked structure and electrically isolated from the source structure; and a second support pillar structure located in a second region of the stacked structure, extending vertically through the stacked structure and electrically connected to the source structure.

[0117] Example 25: The electronic system according to Example 24, wherein the second support pillar structure includes tungsten in electrical communication with the source structure.

[0118] Example 26: The electronic system according to Example 24 or Example 25, wherein the first support pillar structure includes a dielectric liner material and polycrystalline silicon horizontally adjacent to the dielectric liner material.

[0119] While certain illustrative embodiments have been described in conjunction with drawings, those skilled in the art will recognize and understand that the embodiments covered by this disclosure are not limited to those explicitly shown and described herein. Rather, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by this disclosure (such as those claimed herein, including legal equivalents). Furthermore, features of one disclosed embodiment may be combined with features of another disclosed embodiment, and still be included within the scope of this disclosure.

Claims

1. A microelectronic device comprising: A stacked structure comprising alternating conductive and insulating structures arranged in layers, each layer individually comprising one of the conductive structures and one of the insulating structures; A first support pillar structure extends through the stacked structure within a first region of the microelectronic device, and the first support pillar structure is electrically isolated from the source structure underlying the stacked structure. A second support pillar structure extends through the stacked structure within a second region of the microelectronic device, the second support pillar structure comprising a conductive material electrically connected to the source structure; as well as A bridging structure that extends between at least some adjacent first support column structures in the first support column structure.

2. The microelectronic device of claim 1, wherein at least one of the bridging structures physically connects one of the first support pillar structures to the other of the first support pillar structures.

3. The microelectronic device of claim 2, further comprising a replacement gate trench located between the two of the first support pillar structures and in contact with the at least one bridging structure.

4. The microelectronic device of claim 3, wherein the replacement gate trench and the first support pillar structure both comprise the same material composition.

5. The microelectronic device of claim 1, wherein the bridging structure is electrically isolated from the source structure by a lining material.

6. The microelectronic device according to any one of claims 1 to 5, wherein the bridging structure comprises polysilicon.

7. The microelectronic device according to any one of claims 1 to 5, wherein the bridging structure comprises a dielectric liner material in contact with the source structure.

8. The microelectronic device according to any one of claims 1 to 5, wherein at least some of the first support pillar structures are located in a stepped region.

9. The microelectronic device according to any one of claims 1 to 5, wherein the first support pillar structure comprises the same material composition as the bridging structure.

10. The microelectronic device according to any one of claims 1 to 5, wherein the conductive material comprises tungsten.

11. A memory device comprising: A stacked structure comprising layers, each layer comprising at least one conductive structure and at least one insulating structure vertically adjacent to the at least one conductive structure; A stepped structure having steps including at least some of the horizontal ends of the layers; A source structure lies beneath the stacked structure; A first support column structure extends vertically through the stepped structure to the source structure, and at least one of the first support column structures is coupled to at least one of the first support column structures through a bridging structure within the source structure. as well as The second support column structure includes a conductive material that extends vertically through the stacked structure and is electrically connected to the source structure.

12. The memory device of claim 11, wherein the second support pillar structure is located outside the horizontal boundary of the stepped structure.

13. The memory device of claim 11, wherein the first support pillar structure is electrically isolated from the source structure.

14. The memory device of claim 11, further comprising a slot structure located between the at least one of the first support pillar structures and the at least other of the first support pillar structure.

15. The memory device of claim 14, wherein the slot structure physically contacts the bridging structure.

16. The memory device according to any one of claims 11 to 15, wherein the second support column structure extends a greater distance in the vertical direction than the first support column structure.

17. The memory device according to any one of claims 11 to 15, wherein the first support pillar structure comprises a dielectric material.

18. The memory device of claim 17, wherein the first support pillar structure comprises polycrystalline silicon horizontally adjacent to the dielectric material.

19. A method for forming a microelectronic device structure, the method comprising: A conductive support pillar structure is formed through a first region of a stacked structure, the first region of the stacked structure comprising multiple alternating layers of insulating structures and other insulating structures, the conductive support pillar structure contacting a bridging structure underlying the source structure of the stacked structure; A conductive support pillar structure is formed that passes through a second region of the stacked structure and contacts the source structure; An opening is formed that passes through the stacked structure and contacts the bridging structure in the first region and the landing pad in the second region; The conductive material of the bridging structure and the conductive support pillar structure of the first region is removed through the opening to form a support structure including a dielectric lining material, wherein at least one support structure in the first region is connected to at least another support structure through a recess; The insulating structure is replaced with a conductive structure through the opening; as well as The openings in the first and second regions are filled with a dielectric material and another material, and the recesses in the first region are filled with the other material.

20. The method of claim 19, wherein forming a conductive support pillar structure through a second region of the stacked structure and in contact with the source structure includes forming the conductive support pillar structure in the second region having a greater vertical height than the conductive support pillar structure in the first region.

21. The method of claim 19, further comprising forming the bridging structure to include tungsten.

22. The method according to any one of claims 19 to 21, wherein filling the openings in the first region and the second region with a dielectric material and another material comprises filling the openings with a dielectric material and polysilicon.

23. The method according to any one of claims 19 to 21, wherein filling the openings in the first region and the second region with a dielectric material and another material, and filling the recesses of the support structure and the recesses in the first region with the other material, comprises forming the support structure in the first region to be electrically isolated from the source structure.

24. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; as well as A memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure comprising: A string of memory cells that extends through a stacked structure comprising alternating layers of insulating and conductive structures; A first support column structure is located in a first region of the stacked structure, extends vertically through the stacked structure to a source structure lying beneath the stacked structure, and is electrically isolated from the source structure; A second support column structure, located within a second region of the stacked structure, extending vertically through the stacked structure and electrically connected to the source structure; and A bridging structure that extends between at least some adjacent first support column structures in the first support column structure.

25. The electronic system of claim 24, wherein the second support pillar structure comprises tungsten in electrical communication with the source structure.

26. The electronic system of claim 24 or claim 25, wherein the first support pillar structure comprises a dielectric liner material and polycrystalline silicon horizontally adjacent to the dielectric liner material.

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