Integrated assembly and method of forming an integrated assembly

Abstract

Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to the other of the insulative levels due to the at least one of the insulative levels including a dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming an integrated assembly.

Description

[0001] Relevant patent information

[0002] This application claims priority and benefit to U.S. Patent Application No. 16 / 902,897, filed June 16, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] Integrated assemblies (e.g., integrated memory). Methods for forming integrated assemblies. Background Technology

[0004] Memory provides data storage devices for electronic systems. Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to use flash memory, in the form of solid-state drives, instead of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and allows manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0005] NAND can be the basic architecture of flash memory and can be configured to include vertically stacked memory cells.

[0006] Before describing NAND in detail, it may be helpful to describe the relationships of memory arrays within an integrated arrangement more generally. Figure 1 shows a block diagram of a prior art device 1000 including: a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns; access lines 1004 (e.g., word lines for conducting signals WL0 to WLm); and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). Access lines 1004 and first data lines 1006 are used to transfer information to and from memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which memory cells in memory cells 1003 to access. Sensing amplifier circuitry 1015 operates to determine the value of the information read from memory cells 1003. I / O circuitry 1017 transfers the value of the information between memory array 1002 and input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O lines 1005 can represent values ​​of information to be read from or written to memory cell 1003. Other devices can communicate with device 1000 via I / O line 1005, address line 1009, or control line 1020. Memory control unit 1018 controls memory operations to be performed on memory cell 1003 and utilizes signals on control line 1020. Device 1000 can receive supply voltage signals Vcc and Vss on first power line 1030 and second power line 1032, respectively. Device 1000 includes selection circuitry 1040 and input / output (I / O) circuitry 1017. Selection circuitry 1040 can respond to signals CSEL1 to CSELn via I / O circuitry 1017 to select signals on first data line 1006 and second data line 1013, which can represent values ​​of information to be read from or programmed into memory cell 1003. The column decoder 1008 can selectively activate the CSEL1 to CSELn signals based on the A0 to AX address signals on the address lines 1009. The selection circuit 1040 can select the signals on the first data line 1006 and the second data line 1013 to enable communication between the memory array 1002 and the I / O circuit 1017 during read and program operations.

[0007] The memory array 1002 of Figure 1 may be a NAND memory array, and Figure 2 shows a block diagram of a three-dimensional NAND memory device 200 that can be used with the memory array 1002 of Figure 1. Device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices may include, for example, thirty-two charge storage devices stacked one on top of the other, where each charge storage device corresponds to a row in, for example, thirty-two layers (e.g., layers 0 to 31). The charge storage devices in the respective strings may share a common channel region, such as formed in pillars of a corresponding semiconductor material (e.g., polysilicon), around which the charge storage device strings are formed. In a second direction (X-X'), each first group of the multiple strings, for example, sixteen first groups, may include, for example, eight strings sharing multiple (e.g., thirty-two) access lines (i.e., “global control gate (CG) lines”, also referred to as word lines WL). Each of the access lines may couple to a charge storage device within a layer. When each charge storage device includes a cell capable of storing two bits of information, charge storage devices coupled by the same access line (and therefore corresponding to the same layer) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In the third direction (Y-Y'), each second group in the multiple strings, for example, eight second groups, may include sixteen strings coupled by corresponding data lines of eight data lines. The size of the memory block may include 1,024 pages, and approximately 16 MB in total (e.g., 16 word lines × 32 layers × 2 bits = 1,024 pages / block, block size = 1,024 pages × 16 KB / page = 16 MB). The number of strings, layers, access lines, data lines, first groups, second groups, and / or pages may be larger or smaller than those shown in Figure 2.

[0008] Figure 3 shows a cross-sectional view of the memory block 300 of the 3D NAND memory device 200 of Figure 2 in the X-X' direction, containing fifteen strings of charge storage devices in one of the sixteen first groups described in Figure 2. The multi-string memory block 300 can be divided into multiple subsets 310, 320, 330 (e.g., tile columns), such as tile columns. I Puzzle Series j and puzzle series KEach subset (e.g., a tile array) comprises a “partial block” of memory block 300. A global drain-side select-gate (SGD) line 340 may be coupled to the SGDs of the multiple strings. For example, the global SGD line 340 may be coupled to a plurality of (e.g., three) sub-SGD lines 342, 344, 346 via corresponding sub-SGD drivers of a plurality of (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a corresponding subset (e.g., a tile array). Each sub-SGD driver of the sub-SGD drivers 332, 334, 336 may simultaneously couple or disconnect the SGDs of the corresponding partial block (e.g., a tile array) of strings, independent of the SGDs of the strings of other partial blocks. A global source-side select-gate (SGS) line 360 ​​may be coupled to the SGS of the multiple strings. For example, a global SGS line 360 ​​may be coupled to a plurality of sub-SGS lines 362, 364, and 366 via corresponding sub-SGS drivers among a plurality of sub-SGS drivers 322, 324, and 326, wherein each sub-SGS line corresponds to a corresponding subset (e.g., a tile column). Each of the sub-SGS drivers 322, 324, and 326 may couple or disconnect the SGS of the corresponding partial block (e.g., a tile column) string independently of the SGS of the strings of other partial blocks. A global access line (e.g., a global CG line) 350 may be coupled to a charge storage device corresponding to a corresponding layer of each of the multiple strings. Each global CG line (e.g., global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, and 356 via corresponding sub-string drivers among a plurality of sub-string drivers 312, 314, and 316. Each substring driver in the substring driver can simultaneously couple or disconnect the charge storage device corresponding to the corresponding subblock and / or layer, independently of the charge storage devices of other subblocks and / or other layers. The charge storage devices corresponding to the corresponding subset (e.g., a subblock) and the corresponding layer may include charge storage devices of a “sublayer” (e.g., a single “patch”). The string corresponding to the corresponding subset (e.g., a subblock) may be coupled to the corresponding subsource in subsources 372, 374, and 376 (e.g., “patch source”), wherein each subsource is coupled to a corresponding power source.

[0009] Alternatively, the NAND memory device 200 is described with reference to the schematic illustration of FIG4.

[0010] Memory array 200 includes word lines 2021 to 202 N And bit lines 2281 to 228 M .

[0011] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string contains 2081 to 208 charge storage transistors. NCharge storage transistors can use floating gate materials (e.g., polysilicon) to store charge, or they can use charge trapping materials (e.g., silicon nitride, metal nanodots, etc.) to store charge.

[0012] Charge storage transistor 208 is located at the intersection of word line 202 and string 206. Charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source select device (e.g., source-side select gate SGS) 210 and a drain select device (e.g., drain-side select gate SGD) 212. Each source select device 210 is located at the intersection of string 206 and source select line 214, and each drain select device 212 is located at the intersection of string 206 and drain select line 215. Select devices 210 and 212 can be any suitable access device and are generally illustrated by the boxes in FIG4.

[0013] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 corresponding to the NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 corresponding to the NAND string 2061. The source select device 210 is connected to the source select line 214.

[0014] The drain of each drain selector 212 is connected to the bit line (i.e., digital line) 228 at its drain contact. For example, the drain of drain selector 2121 is connected to bit line 2281. The source of each drain selector 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain selector 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N The drain electrode.

[0015] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The control gate 236 of the charge storage transistor 208 is coupled to a word line 202. Columns of the charge storage transistor 208 are those transistors coupled to a given positioning line 228 within a NAND string 206. Rows of the charge storage transistor 208 are those transistors typically coupled to a given word line 202.

[0016] The goal is to develop improved NAND architectures and improved methods for manufacturing NAND architectures. Attached Figure Description

[0017] Figure 1 shows a block diagram of a prior art memory device with a memory array having memory cells.

[0018] Figure 2 shows a schematic diagram of the prior art memory array of Figure 1 in the form of a 3D NAND memory device.

[0019] Figure 3 shows a cross-sectional view of the prior art 3D NAND memory device of Figure 2 in the X-X' direction.

[0020] Figure 4 is a schematic diagram of a conventional NAND memory array.

[0021] Figure 5 This is a schematic cross-sectional side view of an example assembly.

[0022] Figures 6 to 8 for Figure 5 Instance assemblies in Figure 5 A schematic cross-sectional side view of the processing stage following the processing stage.

[0023] Figure 9 This is a schematic cross-sectional side view of an example integrated assembly.

[0024] Figure 10 is Figure 9 Instance assemblies in Figure 9 A schematic cross-sectional side view of the prior art processing stage following the processing stage of the previous stage.

[0025] Figures 11 to 14 for Figure 9 A schematic cross-sectional side view of the instance assembly at the instance sequential processing stage of the instance method.

[0026] Figure 15 A top view of the area of ​​the integrated assembly. Detailed Implementation

[0027] Some embodiments include a method of forming one or more openings through a stack of alternating materials. Dopants may be dispersed within regions of the material to alter the etch characteristics of these regions and thereby improve the configuration of the openings (e.g., to reduce taper, contraction, expansion, etc., that might otherwise be present within the openings). The term "dopant" refers to an impurity provided within the base (main) composition. Impurities may include a single substance or a collection of two or more substances. Reference Figures 5 to 15 Describe an example implementation.

[0028] See Figure 5The integrated assembly 10 includes a stack 12 comprising a pair of layers 14 and 16. Layer 14 includes a first material 18, and layer 16 includes a second material 20. Materials 18 and 20 have compositions different from each other. In some embodiments, material 18 may include silicon dioxide, is substantially composed of silicon dioxide, or is composed of silicon dioxide, and material 20 may include silicon nitride, is substantially composed of silicon nitride, or is composed of silicon nitride.

[0029] refer to Figure 6 An opening 22 is formed to extend through the stack 12. The opening 22 can be formed using any suitable etching, such as plasma (dry) etching using fluorine, wet etching using hydrofluoric acid, etc. Another example of wet etching is that it can be performed, for example, using conditions similar to those of Standard Clean 1 (SC1), where such conditions utilize ammonium hydroxide and hydrogen peroxide.

[0030] The opening 22 can have any suitable configuration when viewed from above, and can be, for example, circular, rectangular, elliptical, etc.

[0031] Opening 22 has along Figure 6 The width W1 of the cross-section. Some embodiments described herein utilize dopants within materials 18 and 20 to alter the width of the opening 22. Figure 7 and 8 This is explained by extending (the process) by incorporating appropriate dopants into materials 18 and 20. Figure 7 ) and contraction ( Figure 8 Example application of width.

[0032] See Figure 7 Dopant is incorporated into materials 18 and 20 to enhance the material removal rate during the etching process, thereby widening the opening 22. Specifically, the opening 22 is now at a width W2 that is greater than the width W1. Figure 7 The opening 22 can be used with the formation Figure 6 The opening 22 is formed under the same conditions, but due to the dopants that have been incorporated into materials 18 and 20, the opening will eventually be wider.

[0033] See Figure 8 Dopant is incorporated into materials 18 and 20 to reduce the material removal rate during the etching process, thereby narrowing the opening 22. Specifically, the opening 22 is now located at a width W3 that is smaller than the width W1. Figure 8 The opening 22 can be used with the formation Figure 6 The opening 22 is formed under the same conditions, but due to the dopants that have been incorporated into materials 18 and 20, the opening will eventually be narrower.

[0034] For Figure 7 and 8The dopant used in the treatment may comprise one or more elements selected from Groups 13 to 16 of the periodic table, and in some embodiments, may comprise one or more substances selected from the group consisting of Al, Ga, Ge, C, Se, S, Sn, Te, P, As, and Sb. In certain embodiments, the dopant may comprise carbon in the form of one or more fluorocarbon compounds. The dopant may be provided at any suitable concentration. For example, the dopant may be dispersed in materials 18 and 20 at a concentration of at least about 0.01 atomic percent (at%). In some embodiments, the dopant may be present in materials 18 and 20 at a concentration ranging from about 0.01 at% to about 1 at%, or at a concentration ranging from about 0.01 at% to about 5 at%.

[0035] The dopant in material 18 may or may not be the same as the dopant in material 20. In some embodiments, the same dopant is present in materials 18 and 20, and is used to enhance the formation of polymer layers along the sidewall edges of the material adjacent to the opening 22, or to reduce the formation of polymer layers. The enhanced formation of polymer layers can reduce the etch rate of materials 18 and 20, and may thereby result in the formation of a narrower opening 22 (i.e., Figure 8 The opening). In contrast, the reduction in the formation of polymer layers can lead to an enhanced etching rate of materials 18 and 20, and may thereby result in the formation of a wider opening 22 (i.e., Figure 7 (the opening).

[0036] Examples of dopants that can promote polymer accumulation include sulfur and silicon. Examples of dopants that can inhibit polymer accumulation include nitrogen and oxygen.

[0037] Polymer accumulation mechanisms are provided to aid the reader's understanding of some of the embodiments described herein and do not limit this disclosure or the appended claims, except where such mechanisms are explicitly stated in the claims. In addition to affecting the rate of polymer accumulation, (various) dopants can alter the etching rates of materials 18 and 20 through other mechanisms. Such other mechanisms may include, for example, hardening or softening one or both of materials 18 and 20 relative to etching conditions.

[0038] Figures 5 to 8 The method can be used to improve the crossing of references Figures 9 to 11 The configuration of the opening formed by the large vertical alternating stacks of material is described.

[0039] Figure 9An assembly 10 is shown comprising an alternating stack 12 of first layers 14 and second layers 16. The first layer 14 comprises a first material 18, and the second layer 16 comprises a second material 20. The first material 18 can be considered to comprise a first major composition, and the second material 20 can be considered to comprise a second major composition different from the first major composition. The term "major composition" refers to a composition that does not contain any dopants that may be present in the material. For example, the major compositions of materials 18 and 20 may be SiO and SiN, respectively, where the chemical formula indicates the major component rather than a specific stoichiometry. In some embodiments, the major composition of material 18 may be SiO2, and the major composition of material 20 may be Si3N4.

[0040] Layers 14 and 16 may have any suitable thickness and may have the same thickness as each other or different thicknesses relative to each other. In some embodiments, layers 14 and 16 may have a vertical thickness ranging from about 10 nanometers (nm) to about 400 nm. In some embodiments, layers 14 and 16 may have a vertical thickness ranging from about 10 nm to about 50 nm. In some embodiments, the first and second layers 14 and 16 may have a vertical thickness ranging from about 15 nm to about 40 nm, from about 15 nm to about 20 nm, and so on. Any suitable number of layers 14 and 16 may exist within stack 12. In some embodiments, more than 10 layers may exist within stack, more than 50 layers may exist within stack, more than 100 layers may exist within stack, and so on.

[0041] In the illustrated embodiment, stack 12 is supported on conductive structure 24. Conductive structure 24 may correspond to a source structure similar to source structure 214 and / or 360 described with reference to Figures 1 to 4, and may be a line, an expande, or any other suitable configuration. Source structure 24 may include any suitable material, and in some applications, a conductive doped semiconductor material (e.g., conductive doped silicon) may be included above a metallic material (e.g., tungsten silicide).

[0042] The source structure 24 may be supported by a substrate (not shown). The substrate may include semiconductor materials and may include, for example, monocrystalline silicon, be substantially composed of monocrystalline silicon, or be composed of monocrystalline silicon. The substrate may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction that includes semiconductor materials, including but not limited to bulk semiconductor materials, such as semiconductor wafers (alone or in combinations of other materials), and semiconductor material layers (alone or in combinations of other materials). The term "substrate" refers to any support structure that includes (but is not limited to) the semiconductor substrate described above.

[0043] A gap is provided between stack 12 and source structure 24. The gap is used to indicate that other components and materials may be disposed between stack 12 and source structure 24. Such other components and materials may include additional stack planes, source-side selected gate (SGS), etc.

[0044] Referring to Figure 10, the opening 22 is formed by a prior art etching process to extend through the stack 12. Prior art processes may include plasma etching, wet etching, etc. The illustrated opening 22 may represent multiple openings formed through the stack 12, wherein such openings are presumably substantially identical to each other.

[0045] Opening 22 has wavy sidewalls along the cross-section of FIG10, which is attributed to the faster removal of material 18 and 20 in some areas by etching compared to other areas. For example, in the illustrated application, opening 22 can be considered as having a bottom area 26, a central area 28, and an upper area 30. The upper area 30 has the desired width W1. The bottom area 26 is tapered and narrower than the desired width; and the central area 28 arches outward and is wider than the desired width. The opening 22 illustrated in FIG10 may be problematic for the intended application because the opening is wider than the desired size W1, which may make the opening too wide for the given level of integration, and because the dimensional variation along the opening may make it difficult (if not impossible) to form multiple such openings with the given uniformity across the opening.

[0046] Figure 11 The stack 12 is shown in a modified form to mitigate the problematic dimensional variations of the opening 22 in Figure 10. Specifically, the stack 12 is subdivided into three regions 32, 34, and 36, each of which is adjusted to achieve the desired etch rate so that the opening 22 can be formed with a uniform width W1 from the top to the bottom of the stack 12 (i.e., so that the sidewalls 21 can be formed to be generally vertically straight).

[0047] Materials 18 and 20 are shown to have different compositions within regions 32, 34, and 36. Specifically, materials 18 and 20 have compositions corresponding to 18a and 20a in the lower region 32, compositions corresponding to 18b and 20b in the middle region 34, and compositions corresponding to 18c and 20c in the upper region 36. Substances 18a, 18b, and 18c may all have the same first principal composition, but may differ from each other with respect to dopants that may or may not be dispersed within such substances. Similarly, substances 20a, 20b, and 20c may all have the same second principal composition, but may differ from each other with respect to dopants that may or may not be dispersed within such substances. Substances 18a and 20a are shown to be formed within lower layers 14a and 16a, substances 18b and 20b are shown to be formed within middle layers 14b and 16b, and substances 18c and 20c are shown to be formed within upper layers 14c and 16c.

[0048] In some embodiments, substances 18c and 20c may correspond to a first major composition and a second major composition, and may contain very little (if present) dopant. For example, in some embodiments, substances 18c and 20c may correspond to SiO2 and Si3N4, respectively (i.e., may consist substantially of SiO2 and Si3N4 or consist of SiO2 and Si3N4).

[0049] Materials 18a and 20a may correspond to a first primary composition and a second primary composition, and may further include dopants that enable lower layers 14a and 16a to etch faster than layers 14b, 16b, 14c, and 16c during the formation of opening 22. Such dopants may make materials 18a and 20a in the lower layers softer than materials 18b, 18c, 20b, and 20c in the upper layers (i.e., etch faster than materials in the upper layers), and / or may reduce the rate of polymer buildup along the sidewalls 21 adjacent to layers 14a and 16a during the formation of opening 22. In some embodiments, the dopants provided in materials 18a and 20a may include one or more of nitrogen, oxygen, etc. If material 18a comprises SiO... x (where x is the number), and the dopant includes oxygen, then the oxygen concentration in material 18a can be greater than the stoichiometric oxygen concentration in silicon dioxide (i.e., material 18a may include SiO2). x (where x is greater than 2). If substance 20a includes silicon nitride and the dopant includes nitrogen, then the nitrogen concentration in substance 20a can be greater than the nitrogen concentration in stoichiometric silicon nitride (i.e., greater than the nitrogen concentration in Si3N4).

[0050] Materials 18b and 20b may correspond to a first primary composition and a second primary composition, and may further include dopants that cause central layers 14b and 16b to etch more slowly than layers 14a, 16a, 14c, and 16c during the formation of opening 22. Such dopants may cause materials 18b and 20b within the central layers to be softer than materials 18a, 18c, 20a, and 20c within the other layers (i.e., etch more slowly than materials within the other layers), and / or may increase the rate of polymer buildup along the sidewalls 21 adjacent to layers 14b and 16b during the formation of opening 22. In some embodiments, the dopants provided within materials 18b and 20b may include one or more of sulfur, silicon, etc. If material 18b comprises SiO... x (where x is the number), and the dopant includes silicon, then the silicon concentration in material 18b can be greater than the silicon concentration in stoichiometric silicon dioxide (i.e., material 18b may include SiO2). x(where x is less than 2). If substance 20b includes silicon nitride and the dopant includes silicon, then the silicon concentration in substance 20b can be greater than the silicon concentration in stoichiometric silicon nitride (i.e., greater than the silicon concentration in Si3N4).

[0051] The dopants used in materials 18a, 18b, 20a, and 20b are referenced above. Figure 7 and 8 Any of those dopants described. Therefore, such dopants may contain one or more elements selected from groups 13 to 16 of the periodic table.

[0052] The first layers 14a, 14b, and 14c can be considered as all comprising the same main composition, but differ in composition from one another due to differences in dopants that may or may not be dispersed within such layers. Similarly, the second layers 16a, 16b, and 16c can be considered as all comprising the same main composition, but differ in composition from one another due to differences in dopants that may or may not be dispersed within such layers.

[0053] In some embodiments, Figure 11 The stack 12 can be considered as comprising vertically shifted regions 32, 34, and 36. Regions 32, 34, and 36 can be considered as a first region, a second region, and a third region, respectively. Materials 18a and 20a of the first region 32 can be considered as comprising a first dopant and a second dopant, respectively; and materials 18b and 20b of the second region 34 can be considered as comprising a third dopant and a fourth dopant, respectively. The third dopant (i.e., the dopant within material 18b) is different from the first dopant (i.e., the dopant within material 18a), and the fourth dopant (i.e., the dopant within material 20b) is different from the second dopant (i.e., the dopant within material 20a). In some embodiments, the first dopant and the second dopant may be the same as each other, and the third dopant and the fourth dopant may be the same as each other. In other embodiments, the first dopant and the second dopant may be different from each other, and / or the third dopant and the fourth dopant may be different from each other. In some embodiments, the materials 18b and 20b of the second region 34 may be considered to include a first dopant and a second dopant, respectively; and the materials 18c and 20c of the third region 36 may be considered to include a third dopant and a fourth dopant, respectively (if the third region includes a dopant).

[0054] although Figure 11 The stack 12 is shown as comprising three vertically shifted regions. In other embodiments, the stack may comprise more than three vertically shifted regions or fewer than three vertically shifted regions. Generally, the stack will contain at least two of the vertically shifted regions.

[0055] Figure 11The opening 22 can be formed using the same process used to form the prior art opening of Figure 10. However, the dopants dispersed within the layers 14 and 16 can make Figure 11 The opening 22 can be formed along regions 26, 28 and 30 to have a uniform width, thereby avoiding the problematic variation in the width of the prior art opening of FIG10.

[0056] refer to Figure 12 A charge-blocking material 38 is formed within the opening 22 to line the opening. The charge-blocking material 38 may include any suitable composition; and in some embodiments, it may include one or both of silicon oxynitride (SiON) and silicon dioxide (SiO2), substantially composed of one or both of silicon oxynitride and silicon dioxide, or composed of one or both of silicon oxynitride and silicon dioxide.

[0057] The charge storage material 40 is formed adjacent to the charge blocking material 38. The charge storage material 40 may include any suitable composition. In some embodiments, the charge storage material 40 may include one or more charge trapping materials, such as one or more of silicon nitride, silicon oxynitride, conductive nanodots, etc. For example, in some embodiments, the charge storage material 40 may include silicon nitride, be substantially composed of silicon nitride, or be composed of silicon nitride.

[0058] A gate dielectric material (i.e., tunneling material, charge transport material) 42 is formed adjacent to the charge storage material 40. The gate dielectric material 42 may include any suitable composition. In some embodiments, the gate dielectric material 42 may include one or more of, for example, silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, etc. The gate dielectric material 42 may be bandgap engineered to achieve the desired electrical properties and may therefore include a combination of two or more different materials.

[0059] The channel material 44 is formed adjacent to the gate dielectric material 42 and extends vertically along (through) the stack 12. The channel material 44 includes a semiconductor material and may include any suitable composition or combination of compositions. For example, the channel material 44 may include one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term III / V semiconductor material refers to a semiconductor material that includes elements selected from Groups III and V of the periodic table (where Groups III and V are older terms and are currently referred to as Groups 13 and 15). In some embodiments, the channel material 44 may include silicon, be substantially composed of silicon, or be composed of silicon.

[0060] Insulating material 46 is formed adjacent to channel material 44 and fills the remainder of opening 22. Insulating material 46 may include any suitable composition; and in some embodiments, it may include silicon dioxide, be composed primarily of silicon dioxide, or be composed of silicon dioxide.

[0061] exist Figure 12 In the illustrated embodiment, the channel material 44 is configured as a ring surrounding the insulating material 46. This configuration of the channel material can be considered to include a hollow channel configuration, since the insulating material 46 is provided within the "hollow" space in the ring-shaped channel configuration. In other embodiments (not shown), the channel material may be configured as a solid pillar configuration.

[0062] exist Figure 12 In the cross-sectional view, the channel material 44 is shown as electrically coupled to the source structure 24. Such electrical coupling can be achieved using any suitable configuration. For example, in some embodiments, the channel material 44 may be in direct contact with the source structure 24.

[0063] The channel material 44 can be viewed as configured as channel material pillars 48, wherein such pillars are shown as extending vertically through the stack 12.

[0064] refer to Figure 13 Remove material 20 ( Figure 12 This leaves a gap 50 along the second layer 16 (i.e., between the first layers 14). The material 20 can be removed using any suitable process. In some embodiments, the main composition of the material 20 is silicon nitride, and the material is removed by etching using phosphoric acid.

[0065] See Figure 14 High-k dielectric material (dielectric resistance barrier material) material 52 is formed in the voids 50 ( Figure 13 The high-k dielectric material 52 is used to line the gaps within the material. The term "high-k" refers to a dielectric constant greater than that of silicon dioxide. In some embodiments, the high-k dielectric material 52 may include one or more of, substantially consist of one or more of, or consist of one or more of the following: aluminum oxide (AlO), hafnium oxide (HfO), hafnium silicate (HfSiO), zirconium oxide (ZrO), and zirconium silicate (ZrSiO); wherein the chemical formula indicates the principal component rather than a specific stoichiometry. The high-k dielectric material 52 may be formed to any suitable thickness; and in some embodiments, it may be formed to a thickness ranging from about 1 nm to about 5 nm.

[0066] A conductive structure 54 is formed within a lined void. The conductive structure 54 may comprise any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In the illustrated embodiment, the conductive structure comprises a conductive core material 56 and a conductive inner liner material 58 extending along the periphery of the core material 56. In some embodiments, the conductive core material 56 may comprise tungsten, be substantially composed of tungsten, or be composed of tungsten, and the conductive inner liner material 58 may comprise one or both of tungsten nitride and titanium nitride, be substantially composed of one or both of tungsten nitride and titanium nitride, or be composed of one or both of tungsten nitride and titanium nitride. In some embodiments, the conductive core material 56 may be referred to as a tungsten-containing core material, and the conductive inner liner material 58 may be referred to as a metal nitride-containing inner liner material.

[0067] Stacking 12 can be considered as in Figure 14 The alternating insulating layers 14 and conductive layers 16 are stacked at the processing stage. The insulating layers 14 are subdivided into three regions 32, 34 and 36, which respectively include insulating materials 18a, 18b and 18c.

[0068] Conductive level 16 can be considered as a memory cell level of the NAND configuration (also referred to herein as a word line level). The NAND configuration comprises memory cell strings (i.e., NAND strings), where the number of memory cells in a string is determined by the number of vertically stacked levels 16. NAND strings can include any suitable number of memory cell levels. For example, a NAND string may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc. Stacking 12 is indicated to extend vertically beyond the illustrated area to demonstrate the possibility of a higher density than the specified stack. Figure 14 The diagram illustrates more vertically stacked levels.

[0069] NAND memory cell 60 includes dielectric barrier material 52, charge blocking material 38, charge storage material 40, gate dielectric material 42, and channel material 44. The illustrated NAND memory cell 60 forms part of a vertically extending string of memory cells. Such a string can represent a large number of substantially identical NAND strings during the manufacture of the NAND memory array (the term "substantially identical" means equivalent within reasonable tolerances of manufacturing and measurement).

[0070] Each of the NAND memory cells 60 includes a control gate region 62 within a conductive structure 54 along a conductive layer 16. The control gate region 62 includes a control gate similar to the control gate described above with reference to Figures 1 to 4. The conductive structure 54 also includes a region 64 adjacent to (close to) the control gate region 62. Region 64 may be referred to as a wiring region (word line region).

[0071] Figure 15 Showing a top view along level 14c, and showing Figure 14 The illustrated channel material pillars 48 represent a plurality of channel material pillars formed along assembly 10. The channel material pillars can be tightly encapsulated and, in the illustrated embodiment, are generally hexagonally close-packed. The method described herein allows for a high degree of integration of the channel material pillars because it eliminates wide areas, twisting, bending, etc., that can occur when forming openings through large stacks using conventional methods (e.g., the prior art methods described above with reference to FIG. 10).

[0072] Despite the above reference Figures 11 to 14 The openings described are used to fabricate channel material pillars, and it should be understood that the methods described herein can be used to form other configurations extending through large material stacks. For example, the methods described herein can be used to form slits, trenches, etc., and / or, in addition to the applications illustrated with respect to NAND memory, to form openings associated with other applications.

[0073] The assemblies and structures discussed above can be used within integrated circuits (the term "integrated circuit" refers to electronic circuitry supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and so on.

[0074] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0075] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others may be used within this disclosure to provide linguistic variation to simplify the premises of the following claims, rather than to indicate any significant chemical or electrical differences.

[0076] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some instances and another in others may be to provide linguistic variation within this disclosure to simplify the presuppositions in the appended claims.

[0077] The specific orientations of the various embodiments in the figures are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The descriptions provided herein and the following claims relate to any structure having the described relationships between various features, regardless of whether the structure is in a specific orientation of the figures or rotated relative to such an orientation.

[0078] Unless otherwise specified, the cross-sectional views in the accompanying drawings show only the features within the plane of the cross-section and do not show the material behind the plane of the cross-section in order to simplify the drawings.

[0079] When a structure is referred to as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be an intervening structure. Conversely, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there is no intervening structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0080] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate that the structure typically extends upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend substantially orthogonally to the upper surface of the substrate.

[0081] Some embodiments include an integrated assembly with alternating vertically stacked insulating and conductive levels. The insulating levels have the same main composition as each other. At least one of the insulating levels differs in composition from the others because the at least one of the insulating levels contains dopants dispersed within the main composition. Openings extend vertically through the stack.

[0082] Some embodiments include an integrated assembly comprising an alternating first and second layer vertically stacked. The second layer comprises a composition different from the first layer. The first layers comprise a first main composition identical to each other. At least one of the first layers differs in composition from the others in the first layer because the at least one of the first layers comprises a first dopant dispersed within the first main composition. The second layers comprise a second main composition identical to each other. At least one of the second layers differs in composition from the others in the second layer because the at least one of the second layer comprises a second dopant dispersed within the second main composition. An opening extends vertically through the stack.

[0083] Some embodiments include a method of forming an integrated assembly. An alternating stack of first and second layers is formed. The first layer includes a first material having a first main composition, and the second layer includes a second material having a second main composition. At least one of the first layers is compositionally different from the others in the first layer because the at least one of the first layers includes a first dopant dispersed within the first main composition. At least one of the second layers is compositionally different from the others in the second layer because the at least one of the second layer includes a second dopant dispersed within the second main composition. Openings are formed to extend through the stacked first and second layers. Charge storage material, tunneling material, and channel material are formed within the openings. The second material is removed to leave gaps between the first layers. Conductive structures are formed within the gaps.

[0084] As per the regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising: A vertically stacked alternating insulating and conductive layers, wherein: The vertical stacking includes a first region and a second region that is vertically shifted from the first region; The insulating layers comprise the same primary composition as each other; At least one of the insulating layers in the first region and at least one of the insulating layers in the second region are compositionally different from the others in the insulating layers due to the inclusion of dopants dispersed within the main composition; and At least one of the insulating layers in the first region is different in composition from at least one of the insulating layers in the second region; and An opening that extends vertically through the first and second regions of the stack.

2. The integrated assembly of claim 1, wherein the main composition comprises SiO, wherein the chemical formula indicates the main component rather than a specific stoichiometry.

3. The integrated assembly of claim 2, wherein the dopant comprises one or more elements selected from groups 13 to 16 of the periodic table.

4. The integrated assembly of claim 3, wherein the dopant comprises one or more of Al, Ga, Ge, C, Se, S, Sn, Te, P, As, and Sb.

5. The integrated assembly according to claim 3, wherein the dopant comprises one or more fluorocarbon compounds.

6. The integrated assembly of claim 3, wherein the dopant comprises one or both of S and Si.

7. The integrated assembly of claim 3, wherein the dopant comprises one or both of N and O.

8. The integrated assembly of claim 3, wherein the dopant is present at a concentration of at least 0.01 at%.

9. The integrated assembly of claim 3, wherein the dopant is present at a concentration in the range of 0.01 at% to 5 at%.

10. The integrated assembly of claim 3, wherein the dopant is present at a concentration in the range of 0.01 at% to 1 at%.

11. The integrated assembly of claim 1, further comprising a channel material column extending vertically through the stack within the opening.

12. The integrated assembly according to claim 11, further comprising: Tunneling material, which is adjacent to the trench material column; A charge storage material, which is adjacent to the tunneling material; as well as A charge-blocking material adjacent to the charge-storing material.

13. The integrated assembly of claim 1, wherein each of the conductive layers comprises a tungsten-containing core and a metal nitride-containing liner along the periphery of the tungsten-containing core.

14. An integrated assembly comprising: Alternating vertical stacking of the first and second layers; The second level includes compositions different from those of the first level; The first layer comprises a first main composition that is identical to each other; at least one of the first layers differs in composition from the others in the first layer because the at least one of the first layers comprises a first dopant dispersed within the first main composition; the second layer comprises a second main composition that is identical to each other; at least one of the second layers differs in composition from the others in the second layer because the at least one of the second layer comprises a second dopant dispersed within the second main composition; as well as An opening that extends vertically through the stack.

15. The integrated assembly according to claim 14, wherein: The first major composition comprises SiO, wherein the chemical formula indicates the major component rather than a specific stoichiometry; and The second major composition includes SiN, wherein the chemical formula indicates the major component rather than a specific stoichiometry.

16. The integrated assembly of claim 15, wherein the first dopant and the second dopant comprise one or more elements selected from groups 13 to 16 of the periodic table.

17. The integrated assembly of claim 16, wherein the first dopant and the second dopant comprise one or more of Al, Ga, Ge, C, Se, S, Sn, Te, P, As, and Sb.

18. The integrated assembly of claim 16, wherein at least one of the first dopant and the second dopant comprises one or more fluorocarbon compounds.

19. The integrated assembly of claim 16, wherein at least one of the first dopant and the second dopant comprises one or both of S and Si.

20. The integrated assembly of claim 16, wherein at least one of the first dopant and the second dopant comprises one or both of N and O.

21. The integrated assembly of claim 16, wherein the first dopant and the second dopant are the same as each other.

22. The integrated assembly of claim 16, wherein the first dopant and the second dopant are different from each other.

23. A method for forming an integrated assembly, comprising: This forms an alternating stack of first and second levels; The first layer includes a first material having a first main composition, and the second layer includes a second material having a second main composition; at least one of the first layers is compositionally different from the others in the first layer because the at least one of the first layer includes a first dopant dispersed within the first main composition; at least one of the second layers is compositionally different from the others in the second layer because the at least one of the second layer includes a second dopant dispersed within the second main composition; An opening is formed to extend through the first and second layers of the stack; Charge storage material, tunneling material, and channel material are formed within the opening; Remove the second material to leave a gap between the first layers; as well as A conductive structure is formed within the void.

24. The method of claim 23, wherein the first dopant and the second dopant are the same as each other.

25. The method of claim 23, wherein the first dopant and the second dopant are different from each other.

26. The method of claim 23, further comprising forming a dielectric barrier material within the void to line the void, and then forming the conductive structure within the lined void.

27. The method of claim 23, wherein the first major composition comprises silicon dioxide and the second major composition comprises silicon nitride.

28. The method of claim 23, wherein the first dopant and the second dopant comprise one or more elements selected from groups 13 to 16 of the periodic table.

29. The method of claim 28, wherein the first dopant and the second dopant comprise one or more of Al, Ga, Ge, C, Se, S, Sn, Te, P, As, and Sb.

30. The method of claim 28, wherein the first dopant and the second dopant comprise one or more fluorocarbon compounds.

31. The method according to claim 23, wherein: The stack comprises at least two vertically shifted zones, one of which is a first zone and the other of which is a second zone; The first dopant and the second dopant are located within the first region; A third dopant is dispersed within the first primary composition in the second region, wherein the third dopant is different from the first dopant; and A fourth dopant is dispersed within the second main composition in the second region, wherein the fourth dopant is different from the second dopant.

32. The method according to claim 31, wherein: The first dopant and the second dopant are the same; and The third dopant is the same as the fourth dopant.

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