Epitaxial growth method for silicon wafers

Abstract

The present disclosure relates to a method for epitaxial growth of a silicon wafer, comprising: forming a polysilicon layer on a surface of a susceptor in a reaction chamber for placing the silicon wafer; placing the silicon wafer in the reaction chamber, placing the silicon wafer on the surface of the susceptor, and introducing H2 into the reaction chamber; raising the temperature of the reaction chamber to a first predetermined temperature; performing an H2 bake on the surface of the silicon wafer at the first predetermined temperature for a first predetermined time; raising the temperature of the reaction chamber to a second predetermined temperature; introducing HCl gas into the reaction chamber at the second predetermined temperature for a second predetermined time; introducing SiHCl3 gas into the reaction chamber to deposit a film on the surface of the silicon wafer; and purging the reaction chamber with H2 and unloading the silicon wafer from the reaction chamber. This method can improve haze defects on the surface of epitaxial silicon wafers.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor processing and manufacturing technology, and in particular, to an epitaxial growth method for silicon wafers. Background Art

[0002] Epitaxial growth refers to the process of growing a single-crystal thin film on a single-crystal silicon substrate using epitaxy. The entire epitaxial silicon wafer production process includes crystal growth, forming, polishing, cleaning, and epitaxy. Epitaxy, as the final, crucial step, improves the polished silicon wafer's crystal properties, native defects, resistivity, and flatness.

[0003] During the epitaxial growth process, many defects will appear on the epitaxial layer. These defects can be roughly divided into two categories according to their location, namely surface defects and body defects. Among them, surface defects refer to defects exposed on the surface of the epitaxial layer, which can be observed with the naked eye or a metallographic microscope.

[0004] A cloud-like surface, also known as a fog defect, is a defect present on the surface of the epitaxial layer that directly affects the performance of the semiconductor. For example, devices made from epitaxial silicon wafers with fog defects may suffer from reliability issues such as decreased minority carrier lifetime, increased leakage current, ion breakdown or soft breakdown, junction degradation, inversion, collector-emitter punch-through, and MOS threshold voltage drift.

[0005] Therefore, it is necessary to provide a method for improving haze defects in epitaxial silicon wafers. Summary of the Invention

[0006] This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.

[0007] The present disclosure aims to provide an epitaxial growth method for silicon wafers that can improve haze defects in epitaxial silicon wafers.

[0008] To achieve the above objectives, according to an embodiment of the present disclosure, a method for epitaxial growth of a silicon wafer is provided, comprising:

[0009] forming a polysilicon layer on a surface of a base of a reaction chamber for placing a silicon wafer;

[0010] Providing a silicon wafer into a reaction chamber so as to be placed on the surface of a susceptor and introducing H2 into the reaction chamber;

[0011] causing the temperature of the reaction chamber to reach a first predetermined temperature;

[0012] performing H2 baking on the surface of the silicon wafer at a first predetermined temperature for a first predetermined time;

[0013] causing the temperature of the reaction chamber to reach a second predetermined temperature;

[0014] introducing HCl gas into the reaction chamber at a second predetermined temperature for a second predetermined time;

[0015] introducing SiHCl3 gas into the reaction chamber to deposit a film on the surface of the silicon wafer; and

[0016] The reaction chamber is purged with H2 and the silicon wafer is unloaded and exited from the reaction chamber.

[0017] In the above-mentioned epitaxial growth method for silicon wafers, it can also include: before the silicon wafer enters the reaction chamber to be placed on the surface of the susceptor, controlling the thermal emissivity of the upper lamp module arranged on the upper side of the susceptor for heating the reaction chamber to be higher than the thermal emissivity of the lower lamp module arranged on the lower side of the susceptor for heating the reaction chamber.

[0018] In the above-mentioned epitaxial growth method for silicon wafers, the thermal emissivity of the upper lamp module can be controlled to be 0.015-0.025 higher than the thermal emissivity of the lower lamp module.

[0019] In the above-mentioned epitaxial growth method for silicon wafers, the first predetermined temperature may be 1135°C.

[0020] In the above-mentioned epitaxial growth method for silicon wafers, the first predetermined time may be 60s-80s.

[0021] In the above-mentioned epitaxial growth method for silicon wafers, the second predetermined temperature may be 1125°C.

[0022] In the above-mentioned epitaxial growth method for silicon wafers, the flow rate of HCl gas may be 3 slm-3.125 slm.

[0023] In the above-mentioned epitaxial growth method for silicon wafers, the second predetermined time may be 10s-30s.

[0024] In the above-mentioned epitaxial growth method for silicon wafers, causing the temperature of the reaction chamber to reach the first predetermined temperature may include increasing the temperature of the reaction chamber to the first predetermined temperature at a rate of 3° C. / s.

[0025] In the above-mentioned epitaxial growth method for silicon wafers, introducing SiHCl3 gas into the reaction chamber to deposit a film on the surface of the silicon wafer may include allowing the SiHCl3 gas to purge the pipeline leading to the reaction chamber for a certain period of time before the SiHCl3 gas enters the reaction chamber.

[0026] According to the present disclosure, by forming a polysilicon layer on the surface of the base, contaminants on the base surface are inhibited from diffusing to the surface of the silicon wafer and being deposited on the surface of the silicon wafer, thereby preventing the formation of fog defects on the surface of the epitaxial silicon wafer. In addition, by controlling the thermal emissivity of the upper lamp module to be higher than the thermal emissivity of the lower lamp module, the surface temperature of the silicon wafer is slightly higher than the temperature of the base, thereby inhibiting the contaminants on the base surface from diffusing to the surface of the epitaxial silicon wafer and removing the natural oxides and organic matter on the surface of the silicon wafer; by setting the temperature of the reaction chamber to 1135°C during H2 baking for 60s-80s, the natural oxides and organic matter on the surface of the silicon wafer are completely removed; and by setting the etching flow rate of HCl to 3slm-3.125slm and the reaction chamber temperature to 1125°C, the natural oxides and organic matter on the surface of the silicon wafer are completely removed, thereby improving the fog defects on the surface of the epitaxial silicon wafer.

[0027] The above features and advantages and other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematically shows an epitaxial reaction device for growing an epitaxial layer on a silicon wafer surface;

[0029] Figure 2 Schematic diagram showing the diffusion path of contaminants on the susceptor surface to the silicon wafer surface at high temperature;

[0030] Figure 3 Graphs are provided showing various exemplary parameters of an epitaxial growth method for a silicon wafer according to an embodiment of the present disclosure;

[0031] Figure 4 Schematically illustrates haze defects on the surface of an epitaxial silicon wafer before process improvement using the epitaxial growth method for a silicon wafer according to an embodiment of the present disclosure;

[0032] Figure 5 schematically illustrates haze defects on the surface of an epitaxial silicon wafer after process improvement using the epitaxial growth method for a silicon wafer according to an embodiment of the present disclosure; and

[0033] Figure 6 A graph shows a comparison of haze defect levels of an epitaxial silicon wafer prepared using the epitaxial growth method for a silicon wafer according to an embodiment of the present disclosure and an epitaxial silicon wafer prepared using a conventional epitaxial growth method. DETAILED DESCRIPTION

[0034] The present disclosure will be described in detail below with reference to the accompanying drawings by means of exemplary embodiments. It should be noted that the following detailed description of the present disclosure is only for illustrative purposes and is by no means limiting of the present disclosure.

[0035] Reference Figure 1 The process of growing an epitaxial layer on a silicon wafer using chemical vapor deposition (CVD) is usually as follows: Figure 1 The epitaxial growth device 1 shown in FIG is generally comprised of an upper quartz bell jar 11, a lower quartz bell jar 12, an air inlet 13, an exhaust port 14, a base 15 for placing silicon wafers disposed inside the epitaxial growth device 1, a base support rod 16 for supporting the base 15, an upper lamp module 17 disposed on the upper side of the base 15, and a lower lamp module 18 disposed on the lower side of the base 15.

[0036] During epitaxial growth, a silicon wafer is transported into the reaction chamber (or simply the chamber) of epitaxial growth apparatus 1 and placed on susceptor 15. Upper lamp module (or simply upper lamp) 17 and lower lamp module (or simply lower lamp) 18 heat the wafer. At the reaction temperature, the raw material gas supplied to the main surface (i.e., the upper surface) of the silicon wafer undergoes a chemical vapor deposition reaction, growing an epitaxial layer on the upper surface of the silicon wafer. During the growth process, susceptor support rods 16 secure susceptor 15 and drive it to rotate, allowing epitaxial growth to proceed uniformly across the upper surface of the silicon wafer.

[0037] As mentioned earlier, during the epitaxial growth process, many defects will appear on the epitaxial layer, which can be roughly divided into surface defects and internal defects. As one of the surface defects, fog defects will have an adverse effect on the performance of the final epitaxial silicon wafer (or epitaxial wafer) and the devices made using it.

[0038] The inventors have found that the sources of fog defects include the following: On the one hand, Figure 2 As shown in FIG, the contaminants on the surface of the base 15 may diffuse from the gap between the edge of the silicon wafer 20 and the edge of the base 15 to the surface 21 of the silicon wafer 20 (as shown in FIG. Figure 2 At high temperatures, these pollutants will be deposited onto the surface 21 of the silicon wafer 20 along with the silicon source gas SiHCl3, resulting in fog defects on the epitaxial layer. On the other hand, during polishing, the micro-roughness of the polishing will appear on the surface of the silicon wafer. As the surface silicon atoms react with oxygen in the air to form a natural oxide film, this will cause fog defects on the epitaxial layer during the epitaxial process.

[0039] Based on the above sources of fog defects, the present disclosure attempts to improve fog defects on epitaxial silicon wafers by inhibiting the contamination of silicon wafer surface by pollutants on the base surface at high temperature and by inhibiting the influence of natural oxides and organic matter on the silicon wafer surface on the epitaxial layer, thereby improving production yield.

[0040] To this end, according to an embodiment of the present disclosure, a method for epitaxial growth of a silicon wafer is provided, comprising:

[0041] forming a polysilicon layer on a surface of a base of a reaction chamber for placing a silicon wafer;

[0042] Providing a silicon wafer into a reaction chamber so as to be placed on the surface of a susceptor and introducing H2 into the reaction chamber;

[0043] causing the temperature of the reaction chamber to reach a first predetermined temperature;

[0044] performing H2 baking on the surface of the silicon wafer at a first predetermined temperature for a first predetermined time;

[0045] causing the temperature of the reaction chamber to reach a second predetermined temperature;

[0046] introducing HCl gas into the reaction chamber at a second predetermined temperature for a second predetermined time;

[0047] introducing SiHCl3 gas into the reaction chamber to deposit a film on the surface of the silicon wafer; and

[0048] The reaction chamber is purged with H2 and the silicon wafer is unloaded and exited from the reaction chamber.

[0049] Specifically, in the present disclosure, by forming a polysilicon layer on the surface of the base 15, the surface of the base 15 is covered by the polysilicon layer, so that the contaminants on the surface of the base cannot diffuse outside the base 15, and cannot diffuse to the surface of the silicon wafer through the gap between the edge of the base and the edge of the silicon wafer and be deposited on the surface of the silicon wafer, thereby preventing the formation of fog defects in the epitaxial layer due to the diffusion of contaminants on the surface of the base. In an embodiment of the present disclosure, a silicon source gas SiHCl3 can be introduced into the reaction chamber before the silicon wafer enters the reaction chamber, and a polysilicon layer is formed on the surface of the silicon wafer through a deposition reaction. However, it is understandable that the polysilicon layer can be formed on the surface of the base in any other known manner.

[0050] In an embodiment of the present disclosure, the method may further include: before the silicon wafer enters the reaction chamber to be placed on the surface of the base 15, controlling the thermal emissivity of the upper lamp module 17 provided on the upper side of the base 15 for heating the reaction chamber to be higher than the thermal emissivity of the lower lamp module 18 provided on the lower side of the base 15 for heating the reaction chamber.

[0051] The epitaxial reaction needs to be carried out in a high temperature environment. In the entire epitaxial system, the reaction chamber is heated by the upper lamp module 17 and the lower lamp module 18. The upper lamp module 17 is arranged on the upper side of the base 15 and mainly heats the surface 21 of the silicon wafer 20 to be grown epitaxially, while the lower lamp module 18 is arranged on the lower side of the base 15 and mainly heats the base 15. Figure 2 As shown in .

[0052] It is known that there is the following relationship between thermal emissivity (or emissivity) and temperature: E = r / T, where r is a constant. That is, the lower the thermal emissivity, the higher the measured temperature; the higher the thermal emissivity, the lower the measured temperature. Therefore, when the thermal emissivity of the upper lamp module is controlled to be higher than that of the lower lamp module, the measured temperature is relatively low. When the process temperature is set to a certain value, the upper lamp module will compensate for the temperature of the silicon wafer surface, causing the silicon wafer surface temperature to be slightly higher than the base temperature. This can inhibit the diffusion of contaminants from the base surface to the epitaxial silicon wafer surface and remove natural oxides and organic matter on the silicon wafer surface, thereby improving haze defects on the epitaxial silicon wafer surface.

[0053] In an embodiment of the present disclosure, the thermal emissivity of the upper lamp module 17 can be controlled to be 0.015-0.025 higher than the thermal emissivity of the lower lamp module 18. For example, the thermal emissivity of the upper lamp module 17 can be 0.675-0.775. Figure 3 As shown in , the thermal emissivity of the upper lamp module 17 can be 0.675.

[0054] The susceptor 15 can be, for example, a SiC susceptor. When the silicon wafer is placed on the surface of the susceptor 15, the temperature of the reaction chamber 5 is generally controlled at 850°C, and H2 is introduced into the reaction chamber from this step to perform

[0055] Purge: H2 purge can remove N2 that may be brought into the reaction chamber along with the silicon wafer, thereby avoiding adverse effects on subsequent deposition reactions.

[0056] In an embodiment of the present disclosure, the first predetermined temperature may be 1135°C.

[0057] The surface of the silicon wafer can be H2 baked at a high temperature of 1135°C. The high-temperature H2 atmosphere can effectively remove the oxides and organic matter remaining on the surface of the polished silicon wafer (or polished wafer), thereby preventing the generation of fog defects in the growing epitaxial layer.

[0058] The first predetermined time for the high temperature H2 baking to continue may be 60s-80s. Figure 3 As shown in , illustratively, when performing H2 baking, the flow rate of H2 can be 75slm.

[0059] It should be noted that slm is a flow unit, which refers to the volume value measured in cubic centimeters that flows every 5 minutes under the conditions of 1 atmosphere and 25°C.

[0060] Enabling the temperature of the reaction chamber to reach the first predetermined temperature may include increasing the temperature of the reaction chamber to the first predetermined temperature at a rate of 3° C. / s. Rapid temperature increase can quickly reach the first predetermined temperature, thereby facilitating better oxide removal.

[0061] At the end of the H2 bake, the temperature of the reaction chamber needs to reach a second predetermined temperature. In the embodiment of the present disclosure, the second predetermined temperature may be 1125°C.

[0062] At this temperature, the HCl etching gas introduced into the reaction chamber removes attached particles and damaged layers on the surface of the silicon wafer and can adjust the flatness of the silicon wafer.

[0063] The flow rate of HCl gas can be 3slm-3.125slm. Figure 3 As shown in , for example, the flow rate of HCl gas can be 3slm. In addition, the second predetermined time for passing the HCl gas can be 510s-30s.

[0064] In an embodiment of the present disclosure, introducing SiHCl 3 gas into the reaction chamber to deposit a film on the surface of the silicon wafer may include purging the SiHCl 3 gas through a pipe leading to the reaction chamber for a certain period of time before the SiHCl 3 gas enters the reaction chamber.

[0065] When the SiHCl3 gas is introduced through the gas inlet, the SiHCl3 gas can be prevented from entering the reaction chamber. For example, the inlet valve of the reaction chamber can be closed, and only the pipeline leading to the reaction chamber can be purged to remove the residual gas in the pipeline. Moreover, by purging the pipeline, the SiHCl3 gas can reach a stable gas pressure before entering the reaction chamber, so as to facilitate the smooth progress of the subsequent vapor deposition reaction. In the embodiment of the present disclosure, the flow rate of the SiHCl3 gas can be 5slm-20slm. Figure 3 As shown in , illustratively, the flow rate of SiHCl 3 gas can be 15 slm.

[0066] SiHCl3 gas can be supplied into the reaction chamber at the same flow rate as that used in the pipeline purge, and a chemical vapor deposition reaction occurs at a reaction temperature of, for example, 1125°C to deposit a film on the surface of the silicon wafer. The flow path of the SiHCl3 gas in the reaction chamber is Figure 2 It is shown as a straight dashed line with an arrow.

[0067] After the entire deposition reaction is completed, the reaction chamber needs to be purged with H2 to exhaust the gas remaining in the reaction chamber and to cool the reaction chamber and the epitaxial silicon wafer after the film is grown. Figure 3As shown in , illustratively, the cooling process can be performed at a rate of 9° C. / s until the temperature of the reaction chamber drops to 850° C. Finally, the silicon wafer is unloaded and exits the reaction chamber.

[0068] Figure 4 and Figure 5 The haze defects on the surface of the epitaxial silicon wafer before and after the process improvement using the epitaxial growth method for silicon wafers according to the embodiment of the present disclosure are respectively shown.

[0069] It can be clearly seen that before the process improvement, serious haze defects appeared on the surface of the epitaxial silicon wafer, especially in the edge area of the epitaxial silicon wafer, where the haze defects were particularly serious; in comparison, after the process improvement, there were almost no haze defects on the surface of the epitaxial silicon wafer.

[0070] also, Figure 6 The figure shows a comparison of haze levels of an epitaxial silicon wafer prepared using the epitaxial growth method for a silicon wafer according to an embodiment of the present disclosure and an epitaxial silicon wafer prepared using a conventional epitaxial growth method.

[0071] In this comparison, five silicon wafers were tested for haze levels, one using conventional epitaxial silicon wafers and one using the improved method. It can be clearly seen that the haze levels of the epitaxial silicon wafers prepared using the method disclosed herein are significantly lower than those of the conventional method. The average (AVG) improvement in haze levels was reduced from 2.852868 to 1.318732, a reduction of more than half.

[0072] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for epitaxial growth of silicon wafers, characterized in that: include: forming a polysilicon layer on a surface of a base of a reaction chamber for placing a silicon wafer; Allowing the silicon wafer to enter the reaction chamber so as to be placed on the surface of the susceptor and introducing H2 into the reaction chamber; causing the temperature of the reaction chamber to reach a first predetermined temperature; performing H2 baking on the surface of the silicon wafer at the first predetermined temperature for a first predetermined time; causing the temperature of the reaction chamber to reach a second predetermined temperature; introducing HCl gas into the reaction chamber at the second predetermined temperature for a second predetermined time; introducing SiHCl3 gas into the reaction chamber to deposit a film on the surface of the silicon wafer; as well as The reaction chamber is purged with H2 and the silicon wafer is unloaded and exits the reaction chamber. The epitaxial growth method further includes controlling the thermal emissivity of an upper lamp module disposed on an upper side of the susceptor for heating the reaction chamber to be higher than the thermal emissivity of a lower lamp module disposed on a lower side of the susceptor for heating the reaction chamber before the silicon wafer enters the reaction chamber to be placed on the surface of the susceptor.

2. The epitaxial growth method for silicon wafers according to claim 1, wherein: The thermal emissivity of the upper lamp module is controlled to be 0.015-0.025 higher than the thermal emissivity of the lower lamp module.

3. The epitaxial growth method for silicon wafers according to claim 1 or 2, characterized in that: The first predetermined temperature is 1135°C.

4. The epitaxial growth method for silicon wafers according to claim 3, characterized in that: The first predetermined time is 60s-80s.

5. The epitaxial growth method for silicon wafers according to claim 1 or 2, characterized in that: The second predetermined temperature is 1125°C.

6. The epitaxial growth method for silicon wafers according to claim 5, characterized in that: The flow rate of the HCl gas is 3slm-3.125slm.

7. The epitaxial growth method for silicon wafers according to claim 5, characterized in that: The second predetermined time is 10s-30s.

8. The epitaxial growth method for silicon wafers according to claim 1 or 2, characterized in that: Enabling the temperature of the reaction chamber to reach a first predetermined temperature includes increasing the temperature of the reaction chamber to the first predetermined temperature at a rate of 3° C. / s.

9. The epitaxial growth method for silicon wafers according to claim 1 or 2, characterized in that: The step of introducing SiHCl 3 gas into the reaction chamber to deposit a film on the surface of the silicon wafer includes allowing the SiHCl 3 gas to purge a pipeline leading to the reaction chamber for a certain period of time before the SiHCl 3 gas enters the reaction chamber.

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